------------------------------------------------------------------------------/
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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-- DISCLAIMER
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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------------------------------------------------------------------------------/
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_misc.all;
     use IEEE.numeric_std.all;
     use ieee.std_logic_arith.all;
     use ieee.std_logic_unsigned.all;

entity  efex_aurora_hub2 is
 port (
    -- AXI TX Interface
    s_axi_tx_tdata         : in  std_logic_vector(63 downto 0);
 
    s_axi_tx_tvalid        : in  std_logic;
    s_axi_tx_tready        : out std_logic;
    s_axi_tx_tkeep         : in std_logic_vector(7 downto 0);
 
    s_axi_tx_tlast         : in  std_logic;



    -- User Flow Control TX Interface
    s_axi_ufc_tx_tvalid    : in std_logic;
    s_axi_ufc_tx_tdata     : in std_logic_vector(2 downto 0);
    s_axi_ufc_tx_tready    : out std_logic;




    txp                    : out std_logic_vector(0 to 3);
    txn                    : out std_logic_vector(0 to 3);

    -- GT Reference Clock Interface
    gt_refclk1               : in  std_logic;

    -- Error Detection Interface
    tx_hard_err            : out std_logic;
    -- Status
    tx_lane_up             : out std_logic_vector(0 to 3);
    tx_channel_up          : out std_logic;




    -- System Interface
    user_clk               : in  std_logic;
    sync_clk               : in  std_logic;
 
    tx_system_reset        : in  std_logic;

    power_down             : in  std_logic;
    loopback               : in  std_logic_vector(2 downto 0);
    gt_reset               : in  std_logic;
    tx_lock                : out std_logic;
    sys_reset_out          : out std_logic;
    init_clk_in            : in  std_logic;
    tx_resetdone_out       : out std_logic;

    --DRP Ports
 
    drpclk_in                         : in   std_logic;
    drpaddr_in             : in   std_logic_vector(8 downto 0);
    drpdi_in               : in   std_logic_vector(15 downto 0);
    drpdo_out              : out  std_logic_vector(15 downto 0);
    drpen_in               : in   std_logic;
    drprdy_out             : out  std_logic;
    drpwe_in               : in   std_logic;
    drpaddr_in_lane1             : in   std_logic_vector(8 downto 0);
    drpdi_in_lane1               : in   std_logic_vector(15 downto 0);
    drpdo_out_lane1              : out  std_logic_vector(15 downto 0);
    drpen_in_lane1               : in   std_logic;
    drprdy_out_lane1             : out  std_logic;
    drpwe_in_lane1               : in   std_logic;
    drpaddr_in_lane2             : in   std_logic_vector(8 downto 0);
    drpdi_in_lane2               : in   std_logic_vector(15 downto 0);
    drpdo_out_lane2              : out  std_logic_vector(15 downto 0);
    drpen_in_lane2               : in   std_logic;
    drprdy_out_lane2             : out  std_logic;
    drpwe_in_lane2               : in   std_logic;
    drpaddr_in_lane3             : in   std_logic_vector(8 downto 0);
    drpdi_in_lane3               : in   std_logic_vector(15 downto 0);
    drpdo_out_lane3              : out  std_logic_vector(15 downto 0);
    drpen_in_lane3               : in   std_logic;
    drprdy_out_lane3             : out  std_logic;
    drpwe_in_lane3               : in   std_logic;
    gt0_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt0_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt0_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt0_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt0_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt0_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt0_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt0_txpolarity_in                           : in   std_logic;
    gt0_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt0_txprbsforceerr_in                       : in   std_logic;
    gt0_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt0_txpcsreset_in                           : in   std_logic;
    gt0_txinhibit_in                            : in   std_logic;
    gt0_txpmareset_in                           : in   std_logic;
    gt0_txresetdone_out                         : out std_logic;
    gt0_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt1_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt1_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt1_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt1_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt1_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt1_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt1_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt1_txpolarity_in                           : in   std_logic;
    gt1_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt1_txprbsforceerr_in                       : in   std_logic;
    gt1_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt1_txpcsreset_in                           : in   std_logic;
    gt1_txinhibit_in                            : in   std_logic;
    gt1_txpmareset_in                           : in   std_logic;
    gt1_txresetdone_out                         : out std_logic;
    gt1_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt2_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt2_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt2_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt2_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt2_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt2_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt2_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt2_txpolarity_in                           : in   std_logic;
    gt2_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt2_txprbsforceerr_in                       : in   std_logic;
    gt2_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt2_txpcsreset_in                           : in   std_logic;
    gt2_txinhibit_in                            : in   std_logic;
    gt2_txpmareset_in                           : in   std_logic;
    gt2_txresetdone_out                         : out std_logic;
    gt2_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt3_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt3_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt3_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt3_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt3_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt3_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt3_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt3_txpolarity_in                           : in   std_logic;
    gt3_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt3_txprbsforceerr_in                       : in   std_logic;
    gt3_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt3_txpcsreset_in                           : in   std_logic;
    gt3_txinhibit_in                            : in   std_logic;
    gt3_txpmareset_in                           : in   std_logic;
    gt3_txresetdone_out                         : out std_logic;
    gt3_txbufstatus_out                         : out  std_logic_vector(1 downto 0);

--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad5_in    : in  std_logic;
   gt_qpllrefclk_quad5_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}
    tx_out_clk             : out std_logic;
    pll_not_locked         : in  std_logic

 );

end efex_aurora_hub2;


architecture STRUCTURE of efex_aurora_hub2 is
  attribute core_generation_info           : string;
  attribute core_generation_info of STRUCTURE : architecture is "efex_aurora_hub2,aurora_8b10b_v11_1_10,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=left,c_gt_clock_1=GTHQ4,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=1,c_gt_loc_18=2,c_gt_loc_19=3,c_gt_loc_2=X,c_gt_loc_20=4,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=64120,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160300,c_simplex=true,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=TX-only_Simplex}";

    component efex_aurora_hub2_core
        port   (
         -- TX Stream Interface
         S_AXI_TX_TDATA         : in  std_logic_vector(63 downto 0);
         S_AXI_TX_TKEEP         : in std_logic_vector(7 downto 0);
         S_AXI_TX_TVALID        : in  std_logic;
         S_AXI_TX_TREADY        : out std_logic;
         S_AXI_TX_TLAST         : in  std_logic;

         -- User Flow Control TX Interface

         S_AXI_UFC_TX_REQ       : in std_logic;
         S_AXI_UFC_TX_MS        : in std_logic_vector(2 downto 0);
         S_AXI_UFC_TX_ACK       : out std_logic;


         TXP                    : out std_logic_vector(0 to 3); 
         TXN                    : out std_logic_vector(0 to 3);

         -- GT Reference Clock Interface

         gt_refclk1             : in std_logic;

         -- Error Detection Interface
         TX_HARD_ERR            : out std_logic;

         -- Status
         TX_CHANNEL_UP          : out std_logic;
         TX_LANE_UP             : out std_logic_vector(0 to 3);

               



         -- Clock Compensation Control Interface

         -- System Interface

         USER_CLK         : in std_logic;
         SYNC_CLK         : in std_logic;
         GT_RESET         : in std_logic;
         TX_SYSTEM_RESET  : in std_logic;
         sys_reset_out    : out std_logic;
         POWER_DOWN       : in std_logic;
         LOOPBACK         : in std_logic_vector(2 downto 0);
         TX_OUT_CLK       : out std_logic;
         INIT_CLK_IN         : in  std_logic; 
         PLL_NOT_LOCKED      : in  std_logic;
         TX_RESETDONE_OUT    : out std_logic;

    gt0_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt0_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt0_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt0_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt0_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt0_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt0_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt0_txpolarity_in                           : in   std_logic;
    gt0_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt0_txprbsforceerr_in                       : in   std_logic;
    gt0_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt0_txpcsreset_in                           : in   std_logic;
    gt0_txinhibit_in                            : in   std_logic;
    gt0_txpmareset_in                           : in   std_logic;
    gt0_txresetdone_out                         : out std_logic;
    gt0_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt1_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt1_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt1_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt1_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt1_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt1_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt1_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt1_txpolarity_in                           : in   std_logic;
    gt1_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt1_txprbsforceerr_in                       : in   std_logic;
    gt1_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt1_txpcsreset_in                           : in   std_logic;
    gt1_txinhibit_in                            : in   std_logic;
    gt1_txpmareset_in                           : in   std_logic;
    gt1_txresetdone_out                         : out std_logic;
    gt1_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt2_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt2_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt2_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt2_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt2_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt2_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt2_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt2_txpolarity_in                           : in   std_logic;
    gt2_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt2_txprbsforceerr_in                       : in   std_logic;
    gt2_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt2_txpcsreset_in                           : in   std_logic;
    gt2_txinhibit_in                            : in   std_logic;
    gt2_txpmareset_in                           : in   std_logic;
    gt2_txresetdone_out                         : out std_logic;
    gt2_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt3_cplllock_out                     : out std_logic;


    ------------------------ TX Configurable Driver Ports ----------------------
    gt3_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt3_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt3_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt3_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt3_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt3_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt3_txpolarity_in                           : in   std_logic;
    gt3_tx_buf_err_out                          : out  std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt3_txprbsforceerr_in                       : in   std_logic;
    gt3_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt3_txpcsreset_in                           : in   std_logic;
    gt3_txinhibit_in                            : in   std_logic;
    gt3_txpmareset_in                           : in   std_logic;
    gt3_txresetdone_out                         : out std_logic;
    gt3_txbufstatus_out                         : out  std_logic_vector(1 downto 0);

         drpclk_in                                    : in   std_logic;
         DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN                                : in   std_logic;
         DRPRDY_OUT                              : out  std_logic;
         DRPWE_IN                                : in   std_logic;
         DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN_LANE1                                : in   std_logic;
         DRPRDY_OUT_LANE1                              : out  std_logic;
         DRPWE_IN_LANE1                                : in   std_logic;
         DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN_LANE2                                : in   std_logic;
         DRPRDY_OUT_LANE2                              : out  std_logic;
         DRPWE_IN_LANE2                                : in   std_logic;
         DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN_LANE3                                : in   std_logic;
         DRPRDY_OUT_LANE3                              : out  std_logic;
         DRPWE_IN_LANE3                                : in   std_logic;
   	
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad5_in    : in  std_logic;
   gt_qpllrefclk_quad5_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}
         TX_LOCK          : out std_logic
    );

    end component;

begin

 --*********************************Main Body of Code**********************************

     U0 : efex_aurora_hub2_core
     port map (
        -- AXI TX Interface
        s_axi_tx_tdata               => s_axi_tx_tdata,
        s_axi_tx_tkeep               => s_axi_tx_tkeep,
        s_axi_tx_tvalid              => s_axi_tx_tvalid,
        s_axi_tx_tlast               => s_axi_tx_tlast,
        s_axi_tx_tready              => s_axi_tx_tready,


        -- User Flow Control TX Interface
        s_axi_ufc_tx_req             => s_axi_ufc_tx_tvalid,
        s_axi_ufc_tx_ms              => s_axi_ufc_tx_tdata,
        s_axi_ufc_tx_ack             => s_axi_ufc_tx_tready,


        -- GT Serial I/O
        txp                          => txp,
        txn                          => txn,

        -- GT Reference Clock Interface
        gt_refclk1                   => gt_refclk1,
        -- Error Detection Interface

        -- Error Detection Interface
        tx_hard_err                  => tx_hard_err,

        -- Status
        tx_channel_up                => tx_channel_up,
        tx_lane_up                   => tx_lane_up,




        -- System Interface
        user_clk                     => user_clk,
        sync_clk                     => sync_clk,
        tx_system_reset              => tx_system_reset,
        sys_reset_out                => sys_reset_out,
        power_down                   => power_down,
        loopback                     => loopback,
        gt_reset                     => gt_reset,
        tx_lock                      => tx_lock,
        init_clk_in                  => init_clk_in,
        pll_not_locked               => pll_not_locked,
	tx_resetdone_out             => tx_resetdone_out,
         gt0_cplllock_out                   => gt0_cplllock_out, 


        ------------------------ TX Configurable Driver Ports ----------------------
         gt0_txpostcursor_in                => gt0_txpostcursor_in,
         gt0_txprecursor_in                 => gt0_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt0_txchardispmode_in              => gt0_txchardispmode_in,
         gt0_txchardispval_in               => gt0_txchardispval_in,
         gt0_txdiffctrl_in                  => gt0_txdiffctrl_in,
         gt0_txmaincursor_in                => gt0_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt0_txpolarity_in                  => gt0_txpolarity_in,
         gt0_tx_buf_err_out                 => gt0_tx_buf_err_out,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt0_txprbsforceerr_in           => gt0_txprbsforceerr_in,
        gt0_txprbssel_in                => gt0_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt0_txpcsreset_in               => gt0_txpcsreset_in,
        gt0_txinhibit_in                => gt0_txinhibit_in,
        gt0_txpmareset_in               => gt0_txpmareset_in,
        gt0_txresetdone_out             => gt0_txresetdone_out,
        gt0_txbufstatus_out             => gt0_txbufstatus_out,

         gt1_cplllock_out                   => gt1_cplllock_out, 


        ------------------------ TX Configurable Driver Ports ----------------------
         gt1_txpostcursor_in                => gt1_txpostcursor_in,
         gt1_txprecursor_in                 => gt1_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt1_txchardispmode_in              => gt1_txchardispmode_in,
         gt1_txchardispval_in               => gt1_txchardispval_in,
         gt1_txdiffctrl_in                  => gt1_txdiffctrl_in,
         gt1_txmaincursor_in                => gt1_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt1_txpolarity_in                  => gt1_txpolarity_in,
         gt1_tx_buf_err_out                 => gt1_tx_buf_err_out,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt1_txprbsforceerr_in           => gt1_txprbsforceerr_in,
        gt1_txprbssel_in                => gt1_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt1_txpcsreset_in               => gt1_txpcsreset_in,
        gt1_txinhibit_in                => gt1_txinhibit_in,
        gt1_txpmareset_in               => gt1_txpmareset_in,
        gt1_txresetdone_out             => gt1_txresetdone_out,
        gt1_txbufstatus_out             => gt1_txbufstatus_out,

         gt2_cplllock_out                   => gt2_cplllock_out, 


        ------------------------ TX Configurable Driver Ports ----------------------
         gt2_txpostcursor_in                => gt2_txpostcursor_in,
         gt2_txprecursor_in                 => gt2_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt2_txchardispmode_in              => gt2_txchardispmode_in,
         gt2_txchardispval_in               => gt2_txchardispval_in,
         gt2_txdiffctrl_in                  => gt2_txdiffctrl_in,
         gt2_txmaincursor_in                => gt2_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt2_txpolarity_in                  => gt2_txpolarity_in,
         gt2_tx_buf_err_out                 => gt2_tx_buf_err_out,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt2_txprbsforceerr_in           => gt2_txprbsforceerr_in,
        gt2_txprbssel_in                => gt2_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt2_txpcsreset_in               => gt2_txpcsreset_in,
        gt2_txinhibit_in                => gt2_txinhibit_in,
        gt2_txpmareset_in               => gt2_txpmareset_in,
        gt2_txresetdone_out             => gt2_txresetdone_out,
        gt2_txbufstatus_out             => gt2_txbufstatus_out,

         gt3_cplllock_out                   => gt3_cplllock_out, 


        ------------------------ TX Configurable Driver Ports ----------------------
         gt3_txpostcursor_in                => gt3_txpostcursor_in,
         gt3_txprecursor_in                 => gt3_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt3_txchardispmode_in              => gt3_txchardispmode_in,
         gt3_txchardispval_in               => gt3_txchardispval_in,
         gt3_txdiffctrl_in                  => gt3_txdiffctrl_in,
         gt3_txmaincursor_in                => gt3_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt3_txpolarity_in                  => gt3_txpolarity_in,
         gt3_tx_buf_err_out                 => gt3_tx_buf_err_out,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt3_txprbsforceerr_in           => gt3_txprbsforceerr_in,
        gt3_txprbssel_in                => gt3_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt3_txpcsreset_in               => gt3_txpcsreset_in,
        gt3_txinhibit_in                => gt3_txinhibit_in,
        gt3_txpmareset_in               => gt3_txpmareset_in,
        gt3_txresetdone_out             => gt3_txresetdone_out,
        gt3_txbufstatus_out             => gt3_txbufstatus_out,

        drpclk_in                    => drpclk_in,
        drpaddr_in                   => drpaddr_in,
        drpen_in                     => drpen_in,
        drpdi_in                     => drpdi_in,
        drprdy_out                   => drprdy_out, 
        drpdo_out                    => drpdo_out,
        drpwe_in                     => drpwe_in,
        drpaddr_in_lane1                   => drpaddr_in_lane1,
        drpen_in_lane1                     => drpen_in_lane1,
        drpdi_in_lane1                     => drpdi_in_lane1,
        drprdy_out_lane1                   => drprdy_out_lane1, 
        drpdo_out_lane1                    => drpdo_out_lane1,
        drpwe_in_lane1                     => drpwe_in_lane1,
        drpaddr_in_lane2                   => drpaddr_in_lane2,
        drpen_in_lane2                     => drpen_in_lane2,
        drpdi_in_lane2                     => drpdi_in_lane2,
        drprdy_out_lane2                   => drprdy_out_lane2, 
        drpdo_out_lane2                    => drpdo_out_lane2,
        drpwe_in_lane2                     => drpwe_in_lane2,
        drpaddr_in_lane3                   => drpaddr_in_lane3,
        drpen_in_lane3                     => drpen_in_lane3,
        drpdi_in_lane3                     => drpdi_in_lane3,
        drprdy_out_lane3                   => drprdy_out_lane3, 
        drpdo_out_lane3                    => drpdo_out_lane3,
        drpwe_in_lane3                     => drpwe_in_lane3,
--------------------{
--____________________________COMMON PORTS INST_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in        =>  gt0_qplllock_in,
      gt0_qpllrefclklost_in  =>  gt0_qpllrefclklost_in,
      gt0_qpllreset_out      =>  gt0_qpllreset_out,
        gt_qpllclk_quad5_in     => gt_qpllclk_quad5_in    ,
        gt_qpllrefclk_quad5_in  => gt_qpllrefclk_quad5_in ,
--____________________________COMMON PORTS INST_______________________________}
--------------------}
        tx_out_clk                   => tx_out_clk

     );

 end STRUCTURE;
