// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
// Date        : Sat Mar  8 22:13:41 2025
// Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit AlmaLinux 9.5 (Teal Serval)
// Command     : write_verilog -force -mode funcsim
//               /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_sim_netlist.v
// Design      : efex_aurora_hub2
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7vx330tffg1157-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* NotValidForBitStream *)
module efex_aurora_hub2
   (s_axi_tx_tdata,
    s_axi_tx_tvalid,
    s_axi_tx_tready,
    s_axi_tx_tkeep,
    s_axi_tx_tlast,
    s_axi_ufc_tx_tvalid,
    s_axi_ufc_tx_tdata,
    s_axi_ufc_tx_tready,
    txp,
    txn,
    gt_refclk1,
    tx_hard_err,
    tx_lane_up,
    tx_channel_up,
    user_clk,
    sync_clk,
    tx_system_reset,
    power_down,
    loopback,
    gt_reset,
    tx_lock,
    sys_reset_out,
    init_clk_in,
    tx_resetdone_out,
    drpclk_in,
    drpaddr_in,
    drpdi_in,
    drpdo_out,
    drpen_in,
    drprdy_out,
    drpwe_in,
    drpaddr_in_lane1,
    drpdi_in_lane1,
    drpdo_out_lane1,
    drpen_in_lane1,
    drprdy_out_lane1,
    drpwe_in_lane1,
    drpaddr_in_lane2,
    drpdi_in_lane2,
    drpdo_out_lane2,
    drpen_in_lane2,
    drprdy_out_lane2,
    drpwe_in_lane2,
    drpaddr_in_lane3,
    drpdi_in_lane3,
    drpdo_out_lane3,
    drpen_in_lane3,
    drprdy_out_lane3,
    drpwe_in_lane3,
    gt0_cplllock_out,
    gt0_txpostcursor_in,
    gt0_txprecursor_in,
    gt0_txchardispmode_in,
    gt0_txchardispval_in,
    gt0_txdiffctrl_in,
    gt0_txmaincursor_in,
    gt0_txpolarity_in,
    gt0_tx_buf_err_out,
    gt0_txprbsforceerr_in,
    gt0_txprbssel_in,
    gt0_txpcsreset_in,
    gt0_txinhibit_in,
    gt0_txpmareset_in,
    gt0_txresetdone_out,
    gt0_txbufstatus_out,
    gt1_cplllock_out,
    gt1_txpostcursor_in,
    gt1_txprecursor_in,
    gt1_txchardispmode_in,
    gt1_txchardispval_in,
    gt1_txdiffctrl_in,
    gt1_txmaincursor_in,
    gt1_txpolarity_in,
    gt1_tx_buf_err_out,
    gt1_txprbsforceerr_in,
    gt1_txprbssel_in,
    gt1_txpcsreset_in,
    gt1_txinhibit_in,
    gt1_txpmareset_in,
    gt1_txresetdone_out,
    gt1_txbufstatus_out,
    gt2_cplllock_out,
    gt2_txpostcursor_in,
    gt2_txprecursor_in,
    gt2_txchardispmode_in,
    gt2_txchardispval_in,
    gt2_txdiffctrl_in,
    gt2_txmaincursor_in,
    gt2_txpolarity_in,
    gt2_tx_buf_err_out,
    gt2_txprbsforceerr_in,
    gt2_txprbssel_in,
    gt2_txpcsreset_in,
    gt2_txinhibit_in,
    gt2_txpmareset_in,
    gt2_txresetdone_out,
    gt2_txbufstatus_out,
    gt3_cplllock_out,
    gt3_txpostcursor_in,
    gt3_txprecursor_in,
    gt3_txchardispmode_in,
    gt3_txchardispval_in,
    gt3_txdiffctrl_in,
    gt3_txmaincursor_in,
    gt3_txpolarity_in,
    gt3_tx_buf_err_out,
    gt3_txprbsforceerr_in,
    gt3_txprbssel_in,
    gt3_txpcsreset_in,
    gt3_txinhibit_in,
    gt3_txpmareset_in,
    gt3_txresetdone_out,
    gt3_txbufstatus_out,
    gt0_qplllock_in,
    gt0_qpllrefclklost_in,
    gt0_qpllreset_out,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    tx_out_clk,
    pll_not_locked);
  input [63:0]s_axi_tx_tdata;
  input s_axi_tx_tvalid;
  output s_axi_tx_tready;
  input [7:0]s_axi_tx_tkeep;
  input s_axi_tx_tlast;
  input s_axi_ufc_tx_tvalid;
  input [2:0]s_axi_ufc_tx_tdata;
  output s_axi_ufc_tx_tready;
  output [0:3]txp;
  output [0:3]txn;
  input gt_refclk1;
  output tx_hard_err;
  output [0:3]tx_lane_up;
  output tx_channel_up;
  input user_clk;
  input sync_clk;
  input tx_system_reset;
  input power_down;
  input [2:0]loopback;
  input gt_reset;
  output tx_lock;
  output sys_reset_out;
  input init_clk_in;
  output tx_resetdone_out;
  input drpclk_in;
  input [8:0]drpaddr_in;
  input [15:0]drpdi_in;
  output [15:0]drpdo_out;
  input drpen_in;
  output drprdy_out;
  input drpwe_in;
  input [8:0]drpaddr_in_lane1;
  input [15:0]drpdi_in_lane1;
  output [15:0]drpdo_out_lane1;
  input drpen_in_lane1;
  output drprdy_out_lane1;
  input drpwe_in_lane1;
  input [8:0]drpaddr_in_lane2;
  input [15:0]drpdi_in_lane2;
  output [15:0]drpdo_out_lane2;
  input drpen_in_lane2;
  output drprdy_out_lane2;
  input drpwe_in_lane2;
  input [8:0]drpaddr_in_lane3;
  input [15:0]drpdi_in_lane3;
  output [15:0]drpdo_out_lane3;
  input drpen_in_lane3;
  output drprdy_out_lane3;
  input drpwe_in_lane3;
  output gt0_cplllock_out;
  input [4:0]gt0_txpostcursor_in;
  input [4:0]gt0_txprecursor_in;
  input [1:0]gt0_txchardispmode_in;
  input [1:0]gt0_txchardispval_in;
  input [3:0]gt0_txdiffctrl_in;
  input [6:0]gt0_txmaincursor_in;
  input gt0_txpolarity_in;
  output gt0_tx_buf_err_out;
  input gt0_txprbsforceerr_in;
  input [2:0]gt0_txprbssel_in;
  input gt0_txpcsreset_in;
  input gt0_txinhibit_in;
  input gt0_txpmareset_in;
  output gt0_txresetdone_out;
  output [1:0]gt0_txbufstatus_out;
  output gt1_cplllock_out;
  input [4:0]gt1_txpostcursor_in;
  input [4:0]gt1_txprecursor_in;
  input [1:0]gt1_txchardispmode_in;
  input [1:0]gt1_txchardispval_in;
  input [3:0]gt1_txdiffctrl_in;
  input [6:0]gt1_txmaincursor_in;
  input gt1_txpolarity_in;
  output gt1_tx_buf_err_out;
  input gt1_txprbsforceerr_in;
  input [2:0]gt1_txprbssel_in;
  input gt1_txpcsreset_in;
  input gt1_txinhibit_in;
  input gt1_txpmareset_in;
  output gt1_txresetdone_out;
  output [1:0]gt1_txbufstatus_out;
  output gt2_cplllock_out;
  input [4:0]gt2_txpostcursor_in;
  input [4:0]gt2_txprecursor_in;
  input [1:0]gt2_txchardispmode_in;
  input [1:0]gt2_txchardispval_in;
  input [3:0]gt2_txdiffctrl_in;
  input [6:0]gt2_txmaincursor_in;
  input gt2_txpolarity_in;
  output gt2_tx_buf_err_out;
  input gt2_txprbsforceerr_in;
  input [2:0]gt2_txprbssel_in;
  input gt2_txpcsreset_in;
  input gt2_txinhibit_in;
  input gt2_txpmareset_in;
  output gt2_txresetdone_out;
  output [1:0]gt2_txbufstatus_out;
  output gt3_cplllock_out;
  input [4:0]gt3_txpostcursor_in;
  input [4:0]gt3_txprecursor_in;
  input [1:0]gt3_txchardispmode_in;
  input [1:0]gt3_txchardispval_in;
  input [3:0]gt3_txdiffctrl_in;
  input [6:0]gt3_txmaincursor_in;
  input gt3_txpolarity_in;
  output gt3_tx_buf_err_out;
  input gt3_txprbsforceerr_in;
  input [2:0]gt3_txprbssel_in;
  input gt3_txpcsreset_in;
  input gt3_txinhibit_in;
  input gt3_txpmareset_in;
  output gt3_txresetdone_out;
  output [1:0]gt3_txbufstatus_out;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  output tx_out_clk;
  input pll_not_locked;

  wire \<const0> ;
  wire [8:0]drpaddr_in;
  wire [8:0]drpaddr_in_lane1;
  wire [8:0]drpaddr_in_lane2;
  wire [8:0]drpaddr_in_lane3;
  wire drpclk_in;
  wire [15:0]drpdi_in;
  wire [15:0]drpdi_in_lane1;
  wire [15:0]drpdi_in_lane2;
  wire [15:0]drpdi_in_lane3;
  wire [15:0]drpdo_out;
  wire [15:0]drpdo_out_lane1;
  wire [15:0]drpdo_out_lane2;
  wire [15:0]drpdo_out_lane3;
  wire drpen_in;
  wire drpen_in_lane1;
  wire drpen_in_lane2;
  wire drpen_in_lane3;
  wire drprdy_out;
  wire drprdy_out_lane1;
  wire drprdy_out_lane2;
  wire drprdy_out_lane3;
  wire drpwe_in;
  wire drpwe_in_lane1;
  wire drpwe_in_lane2;
  wire drpwe_in_lane3;
  wire gt0_cplllock_out;
  wire gt0_tx_buf_err_out;
  wire [1:0]gt0_txbufstatus_out;
  wire [1:0]gt0_txchardispmode_in;
  wire [1:0]gt0_txchardispval_in;
  wire [3:0]gt0_txdiffctrl_in;
  wire gt0_txinhibit_in;
  wire [6:0]gt0_txmaincursor_in;
  wire gt0_txpcsreset_in;
  wire gt0_txpmareset_in;
  wire gt0_txpolarity_in;
  wire [4:0]gt0_txpostcursor_in;
  wire gt0_txprbsforceerr_in;
  wire [2:0]gt0_txprbssel_in;
  wire [4:0]gt0_txprecursor_in;
  wire gt0_txresetdone_out;
  wire gt1_cplllock_out;
  wire gt1_tx_buf_err_out;
  wire [1:0]gt1_txbufstatus_out;
  wire [1:0]gt1_txchardispmode_in;
  wire [1:0]gt1_txchardispval_in;
  wire [3:0]gt1_txdiffctrl_in;
  wire gt1_txinhibit_in;
  wire [6:0]gt1_txmaincursor_in;
  wire gt1_txpcsreset_in;
  wire gt1_txpmareset_in;
  wire gt1_txpolarity_in;
  wire [4:0]gt1_txpostcursor_in;
  wire gt1_txprbsforceerr_in;
  wire [2:0]gt1_txprbssel_in;
  wire [4:0]gt1_txprecursor_in;
  wire gt1_txresetdone_out;
  wire gt2_cplllock_out;
  wire gt2_tx_buf_err_out;
  wire [1:0]gt2_txbufstatus_out;
  wire [1:0]gt2_txchardispmode_in;
  wire [1:0]gt2_txchardispval_in;
  wire [3:0]gt2_txdiffctrl_in;
  wire gt2_txinhibit_in;
  wire [6:0]gt2_txmaincursor_in;
  wire gt2_txpcsreset_in;
  wire gt2_txpmareset_in;
  wire gt2_txpolarity_in;
  wire [4:0]gt2_txpostcursor_in;
  wire gt2_txprbsforceerr_in;
  wire [2:0]gt2_txprbssel_in;
  wire [4:0]gt2_txprecursor_in;
  wire gt2_txresetdone_out;
  wire gt3_cplllock_out;
  wire gt3_tx_buf_err_out;
  wire [1:0]gt3_txbufstatus_out;
  wire [1:0]gt3_txchardispmode_in;
  wire [1:0]gt3_txchardispval_in;
  wire [3:0]gt3_txdiffctrl_in;
  wire gt3_txinhibit_in;
  wire [6:0]gt3_txmaincursor_in;
  wire gt3_txpcsreset_in;
  wire gt3_txpmareset_in;
  wire gt3_txpolarity_in;
  wire [4:0]gt3_txpostcursor_in;
  wire gt3_txprbsforceerr_in;
  wire [2:0]gt3_txprbssel_in;
  wire [4:0]gt3_txprecursor_in;
  wire gt3_txresetdone_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_reset;
  wire init_clk_in;
  wire [2:0]loopback;
  wire power_down;
  wire [63:0]s_axi_tx_tdata;
  wire [7:0]s_axi_tx_tkeep;
  wire s_axi_tx_tlast;
  wire s_axi_tx_tready;
  wire s_axi_tx_tvalid;
  wire [2:0]s_axi_ufc_tx_tdata;
  wire s_axi_ufc_tx_tready;
  wire s_axi_ufc_tx_tvalid;
  wire sync_clk;
  wire sys_reset_out;
  wire tx_channel_up;
  wire tx_hard_err;
  wire [0:3]tx_lane_up;
  wire tx_lock;
  wire tx_out_clk;
  wire tx_resetdone_out;
  wire tx_system_reset;
  wire [0:3]txn;
  wire [0:3]txp;
  wire user_clk;
  wire NLW_U0_gt0_qpllreset_out_UNCONNECTED;

  assign gt0_qpllreset_out = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* CC_FREQ_FACTOR = "24" *) 
  (* EXAMPLE_SIMULATION = "0" *) 
  (* SIM_GTRESET_SPEEDUP = "FALSE" *) 
  efex_aurora_hub2_efex_aurora_hub2_core U0
       (.DRPADDR_IN(drpaddr_in),
        .DRPADDR_IN_LANE1(drpaddr_in_lane1),
        .DRPADDR_IN_LANE2(drpaddr_in_lane2),
        .DRPADDR_IN_LANE3(drpaddr_in_lane3),
        .DRPDI_IN(drpdi_in),
        .DRPDI_IN_LANE1(drpdi_in_lane1),
        .DRPDI_IN_LANE2(drpdi_in_lane2),
        .DRPDI_IN_LANE3(drpdi_in_lane3),
        .DRPDO_OUT(drpdo_out),
        .DRPDO_OUT_LANE1(drpdo_out_lane1),
        .DRPDO_OUT_LANE2(drpdo_out_lane2),
        .DRPDO_OUT_LANE3(drpdo_out_lane3),
        .DRPEN_IN(drpen_in),
        .DRPEN_IN_LANE1(drpen_in_lane1),
        .DRPEN_IN_LANE2(drpen_in_lane2),
        .DRPEN_IN_LANE3(drpen_in_lane3),
        .DRPRDY_OUT(drprdy_out),
        .DRPRDY_OUT_LANE1(drprdy_out_lane1),
        .DRPRDY_OUT_LANE2(drprdy_out_lane2),
        .DRPRDY_OUT_LANE3(drprdy_out_lane3),
        .DRPWE_IN(drpwe_in),
        .DRPWE_IN_LANE1(drpwe_in_lane1),
        .DRPWE_IN_LANE2(drpwe_in_lane2),
        .DRPWE_IN_LANE3(drpwe_in_lane3),
        .GT_RESET(gt_reset),
        .LOOPBACK(loopback),
        .PLL_NOT_LOCKED(1'b0),
        .POWER_DOWN(power_down),
        .S_AXI_TX_TDATA(s_axi_tx_tdata),
        .S_AXI_TX_TKEEP(s_axi_tx_tkeep),
        .S_AXI_TX_TLAST(s_axi_tx_tlast),
        .S_AXI_TX_TREADY(s_axi_tx_tready),
        .S_AXI_TX_TVALID(s_axi_tx_tvalid),
        .S_AXI_UFC_TX_ACK(s_axi_ufc_tx_tready),
        .S_AXI_UFC_TX_MS(s_axi_ufc_tx_tdata),
        .S_AXI_UFC_TX_REQ(s_axi_ufc_tx_tvalid),
        .TXN(txn),
        .TXP(txp),
        .TX_CHANNEL_UP(tx_channel_up),
        .TX_HARD_ERR(tx_hard_err),
        .TX_LANE_UP(tx_lane_up),
        .TX_LOCK(tx_lock),
        .TX_OUT_CLK(tx_out_clk),
        .TX_RESETDONE_OUT(tx_resetdone_out),
        .TX_SYSTEM_RESET(tx_system_reset),
        .drpclk_in(drpclk_in),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_qplllock_in(1'b0),
        .gt0_qpllrefclklost_in(1'b0),
        .gt0_qpllreset_out(NLW_U0_gt0_qpllreset_out_UNCONNECTED),
        .gt0_tx_buf_err_out(gt0_tx_buf_err_out),
        .gt0_txbufstatus_out(gt0_txbufstatus_out),
        .gt0_txchardispmode_in(gt0_txchardispmode_in),
        .gt0_txchardispval_in(gt0_txchardispval_in),
        .gt0_txdiffctrl_in(gt0_txdiffctrl_in),
        .gt0_txinhibit_in(gt0_txinhibit_in),
        .gt0_txmaincursor_in(gt0_txmaincursor_in),
        .gt0_txpcsreset_in(gt0_txpcsreset_in),
        .gt0_txpmareset_in(gt0_txpmareset_in),
        .gt0_txpolarity_in(gt0_txpolarity_in),
        .gt0_txpostcursor_in(gt0_txpostcursor_in),
        .gt0_txprbsforceerr_in(gt0_txprbsforceerr_in),
        .gt0_txprbssel_in(gt0_txprbssel_in),
        .gt0_txprecursor_in(gt0_txprecursor_in),
        .gt0_txresetdone_out(gt0_txresetdone_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_tx_buf_err_out(gt1_tx_buf_err_out),
        .gt1_txbufstatus_out(gt1_txbufstatus_out),
        .gt1_txchardispmode_in(gt1_txchardispmode_in),
        .gt1_txchardispval_in(gt1_txchardispval_in),
        .gt1_txdiffctrl_in(gt1_txdiffctrl_in),
        .gt1_txinhibit_in(gt1_txinhibit_in),
        .gt1_txmaincursor_in(gt1_txmaincursor_in),
        .gt1_txpcsreset_in(gt1_txpcsreset_in),
        .gt1_txpmareset_in(gt1_txpmareset_in),
        .gt1_txpolarity_in(gt1_txpolarity_in),
        .gt1_txpostcursor_in(gt1_txpostcursor_in),
        .gt1_txprbsforceerr_in(gt1_txprbsforceerr_in),
        .gt1_txprbssel_in(gt1_txprbssel_in),
        .gt1_txprecursor_in(gt1_txprecursor_in),
        .gt1_txresetdone_out(gt1_txresetdone_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_tx_buf_err_out(gt2_tx_buf_err_out),
        .gt2_txbufstatus_out(gt2_txbufstatus_out),
        .gt2_txchardispmode_in(gt2_txchardispmode_in),
        .gt2_txchardispval_in(gt2_txchardispval_in),
        .gt2_txdiffctrl_in(gt2_txdiffctrl_in),
        .gt2_txinhibit_in(gt2_txinhibit_in),
        .gt2_txmaincursor_in(gt2_txmaincursor_in),
        .gt2_txpcsreset_in(gt2_txpcsreset_in),
        .gt2_txpmareset_in(gt2_txpmareset_in),
        .gt2_txpolarity_in(gt2_txpolarity_in),
        .gt2_txpostcursor_in(gt2_txpostcursor_in),
        .gt2_txprbsforceerr_in(gt2_txprbsforceerr_in),
        .gt2_txprbssel_in(gt2_txprbssel_in),
        .gt2_txprecursor_in(gt2_txprecursor_in),
        .gt2_txresetdone_out(gt2_txresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_tx_buf_err_out(gt3_tx_buf_err_out),
        .gt3_txbufstatus_out(gt3_txbufstatus_out),
        .gt3_txchardispmode_in(gt3_txchardispmode_in),
        .gt3_txchardispval_in(gt3_txchardispval_in),
        .gt3_txdiffctrl_in(gt3_txdiffctrl_in),
        .gt3_txinhibit_in(gt3_txinhibit_in),
        .gt3_txmaincursor_in(gt3_txmaincursor_in),
        .gt3_txpcsreset_in(gt3_txpcsreset_in),
        .gt3_txpmareset_in(gt3_txpmareset_in),
        .gt3_txpolarity_in(gt3_txpolarity_in),
        .gt3_txpostcursor_in(gt3_txpostcursor_in),
        .gt3_txprbsforceerr_in(gt3_txprbsforceerr_in),
        .gt3_txprbssel_in(gt3_txprbssel_in),
        .gt3_txprecursor_in(gt3_txprecursor_in),
        .gt3_txresetdone_out(gt3_txresetdone_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .sys_reset_out(sys_reset_out),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_AXI_TO_LL" *) 
module efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL
   (new_pkt_r_reg_0,
    new_pkt_r,
    user_clk);
  output new_pkt_r_reg_0;
  input new_pkt_r;
  input user_clk;

  wire new_pkt_r;
  wire new_pkt_r_reg_0;
  wire user_clk;

  FDRE new_pkt_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(new_pkt_r),
        .Q(new_pkt_r_reg_0),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_GT_WRAPPER" *) 
module efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER
   (TX_RESETDONE_OUT,
    gt0_cplllock_out,
    DRPRDY_OUT,
    TXN,
    TXP,
    gt0_txresetdone_out,
    DRPDO_OUT,
    gt0_txbufstatus_out,
    gt1_cplllock_out,
    DRPRDY_OUT_LANE1,
    gt1_txresetdone_out,
    DRPDO_OUT_LANE1,
    gt1_txbufstatus_out,
    gt2_cplllock_out,
    DRPRDY_OUT_LANE2,
    TX_OUT_CLK,
    gt2_txresetdone_out,
    DRPDO_OUT_LANE2,
    gt2_txbufstatus_out,
    gt3_cplllock_out,
    DRPRDY_OUT_LANE3,
    gt3_txresetdone_out,
    DRPDO_OUT_LANE3,
    gt3_txbufstatus_out,
    ENABLE_ERR_DETECT_Buffer_reg,
    ENABLE_ERR_DETECT_Buffer_reg_0,
    ENABLE_ERR_DETECT_Buffer_reg_1,
    ENABLE_ERR_DETECT_Buffer_reg_2,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ,
    TX_LOCK,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt_refclk1,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    sync_clk,
    user_clk,
    POWER_DOWN,
    gt0_txinhibit_in,
    gt0_txpcsreset_in,
    gt0_txpmareset_in,
    gt0_txpolarity_in,
    gt0_txprbsforceerr_in,
    DRPDI_IN,
    LOOPBACK,
    gt0_txprbssel_in,
    gt0_txdiffctrl_in,
    gt0_txpostcursor_in,
    gt0_txprecursor_in,
    TXDATA,
    gt0_txmaincursor_in,
    gt0_txchardispmode_in,
    gt0_txchardispval_in,
    TXCHARISK,
    DRPADDR_IN,
    DRPEN_IN_LANE1,
    DRPWE_IN_LANE1,
    gt1_txinhibit_in,
    gt1_txpcsreset_in,
    gt1_txpmareset_in,
    gt1_txpolarity_in,
    gt1_txprbsforceerr_in,
    DRPDI_IN_LANE1,
    gt1_txprbssel_in,
    gt1_txdiffctrl_in,
    gt1_txpostcursor_in,
    gt1_txprecursor_in,
    gt1_cplllock_out_0,
    gt1_txmaincursor_in,
    gt1_txchardispmode_in,
    gt1_txchardispval_in,
    gt1_cplllock_out_1,
    DRPADDR_IN_LANE1,
    DRPEN_IN_LANE2,
    DRPWE_IN_LANE2,
    gt2_txinhibit_in,
    gt2_txpcsreset_in,
    gt2_txpmareset_in,
    gt2_txpolarity_in,
    gt2_txprbsforceerr_in,
    DRPDI_IN_LANE2,
    gt2_txprbssel_in,
    gt2_txdiffctrl_in,
    gt2_txpostcursor_in,
    gt2_txprecursor_in,
    gt2_cplllock_out_0,
    gt2_txmaincursor_in,
    gt2_txchardispmode_in,
    gt2_txchardispval_in,
    gt2_cplllock_out_1,
    DRPADDR_IN_LANE2,
    DRPEN_IN_LANE3,
    DRPWE_IN_LANE3,
    gt3_txinhibit_in,
    gt3_txpcsreset_in,
    gt3_txpmareset_in,
    gt3_txpolarity_in,
    gt3_txprbsforceerr_in,
    DRPDI_IN_LANE3,
    gt3_txprbssel_in,
    gt3_txdiffctrl_in,
    gt3_txpostcursor_in,
    gt3_txprecursor_in,
    gt3_cplllock_out_0,
    gt3_txmaincursor_in,
    gt3_txchardispmode_in,
    gt3_txchardispval_in,
    gt3_cplllock_out_1,
    DRPADDR_IN_LANE3,
    AR,
    ENABLE_ERR_DETECT,
    ENABLE_ERR_DETECT_0,
    ENABLE_ERR_DETECT_1,
    ENABLE_ERR_DETECT_2);
  output TX_RESETDONE_OUT;
  output gt0_cplllock_out;
  output DRPRDY_OUT;
  output [0:3]TXN;
  output [0:3]TXP;
  output gt0_txresetdone_out;
  output [15:0]DRPDO_OUT;
  output [1:0]gt0_txbufstatus_out;
  output gt1_cplllock_out;
  output DRPRDY_OUT_LANE1;
  output gt1_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE1;
  output [1:0]gt1_txbufstatus_out;
  output gt2_cplllock_out;
  output DRPRDY_OUT_LANE2;
  output TX_OUT_CLK;
  output gt2_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE2;
  output [1:0]gt2_txbufstatus_out;
  output gt3_cplllock_out;
  output DRPRDY_OUT_LANE3;
  output gt3_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE3;
  output [1:0]gt3_txbufstatus_out;
  output ENABLE_ERR_DETECT_Buffer_reg;
  output ENABLE_ERR_DETECT_Buffer_reg_0;
  output ENABLE_ERR_DETECT_Buffer_reg_1;
  output ENABLE_ERR_DETECT_Buffer_reg_2;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ;
  output TX_LOCK;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt_refclk1;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  input sync_clk;
  input user_clk;
  input POWER_DOWN;
  input gt0_txinhibit_in;
  input gt0_txpcsreset_in;
  input gt0_txpmareset_in;
  input gt0_txpolarity_in;
  input gt0_txprbsforceerr_in;
  input [15:0]DRPDI_IN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_txprbssel_in;
  input [3:0]gt0_txdiffctrl_in;
  input [4:0]gt0_txpostcursor_in;
  input [4:0]gt0_txprecursor_in;
  input [15:0]TXDATA;
  input [6:0]gt0_txmaincursor_in;
  input [1:0]gt0_txchardispmode_in;
  input [1:0]gt0_txchardispval_in;
  input [1:0]TXCHARISK;
  input [8:0]DRPADDR_IN;
  input DRPEN_IN_LANE1;
  input DRPWE_IN_LANE1;
  input gt1_txinhibit_in;
  input gt1_txpcsreset_in;
  input gt1_txpmareset_in;
  input gt1_txpolarity_in;
  input gt1_txprbsforceerr_in;
  input [15:0]DRPDI_IN_LANE1;
  input [2:0]gt1_txprbssel_in;
  input [3:0]gt1_txdiffctrl_in;
  input [4:0]gt1_txpostcursor_in;
  input [4:0]gt1_txprecursor_in;
  input [15:0]gt1_cplllock_out_0;
  input [6:0]gt1_txmaincursor_in;
  input [1:0]gt1_txchardispmode_in;
  input [1:0]gt1_txchardispval_in;
  input [1:0]gt1_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE1;
  input DRPEN_IN_LANE2;
  input DRPWE_IN_LANE2;
  input gt2_txinhibit_in;
  input gt2_txpcsreset_in;
  input gt2_txpmareset_in;
  input gt2_txpolarity_in;
  input gt2_txprbsforceerr_in;
  input [15:0]DRPDI_IN_LANE2;
  input [2:0]gt2_txprbssel_in;
  input [3:0]gt2_txdiffctrl_in;
  input [4:0]gt2_txpostcursor_in;
  input [4:0]gt2_txprecursor_in;
  input [15:0]gt2_cplllock_out_0;
  input [6:0]gt2_txmaincursor_in;
  input [1:0]gt2_txchardispmode_in;
  input [1:0]gt2_txchardispval_in;
  input [1:0]gt2_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE2;
  input DRPEN_IN_LANE3;
  input DRPWE_IN_LANE3;
  input gt3_txinhibit_in;
  input gt3_txpcsreset_in;
  input gt3_txpmareset_in;
  input gt3_txpolarity_in;
  input gt3_txprbsforceerr_in;
  input [15:0]DRPDI_IN_LANE3;
  input [2:0]gt3_txprbssel_in;
  input [3:0]gt3_txdiffctrl_in;
  input [4:0]gt3_txpostcursor_in;
  input [4:0]gt3_txprecursor_in;
  input [15:0]gt3_cplllock_out_0;
  input [6:0]gt3_txmaincursor_in;
  input [1:0]gt3_txchardispmode_in;
  input [1:0]gt3_txchardispval_in;
  input [1:0]gt3_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE3;
  input [0:0]AR;
  input ENABLE_ERR_DETECT;
  input ENABLE_ERR_DETECT_0;
  input ENABLE_ERR_DETECT_1;
  input ENABLE_ERR_DETECT_2;

  wire [0:0]AR;
  wire CPLLLOCK;
  wire [8:0]DRPADDR_IN;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT;
  wire [15:0]DRPDO_OUT_LANE1;
  wire [15:0]DRPDO_OUT_LANE2;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN;
  wire DRPEN_IN_LANE1;
  wire DRPEN_IN_LANE2;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT;
  wire DRPRDY_OUT_LANE1;
  wire DRPRDY_OUT_LANE2;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN;
  wire DRPWE_IN_LANE1;
  wire DRPWE_IN_LANE2;
  wire DRPWE_IN_LANE3;
  wire ENABLE_ERR_DETECT;
  wire ENABLE_ERR_DETECT_0;
  wire ENABLE_ERR_DETECT_1;
  wire ENABLE_ERR_DETECT_2;
  wire ENABLE_ERR_DETECT_Buffer_reg;
  wire ENABLE_ERR_DETECT_Buffer_reg_0;
  wire ENABLE_ERR_DETECT_Buffer_reg_1;
  wire ENABLE_ERR_DETECT_Buffer_reg_2;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [1:0]TXCHARISK;
  wire [15:0]TXDATA;
  wire [0:3]TXN;
  wire [0:3]TXP;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire TX_RESETDONE_OUT;
  wire cpll_reset_i;
  wire drpclk_in;
  wire gt0_cplllock_out;
  wire [1:0]gt0_txbufstatus_out;
  wire [1:0]gt0_txchardispmode_in;
  wire [1:0]gt0_txchardispval_in;
  wire [3:0]gt0_txdiffctrl_in;
  wire gt0_txinhibit_in;
  wire [6:0]gt0_txmaincursor_in;
  wire gt0_txpcsreset_in;
  wire gt0_txpmareset_in;
  wire gt0_txpolarity_in;
  wire [4:0]gt0_txpostcursor_in;
  wire gt0_txprbsforceerr_in;
  wire [2:0]gt0_txprbssel_in;
  wire [4:0]gt0_txprecursor_in;
  wire gt0_txresetdone_out;
  wire gt0_txresetdone_r2_reg_srl2_n_0;
  wire gt0_txresetdone_r3;
  wire gt1_cplllock_out;
  wire [15:0]gt1_cplllock_out_0;
  wire [1:0]gt1_cplllock_out_1;
  wire [1:0]gt1_txbufstatus_out;
  wire [1:0]gt1_txchardispmode_in;
  wire [1:0]gt1_txchardispval_in;
  wire [3:0]gt1_txdiffctrl_in;
  wire gt1_txinhibit_in;
  wire [6:0]gt1_txmaincursor_in;
  wire gt1_txpcsreset_in;
  wire gt1_txpmareset_in;
  wire gt1_txpolarity_in;
  wire [4:0]gt1_txpostcursor_in;
  wire gt1_txprbsforceerr_in;
  wire [2:0]gt1_txprbssel_in;
  wire [4:0]gt1_txprecursor_in;
  wire gt1_txresetdone_out;
  wire gt1_txresetdone_r2_reg_srl2_n_0;
  wire gt1_txresetdone_r3;
  wire gt2_cplllock_out;
  wire [15:0]gt2_cplllock_out_0;
  wire [1:0]gt2_cplllock_out_1;
  wire [1:0]gt2_txbufstatus_out;
  wire [1:0]gt2_txchardispmode_in;
  wire [1:0]gt2_txchardispval_in;
  wire [3:0]gt2_txdiffctrl_in;
  wire gt2_txinhibit_in;
  wire [6:0]gt2_txmaincursor_in;
  wire gt2_txpcsreset_in;
  wire gt2_txpmareset_in;
  wire gt2_txpolarity_in;
  wire [4:0]gt2_txpostcursor_in;
  wire gt2_txprbsforceerr_in;
  wire [2:0]gt2_txprbssel_in;
  wire [4:0]gt2_txprecursor_in;
  wire gt2_txresetdone_out;
  wire gt2_txresetdone_r2_reg_srl2_n_0;
  wire gt2_txresetdone_r3;
  wire gt3_cplllock_out;
  wire [15:0]gt3_cplllock_out_0;
  wire [1:0]gt3_cplllock_out_1;
  wire [1:0]gt3_txbufstatus_out;
  wire [1:0]gt3_txchardispmode_in;
  wire [1:0]gt3_txchardispval_in;
  wire [3:0]gt3_txdiffctrl_in;
  wire gt3_txinhibit_in;
  wire [6:0]gt3_txmaincursor_in;
  wire gt3_txpcsreset_in;
  wire gt3_txpmareset_in;
  wire gt3_txpolarity_in;
  wire [4:0]gt3_txpostcursor_in;
  wire gt3_txprbsforceerr_in;
  wire [2:0]gt3_txprbssel_in;
  wire [4:0]gt3_txprecursor_in;
  wire gt3_txresetdone_out;
  wire gt3_txresetdone_r2_reg_srl2_n_0;
  wire gt3_txresetdone_r3;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_tx_reset_i;
  wire gt_txresetfsm_i_n_5;
  wire gt_txuserrdy_i;
  wire init_clk_in;
  wire sync_clk;
  wire txfsm_txresetdone_i__0;
  wire txfsm_txresetdone_r;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_multi_gt efex_aurora_hub2_multi_gt_i
       (.DRPADDR_IN(DRPADDR_IN),
        .DRPADDR_IN_LANE1(DRPADDR_IN_LANE1),
        .DRPADDR_IN_LANE2(DRPADDR_IN_LANE2),
        .DRPADDR_IN_LANE3(DRPADDR_IN_LANE3),
        .DRPDI_IN(DRPDI_IN),
        .DRPDI_IN_LANE1(DRPDI_IN_LANE1),
        .DRPDI_IN_LANE2(DRPDI_IN_LANE2),
        .DRPDI_IN_LANE3(DRPDI_IN_LANE3),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPDO_OUT_LANE1(DRPDO_OUT_LANE1),
        .DRPDO_OUT_LANE2(DRPDO_OUT_LANE2),
        .DRPDO_OUT_LANE3(DRPDO_OUT_LANE3),
        .DRPEN_IN(DRPEN_IN),
        .DRPEN_IN_LANE1(DRPEN_IN_LANE1),
        .DRPEN_IN_LANE2(DRPEN_IN_LANE2),
        .DRPEN_IN_LANE3(DRPEN_IN_LANE3),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPRDY_OUT_LANE1(DRPRDY_OUT_LANE1),
        .DRPRDY_OUT_LANE2(DRPRDY_OUT_LANE2),
        .DRPRDY_OUT_LANE3(DRPRDY_OUT_LANE3),
        .DRPWE_IN(DRPWE_IN),
        .DRPWE_IN_LANE1(DRPWE_IN_LANE1),
        .DRPWE_IN_LANE2(DRPWE_IN_LANE2),
        .DRPWE_IN_LANE3(DRPWE_IN_LANE3),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .ENABLE_ERR_DETECT_0(ENABLE_ERR_DETECT_0),
        .ENABLE_ERR_DETECT_1(ENABLE_ERR_DETECT_1),
        .ENABLE_ERR_DETECT_2(ENABLE_ERR_DETECT_2),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg),
        .ENABLE_ERR_DETECT_Buffer_reg_0(ENABLE_ERR_DETECT_Buffer_reg_0),
        .ENABLE_ERR_DETECT_Buffer_reg_1(ENABLE_ERR_DETECT_Buffer_reg_1),
        .ENABLE_ERR_DETECT_Buffer_reg_2(ENABLE_ERR_DETECT_Buffer_reg_2),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .TXCHARISK(TXCHARISK),
        .TXDATA(TXDATA),
        .TXN(TXN),
        .TXP(TXP),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .flag2_reg(gt_txresetfsm_i_n_5),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_txbufstatus_out(gt0_txbufstatus_out),
        .gt0_txchardispmode_in(gt0_txchardispmode_in),
        .gt0_txchardispval_in(gt0_txchardispval_in),
        .gt0_txdiffctrl_in(gt0_txdiffctrl_in),
        .gt0_txinhibit_in(gt0_txinhibit_in),
        .gt0_txmaincursor_in(gt0_txmaincursor_in),
        .gt0_txpcsreset_in(gt0_txpcsreset_in),
        .gt0_txpmareset_in(gt0_txpmareset_in),
        .gt0_txpolarity_in(gt0_txpolarity_in),
        .gt0_txpostcursor_in(gt0_txpostcursor_in),
        .gt0_txprbsforceerr_in(gt0_txprbsforceerr_in),
        .gt0_txprbssel_in(gt0_txprbssel_in),
        .gt0_txprecursor_in(gt0_txprecursor_in),
        .gt0_txresetdone_out(gt0_txresetdone_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_cplllock_out_0(gt1_cplllock_out_0),
        .gt1_cplllock_out_1(gt1_cplllock_out_1),
        .gt1_txbufstatus_out(gt1_txbufstatus_out),
        .gt1_txchardispmode_in(gt1_txchardispmode_in),
        .gt1_txchardispval_in(gt1_txchardispval_in),
        .gt1_txdiffctrl_in(gt1_txdiffctrl_in),
        .gt1_txinhibit_in(gt1_txinhibit_in),
        .gt1_txmaincursor_in(gt1_txmaincursor_in),
        .gt1_txpcsreset_in(gt1_txpcsreset_in),
        .gt1_txpmareset_in(gt1_txpmareset_in),
        .gt1_txpolarity_in(gt1_txpolarity_in),
        .gt1_txpostcursor_in(gt1_txpostcursor_in),
        .gt1_txprbsforceerr_in(gt1_txprbsforceerr_in),
        .gt1_txprbssel_in(gt1_txprbssel_in),
        .gt1_txprecursor_in(gt1_txprecursor_in),
        .gt1_txresetdone_out(gt1_txresetdone_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_cplllock_out_0(gt2_cplllock_out_0),
        .gt2_cplllock_out_1(gt2_cplllock_out_1),
        .gt2_txbufstatus_out(gt2_txbufstatus_out),
        .gt2_txchardispmode_in(gt2_txchardispmode_in),
        .gt2_txchardispval_in(gt2_txchardispval_in),
        .gt2_txdiffctrl_in(gt2_txdiffctrl_in),
        .gt2_txinhibit_in(gt2_txinhibit_in),
        .gt2_txmaincursor_in(gt2_txmaincursor_in),
        .gt2_txpcsreset_in(gt2_txpcsreset_in),
        .gt2_txpmareset_in(gt2_txpmareset_in),
        .gt2_txpolarity_in(gt2_txpolarity_in),
        .gt2_txpostcursor_in(gt2_txpostcursor_in),
        .gt2_txprbsforceerr_in(gt2_txprbsforceerr_in),
        .gt2_txprbssel_in(gt2_txprbssel_in),
        .gt2_txprecursor_in(gt2_txprecursor_in),
        .gt2_txresetdone_out(gt2_txresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_cplllock_out_0(gt3_cplllock_out_0),
        .gt3_cplllock_out_1(gt3_cplllock_out_1),
        .gt3_txbufstatus_out(gt3_txbufstatus_out),
        .gt3_txchardispmode_in(gt3_txchardispmode_in),
        .gt3_txchardispval_in(gt3_txchardispval_in),
        .gt3_txdiffctrl_in(gt3_txdiffctrl_in),
        .gt3_txinhibit_in(gt3_txinhibit_in),
        .gt3_txmaincursor_in(gt3_txmaincursor_in),
        .gt3_txpcsreset_in(gt3_txpcsreset_in),
        .gt3_txpmareset_in(gt3_txpmareset_in),
        .gt3_txpolarity_in(gt3_txpolarity_in),
        .gt3_txpostcursor_in(gt3_txpostcursor_in),
        .gt3_txprbsforceerr_in(gt3_txprbsforceerr_in),
        .gt3_txprbssel_in(gt3_txprbssel_in),
        .gt3_txprecursor_in(gt3_txprecursor_in),
        .gt3_txresetdone_out(gt3_txresetdone_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .gt_tx_reset_i(gt_tx_reset_i),
        .gt_txuserrdy_i(gt_txuserrdy_i),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .user_clk(user_clk));
  (* srl_name = "U0/\gt_wrapper_i/gt0_txresetdone_r2_reg_srl2 " *) 
  SRL16E gt0_txresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt0_txresetdone_out),
        .Q(gt0_txresetdone_r2_reg_srl2_n_0));
  FDRE gt0_txresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt0_txresetdone_r2_reg_srl2_n_0),
        .Q(gt0_txresetdone_r3),
        .R(1'b0));
  (* srl_name = "U0/\gt_wrapper_i/gt1_txresetdone_r2_reg_srl2 " *) 
  SRL16E gt1_txresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt1_txresetdone_out),
        .Q(gt1_txresetdone_r2_reg_srl2_n_0));
  FDRE gt1_txresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt1_txresetdone_r2_reg_srl2_n_0),
        .Q(gt1_txresetdone_r3),
        .R(1'b0));
  (* srl_name = "U0/\gt_wrapper_i/gt2_txresetdone_r2_reg_srl2 " *) 
  SRL16E gt2_txresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt2_txresetdone_out),
        .Q(gt2_txresetdone_r2_reg_srl2_n_0));
  FDRE gt2_txresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt2_txresetdone_r2_reg_srl2_n_0),
        .Q(gt2_txresetdone_r3),
        .R(1'b0));
  (* srl_name = "U0/\gt_wrapper_i/gt3_txresetdone_r2_reg_srl2 " *) 
  SRL16E gt3_txresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt3_txresetdone_out),
        .Q(gt3_txresetdone_r2_reg_srl2_n_0));
  FDRE gt3_txresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt3_txresetdone_r2_reg_srl2_n_0),
        .Q(gt3_txresetdone_r3),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    gt_pll_lock_i
       (.I0(gt3_cplllock_out),
        .I1(gt0_cplllock_out),
        .I2(gt1_cplllock_out),
        .I3(gt2_cplllock_out),
        .O(CPLLLOCK));
  efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm gt_txresetfsm_i
       (.AR(AR),
        .CPLL_RESET_reg_0(gt_txresetfsm_i_n_5),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ),
        .cpll_reset_i(cpll_reset_i),
        .gt_tx_reset_i(gt_tx_reset_i),
        .gt_txuserrdy_i(gt_txuserrdy_i),
        .in0(CPLLLOCK),
        .init_clk_in(init_clk_in),
        .out(TX_RESETDONE_OUT),
        .txfsm_txresetdone_r(txfsm_txresetdone_r),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2 gtrxreset_cdc_sync
       (.init_clk_in(init_clk_in),
        .user_clk(user_clk));
  LUT4 #(
    .INIT(16'h8000)) 
    txfsm_txresetdone_i
       (.I0(gt3_txresetdone_r3),
        .I1(gt0_txresetdone_r3),
        .I2(gt1_txresetdone_r3),
        .I3(gt2_txresetdone_r3),
        .O(txfsm_txresetdone_i__0));
  FDRE txfsm_txresetdone_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(txfsm_txresetdone_i__0),
        .Q(txfsm_txresetdone_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_IDLE_AND_VER_GEN" *) 
module efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN
   (gen_v_flop_0_i_0,
    gen_v_flop_2_i_0,
    gen_v_flop_4_i_0,
    gen_v_flop_6_i_0,
    GEN_A,
    gen_a_flop_1_i_0,
    gen_a_flop_2_i_0,
    gen_a_flop_3_i_0,
    gen_k_flop_0_i_0,
    gen_k_flop_2_i_0,
    gen_k_flop_4_i_0,
    gen_k_flop_6_i_0,
    gen_r_flop_0_i_0,
    gen_r_flop_2_i_0,
    gen_r_flop_4_i_0,
    gen_r_flop_6_i_0,
    RESET_SYMGEN,
    user_clk,
    gen_ver_i,
    tx_reset_simplex_r,
    \downcounter_r_reg[0]_0 );
  output [1:0]gen_v_flop_0_i_0;
  output [1:0]gen_v_flop_2_i_0;
  output [1:0]gen_v_flop_4_i_0;
  output [1:0]gen_v_flop_6_i_0;
  output GEN_A;
  output gen_a_flop_1_i_0;
  output gen_a_flop_2_i_0;
  output gen_a_flop_3_i_0;
  output [1:0]gen_k_flop_0_i_0;
  output [1:0]gen_k_flop_2_i_0;
  output [1:0]gen_k_flop_4_i_0;
  output [1:0]gen_k_flop_6_i_0;
  output [1:0]gen_r_flop_0_i_0;
  output [1:0]gen_r_flop_2_i_0;
  output [1:0]gen_r_flop_4_i_0;
  output [1:0]gen_r_flop_6_i_0;
  input RESET_SYMGEN;
  input user_clk;
  input gen_ver_i;
  input tx_reset_simplex_r;
  input \downcounter_r_reg[0]_0 ;

  wire D;
  wire D0_out;
  wire D1_out;
  wire D2_out;
  wire GEN_A;
  wire RESET_SYMGEN;
  wire \downcounter_r[0]_i_1_n_0 ;
  wire \downcounter_r[1]_i_1_n_0 ;
  wire \downcounter_r[2]_i_1_n_0 ;
  wire \downcounter_r[3]_i_1_n_0 ;
  wire \downcounter_r_reg[0]_0 ;
  wire \downcounter_r_reg_n_0_[0] ;
  wire \downcounter_r_reg_n_0_[1] ;
  wire \downcounter_r_reg_n_0_[2] ;
  wire \downcounter_r_reg_n_0_[3] ;
  wire gen_a_flop_1_i_0;
  wire gen_a_flop_2_i_0;
  wire gen_a_flop_3_i_0;
  wire [1:0]gen_k_flop_0_i_0;
  wire gen_k_flop_0_i_i_1_n_0;
  wire [1:0]gen_k_flop_2_i_0;
  wire [1:0]gen_k_flop_4_i_0;
  wire [1:0]gen_k_flop_6_i_0;
  wire [1:0]gen_r_flop_0_i_0;
  wire gen_r_flop_0_i_i_1_n_0;
  wire gen_r_flop_1_i_i_1_n_0;
  wire [1:0]gen_r_flop_2_i_0;
  wire [1:0]gen_r_flop_4_i_0;
  wire [1:0]gen_r_flop_6_i_0;
  wire [1:0]gen_v_flop_0_i_0;
  wire gen_v_flop_1_i_i_1_n_0;
  wire [1:0]gen_v_flop_2_i_0;
  wire [1:0]gen_v_flop_4_i_0;
  wire [1:0]gen_v_flop_6_i_0;
  wire gen_ver_i;
  wire gen_ver_word_2_r_reg_n_0;
  wire lfsr_last_flop_r;
  wire \lfsr_shift_register_r_reg[2]_srl3_n_0 ;
  wire lfsr_taps_i_i_1_n_0;
  wire lfsr_taps_r;
  wire prev_cycle_gen_ver_r;
  wire tx_reset_simplex_r;
  wire user_clk;
  wire ver_counter_r_0;
  wire ver_counter_r_1;

  LUT6 #(
    .INIT(64'h1010101010101001)) 
    \downcounter_r[0]_i_1 
       (.I0(tx_reset_simplex_r),
        .I1(\downcounter_r_reg[0]_0 ),
        .I2(\downcounter_r_reg_n_0_[0] ),
        .I3(\downcounter_r_reg_n_0_[2] ),
        .I4(\downcounter_r_reg_n_0_[1] ),
        .I5(\downcounter_r_reg_n_0_[3] ),
        .O(\downcounter_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F0C3F0C2)) 
    \downcounter_r[1]_i_1 
       (.I0(\downcounter_r_reg_n_0_[0] ),
        .I1(\downcounter_r_reg_n_0_[2] ),
        .I2(\downcounter_r_reg_n_0_[1] ),
        .I3(\downcounter_r_reg_n_0_[3] ),
        .I4(lfsr_taps_r),
        .I5(RESET_SYMGEN),
        .O(\downcounter_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CC33CC32)) 
    \downcounter_r[2]_i_1 
       (.I0(\downcounter_r_reg_n_0_[0] ),
        .I1(\downcounter_r_reg_n_0_[2] ),
        .I2(\downcounter_r_reg_n_0_[1] ),
        .I3(\downcounter_r_reg_n_0_[3] ),
        .I4(D),
        .I5(RESET_SYMGEN),
        .O(\downcounter_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \downcounter_r[3]_i_1 
       (.I0(\downcounter_r_reg_n_0_[3] ),
        .I1(RESET_SYMGEN),
        .I2(lfsr_last_flop_r),
        .I3(\downcounter_r_reg_n_0_[1] ),
        .I4(\downcounter_r_reg_n_0_[2] ),
        .I5(\downcounter_r_reg_n_0_[0] ),
        .O(\downcounter_r[3]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \downcounter_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\downcounter_r[0]_i_1_n_0 ),
        .Q(\downcounter_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \downcounter_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\downcounter_r[1]_i_1_n_0 ),
        .Q(\downcounter_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \downcounter_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\downcounter_r[2]_i_1_n_0 ),
        .Q(\downcounter_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \downcounter_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\downcounter_r[3]_i_1_n_0 ),
        .Q(\downcounter_r_reg_n_0_[3] ),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_a_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D2_out),
        .Q(GEN_A),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000001)) 
    gen_a_flop_0_i_i_1
       (.I0(\downcounter_r_reg_n_0_[3] ),
        .I1(\downcounter_r_reg_n_0_[1] ),
        .I2(\downcounter_r_reg_n_0_[2] ),
        .I3(\downcounter_r_reg_n_0_[0] ),
        .I4(ver_counter_r_0),
        .O(D2_out));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_a_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D2_out),
        .Q(gen_a_flop_1_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_a_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D2_out),
        .Q(gen_a_flop_2_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_a_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D2_out),
        .Q(gen_a_flop_3_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_flop_0_i_i_1_n_0),
        .Q(gen_k_flop_0_i_0[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAA8)) 
    gen_k_flop_0_i_i_1
       (.I0(lfsr_taps_r),
        .I1(\downcounter_r_reg_n_0_[0] ),
        .I2(\downcounter_r_reg_n_0_[2] ),
        .I3(\downcounter_r_reg_n_0_[1] ),
        .I4(\downcounter_r_reg_n_0_[3] ),
        .I5(ver_counter_r_0),
        .O(gen_k_flop_0_i_i_1_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(gen_k_flop_0_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_flop_0_i_i_1_n_0),
        .Q(gen_k_flop_2_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(gen_k_flop_2_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_4_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_flop_0_i_i_1_n_0),
        .Q(gen_k_flop_4_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_5_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(gen_k_flop_4_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_6_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_flop_0_i_i_1_n_0),
        .Q(gen_k_flop_6_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_k_flop_7_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(gen_k_flop_6_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_0_i_i_1_n_0),
        .Q(gen_r_flop_0_i_0[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    gen_r_flop_0_i_i_1
       (.I0(lfsr_taps_r),
        .I1(ver_counter_r_0),
        .I2(\downcounter_r_reg_n_0_[3] ),
        .I3(\downcounter_r_reg_n_0_[1] ),
        .I4(\downcounter_r_reg_n_0_[2] ),
        .I5(\downcounter_r_reg_n_0_[0] ),
        .O(gen_r_flop_0_i_i_1_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_1_i_i_1_n_0),
        .Q(gen_r_flop_0_i_0[0]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT1 #(
    .INIT(2'h1)) 
    gen_r_flop_1_i_i_1
       (.I0(D),
        .O(gen_r_flop_1_i_i_1_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_0_i_i_1_n_0),
        .Q(gen_r_flop_2_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_1_i_i_1_n_0),
        .Q(gen_r_flop_2_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_4_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_0_i_i_1_n_0),
        .Q(gen_r_flop_4_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_5_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_1_i_i_1_n_0),
        .Q(gen_r_flop_4_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_6_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_0_i_i_1_n_0),
        .Q(gen_r_flop_6_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_r_flop_7_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_r_flop_1_i_i_1_n_0),
        .Q(gen_r_flop_6_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D1_out),
        .Q(gen_v_flop_0_i_0[1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    gen_v_flop_0_i_i_1
       (.I0(gen_ver_word_2_r_reg_n_0),
        .I1(gen_ver_i),
        .O(D1_out));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_v_flop_1_i_i_1_n_0),
        .Q(gen_v_flop_0_i_0[0]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hC8)) 
    gen_v_flop_1_i_i_1
       (.I0(ver_counter_r_0),
        .I1(gen_ver_i),
        .I2(gen_ver_word_2_r_reg_n_0),
        .O(gen_v_flop_1_i_i_1_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D1_out),
        .Q(gen_v_flop_2_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_v_flop_1_i_i_1_n_0),
        .Q(gen_v_flop_2_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_4_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D1_out),
        .Q(gen_v_flop_4_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_5_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_v_flop_1_i_i_1_n_0),
        .Q(gen_v_flop_4_i_0[0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_6_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D1_out),
        .Q(gen_v_flop_6_i_0[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_v_flop_7_i
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_v_flop_1_i_i_1_n_0),
        .Q(gen_v_flop_6_i_0[0]),
        .R(1'b0));
  FDRE gen_ver_word_2_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ver_counter_r_0),
        .Q(gen_ver_word_2_r_reg_n_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lfsr_last_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(lfsr_last_flop_r),
        .R(RESET_SYMGEN));
  (* srl_bus_name = "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/lfsr_shift_register_r_reg " *) 
  (* srl_name = "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/lfsr_shift_register_r_reg[2]_srl3 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \lfsr_shift_register_r_reg[2]_srl3 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(lfsr_taps_r),
        .Q(\lfsr_shift_register_r_reg[2]_srl3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \lfsr_shift_register_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\lfsr_shift_register_r_reg[2]_srl3_n_0 ),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lfsr_taps_i
       (.C(user_clk),
        .CE(1'b1),
        .D(lfsr_taps_i_i_1_n_0),
        .Q(lfsr_taps_r),
        .R(RESET_SYMGEN));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h9)) 
    lfsr_taps_i_i_1
       (.I0(lfsr_last_flop_r),
        .I1(D),
        .O(lfsr_taps_i_i_1_n_0));
  FDRE prev_cycle_gen_ver_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_ver_i),
        .Q(prev_cycle_gen_ver_r),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "SRL16" *) 
  (* srl_name = "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/ver_counter_0_i " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    ver_counter_0_i
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(user_clk),
        .D(D0_out),
        .Q(ver_counter_r_1));
  LUT3 #(
    .INIT(8'hB0)) 
    ver_counter_0_i_i_1
       (.I0(gen_ver_word_2_r_reg_n_0),
        .I1(prev_cycle_gen_ver_r),
        .I2(gen_ver_i),
        .O(D0_out));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "SRL16" *) 
  (* srl_name = "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/ver_counter_1_i " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    ver_counter_1_i
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(user_clk),
        .D(ver_counter_r_1),
        .Q(ver_counter_r_0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_RESET_LOGIC" *) 
module efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC
   (SYSTEM_RESET_reg_0,
    wait_for_lane_up_r0,
    new_pkt_r,
    RESET_SYMGEN,
    out,
    init_clk_in,
    user_clk,
    TX_LOCK,
    gt_txresetdone_r2_reg_0,
    tx_reset_simplex_r,
    reset_channel_i,
    TX_CHANNEL_UP,
    S_AXI_TX_TLAST,
    S_AXI_TX_TVALID,
    tx_dst_rdy,
    new_pkt_r_reg);
  output SYSTEM_RESET_reg_0;
  output wait_for_lane_up_r0;
  output new_pkt_r;
  output RESET_SYMGEN;
  input out;
  input init_clk_in;
  input user_clk;
  input TX_LOCK;
  input gt_txresetdone_r2_reg_0;
  input tx_reset_simplex_r;
  input reset_channel_i;
  input TX_CHANNEL_UP;
  input S_AXI_TX_TLAST;
  input S_AXI_TX_TVALID;
  input tx_dst_rdy;
  input new_pkt_r_reg;

  wire RESET_SYMGEN;
  wire SYSTEM_RESET0_n_0;
  wire SYSTEM_RESET_reg_0;
  wire S_AXI_TX_TLAST;
  wire S_AXI_TX_TVALID;
  wire TX_CHANNEL_UP;
  wire TX_LOCK;
  wire gt_txresetdone_r;
  wire gt_txresetdone_r2;
  wire gt_txresetdone_r2_reg_0;
  wire gt_txresetdone_r3;
  wire init_clk_in;
  wire new_pkt_r;
  wire new_pkt_r_reg;
  wire out;
  wire reset_channel_i;
  wire scndry_out;
  wire tx_dst_rdy;
  wire tx_lock_comb_r;
  wire tx_lock_sync;
  wire tx_reset_simplex_r;
  wire user_clk;
  wire wait_for_lane_up_r0;

  LUT4 #(
    .INIT(16'hFFDF)) 
    SYSTEM_RESET0
       (.I0(tx_lock_sync),
        .I1(out),
        .I2(gt_txresetdone_r3),
        .I3(scndry_out),
        .O(SYSTEM_RESET0_n_0));
  FDRE SYSTEM_RESET_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SYSTEM_RESET0_n_0),
        .Q(SYSTEM_RESET_reg_0),
        .R(1'b0));
  FDCE gt_txresetdone_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(gt_txresetdone_r2_reg_0),
        .D(gt_txresetdone_r),
        .Q(gt_txresetdone_r2));
  FDRE gt_txresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt_txresetdone_r2),
        .Q(gt_txresetdone_r3),
        .R(1'b0));
  FDCE gt_txresetdone_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(gt_txresetdone_r2_reg_0),
        .D(1'b1),
        .Q(gt_txresetdone_r));
  LUT2 #(
    .INIT(4'hE)) 
    lfsr_last_flop_i_i_1
       (.I0(tx_reset_simplex_r),
        .I1(SYSTEM_RESET_reg_0),
        .O(RESET_SYMGEN));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23 link_reset_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(scndry_out),
        .user_clk(user_clk));
  LUT6 #(
    .INIT(64'h4444044400000400)) 
    new_pkt_r_i_1
       (.I0(RESET_SYMGEN),
        .I1(TX_CHANNEL_UP),
        .I2(S_AXI_TX_TLAST),
        .I3(S_AXI_TX_TVALID),
        .I4(tx_dst_rdy),
        .I5(new_pkt_r_reg),
        .O(new_pkt_r));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24 tx_lock_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(tx_lock_sync),
        .tx_lock_comb_r(tx_lock_comb_r),
        .user_clk(user_clk));
  FDRE tx_lock_comb_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(TX_LOCK),
        .Q(tx_lock_comb_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    wait_for_lane_up_r_i_1
       (.I0(SYSTEM_RESET_reg_0),
        .I1(tx_reset_simplex_r),
        .I2(reset_channel_i),
        .O(wait_for_lane_up_r0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_STANDARD_CC_MODULE" *) 
module efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE
   (WARN_CC,
    DO_CC_I,
    next_ufc_idle_c,
    next_ufc_header_c,
    DO_CC_reg_0,
    user_clk,
    ufc_idle_r_reg,
    S_AXI_UFC_TX_REQ);
  output WARN_CC;
  output DO_CC_I;
  output next_ufc_idle_c;
  output next_ufc_header_c;
  input DO_CC_reg_0;
  input user_clk;
  input ufc_idle_r_reg;
  input S_AXI_UFC_TX_REQ;

  wire DO_CC_I;
  wire DO_CC_i_1_n_0;
  wire DO_CC_i_2_n_0;
  wire DO_CC_reg_0;
  wire S_AXI_UFC_TX_REQ;
  wire WARN_CC;
  wire WARN_CC_i_1_n_0;
  wire [5:5]cc_count_r;
  wire cc_idle_count_done_c;
  wire count_13d_flop_r_reg_r_n_0;
  wire \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ;
  wire \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ;
  wire \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ;
  wire count_13d_srl_r_reg_gate_n_0;
  wire count_13d_srl_r_reg_r_0_n_0;
  wire count_13d_srl_r_reg_r_1_n_0;
  wire count_13d_srl_r_reg_r_2_n_0;
  wire count_13d_srl_r_reg_r_3_n_0;
  wire count_13d_srl_r_reg_r_4_n_0;
  wire count_13d_srl_r_reg_r_5_n_0;
  wire count_13d_srl_r_reg_r_6_n_0;
  wire count_13d_srl_r_reg_r_7_n_0;
  wire count_13d_srl_r_reg_r_8_n_0;
  wire count_13d_srl_r_reg_r_9_n_0;
  wire count_13d_srl_r_reg_r_n_0;
  wire count_16d_flop_r;
  wire count_16d_flop_r_i_1_n_0;
  wire count_16d_srl_r0;
  wire \count_16d_srl_r_reg_n_0_[0] ;
  wire \count_16d_srl_r_reg_n_0_[10] ;
  wire \count_16d_srl_r_reg_n_0_[11] ;
  wire \count_16d_srl_r_reg_n_0_[12] ;
  wire \count_16d_srl_r_reg_n_0_[13] ;
  wire \count_16d_srl_r_reg_n_0_[14] ;
  wire \count_16d_srl_r_reg_n_0_[1] ;
  wire \count_16d_srl_r_reg_n_0_[2] ;
  wire \count_16d_srl_r_reg_n_0_[3] ;
  wire \count_16d_srl_r_reg_n_0_[4] ;
  wire \count_16d_srl_r_reg_n_0_[5] ;
  wire \count_16d_srl_r_reg_n_0_[6] ;
  wire \count_16d_srl_r_reg_n_0_[7] ;
  wire \count_16d_srl_r_reg_n_0_[8] ;
  wire \count_16d_srl_r_reg_n_0_[9] ;
  wire count_24d_flop_r;
  wire count_24d_flop_r_i_1_n_0;
  wire count_24d_srl_r0;
  wire \count_24d_srl_r_reg_n_0_[0] ;
  wire \count_24d_srl_r_reg_n_0_[10] ;
  wire \count_24d_srl_r_reg_n_0_[11] ;
  wire \count_24d_srl_r_reg_n_0_[12] ;
  wire \count_24d_srl_r_reg_n_0_[13] ;
  wire \count_24d_srl_r_reg_n_0_[14] ;
  wire \count_24d_srl_r_reg_n_0_[15] ;
  wire \count_24d_srl_r_reg_n_0_[16] ;
  wire \count_24d_srl_r_reg_n_0_[17] ;
  wire \count_24d_srl_r_reg_n_0_[18] ;
  wire \count_24d_srl_r_reg_n_0_[19] ;
  wire \count_24d_srl_r_reg_n_0_[1] ;
  wire \count_24d_srl_r_reg_n_0_[20] ;
  wire \count_24d_srl_r_reg_n_0_[21] ;
  wire \count_24d_srl_r_reg_n_0_[22] ;
  wire \count_24d_srl_r_reg_n_0_[2] ;
  wire \count_24d_srl_r_reg_n_0_[3] ;
  wire \count_24d_srl_r_reg_n_0_[4] ;
  wire \count_24d_srl_r_reg_n_0_[5] ;
  wire \count_24d_srl_r_reg_n_0_[6] ;
  wire \count_24d_srl_r_reg_n_0_[7] ;
  wire \count_24d_srl_r_reg_n_0_[8] ;
  wire \count_24d_srl_r_reg_n_0_[9] ;
  wire next_ufc_header_c;
  wire next_ufc_idle_c;
  wire [4:0]p_2_in;
  wire [5:5]p_3_out;
  wire \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_n_0 ;
  wire \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0_n_0 ;
  wire prepare_count_r_reg_gate_n_0;
  wire reset_r;
  wire ufc_idle_r_reg;
  wire user_clk;

  LUT4 #(
    .INIT(16'hFFFE)) 
    DO_CC_i_1
       (.I0(cc_count_r),
        .I1(p_2_in[0]),
        .I2(p_2_in[1]),
        .I3(DO_CC_i_2_n_0),
        .O(DO_CC_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF2)) 
    DO_CC_i_2
       (.I0(reset_r),
        .I1(DO_CC_reg_0),
        .I2(p_2_in[4]),
        .I3(p_3_out),
        .I4(p_2_in[3]),
        .I5(p_2_in[2]),
        .O(DO_CC_i_2_n_0));
  FDRE DO_CC_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(DO_CC_i_1_n_0),
        .Q(DO_CC_I),
        .R(DO_CC_reg_0));
  LUT5 #(
    .INIT(32'h80FF8080)) 
    WARN_CC_i_1
       (.I0(\count_24d_srl_r_reg_n_0_[22] ),
        .I1(\count_16d_srl_r_reg_n_0_[14] ),
        .I2(count_16d_srl_r0),
        .I3(p_3_out),
        .I4(WARN_CC),
        .O(WARN_CC_i_1_n_0));
  FDRE WARN_CC_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(WARN_CC_i_1_n_0),
        .Q(WARN_CC),
        .R(DO_CC_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \cc_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out),
        .Q(p_2_in[4]),
        .R(DO_CC_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \cc_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_2_in[4]),
        .Q(p_2_in[3]),
        .R(DO_CC_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \cc_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_2_in[3]),
        .Q(p_2_in[2]),
        .R(DO_CC_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \cc_count_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_2_in[2]),
        .Q(p_2_in[1]),
        .R(DO_CC_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \cc_count_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_2_in[1]),
        .Q(p_2_in[0]),
        .R(DO_CC_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \cc_count_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_2_in[0]),
        .Q(cc_count_r),
        .R(DO_CC_reg_0));
  FDRE count_13d_flop_r_reg_r
       (.C(user_clk),
        .CE(1'b1),
        .D(1'b1),
        .Q(count_13d_flop_r_reg_r_n_0),
        .R(DO_CC_reg_0));
  FDRE \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ),
        .Q(\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ),
        .R(1'b0));
  FDRE \count_13d_srl_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_gate_n_0),
        .Q(count_16d_srl_r0),
        .R(DO_CC_reg_0));
  (* srl_bus_name = "U0/\standard_cc_module_i/count_13d_srl_r_reg " *) 
  (* srl_name = "U0/\standard_cc_module_i/count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8 " *) 
  SRL16E \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ),
        .Q(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1 
       (.I0(count_16d_srl_r0),
        .I1(reset_r),
        .O(\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    count_13d_srl_r_reg_gate
       (.I0(\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0 ),
        .I1(count_13d_srl_r_reg_r_9_n_0),
        .O(count_13d_srl_r_reg_gate_n_0));
  FDRE count_13d_srl_r_reg_r
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_flop_r_reg_r_n_0),
        .Q(count_13d_srl_r_reg_r_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_0
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_n_0),
        .Q(count_13d_srl_r_reg_r_0_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_1
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_0_n_0),
        .Q(count_13d_srl_r_reg_r_1_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_2
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_1_n_0),
        .Q(count_13d_srl_r_reg_r_2_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_3
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_2_n_0),
        .Q(count_13d_srl_r_reg_r_3_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_4
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_3_n_0),
        .Q(count_13d_srl_r_reg_r_4_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_5
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_4_n_0),
        .Q(count_13d_srl_r_reg_r_5_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_6
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_5_n_0),
        .Q(count_13d_srl_r_reg_r_6_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_7
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_6_n_0),
        .Q(count_13d_srl_r_reg_r_7_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_8
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_7_n_0),
        .Q(count_13d_srl_r_reg_r_8_n_0),
        .R(DO_CC_reg_0));
  FDRE count_13d_srl_r_reg_r_9
       (.C(user_clk),
        .CE(1'b1),
        .D(count_13d_srl_r_reg_r_8_n_0),
        .Q(count_13d_srl_r_reg_r_9_n_0),
        .R(DO_CC_reg_0));
  LUT4 #(
    .INIT(16'hFBF8)) 
    count_16d_flop_r_i_1
       (.I0(\count_16d_srl_r_reg_n_0_[14] ),
        .I1(count_16d_srl_r0),
        .I2(reset_r),
        .I3(count_16d_flop_r),
        .O(count_16d_flop_r_i_1_n_0));
  FDRE count_16d_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(count_16d_flop_r_i_1_n_0),
        .Q(count_16d_flop_r),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[0] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(count_16d_flop_r),
        .Q(\count_16d_srl_r_reg_n_0_[0] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[10] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[9] ),
        .Q(\count_16d_srl_r_reg_n_0_[10] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[11] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[10] ),
        .Q(\count_16d_srl_r_reg_n_0_[11] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[12] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[11] ),
        .Q(\count_16d_srl_r_reg_n_0_[12] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[13] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[12] ),
        .Q(\count_16d_srl_r_reg_n_0_[13] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[14] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[13] ),
        .Q(\count_16d_srl_r_reg_n_0_[14] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[1] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[0] ),
        .Q(\count_16d_srl_r_reg_n_0_[1] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[2] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[1] ),
        .Q(\count_16d_srl_r_reg_n_0_[2] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[3] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[2] ),
        .Q(\count_16d_srl_r_reg_n_0_[3] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[4] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[3] ),
        .Q(\count_16d_srl_r_reg_n_0_[4] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[5] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[4] ),
        .Q(\count_16d_srl_r_reg_n_0_[5] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[6] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[5] ),
        .Q(\count_16d_srl_r_reg_n_0_[6] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[7] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[6] ),
        .Q(\count_16d_srl_r_reg_n_0_[7] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[8] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[7] ),
        .Q(\count_16d_srl_r_reg_n_0_[8] ),
        .R(DO_CC_reg_0));
  FDRE \count_16d_srl_r_reg[9] 
       (.C(user_clk),
        .CE(count_16d_srl_r0),
        .D(\count_16d_srl_r_reg_n_0_[8] ),
        .Q(\count_16d_srl_r_reg_n_0_[9] ),
        .R(DO_CC_reg_0));
  LUT5 #(
    .INIT(32'hFFBFFF80)) 
    count_24d_flop_r_i_1
       (.I0(\count_24d_srl_r_reg_n_0_[22] ),
        .I1(count_16d_srl_r0),
        .I2(\count_16d_srl_r_reg_n_0_[14] ),
        .I3(reset_r),
        .I4(count_24d_flop_r),
        .O(count_24d_flop_r_i_1_n_0));
  FDRE count_24d_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(count_24d_flop_r_i_1_n_0),
        .Q(count_24d_flop_r),
        .R(DO_CC_reg_0));
  LUT2 #(
    .INIT(4'h8)) 
    \count_24d_srl_r[0]_i_1 
       (.I0(count_16d_srl_r0),
        .I1(\count_16d_srl_r_reg_n_0_[14] ),
        .O(count_24d_srl_r0));
  FDRE \count_24d_srl_r_reg[0] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(count_24d_flop_r),
        .Q(\count_24d_srl_r_reg_n_0_[0] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[10] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[9] ),
        .Q(\count_24d_srl_r_reg_n_0_[10] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[11] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[10] ),
        .Q(\count_24d_srl_r_reg_n_0_[11] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[12] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[11] ),
        .Q(\count_24d_srl_r_reg_n_0_[12] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[13] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[12] ),
        .Q(\count_24d_srl_r_reg_n_0_[13] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[14] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[13] ),
        .Q(\count_24d_srl_r_reg_n_0_[14] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[15] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[14] ),
        .Q(\count_24d_srl_r_reg_n_0_[15] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[16] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[15] ),
        .Q(\count_24d_srl_r_reg_n_0_[16] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[17] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[16] ),
        .Q(\count_24d_srl_r_reg_n_0_[17] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[18] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[17] ),
        .Q(\count_24d_srl_r_reg_n_0_[18] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[19] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[18] ),
        .Q(\count_24d_srl_r_reg_n_0_[19] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[1] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[0] ),
        .Q(\count_24d_srl_r_reg_n_0_[1] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[20] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[19] ),
        .Q(\count_24d_srl_r_reg_n_0_[20] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[21] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[20] ),
        .Q(\count_24d_srl_r_reg_n_0_[21] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[22] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[21] ),
        .Q(\count_24d_srl_r_reg_n_0_[22] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[2] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[1] ),
        .Q(\count_24d_srl_r_reg_n_0_[2] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[3] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[2] ),
        .Q(\count_24d_srl_r_reg_n_0_[3] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[4] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[3] ),
        .Q(\count_24d_srl_r_reg_n_0_[4] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[5] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[4] ),
        .Q(\count_24d_srl_r_reg_n_0_[5] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[6] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[5] ),
        .Q(\count_24d_srl_r_reg_n_0_[6] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[7] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[6] ),
        .Q(\count_24d_srl_r_reg_n_0_[7] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[8] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[7] ),
        .Q(\count_24d_srl_r_reg_n_0_[8] ),
        .R(DO_CC_reg_0));
  FDRE \count_24d_srl_r_reg[9] 
       (.C(user_clk),
        .CE(count_24d_srl_r0),
        .D(\count_24d_srl_r_reg_n_0_[8] ),
        .Q(\count_24d_srl_r_reg_n_0_[9] ),
        .R(DO_CC_reg_0));
  (* srl_bus_name = "U0/\standard_cc_module_i/prepare_count_r_reg " *) 
  (* srl_name = "U0/\standard_cc_module_i/prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(cc_idle_count_done_c),
        .Q(\prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_i_1 
       (.I0(count_16d_srl_r0),
        .I1(\count_16d_srl_r_reg_n_0_[14] ),
        .I2(\count_24d_srl_r_reg_n_0_[22] ),
        .O(cc_idle_count_done_c));
  FDRE \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0 
       (.C(user_clk),
        .CE(1'b1),
        .D(\prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_n_0 ),
        .Q(\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0_n_0 ),
        .R(1'b0));
  FDRE \prepare_count_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(prepare_count_r_reg_gate_n_0),
        .Q(p_3_out),
        .R(DO_CC_reg_0));
  LUT2 #(
    .INIT(4'h8)) 
    prepare_count_r_reg_gate
       (.I0(\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0_n_0 ),
        .I1(count_13d_srl_r_reg_r_0_n_0),
        .O(prepare_count_r_reg_gate_n_0));
  FDRE reset_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(DO_CC_reg_0),
        .Q(reset_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0200)) 
    ufc_header_r_i_2
       (.I0(ufc_idle_r_reg),
        .I1(DO_CC_I),
        .I2(WARN_CC),
        .I3(S_AXI_UFC_TX_REQ),
        .O(next_ufc_header_c));
  LUT4 #(
    .INIT(16'hA8AA)) 
    ufc_idle_r_i_1
       (.I0(ufc_idle_r_reg),
        .I1(DO_CC_I),
        .I2(WARN_CC),
        .I3(S_AXI_UFC_TX_REQ),
        .O(next_ufc_idle_c));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_SYM_GEN" *) 
module efex_aurora_hub2_efex_aurora_hub2_SYM_GEN
   (\TX_CHAR_IS_K_Buffer_reg[0]_0 ,
    \TX_DATA_Buffer_reg[7]_0 ,
    Q,
    user_clk,
    tx_pe_data_v_r_reg_0,
    gen_k_fsm_r_reg_0,
    gen_cc_r_reg_0,
    gen_ecp_i,
    gen_a_r_reg_0,
    D,
    \gen_v_r_reg[0]_0 ,
    \gen_r_r_reg[0]_0 ,
    \gen_k_r_reg[0]_0 ,
    \tx_pe_data_r_reg[0]_0 );
  output [1:0]\TX_CHAR_IS_K_Buffer_reg[0]_0 ;
  output [15:0]\TX_DATA_Buffer_reg[7]_0 ;
  input [0:0]Q;
  input user_clk;
  input [0:0]tx_pe_data_v_r_reg_0;
  input gen_k_fsm_r_reg_0;
  input gen_cc_r_reg_0;
  input gen_ecp_i;
  input gen_a_r_reg_0;
  input [1:0]D;
  input [1:0]\gen_v_r_reg[0]_0 ;
  input [1:0]\gen_r_r_reg[0]_0 ;
  input [1:0]\gen_k_r_reg[0]_0 ;
  input [15:0]\tx_pe_data_r_reg[0]_0 ;

  wire [1:0]D;
  wire [0:0]Q;
  wire TX_CHAR_IS_K_Buffer_reg0;
  wire TX_CHAR_IS_K_Buffer_reg04_out;
  wire [1:0]\TX_CHAR_IS_K_Buffer_reg[0]_0 ;
  wire \TX_DATA_Buffer[0]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[10]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[11]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[12]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[12]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[13]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[13]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[13]_i_3__0_n_0 ;
  wire \TX_DATA_Buffer[14]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[14]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[14]_i_3__0_n_0 ;
  wire \TX_DATA_Buffer[15]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[15]_i_3__2_n_0 ;
  wire \TX_DATA_Buffer[15]_i_4__2_n_0 ;
  wire \TX_DATA_Buffer[15]_i_5__0_n_0 ;
  wire \TX_DATA_Buffer[1]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[2]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[3]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[4]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[4]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[4]_i_3__0_n_0 ;
  wire \TX_DATA_Buffer[5]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[6]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[6]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[7]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[7]_i_2__2_n_0 ;
  wire \TX_DATA_Buffer[7]_i_3__2_n_0 ;
  wire \TX_DATA_Buffer[7]_i_4__0_n_0 ;
  wire \TX_DATA_Buffer[8]_i_1__2_n_0 ;
  wire \TX_DATA_Buffer[9]_i_1__2_n_0 ;
  wire TX_DATA_Buffer_reg0;
  wire [15:0]\TX_DATA_Buffer_reg[7]_0 ;
  wire [7:0]data0;
  wire gen_a_r;
  wire gen_a_r_reg_0;
  wire gen_cc_r;
  wire gen_cc_r_reg_0;
  wire gen_ecp_i;
  wire gen_ecp_r;
  wire gen_k_fsm_r;
  wire gen_k_fsm_r_reg_0;
  wire [1:0]\gen_k_r_reg[0]_0 ;
  wire \gen_k_r_reg_n_0_[1] ;
  wire gen_pad_r;
  wire [1:0]\gen_r_r_reg[0]_0 ;
  wire \gen_r_r_reg_n_0_[1] ;
  wire \gen_sp_data_r_reg_n_0_[1] ;
  wire [1:0]\gen_v_r_reg[0]_0 ;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_0_in4_in;
  wire p_2_in;
  wire p_3_in;
  wire [15:0]\tx_pe_data_r_reg[0]_0 ;
  wire \tx_pe_data_r_reg_n_0_[10] ;
  wire \tx_pe_data_r_reg_n_0_[11] ;
  wire \tx_pe_data_r_reg_n_0_[12] ;
  wire \tx_pe_data_r_reg_n_0_[13] ;
  wire \tx_pe_data_r_reg_n_0_[14] ;
  wire \tx_pe_data_r_reg_n_0_[15] ;
  wire \tx_pe_data_r_reg_n_0_[8] ;
  wire \tx_pe_data_r_reg_n_0_[9] ;
  wire tx_pe_data_v_r;
  wire [0:0]tx_pe_data_v_r_reg_0;
  wire user_clk;

  LUT5 #(
    .INIT(32'hCCCFCCCD)) 
    \TX_CHAR_IS_K_Buffer[0]_i_1__2 
       (.I0(tx_pe_data_v_r),
        .I1(gen_cc_r),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(gen_pad_r),
        .O(TX_CHAR_IS_K_Buffer_reg0));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \TX_CHAR_IS_K_Buffer[1]_i_1__2 
       (.I0(gen_cc_r),
        .I1(p_2_in),
        .I2(p_0_in1_in),
        .I3(tx_pe_data_v_r),
        .O(TX_CHAR_IS_K_Buffer_reg04_out));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg0),
        .Q(\TX_CHAR_IS_K_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg04_out),
        .Q(\TX_CHAR_IS_K_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00002E22)) 
    \TX_DATA_Buffer[0]_i_1__2 
       (.I0(gen_cc_r),
        .I1(tx_pe_data_v_r),
        .I2(gen_pad_r),
        .I3(\tx_pe_data_r_reg_n_0_[15] ),
        .I4(gen_ecp_r),
        .O(\TX_DATA_Buffer[0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_DATA_Buffer[10]_i_1__2 
       (.I0(tx_pe_data_v_r),
        .I1(data0[2]),
        .I2(\TX_DATA_Buffer[12]_i_2__2_n_0 ),
        .O(\TX_DATA_Buffer[10]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAFAEAFAF)) 
    \TX_DATA_Buffer[11]_i_1__2 
       (.I0(gen_ecp_r),
        .I1(data0[3]),
        .I2(gen_cc_r),
        .I3(gen_k_fsm_r),
        .I4(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[11]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_DATA_Buffer[12]_i_1__2 
       (.I0(tx_pe_data_v_r),
        .I1(data0[4]),
        .I2(\TX_DATA_Buffer[12]_i_2__2_n_0 ),
        .O(\TX_DATA_Buffer[12]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF11111110)) 
    \TX_DATA_Buffer[12]_i_2__2 
       (.I0(\TX_DATA_Buffer[15]_i_4__2_n_0 ),
        .I1(p_2_in),
        .I2(p_0_in4_in),
        .I3(gen_a_r),
        .I4(p_0_in),
        .I5(\TX_DATA_Buffer[15]_i_3__2_n_0 ),
        .O(\TX_DATA_Buffer[12]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFCF0FCFAFCF0FCFF)) 
    \TX_DATA_Buffer[13]_i_1__2 
       (.I0(\TX_DATA_Buffer[13]_i_2__2_n_0 ),
        .I1(data0[5]),
        .I2(\TX_DATA_Buffer[13]_i_3__0_n_0 ),
        .I3(tx_pe_data_v_r),
        .I4(p_0_in1_in),
        .I5(p_0_in),
        .O(\TX_DATA_Buffer[13]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_DATA_Buffer[13]_i_2__2 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .O(\TX_DATA_Buffer[13]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF10)) 
    \TX_DATA_Buffer[13]_i_3__0 
       (.I0(p_0_in1_in),
        .I1(tx_pe_data_v_r),
        .I2(p_2_in),
        .I3(gen_k_fsm_r),
        .I4(gen_cc_r),
        .I5(gen_ecp_r),
        .O(\TX_DATA_Buffer[13]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEEEEFEEE)) 
    \TX_DATA_Buffer[14]_i_1__2 
       (.I0(gen_cc_r),
        .I1(gen_ecp_r),
        .I2(data0[6]),
        .I3(tx_pe_data_v_r),
        .I4(gen_k_fsm_r),
        .I5(\TX_DATA_Buffer[14]_i_2__2_n_0 ),
        .O(\TX_DATA_Buffer[14]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000EEEF0000)) 
    \TX_DATA_Buffer[14]_i_2__2 
       (.I0(p_2_in),
        .I1(gen_a_r),
        .I2(p_0_in),
        .I3(p_0_in4_in),
        .I4(\TX_DATA_Buffer[14]_i_3__0_n_0 ),
        .I5(p_0_in1_in),
        .O(\TX_DATA_Buffer[14]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \TX_DATA_Buffer[14]_i_3__0 
       (.I0(tx_pe_data_v_r),
        .I1(gen_k_fsm_r),
        .O(\TX_DATA_Buffer[14]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[15]_i_1__2 
       (.I0(\TX_DATA_Buffer[15]_i_3__2_n_0 ),
        .I1(\TX_DATA_Buffer[15]_i_4__2_n_0 ),
        .I2(p_2_in),
        .I3(p_0_in),
        .I4(gen_a_r),
        .I5(p_0_in4_in),
        .O(TX_DATA_Buffer_reg0));
  LUT6 #(
    .INIT(64'hFFFFFFF4FFF0FFF4)) 
    \TX_DATA_Buffer[15]_i_2__2 
       (.I0(p_0_in1_in),
        .I1(p_2_in),
        .I2(\TX_DATA_Buffer[15]_i_3__2_n_0 ),
        .I3(\TX_DATA_Buffer[15]_i_5__0_n_0 ),
        .I4(tx_pe_data_v_r),
        .I5(data0[7]),
        .O(\TX_DATA_Buffer[15]_i_2__2_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \TX_DATA_Buffer[15]_i_3__2 
       (.I0(gen_ecp_r),
        .I1(gen_cc_r),
        .I2(gen_k_fsm_r),
        .O(\TX_DATA_Buffer[15]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_DATA_Buffer[15]_i_4__2 
       (.I0(p_0_in1_in),
        .I1(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[15]_i_4__2_n_0 ));
  LUT5 #(
    .INIT(32'h01010001)) 
    \TX_DATA_Buffer[15]_i_5__0 
       (.I0(gen_a_r),
        .I1(p_0_in1_in),
        .I2(tx_pe_data_v_r),
        .I3(p_0_in),
        .I4(p_0_in4_in),
        .O(\TX_DATA_Buffer[15]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'hCFCCFFFFCFCCEEEE)) 
    \TX_DATA_Buffer[1]_i_1__2 
       (.I0(gen_cc_r),
        .I1(gen_ecp_r),
        .I2(gen_pad_r),
        .I3(\tx_pe_data_r_reg_n_0_[14] ),
        .I4(tx_pe_data_v_r),
        .I5(\gen_sp_data_r_reg_n_0_[1] ),
        .O(\TX_DATA_Buffer[1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_DATA_Buffer[2]_i_1__2 
       (.I0(tx_pe_data_v_r),
        .I1(\tx_pe_data_r_reg_n_0_[13] ),
        .I2(\TX_DATA_Buffer[4]_i_2__2_n_0 ),
        .O(\TX_DATA_Buffer[2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFF5FCF5)) 
    \TX_DATA_Buffer[3]_i_1__2 
       (.I0(gen_cc_r),
        .I1(\tx_pe_data_r_reg_n_0_[12] ),
        .I2(gen_ecp_r),
        .I3(tx_pe_data_v_r),
        .I4(gen_pad_r),
        .O(\TX_DATA_Buffer[3]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_DATA_Buffer[4]_i_1__2 
       (.I0(tx_pe_data_v_r),
        .I1(\tx_pe_data_r_reg_n_0_[11] ),
        .I2(\TX_DATA_Buffer[4]_i_2__2_n_0 ),
        .O(\TX_DATA_Buffer[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF01010100)) 
    \TX_DATA_Buffer[4]_i_2__2 
       (.I0(tx_pe_data_v_r),
        .I1(\gen_sp_data_r_reg_n_0_[1] ),
        .I2(p_3_in),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(\gen_r_r_reg_n_0_[1] ),
        .I5(\TX_DATA_Buffer[4]_i_3__0_n_0 ),
        .O(\TX_DATA_Buffer[4]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'hEEFC)) 
    \TX_DATA_Buffer[4]_i_3__0 
       (.I0(gen_pad_r),
        .I1(gen_ecp_r),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[4]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF4FEF4F4)) 
    \TX_DATA_Buffer[5]_i_1__2 
       (.I0(tx_pe_data_v_r),
        .I1(gen_cc_r),
        .I2(gen_ecp_r),
        .I3(gen_pad_r),
        .I4(\tx_pe_data_r_reg_n_0_[10] ),
        .I5(\TX_DATA_Buffer[7]_i_4__0_n_0 ),
        .O(\TX_DATA_Buffer[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0E0E0E0F)) 
    \TX_DATA_Buffer[6]_i_1__2 
       (.I0(p_3_in),
        .I1(\gen_sp_data_r_reg_n_0_[1] ),
        .I2(tx_pe_data_v_r),
        .I3(\gen_r_r_reg_n_0_[1] ),
        .I4(\gen_k_r_reg_n_0_[1] ),
        .I5(\TX_DATA_Buffer[6]_i_2__2_n_0 ),
        .O(\TX_DATA_Buffer[6]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'hF2F2FFF0)) 
    \TX_DATA_Buffer[6]_i_2__2 
       (.I0(\tx_pe_data_r_reg_n_0_[9] ),
        .I1(gen_pad_r),
        .I2(gen_ecp_r),
        .I3(gen_cc_r),
        .I4(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[6]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[7]_i_1__2 
       (.I0(\TX_DATA_Buffer[7]_i_3__2_n_0 ),
        .I1(\gen_k_r_reg_n_0_[1] ),
        .I2(\gen_r_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(\gen_sp_data_r_reg_n_0_[1] ),
        .I5(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[7]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFFEEFFFC)) 
    \TX_DATA_Buffer[7]_i_2__2 
       (.I0(gen_pad_r),
        .I1(gen_ecp_r),
        .I2(gen_cc_r),
        .I3(\TX_DATA_Buffer[7]_i_4__0_n_0 ),
        .I4(tx_pe_data_v_r),
        .I5(\tx_pe_data_r_reg_n_0_[8] ),
        .O(\TX_DATA_Buffer[7]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_DATA_Buffer[7]_i_3__2 
       (.I0(gen_cc_r),
        .I1(gen_ecp_r),
        .O(\TX_DATA_Buffer[7]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'h000000EF)) 
    \TX_DATA_Buffer[7]_i_4__0 
       (.I0(\gen_k_r_reg_n_0_[1] ),
        .I1(p_3_in),
        .I2(\gen_r_r_reg_n_0_[1] ),
        .I3(tx_pe_data_v_r),
        .I4(\gen_sp_data_r_reg_n_0_[1] ),
        .O(\TX_DATA_Buffer[7]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF40)) 
    \TX_DATA_Buffer[8]_i_1__2 
       (.I0(gen_k_fsm_r),
        .I1(tx_pe_data_v_r),
        .I2(data0[0]),
        .I3(gen_ecp_r),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[8]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AFAEAAAE)) 
    \TX_DATA_Buffer[9]_i_1__2 
       (.I0(gen_cc_r),
        .I1(p_0_in1_in),
        .I2(gen_k_fsm_r),
        .I3(tx_pe_data_v_r),
        .I4(data0[1]),
        .I5(gen_ecp_r),
        .O(\TX_DATA_Buffer[9]_i_1__2_n_0 ));
  FDRE \TX_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[0]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [8]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[10]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [2]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[11]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [3]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[12]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [4]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[13]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [5]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[14]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [6]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[15]_i_2__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [7]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[1]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [9]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[2]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [10]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[3]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [11]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[4]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [12]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[5]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [13]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[6]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [14]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__2_n_0 ),
        .D(\TX_DATA_Buffer[7]_i_2__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [15]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[8]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[9]_i_1__2_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [1]),
        .R(1'b0));
  FDRE gen_a_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_a_r_reg_0),
        .Q(gen_a_r),
        .R(1'b0));
  FDRE gen_cc_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_cc_r_reg_0),
        .Q(gen_cc_r),
        .R(1'b0));
  FDRE gen_ecp_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_ecp_i),
        .Q(gen_ecp_r),
        .R(1'b0));
  FDRE gen_k_fsm_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_fsm_r_reg_0),
        .Q(gen_k_fsm_r),
        .R(1'b0));
  FDRE \gen_k_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [1]),
        .Q(p_0_in4_in),
        .R(1'b0));
  FDRE \gen_k_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [0]),
        .Q(\gen_k_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE gen_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(Q),
        .Q(gen_pad_r),
        .R(1'b0));
  FDRE \gen_r_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [1]),
        .Q(p_0_in),
        .R(1'b0));
  FDRE \gen_r_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [0]),
        .Q(\gen_r_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_0_in1_in),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\gen_sp_data_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [1]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \gen_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [0]),
        .Q(p_3_in),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [15]),
        .Q(data0[7]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [5]),
        .Q(\tx_pe_data_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [4]),
        .Q(\tx_pe_data_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [3]),
        .Q(\tx_pe_data_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [2]),
        .Q(\tx_pe_data_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [1]),
        .Q(\tx_pe_data_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [0]),
        .Q(\tx_pe_data_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [14]),
        .Q(data0[6]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [13]),
        .Q(data0[5]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [12]),
        .Q(data0[4]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [11]),
        .Q(data0[3]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [10]),
        .Q(data0[2]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [9]),
        .Q(data0[1]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [8]),
        .Q(data0[0]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [7]),
        .Q(\tx_pe_data_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [6]),
        .Q(\tx_pe_data_r_reg_n_0_[9] ),
        .R(1'b0));
  FDRE tx_pe_data_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_v_r_reg_0),
        .Q(tx_pe_data_v_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_SYM_GEN" *) 
module efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10
   (TXCHARISK,
    TXDATA,
    Q,
    user_clk,
    tx_pe_data_v_r_reg_0,
    gen_k_fsm_r_reg_0,
    GEN_CC,
    gen_suf_i,
    gen_scp_i,
    GEN_A,
    \fc_nb_r_reg[0]_0 ,
    \fc_nb_r_reg[1]_0 ,
    \fc_nb_r_reg[2]_0 ,
    D,
    \gen_v_r_reg[0]_0 ,
    \gen_r_r_reg[0]_0 ,
    \gen_k_r_reg[0]_0 ,
    \tx_pe_data_r_reg[0]_0 );
  output [1:0]TXCHARISK;
  output [15:0]TXDATA;
  input [0:0]Q;
  input user_clk;
  input [0:0]tx_pe_data_v_r_reg_0;
  input gen_k_fsm_r_reg_0;
  input GEN_CC;
  input gen_suf_i;
  input gen_scp_i;
  input GEN_A;
  input \fc_nb_r_reg[0]_0 ;
  input \fc_nb_r_reg[1]_0 ;
  input \fc_nb_r_reg[2]_0 ;
  input [1:0]D;
  input [1:0]\gen_v_r_reg[0]_0 ;
  input [1:0]\gen_r_r_reg[0]_0 ;
  input [1:0]\gen_k_r_reg[0]_0 ;
  input [15:0]\tx_pe_data_r_reg[0]_0 ;

  wire [1:0]D;
  wire GEN_A;
  wire GEN_CC;
  wire [0:0]Q;
  wire [1:0]TXCHARISK;
  wire [15:0]TXDATA;
  wire TX_CHAR_IS_K_Buffer_reg0;
  wire TX_CHAR_IS_K_Buffer_reg04_out;
  wire \TX_DATA_Buffer[0]_i_1_n_0 ;
  wire \TX_DATA_Buffer[10]_i_1_n_0 ;
  wire \TX_DATA_Buffer[11]_i_1_n_0 ;
  wire \TX_DATA_Buffer[12]_i_1_n_0 ;
  wire \TX_DATA_Buffer[12]_i_2_n_0 ;
  wire \TX_DATA_Buffer[13]_i_1_n_0 ;
  wire \TX_DATA_Buffer[13]_i_2_n_0 ;
  wire \TX_DATA_Buffer[13]_i_3_n_0 ;
  wire \TX_DATA_Buffer[14]_i_1_n_0 ;
  wire \TX_DATA_Buffer[14]_i_2_n_0 ;
  wire \TX_DATA_Buffer[14]_i_3_n_0 ;
  wire \TX_DATA_Buffer[15]_i_2_n_0 ;
  wire \TX_DATA_Buffer[15]_i_3_n_0 ;
  wire \TX_DATA_Buffer[15]_i_4_n_0 ;
  wire \TX_DATA_Buffer[15]_i_5_n_0 ;
  wire \TX_DATA_Buffer[15]_i_6_n_0 ;
  wire \TX_DATA_Buffer[1]_i_1_n_0 ;
  wire \TX_DATA_Buffer[2]_i_1_n_0 ;
  wire \TX_DATA_Buffer[2]_i_2_n_0 ;
  wire \TX_DATA_Buffer[2]_i_3_n_0 ;
  wire \TX_DATA_Buffer[3]_i_1_n_0 ;
  wire \TX_DATA_Buffer[4]_i_1_n_0 ;
  wire \TX_DATA_Buffer[4]_i_2_n_0 ;
  wire \TX_DATA_Buffer[4]_i_3_n_0 ;
  wire \TX_DATA_Buffer[5]_i_1_n_0 ;
  wire \TX_DATA_Buffer[6]_i_1_n_0 ;
  wire \TX_DATA_Buffer[6]_i_2_n_0 ;
  wire \TX_DATA_Buffer[6]_i_3_n_0 ;
  wire \TX_DATA_Buffer[6]_i_4_n_0 ;
  wire \TX_DATA_Buffer[7]_i_1_n_0 ;
  wire \TX_DATA_Buffer[7]_i_2_n_0 ;
  wire \TX_DATA_Buffer[7]_i_3_n_0 ;
  wire \TX_DATA_Buffer[7]_i_4_n_0 ;
  wire \TX_DATA_Buffer[7]_i_5_n_0 ;
  wire \TX_DATA_Buffer[8]_i_1_n_0 ;
  wire \TX_DATA_Buffer[9]_i_1_n_0 ;
  wire \TX_DATA_Buffer[9]_i_2_n_0 ;
  wire \TX_DATA_Buffer[9]_i_3_n_0 ;
  wire TX_DATA_Buffer_reg0;
  wire [7:0]data0;
  wire [0:2]fc_nb_r;
  wire \fc_nb_r_reg[0]_0 ;
  wire \fc_nb_r_reg[1]_0 ;
  wire \fc_nb_r_reg[2]_0 ;
  wire gen_a_r;
  wire gen_cc_r;
  wire gen_k_fsm_r;
  wire gen_k_fsm_r_reg_0;
  wire [1:0]\gen_k_r_reg[0]_0 ;
  wire \gen_k_r_reg_n_0_[1] ;
  wire gen_pad_r;
  wire [1:0]\gen_r_r_reg[0]_0 ;
  wire \gen_r_r_reg_n_0_[1] ;
  wire gen_scp_i;
  wire gen_scp_r;
  wire \gen_sp_data_r_reg_n_0_[1] ;
  wire gen_suf_i;
  wire gen_suf_r;
  wire [1:0]\gen_v_r_reg[0]_0 ;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_0_in4_in;
  wire p_2_in;
  wire p_3_in;
  wire [15:0]\tx_pe_data_r_reg[0]_0 ;
  wire \tx_pe_data_r_reg_n_0_[10] ;
  wire \tx_pe_data_r_reg_n_0_[11] ;
  wire \tx_pe_data_r_reg_n_0_[12] ;
  wire \tx_pe_data_r_reg_n_0_[13] ;
  wire \tx_pe_data_r_reg_n_0_[14] ;
  wire \tx_pe_data_r_reg_n_0_[15] ;
  wire \tx_pe_data_r_reg_n_0_[8] ;
  wire \tx_pe_data_r_reg_n_0_[9] ;
  wire tx_pe_data_v_r;
  wire [0:0]tx_pe_data_v_r_reg_0;
  wire user_clk;

  LUT6 #(
    .INIT(64'hCCCCCCCCCCCFCCCD)) 
    \TX_CHAR_IS_K_Buffer[0]_i_1 
       (.I0(tx_pe_data_v_r),
        .I1(gen_cc_r),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(gen_pad_r),
        .I5(gen_suf_r),
        .O(TX_CHAR_IS_K_Buffer_reg0));
  LUT4 #(
    .INIT(16'hFF01)) 
    \TX_CHAR_IS_K_Buffer[1]_i_1 
       (.I0(tx_pe_data_v_r),
        .I1(p_2_in),
        .I2(p_0_in1_in),
        .I3(gen_cc_r),
        .O(TX_CHAR_IS_K_Buffer_reg04_out));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg0),
        .Q(TXCHARISK[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg04_out),
        .Q(TXCHARISK[0]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hF0F0F2F2F0F0FFF0)) 
    \TX_DATA_Buffer[0]_i_1 
       (.I0(\tx_pe_data_r_reg_n_0_[15] ),
        .I1(gen_pad_r),
        .I2(gen_scp_r),
        .I3(gen_cc_r),
        .I4(gen_suf_r),
        .I5(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hEA)) 
    \TX_DATA_Buffer[10]_i_1 
       (.I0(\TX_DATA_Buffer[12]_i_2_n_0 ),
        .I1(tx_pe_data_v_r),
        .I2(data0[2]),
        .O(\TX_DATA_Buffer[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0FFF0FFFFFFFD)) 
    \TX_DATA_Buffer[11]_i_1 
       (.I0(tx_pe_data_v_r),
        .I1(data0[3]),
        .I2(gen_suf_r),
        .I3(gen_scp_r),
        .I4(gen_k_fsm_r),
        .I5(gen_cc_r),
        .O(\TX_DATA_Buffer[11]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hEA)) 
    \TX_DATA_Buffer[12]_i_1 
       (.I0(\TX_DATA_Buffer[12]_i_2_n_0 ),
        .I1(tx_pe_data_v_r),
        .I2(data0[4]),
        .O(\TX_DATA_Buffer[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEFEEEEEEEE)) 
    \TX_DATA_Buffer[12]_i_2 
       (.I0(\TX_DATA_Buffer[13]_i_3_n_0 ),
        .I1(\TX_DATA_Buffer[4]_i_3_n_0 ),
        .I2(tx_pe_data_v_r),
        .I3(p_2_in),
        .I4(p_0_in1_in),
        .I5(\TX_DATA_Buffer[15]_i_3_n_0 ),
        .O(\TX_DATA_Buffer[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0FFF8)) 
    \TX_DATA_Buffer[13]_i_1 
       (.I0(data0[5]),
        .I1(tx_pe_data_v_r),
        .I2(\TX_DATA_Buffer[13]_i_2_n_0 ),
        .I3(\TX_DATA_Buffer[13]_i_3_n_0 ),
        .I4(gen_scp_r),
        .I5(gen_suf_r),
        .O(\TX_DATA_Buffer[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1111111011111111)) 
    \TX_DATA_Buffer[13]_i_2 
       (.I0(p_0_in1_in),
        .I1(\TX_DATA_Buffer[15]_i_4_n_0 ),
        .I2(gen_a_r),
        .I3(p_0_in4_in),
        .I4(p_2_in),
        .I5(p_0_in),
        .O(\TX_DATA_Buffer[13]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_DATA_Buffer[13]_i_3 
       (.I0(gen_k_fsm_r),
        .I1(gen_cc_r),
        .O(\TX_DATA_Buffer[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00AB00AA)) 
    \TX_DATA_Buffer[14]_i_1 
       (.I0(gen_cc_r),
        .I1(gen_k_fsm_r),
        .I2(tx_pe_data_v_r),
        .I3(gen_suf_r),
        .I4(\TX_DATA_Buffer[14]_i_2_n_0 ),
        .I5(\TX_DATA_Buffer[14]_i_3_n_0 ),
        .O(\TX_DATA_Buffer[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'hFFFFFFAB)) 
    \TX_DATA_Buffer[14]_i_2 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_0_in),
        .I3(p_0_in1_in),
        .I4(p_2_in),
        .O(\TX_DATA_Buffer[14]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    \TX_DATA_Buffer[14]_i_3 
       (.I0(tx_pe_data_v_r),
        .I1(gen_suf_r),
        .I2(data0[6]),
        .I3(gen_k_fsm_r),
        .I4(gen_scp_r),
        .O(\TX_DATA_Buffer[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[15]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in1_in),
        .I2(\TX_DATA_Buffer[15]_i_3_n_0 ),
        .I3(\TX_DATA_Buffer[15]_i_4_n_0 ),
        .I4(gen_k_fsm_r),
        .I5(gen_cc_r),
        .O(TX_DATA_Buffer_reg0));
  LUT4 #(
    .INIT(16'hFF54)) 
    \TX_DATA_Buffer[15]_i_2 
       (.I0(gen_scp_r),
        .I1(gen_k_fsm_r),
        .I2(gen_cc_r),
        .I3(\TX_DATA_Buffer[15]_i_5_n_0 ),
        .O(\TX_DATA_Buffer[15]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \TX_DATA_Buffer[15]_i_3 
       (.I0(p_0_in4_in),
        .I1(gen_a_r),
        .I2(p_0_in),
        .O(\TX_DATA_Buffer[15]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \TX_DATA_Buffer[15]_i_4 
       (.I0(gen_suf_r),
        .I1(tx_pe_data_v_r),
        .I2(gen_scp_r),
        .O(\TX_DATA_Buffer[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFF0000BA10)) 
    \TX_DATA_Buffer[15]_i_5 
       (.I0(tx_pe_data_v_r),
        .I1(p_0_in1_in),
        .I2(\TX_DATA_Buffer[15]_i_6_n_0 ),
        .I3(data0[7]),
        .I4(gen_scp_r),
        .I5(gen_suf_r),
        .O(\TX_DATA_Buffer[15]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'hFF45)) 
    \TX_DATA_Buffer[15]_i_6 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_0_in),
        .I3(p_2_in),
        .O(\TX_DATA_Buffer[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAABAFFAAAABAAA)) 
    \TX_DATA_Buffer[1]_i_1 
       (.I0(\TX_DATA_Buffer[6]_i_4_n_0 ),
        .I1(gen_pad_r),
        .I2(\tx_pe_data_r_reg_n_0_[14] ),
        .I3(tx_pe_data_v_r),
        .I4(gen_suf_r),
        .I5(\gen_sp_data_r_reg_n_0_[1] ),
        .O(\TX_DATA_Buffer[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000C0A)) 
    \TX_DATA_Buffer[2]_i_1 
       (.I0(gen_cc_r),
        .I1(\tx_pe_data_r_reg_n_0_[13] ),
        .I2(gen_scp_r),
        .I3(tx_pe_data_v_r),
        .I4(gen_suf_r),
        .I5(\TX_DATA_Buffer[2]_i_2_n_0 ),
        .O(\TX_DATA_Buffer[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000008F8F8F88)) 
    \TX_DATA_Buffer[2]_i_2 
       (.I0(gen_pad_r),
        .I1(\TX_DATA_Buffer[2]_i_3_n_0 ),
        .I2(\TX_DATA_Buffer[7]_i_3_n_0 ),
        .I3(\gen_r_r_reg_n_0_[1] ),
        .I4(\gen_k_r_reg_n_0_[1] ),
        .I5(gen_scp_r),
        .O(\TX_DATA_Buffer[2]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \TX_DATA_Buffer[2]_i_3 
       (.I0(tx_pe_data_v_r),
        .I1(gen_suf_r),
        .O(\TX_DATA_Buffer[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFF0F5F0FCF0F5)) 
    \TX_DATA_Buffer[3]_i_1 
       (.I0(gen_cc_r),
        .I1(\tx_pe_data_r_reg_n_0_[12] ),
        .I2(gen_scp_r),
        .I3(gen_suf_r),
        .I4(tx_pe_data_v_r),
        .I5(gen_pad_r),
        .O(\TX_DATA_Buffer[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF5FCFCFFF5)) 
    \TX_DATA_Buffer[4]_i_1 
       (.I0(\TX_DATA_Buffer[4]_i_2_n_0 ),
        .I1(gen_pad_r),
        .I2(\TX_DATA_Buffer[4]_i_3_n_0 ),
        .I3(gen_cc_r),
        .I4(tx_pe_data_v_r),
        .I5(\tx_pe_data_r_reg_n_0_[11] ),
        .O(\TX_DATA_Buffer[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hEEEF)) 
    \TX_DATA_Buffer[4]_i_2 
       (.I0(p_3_in),
        .I1(\gen_sp_data_r_reg_n_0_[1] ),
        .I2(\gen_r_r_reg_n_0_[1] ),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .O(\TX_DATA_Buffer[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_DATA_Buffer[4]_i_3 
       (.I0(gen_suf_r),
        .I1(gen_scp_r),
        .O(\TX_DATA_Buffer[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFBAAAAAAABAAA)) 
    \TX_DATA_Buffer[5]_i_1 
       (.I0(\TX_DATA_Buffer[7]_i_4_n_0 ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\tx_pe_data_r_reg_n_0_[10] ),
        .I4(gen_suf_r),
        .I5(fc_nb_r[2]),
        .O(\TX_DATA_Buffer[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF8F8F8)) 
    \TX_DATA_Buffer[6]_i_1 
       (.I0(fc_nb_r[1]),
        .I1(gen_suf_r),
        .I2(\TX_DATA_Buffer[6]_i_2_n_0 ),
        .I3(\tx_pe_data_r_reg_n_0_[9] ),
        .I4(\TX_DATA_Buffer[6]_i_3_n_0 ),
        .I5(\TX_DATA_Buffer[6]_i_4_n_0 ),
        .O(\TX_DATA_Buffer[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FFF1)) 
    \TX_DATA_Buffer[6]_i_2 
       (.I0(\gen_k_r_reg_n_0_[1] ),
        .I1(\gen_r_r_reg_n_0_[1] ),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(gen_suf_r),
        .I5(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[6]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \TX_DATA_Buffer[6]_i_3 
       (.I0(gen_suf_r),
        .I1(tx_pe_data_v_r),
        .I2(gen_pad_r),
        .O(\TX_DATA_Buffer[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'hFF10)) 
    \TX_DATA_Buffer[6]_i_4 
       (.I0(tx_pe_data_v_r),
        .I1(gen_suf_r),
        .I2(gen_cc_r),
        .I3(gen_scp_r),
        .O(\TX_DATA_Buffer[6]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \TX_DATA_Buffer[7]_i_1 
       (.I0(\TX_DATA_Buffer[7]_i_3_n_0 ),
        .I1(\gen_k_r_reg_n_0_[1] ),
        .I2(\gen_r_r_reg_n_0_[1] ),
        .I3(gen_scp_r),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFCFFFCF0FCFAFCF0)) 
    \TX_DATA_Buffer[7]_i_2 
       (.I0(\tx_pe_data_r_reg_n_0_[8] ),
        .I1(fc_nb_r[0]),
        .I2(\TX_DATA_Buffer[7]_i_4_n_0 ),
        .I3(gen_suf_r),
        .I4(tx_pe_data_v_r),
        .I5(gen_pad_r),
        .O(\TX_DATA_Buffer[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \TX_DATA_Buffer[7]_i_3 
       (.I0(\gen_sp_data_r_reg_n_0_[1] ),
        .I1(tx_pe_data_v_r),
        .I2(gen_suf_r),
        .I3(p_3_in),
        .O(\TX_DATA_Buffer[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF11111101)) 
    \TX_DATA_Buffer[7]_i_4 
       (.I0(\TX_DATA_Buffer[7]_i_5_n_0 ),
        .I1(\gen_sp_data_r_reg_n_0_[1] ),
        .I2(\gen_r_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(\gen_k_r_reg_n_0_[1] ),
        .I5(\TX_DATA_Buffer[6]_i_4_n_0 ),
        .O(\TX_DATA_Buffer[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \TX_DATA_Buffer[7]_i_5 
       (.I0(tx_pe_data_v_r),
        .I1(gen_suf_r),
        .O(\TX_DATA_Buffer[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF00000008)) 
    \TX_DATA_Buffer[8]_i_1 
       (.I0(tx_pe_data_v_r),
        .I1(data0[0]),
        .I2(gen_k_fsm_r),
        .I3(gen_suf_r),
        .I4(gen_scp_r),
        .I5(gen_cc_r),
        .O(\TX_DATA_Buffer[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBAABAAABAAABA)) 
    \TX_DATA_Buffer[9]_i_1 
       (.I0(\TX_DATA_Buffer[9]_i_2_n_0 ),
        .I1(gen_k_fsm_r),
        .I2(p_0_in1_in),
        .I3(\TX_DATA_Buffer[15]_i_4_n_0 ),
        .I4(data0[1]),
        .I5(\TX_DATA_Buffer[9]_i_3_n_0 ),
        .O(\TX_DATA_Buffer[9]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \TX_DATA_Buffer[9]_i_2 
       (.I0(gen_cc_r),
        .I1(gen_scp_r),
        .I2(gen_suf_r),
        .O(\TX_DATA_Buffer[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \TX_DATA_Buffer[9]_i_3 
       (.I0(gen_suf_r),
        .I1(tx_pe_data_v_r),
        .I2(gen_scp_r),
        .O(\TX_DATA_Buffer[9]_i_3_n_0 ));
  FDRE \TX_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[0]_i_1_n_0 ),
        .Q(TXDATA[8]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[10]_i_1_n_0 ),
        .Q(TXDATA[2]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[11]_i_1_n_0 ),
        .Q(TXDATA[3]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[12]_i_1_n_0 ),
        .Q(TXDATA[4]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[13]_i_1_n_0 ),
        .Q(TXDATA[5]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[14]_i_1_n_0 ),
        .Q(TXDATA[6]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[15]_i_2_n_0 ),
        .Q(TXDATA[7]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[1]_i_1_n_0 ),
        .Q(TXDATA[9]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[2]_i_1_n_0 ),
        .Q(TXDATA[10]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[3]_i_1_n_0 ),
        .Q(TXDATA[11]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[4]_i_1_n_0 ),
        .Q(TXDATA[12]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[5]_i_1_n_0 ),
        .Q(TXDATA[13]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[6]_i_1_n_0 ),
        .Q(TXDATA[14]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1_n_0 ),
        .D(\TX_DATA_Buffer[7]_i_2_n_0 ),
        .Q(TXDATA[15]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[8]_i_1_n_0 ),
        .Q(TXDATA[0]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[9]_i_1_n_0 ),
        .Q(TXDATA[1]),
        .R(1'b0));
  FDRE \fc_nb_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\fc_nb_r_reg[0]_0 ),
        .Q(fc_nb_r[0]),
        .R(1'b0));
  FDRE \fc_nb_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\fc_nb_r_reg[1]_0 ),
        .Q(fc_nb_r[1]),
        .R(1'b0));
  FDRE \fc_nb_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\fc_nb_r_reg[2]_0 ),
        .Q(fc_nb_r[2]),
        .R(1'b0));
  FDRE gen_a_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(GEN_A),
        .Q(gen_a_r),
        .R(1'b0));
  FDRE gen_cc_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(GEN_CC),
        .Q(gen_cc_r),
        .R(1'b0));
  FDRE gen_k_fsm_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_fsm_r_reg_0),
        .Q(gen_k_fsm_r),
        .R(1'b0));
  FDRE \gen_k_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [1]),
        .Q(p_0_in4_in),
        .R(1'b0));
  FDRE \gen_k_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [0]),
        .Q(\gen_k_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE gen_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(Q),
        .Q(gen_pad_r),
        .R(1'b0));
  FDRE \gen_r_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [1]),
        .Q(p_0_in),
        .R(1'b0));
  FDRE \gen_r_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [0]),
        .Q(\gen_r_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE gen_scp_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_scp_i),
        .Q(gen_scp_r),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_0_in1_in),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\gen_sp_data_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE gen_suf_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_suf_i),
        .Q(gen_suf_r),
        .R(1'b0));
  FDRE \gen_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [1]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \gen_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [0]),
        .Q(p_3_in),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [15]),
        .Q(data0[7]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [5]),
        .Q(\tx_pe_data_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [4]),
        .Q(\tx_pe_data_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [3]),
        .Q(\tx_pe_data_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [2]),
        .Q(\tx_pe_data_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [1]),
        .Q(\tx_pe_data_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [0]),
        .Q(\tx_pe_data_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [14]),
        .Q(data0[6]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [13]),
        .Q(data0[5]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [12]),
        .Q(data0[4]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [11]),
        .Q(data0[3]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [10]),
        .Q(data0[2]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [9]),
        .Q(data0[1]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [8]),
        .Q(data0[0]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [7]),
        .Q(\tx_pe_data_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [6]),
        .Q(\tx_pe_data_r_reg_n_0_[9] ),
        .R(1'b0));
  FDRE tx_pe_data_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_v_r_reg_0),
        .Q(tx_pe_data_v_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_SYM_GEN" *) 
module efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4
   (\TX_CHAR_IS_K_Buffer_reg[0]_0 ,
    \TX_DATA_Buffer_reg[7]_0 ,
    Q,
    user_clk,
    tx_pe_data_v_r_reg_0,
    gen_k_fsm_r_reg_0,
    gen_cc_r_reg_0,
    gen_a_r_reg_0,
    D,
    \gen_v_r_reg[0]_0 ,
    \gen_r_r_reg[0]_0 ,
    \gen_k_r_reg[0]_0 ,
    \tx_pe_data_r_reg[0]_0 );
  output [1:0]\TX_CHAR_IS_K_Buffer_reg[0]_0 ;
  output [15:0]\TX_DATA_Buffer_reg[7]_0 ;
  input [0:0]Q;
  input user_clk;
  input [0:0]tx_pe_data_v_r_reg_0;
  input gen_k_fsm_r_reg_0;
  input gen_cc_r_reg_0;
  input gen_a_r_reg_0;
  input [1:0]D;
  input [1:0]\gen_v_r_reg[0]_0 ;
  input [1:0]\gen_r_r_reg[0]_0 ;
  input [1:0]\gen_k_r_reg[0]_0 ;
  input [15:0]\tx_pe_data_r_reg[0]_0 ;

  wire [1:0]D;
  wire [0:0]Q;
  wire TX_CHAR_IS_K_Buffer_reg0;
  wire TX_CHAR_IS_K_Buffer_reg04_out;
  wire [1:0]\TX_CHAR_IS_K_Buffer_reg[0]_0 ;
  wire \TX_DATA_Buffer[0]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[10]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[11]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[12]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[12]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[12]_i_3__0_n_0 ;
  wire \TX_DATA_Buffer[13]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[13]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[14]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[14]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[15]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[15]_i_3__1_n_0 ;
  wire \TX_DATA_Buffer[15]_i_4__1_n_0 ;
  wire \TX_DATA_Buffer[1]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[2]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[3]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[4]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[4]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[5]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[6]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[6]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[7]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[7]_i_2__1_n_0 ;
  wire \TX_DATA_Buffer[7]_i_3__1_n_0 ;
  wire \TX_DATA_Buffer[8]_i_1__1_n_0 ;
  wire \TX_DATA_Buffer[9]_i_1__1_n_0 ;
  wire TX_DATA_Buffer_reg0;
  wire [15:0]\TX_DATA_Buffer_reg[7]_0 ;
  wire [7:0]data0;
  wire gen_a_r;
  wire gen_a_r_reg_0;
  wire gen_cc_r;
  wire gen_cc_r_reg_0;
  wire gen_k_fsm_r;
  wire gen_k_fsm_r_reg_0;
  wire [1:0]\gen_k_r_reg[0]_0 ;
  wire \gen_k_r_reg_n_0_[1] ;
  wire gen_pad_r;
  wire [1:0]\gen_r_r_reg[0]_0 ;
  wire \gen_r_r_reg_n_0_[1] ;
  wire \gen_sp_data_r_reg_n_0_[1] ;
  wire [1:0]\gen_v_r_reg[0]_0 ;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_0_in4_in;
  wire p_2_in;
  wire p_3_in;
  wire [15:0]\tx_pe_data_r_reg[0]_0 ;
  wire \tx_pe_data_r_reg_n_0_[10] ;
  wire \tx_pe_data_r_reg_n_0_[11] ;
  wire \tx_pe_data_r_reg_n_0_[12] ;
  wire \tx_pe_data_r_reg_n_0_[13] ;
  wire \tx_pe_data_r_reg_n_0_[14] ;
  wire \tx_pe_data_r_reg_n_0_[15] ;
  wire \tx_pe_data_r_reg_n_0_[8] ;
  wire \tx_pe_data_r_reg_n_0_[9] ;
  wire tx_pe_data_v_r;
  wire [0:0]tx_pe_data_v_r_reg_0;
  wire user_clk;

  LUT5 #(
    .INIT(32'hFFFF000B)) 
    \TX_CHAR_IS_K_Buffer[0]_i_1__1 
       (.I0(gen_pad_r),
        .I1(tx_pe_data_v_r),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(gen_cc_r),
        .O(TX_CHAR_IS_K_Buffer_reg0));
  LUT4 #(
    .INIT(16'hFF01)) 
    \TX_CHAR_IS_K_Buffer[1]_i_1__1 
       (.I0(tx_pe_data_v_r),
        .I1(p_2_in),
        .I2(p_0_in1_in),
        .I3(gen_cc_r),
        .O(TX_CHAR_IS_K_Buffer_reg04_out));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg0),
        .Q(\TX_CHAR_IS_K_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg04_out),
        .Q(\TX_CHAR_IS_K_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'h44F0)) 
    \TX_DATA_Buffer[0]_i_1__1 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[15] ),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    \TX_DATA_Buffer[10]_i_1__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[2]),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .I4(\TX_DATA_Buffer[12]_i_2__1_n_0 ),
        .O(\TX_DATA_Buffer[10]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT4 #(
    .INIT(16'h00EF)) 
    \TX_DATA_Buffer[11]_i_1__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[3]),
        .I2(tx_pe_data_v_r),
        .I3(gen_cc_r),
        .O(\TX_DATA_Buffer[11]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    \TX_DATA_Buffer[12]_i_1__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[4]),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .I4(\TX_DATA_Buffer[12]_i_2__1_n_0 ),
        .O(\TX_DATA_Buffer[12]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF0F0F0E2)) 
    \TX_DATA_Buffer[12]_i_2__1 
       (.I0(gen_k_fsm_r),
        .I1(p_0_in),
        .I2(\TX_DATA_Buffer[12]_i_3__0_n_0 ),
        .I3(p_0_in4_in),
        .I4(gen_a_r),
        .I5(gen_cc_r),
        .O(\TX_DATA_Buffer[12]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hCD)) 
    \TX_DATA_Buffer[12]_i_3__0 
       (.I0(p_2_in),
        .I1(gen_k_fsm_r),
        .I2(p_0_in1_in),
        .O(\TX_DATA_Buffer[12]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFEFE0)) 
    \TX_DATA_Buffer[13]_i_1__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[5]),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[13]_i_2__1_n_0 ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[13]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFFFEFF)) 
    \TX_DATA_Buffer[13]_i_2__1 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_2_in),
        .I3(p_0_in),
        .I4(gen_k_fsm_r),
        .I5(p_0_in1_in),
        .O(\TX_DATA_Buffer[13]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4F40)) 
    \TX_DATA_Buffer[14]_i_1__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[6]),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[14]_i_2__1_n_0 ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[14]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFAFFFB)) 
    \TX_DATA_Buffer[14]_i_2__1 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_2_in),
        .I3(p_0_in1_in),
        .I4(p_0_in),
        .I5(gen_k_fsm_r),
        .O(\TX_DATA_Buffer[14]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \TX_DATA_Buffer[15]_i_1__1 
       (.I0(gen_cc_r),
        .I1(\TX_DATA_Buffer[15]_i_3__1_n_0 ),
        .I2(tx_pe_data_v_r),
        .O(TX_DATA_Buffer_reg0));
  LUT5 #(
    .INIT(32'hFFFFEFE0)) 
    \TX_DATA_Buffer[15]_i_2__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[7]),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[15]_i_4__1_n_0 ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[15]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[15]_i_3__1 
       (.I0(p_0_in4_in),
        .I1(p_2_in),
        .I2(p_0_in1_in),
        .I3(gen_k_fsm_r),
        .I4(p_0_in),
        .I5(gen_a_r),
        .O(\TX_DATA_Buffer[15]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFFF4F5)) 
    \TX_DATA_Buffer[15]_i_4__1 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_2_in),
        .I3(p_0_in),
        .I4(gen_k_fsm_r),
        .I5(p_0_in1_in),
        .O(\TX_DATA_Buffer[15]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h2F2F2F20)) 
    \TX_DATA_Buffer[1]_i_1__1 
       (.I0(\tx_pe_data_r_reg_n_0_[14] ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\gen_sp_data_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \TX_DATA_Buffer[2]_i_1__1 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[13] ),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[4]_i_2__1_n_0 ),
        .O(\TX_DATA_Buffer[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'hE0EF)) 
    \TX_DATA_Buffer[3]_i_1__1 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[12] ),
        .I2(tx_pe_data_v_r),
        .I3(gen_cc_r),
        .O(\TX_DATA_Buffer[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \TX_DATA_Buffer[4]_i_1__1 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[11] ),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[4]_i_2__1_n_0 ),
        .O(\TX_DATA_Buffer[4]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'hFFFF0302)) 
    \TX_DATA_Buffer[4]_i_2__1 
       (.I0(\gen_r_r_reg_n_0_[1] ),
        .I1(p_3_in),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[4]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \TX_DATA_Buffer[5]_i_1__1 
       (.I0(\tx_pe_data_r_reg_n_0_[10] ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[7]_i_3__1_n_0 ),
        .O(\TX_DATA_Buffer[5]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \TX_DATA_Buffer[6]_i_1__1 
       (.I0(\tx_pe_data_r_reg_n_0_[9] ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[6]_i_2__1_n_0 ),
        .O(\TX_DATA_Buffer[6]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFCFD)) 
    \TX_DATA_Buffer[6]_i_2__1 
       (.I0(\gen_r_r_reg_n_0_[1] ),
        .I1(\gen_sp_data_r_reg_n_0_[1] ),
        .I2(p_3_in),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[6]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[7]_i_1__1 
       (.I0(gen_cc_r),
        .I1(\gen_r_r_reg_n_0_[1] ),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(\gen_k_r_reg_n_0_[1] ),
        .I5(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[7]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \TX_DATA_Buffer[7]_i_2__1 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[8] ),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[7]_i_3__1_n_0 ),
        .O(\TX_DATA_Buffer[7]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'hFFFF5551)) 
    \TX_DATA_Buffer[7]_i_3__1 
       (.I0(\gen_sp_data_r_reg_n_0_[1] ),
        .I1(\gen_r_r_reg_n_0_[1] ),
        .I2(p_3_in),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[7]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT4 #(
    .INIT(16'hFF40)) 
    \TX_DATA_Buffer[8]_i_1__1 
       (.I0(gen_k_fsm_r),
        .I1(data0[0]),
        .I2(tx_pe_data_v_r),
        .I3(gen_cc_r),
        .O(\TX_DATA_Buffer[8]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0B08)) 
    \TX_DATA_Buffer[9]_i_1__1 
       (.I0(data0[1]),
        .I1(tx_pe_data_v_r),
        .I2(gen_k_fsm_r),
        .I3(p_0_in1_in),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[9]_i_1__1_n_0 ));
  FDRE \TX_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[0]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [8]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[10]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [2]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[11]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [3]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[12]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [4]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[13]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [5]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[14]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [6]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[15]_i_2__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [7]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[1]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [9]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[2]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [10]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[3]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [11]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[4]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [12]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[5]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [13]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[6]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [14]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__1_n_0 ),
        .D(\TX_DATA_Buffer[7]_i_2__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [15]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[8]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[9]_i_1__1_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [1]),
        .R(1'b0));
  FDRE gen_a_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_a_r_reg_0),
        .Q(gen_a_r),
        .R(1'b0));
  FDRE gen_cc_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_cc_r_reg_0),
        .Q(gen_cc_r),
        .R(1'b0));
  FDRE gen_k_fsm_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_fsm_r_reg_0),
        .Q(gen_k_fsm_r),
        .R(1'b0));
  FDRE \gen_k_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [1]),
        .Q(p_0_in4_in),
        .R(1'b0));
  FDRE \gen_k_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [0]),
        .Q(\gen_k_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE gen_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(Q),
        .Q(gen_pad_r),
        .R(1'b0));
  FDRE \gen_r_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [1]),
        .Q(p_0_in),
        .R(1'b0));
  FDRE \gen_r_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [0]),
        .Q(\gen_r_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_0_in1_in),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\gen_sp_data_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [1]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \gen_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [0]),
        .Q(p_3_in),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [15]),
        .Q(data0[7]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [5]),
        .Q(\tx_pe_data_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [4]),
        .Q(\tx_pe_data_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [3]),
        .Q(\tx_pe_data_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [2]),
        .Q(\tx_pe_data_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [1]),
        .Q(\tx_pe_data_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [0]),
        .Q(\tx_pe_data_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [14]),
        .Q(data0[6]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [13]),
        .Q(data0[5]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [12]),
        .Q(data0[4]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [11]),
        .Q(data0[3]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [10]),
        .Q(data0[2]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [9]),
        .Q(data0[1]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [8]),
        .Q(data0[0]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [7]),
        .Q(\tx_pe_data_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [6]),
        .Q(\tx_pe_data_r_reg_n_0_[9] ),
        .R(1'b0));
  FDRE tx_pe_data_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_v_r_reg_0),
        .Q(tx_pe_data_v_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_SYM_GEN" *) 
module efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7
   (\TX_CHAR_IS_K_Buffer_reg[0]_0 ,
    \TX_DATA_Buffer_reg[7]_0 ,
    Q,
    user_clk,
    tx_pe_data_v_r_reg_0,
    gen_k_fsm_r_reg_0,
    gen_cc_r_reg_0,
    gen_a_r_reg_0,
    D,
    \gen_v_r_reg[0]_0 ,
    \gen_r_r_reg[0]_0 ,
    \gen_k_r_reg[0]_0 ,
    \tx_pe_data_r_reg[0]_0 );
  output [1:0]\TX_CHAR_IS_K_Buffer_reg[0]_0 ;
  output [15:0]\TX_DATA_Buffer_reg[7]_0 ;
  input [0:0]Q;
  input user_clk;
  input [0:0]tx_pe_data_v_r_reg_0;
  input gen_k_fsm_r_reg_0;
  input gen_cc_r_reg_0;
  input gen_a_r_reg_0;
  input [1:0]D;
  input [1:0]\gen_v_r_reg[0]_0 ;
  input [1:0]\gen_r_r_reg[0]_0 ;
  input [1:0]\gen_k_r_reg[0]_0 ;
  input [15:0]\tx_pe_data_r_reg[0]_0 ;

  wire [1:0]D;
  wire [0:0]Q;
  wire TX_CHAR_IS_K_Buffer_reg0;
  wire TX_CHAR_IS_K_Buffer_reg04_out;
  wire [1:0]\TX_CHAR_IS_K_Buffer_reg[0]_0 ;
  wire \TX_DATA_Buffer[0]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[10]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[11]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[12]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[12]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[12]_i_3_n_0 ;
  wire \TX_DATA_Buffer[13]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[13]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[14]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[14]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[15]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[15]_i_3__0_n_0 ;
  wire \TX_DATA_Buffer[15]_i_4__0_n_0 ;
  wire \TX_DATA_Buffer[1]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[2]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[3]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[4]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[4]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[5]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[6]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[6]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[7]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[7]_i_2__0_n_0 ;
  wire \TX_DATA_Buffer[7]_i_3__0_n_0 ;
  wire \TX_DATA_Buffer[8]_i_1__0_n_0 ;
  wire \TX_DATA_Buffer[9]_i_1__0_n_0 ;
  wire TX_DATA_Buffer_reg0;
  wire [15:0]\TX_DATA_Buffer_reg[7]_0 ;
  wire [7:0]data0;
  wire gen_a_r;
  wire gen_a_r_reg_0;
  wire gen_cc_r;
  wire gen_cc_r_reg_0;
  wire gen_k_fsm_r;
  wire gen_k_fsm_r_reg_0;
  wire [1:0]\gen_k_r_reg[0]_0 ;
  wire \gen_k_r_reg_n_0_[1] ;
  wire gen_pad_r;
  wire [1:0]\gen_r_r_reg[0]_0 ;
  wire \gen_r_r_reg_n_0_[1] ;
  wire \gen_sp_data_r_reg_n_0_[1] ;
  wire [1:0]\gen_v_r_reg[0]_0 ;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_0_in4_in;
  wire p_2_in;
  wire p_3_in;
  wire [15:0]\tx_pe_data_r_reg[0]_0 ;
  wire \tx_pe_data_r_reg_n_0_[10] ;
  wire \tx_pe_data_r_reg_n_0_[11] ;
  wire \tx_pe_data_r_reg_n_0_[12] ;
  wire \tx_pe_data_r_reg_n_0_[13] ;
  wire \tx_pe_data_r_reg_n_0_[14] ;
  wire \tx_pe_data_r_reg_n_0_[15] ;
  wire \tx_pe_data_r_reg_n_0_[8] ;
  wire \tx_pe_data_r_reg_n_0_[9] ;
  wire tx_pe_data_v_r;
  wire [0:0]tx_pe_data_v_r_reg_0;
  wire user_clk;

  LUT5 #(
    .INIT(32'hFFFF000B)) 
    \TX_CHAR_IS_K_Buffer[0]_i_1__0 
       (.I0(gen_pad_r),
        .I1(tx_pe_data_v_r),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(gen_cc_r),
        .O(TX_CHAR_IS_K_Buffer_reg0));
  LUT4 #(
    .INIT(16'hFF01)) 
    \TX_CHAR_IS_K_Buffer[1]_i_1__0 
       (.I0(tx_pe_data_v_r),
        .I1(p_2_in),
        .I2(p_0_in1_in),
        .I3(gen_cc_r),
        .O(TX_CHAR_IS_K_Buffer_reg04_out));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg0),
        .Q(\TX_CHAR_IS_K_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CHAR_IS_K_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_CHAR_IS_K_Buffer_reg04_out),
        .Q(\TX_CHAR_IS_K_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'h44F0)) 
    \TX_DATA_Buffer[0]_i_1__0 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[15] ),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    \TX_DATA_Buffer[10]_i_1__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[2]),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .I4(\TX_DATA_Buffer[12]_i_2__0_n_0 ),
        .O(\TX_DATA_Buffer[10]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h00EF)) 
    \TX_DATA_Buffer[11]_i_1__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[3]),
        .I2(tx_pe_data_v_r),
        .I3(gen_cc_r),
        .O(\TX_DATA_Buffer[11]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    \TX_DATA_Buffer[12]_i_1__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[4]),
        .I2(gen_cc_r),
        .I3(tx_pe_data_v_r),
        .I4(\TX_DATA_Buffer[12]_i_2__0_n_0 ),
        .O(\TX_DATA_Buffer[12]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF0F0F0E2)) 
    \TX_DATA_Buffer[12]_i_2__0 
       (.I0(gen_k_fsm_r),
        .I1(p_0_in),
        .I2(\TX_DATA_Buffer[12]_i_3_n_0 ),
        .I3(p_0_in4_in),
        .I4(gen_a_r),
        .I5(gen_cc_r),
        .O(\TX_DATA_Buffer[12]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'hCD)) 
    \TX_DATA_Buffer[12]_i_3 
       (.I0(p_2_in),
        .I1(gen_k_fsm_r),
        .I2(p_0_in1_in),
        .O(\TX_DATA_Buffer[12]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFEFE0)) 
    \TX_DATA_Buffer[13]_i_1__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[5]),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[13]_i_2__0_n_0 ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[13]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFFFEFF)) 
    \TX_DATA_Buffer[13]_i_2__0 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_2_in),
        .I3(p_0_in),
        .I4(gen_k_fsm_r),
        .I5(p_0_in1_in),
        .O(\TX_DATA_Buffer[13]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4F40)) 
    \TX_DATA_Buffer[14]_i_1__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[6]),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[14]_i_2__0_n_0 ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[14]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFAFFFB)) 
    \TX_DATA_Buffer[14]_i_2__0 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_2_in),
        .I3(p_0_in1_in),
        .I4(p_0_in),
        .I5(gen_k_fsm_r),
        .O(\TX_DATA_Buffer[14]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \TX_DATA_Buffer[15]_i_1__0 
       (.I0(gen_cc_r),
        .I1(\TX_DATA_Buffer[15]_i_3__0_n_0 ),
        .I2(tx_pe_data_v_r),
        .O(TX_DATA_Buffer_reg0));
  LUT5 #(
    .INIT(32'hFFFFEFE0)) 
    \TX_DATA_Buffer[15]_i_2__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[7]),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[15]_i_4__0_n_0 ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[15]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[15]_i_3__0 
       (.I0(p_0_in4_in),
        .I1(p_2_in),
        .I2(p_0_in1_in),
        .I3(gen_k_fsm_r),
        .I4(p_0_in),
        .I5(gen_a_r),
        .O(\TX_DATA_Buffer[15]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFFF4F5)) 
    \TX_DATA_Buffer[15]_i_4__0 
       (.I0(gen_a_r),
        .I1(p_0_in4_in),
        .I2(p_2_in),
        .I3(p_0_in),
        .I4(gen_k_fsm_r),
        .I5(p_0_in1_in),
        .O(\TX_DATA_Buffer[15]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h2F2F2F20)) 
    \TX_DATA_Buffer[1]_i_1__0 
       (.I0(\tx_pe_data_r_reg_n_0_[14] ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\gen_sp_data_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \TX_DATA_Buffer[2]_i_1__0 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[13] ),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[4]_i_2__0_n_0 ),
        .O(\TX_DATA_Buffer[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'hE0EF)) 
    \TX_DATA_Buffer[3]_i_1__0 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[12] ),
        .I2(tx_pe_data_v_r),
        .I3(gen_cc_r),
        .O(\TX_DATA_Buffer[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \TX_DATA_Buffer[4]_i_1__0 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[11] ),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[4]_i_2__0_n_0 ),
        .O(\TX_DATA_Buffer[4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'hFFFF0302)) 
    \TX_DATA_Buffer[4]_i_2__0 
       (.I0(\gen_r_r_reg_n_0_[1] ),
        .I1(p_3_in),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \TX_DATA_Buffer[5]_i_1__0 
       (.I0(\tx_pe_data_r_reg_n_0_[10] ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[7]_i_3__0_n_0 ),
        .O(\TX_DATA_Buffer[5]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \TX_DATA_Buffer[6]_i_1__0 
       (.I0(\tx_pe_data_r_reg_n_0_[9] ),
        .I1(gen_pad_r),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[6]_i_2__0_n_0 ),
        .O(\TX_DATA_Buffer[6]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFCFD)) 
    \TX_DATA_Buffer[6]_i_2__0 
       (.I0(\gen_r_r_reg_n_0_[1] ),
        .I1(\gen_sp_data_r_reg_n_0_[1] ),
        .I2(p_3_in),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[6]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_Buffer[7]_i_1__0 
       (.I0(gen_cc_r),
        .I1(\gen_r_r_reg_n_0_[1] ),
        .I2(\gen_sp_data_r_reg_n_0_[1] ),
        .I3(p_3_in),
        .I4(\gen_k_r_reg_n_0_[1] ),
        .I5(tx_pe_data_v_r),
        .O(\TX_DATA_Buffer[7]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \TX_DATA_Buffer[7]_i_2__0 
       (.I0(gen_pad_r),
        .I1(\tx_pe_data_r_reg_n_0_[8] ),
        .I2(tx_pe_data_v_r),
        .I3(\TX_DATA_Buffer[7]_i_3__0_n_0 ),
        .O(\TX_DATA_Buffer[7]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'hFFFF5551)) 
    \TX_DATA_Buffer[7]_i_3__0 
       (.I0(\gen_sp_data_r_reg_n_0_[1] ),
        .I1(\gen_r_r_reg_n_0_[1] ),
        .I2(p_3_in),
        .I3(\gen_k_r_reg_n_0_[1] ),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[7]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'hFF40)) 
    \TX_DATA_Buffer[8]_i_1__0 
       (.I0(gen_k_fsm_r),
        .I1(data0[0]),
        .I2(tx_pe_data_v_r),
        .I3(gen_cc_r),
        .O(\TX_DATA_Buffer[8]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0B08)) 
    \TX_DATA_Buffer[9]_i_1__0 
       (.I0(data0[1]),
        .I1(tx_pe_data_v_r),
        .I2(gen_k_fsm_r),
        .I3(p_0_in1_in),
        .I4(gen_cc_r),
        .O(\TX_DATA_Buffer[9]_i_1__0_n_0 ));
  FDRE \TX_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[0]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [8]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[10]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [2]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[11]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [3]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[12]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [4]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[13]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [5]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[14]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [6]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[15]_i_2__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [7]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[1]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [9]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[2]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [10]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[3]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [11]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[4]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [12]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[5]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [13]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[6]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [14]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(\TX_DATA_Buffer[7]_i_1__0_n_0 ),
        .D(\TX_DATA_Buffer[7]_i_2__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [15]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[8]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \TX_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(TX_DATA_Buffer_reg0),
        .D(\TX_DATA_Buffer[9]_i_1__0_n_0 ),
        .Q(\TX_DATA_Buffer_reg[7]_0 [1]),
        .R(1'b0));
  FDRE gen_a_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_a_r_reg_0),
        .Q(gen_a_r),
        .R(1'b0));
  FDRE gen_cc_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_cc_r_reg_0),
        .Q(gen_cc_r),
        .R(1'b0));
  FDRE gen_k_fsm_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_k_fsm_r_reg_0),
        .Q(gen_k_fsm_r),
        .R(1'b0));
  FDRE \gen_k_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [1]),
        .Q(p_0_in4_in),
        .R(1'b0));
  FDRE \gen_k_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_k_r_reg[0]_0 [0]),
        .Q(\gen_k_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE gen_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(Q),
        .Q(gen_pad_r),
        .R(1'b0));
  FDRE \gen_r_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [1]),
        .Q(p_0_in),
        .R(1'b0));
  FDRE \gen_r_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_r_r_reg[0]_0 [0]),
        .Q(\gen_r_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_0_in1_in),
        .R(1'b0));
  FDRE \gen_sp_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\gen_sp_data_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [1]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \gen_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\gen_v_r_reg[0]_0 [0]),
        .Q(p_3_in),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [15]),
        .Q(data0[7]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [5]),
        .Q(\tx_pe_data_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [4]),
        .Q(\tx_pe_data_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [3]),
        .Q(\tx_pe_data_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [2]),
        .Q(\tx_pe_data_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [1]),
        .Q(\tx_pe_data_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [0]),
        .Q(\tx_pe_data_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [14]),
        .Q(data0[6]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [13]),
        .Q(data0[5]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [12]),
        .Q(data0[4]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [11]),
        .Q(data0[3]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [10]),
        .Q(data0[2]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [9]),
        .Q(data0[1]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [8]),
        .Q(data0[0]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [7]),
        .Q(\tx_pe_data_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_pe_data_r_reg[0]_0 [6]),
        .Q(\tx_pe_data_r_reg_n_0_[9] ),
        .R(1'b0));
  FDRE tx_pe_data_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_v_r_reg_0),
        .Q(tx_pe_data_v_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
   (TX_LANE_UP,
    TXCHARISK,
    ENABLE_ERR_DETECT,
    tx_aligned_r,
    hard_err_reset_i,
    D,
    TXDATA,
    RESET,
    user_clk,
    SS,
    Q,
    tx_pe_data_v_r_reg,
    GEN_CC,
    gen_suf_i,
    gen_scp_i,
    GEN_A,
    tx_aligned_simplex_r,
    hard_err_flop_r_reg,
    \fc_nb_r_reg[0] ,
    \fc_nb_r_reg[1] ,
    \fc_nb_r_reg[2] ,
    \gen_v_r_reg[0] ,
    \gen_r_r_reg[0] ,
    \gen_k_r_reg[0] ,
    \tx_pe_data_r_reg[0] );
  output [0:0]TX_LANE_UP;
  output [1:0]TXCHARISK;
  output ENABLE_ERR_DETECT;
  output tx_aligned_r;
  output hard_err_reset_i;
  output [0:0]D;
  output [15:0]TXDATA;
  input RESET;
  input user_clk;
  input [0:0]SS;
  input [0:0]Q;
  input [0:0]tx_pe_data_v_r_reg;
  input GEN_CC;
  input gen_suf_i;
  input gen_scp_i;
  input GEN_A;
  input tx_aligned_simplex_r;
  input hard_err_flop_r_reg;
  input \fc_nb_r_reg[0] ;
  input \fc_nb_r_reg[1] ;
  input \fc_nb_r_reg[2] ;
  input [1:0]\gen_v_r_reg[0] ;
  input [1:0]\gen_r_r_reg[0] ;
  input [1:0]\gen_k_r_reg[0] ;
  input [15:0]\tx_pe_data_r_reg[0] ;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire GEN_A;
  wire GEN_CC;
  wire [0:0]Q;
  wire RESET;
  wire [0:0]SS;
  wire [1:0]TXCHARISK;
  wire [15:0]TXDATA;
  wire [0:0]TX_LANE_UP;
  wire \fc_nb_r_reg[0] ;
  wire \fc_nb_r_reg[1] ;
  wire \fc_nb_r_reg[2] ;
  wire [1:0]\gen_k_r_reg[0] ;
  wire [1:0]\gen_r_r_reg[0] ;
  wire gen_scp_i;
  wire gen_suf_i;
  wire [1:0]\gen_v_r_reg[0] ;
  wire hard_err_flop_r_reg;
  wire hard_err_reset_i;
  wire send_sp_c;
  wire tx_aligned_r;
  wire tx_aligned_simplex_r;
  wire tx_lane_init_simplex_sm_i_n_3;
  wire tx_lane_init_simplex_sm_i_n_5;
  wire [15:0]\tx_pe_data_r_reg[0] ;
  wire [0:0]tx_pe_data_v_r_reg;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10 sym_gen_i
       (.D({tx_lane_init_simplex_sm_i_n_3,send_sp_c}),
        .GEN_A(GEN_A),
        .GEN_CC(GEN_CC),
        .Q(Q),
        .TXCHARISK(TXCHARISK),
        .TXDATA(TXDATA),
        .\fc_nb_r_reg[0]_0 (\fc_nb_r_reg[0] ),
        .\fc_nb_r_reg[1]_0 (\fc_nb_r_reg[1] ),
        .\fc_nb_r_reg[2]_0 (\fc_nb_r_reg[2] ),
        .gen_k_fsm_r_reg_0(tx_lane_init_simplex_sm_i_n_5),
        .\gen_k_r_reg[0]_0 (\gen_k_r_reg[0] ),
        .\gen_r_r_reg[0]_0 (\gen_r_r_reg[0] ),
        .gen_scp_i(gen_scp_i),
        .gen_suf_i(gen_suf_i),
        .\gen_v_r_reg[0]_0 (\gen_v_r_reg[0] ),
        .\tx_pe_data_r_reg[0]_0 (\tx_pe_data_r_reg[0] ),
        .tx_pe_data_v_r_reg_0(tx_pe_data_v_r_reg),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11 tx_err_detect_simplex_i
       (.D(D),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .hard_err_flop_r_reg_0(hard_err_flop_r_reg),
        .hard_err_reset_i(hard_err_reset_i),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12 tx_lane_init_simplex_sm_i
       (.D({tx_lane_init_simplex_sm_i_n_3,send_sp_c}),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .RESET(RESET),
        .SS(SS),
        .TX_LANE_UP(TX_LANE_UP),
        .odd_word_r_reg_0(tx_lane_init_simplex_sm_i_n_5),
        .tx_aligned_r(tx_aligned_r),
        .tx_aligned_simplex_r(tx_aligned_simplex_r),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1
   (TX_LANE_UP,
    \TX_CHAR_IS_K_Buffer_reg[0] ,
    ENABLE_ERR_DETECT,
    hard_err_reset_i,
    D,
    \TX_DATA_Buffer_reg[7] ,
    lane_up_flop_i,
    user_clk,
    SS,
    Q,
    tx_pe_data_v_r_reg,
    gen_cc_r_reg,
    gen_a_r_reg,
    hard_err_flop_r_reg,
    tx_aligned_r,
    \gen_v_r_reg[0] ,
    \gen_r_r_reg[0] ,
    \gen_k_r_reg[0] ,
    \tx_pe_data_r_reg[0] );
  output [0:0]TX_LANE_UP;
  output [1:0]\TX_CHAR_IS_K_Buffer_reg[0] ;
  output ENABLE_ERR_DETECT;
  output hard_err_reset_i;
  output [0:0]D;
  output [15:0]\TX_DATA_Buffer_reg[7] ;
  input lane_up_flop_i;
  input user_clk;
  input [0:0]SS;
  input [0:0]Q;
  input [0:0]tx_pe_data_v_r_reg;
  input gen_cc_r_reg;
  input gen_a_r_reg;
  input hard_err_flop_r_reg;
  input tx_aligned_r;
  input [1:0]\gen_v_r_reg[0] ;
  input [1:0]\gen_r_r_reg[0] ;
  input [1:0]\gen_k_r_reg[0] ;
  input [15:0]\tx_pe_data_r_reg[0] ;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire [0:0]Q;
  wire [0:0]SS;
  wire [1:0]\TX_CHAR_IS_K_Buffer_reg[0] ;
  wire [15:0]\TX_DATA_Buffer_reg[7] ;
  wire [0:0]TX_LANE_UP;
  wire gen_a_r_reg;
  wire gen_cc_r_reg;
  wire [1:0]\gen_k_r_reg[0] ;
  wire [1:0]\gen_r_r_reg[0] ;
  wire [1:0]\gen_v_r_reg[0] ;
  wire hard_err_flop_r_reg;
  wire hard_err_reset_i;
  wire lane_up_flop_i;
  wire send_sp_c;
  wire tx_aligned_r;
  wire tx_lane_init_simplex_sm_i_n_2;
  wire tx_lane_init_simplex_sm_i_n_4;
  wire [15:0]\tx_pe_data_r_reg[0] ;
  wire [0:0]tx_pe_data_v_r_reg;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7 sym_gen_i
       (.D({tx_lane_init_simplex_sm_i_n_2,send_sp_c}),
        .Q(Q),
        .\TX_CHAR_IS_K_Buffer_reg[0]_0 (\TX_CHAR_IS_K_Buffer_reg[0] ),
        .\TX_DATA_Buffer_reg[7]_0 (\TX_DATA_Buffer_reg[7] ),
        .gen_a_r_reg_0(gen_a_r_reg),
        .gen_cc_r_reg_0(gen_cc_r_reg),
        .gen_k_fsm_r_reg_0(tx_lane_init_simplex_sm_i_n_4),
        .\gen_k_r_reg[0]_0 (\gen_k_r_reg[0] ),
        .\gen_r_r_reg[0]_0 (\gen_r_r_reg[0] ),
        .\gen_v_r_reg[0]_0 (\gen_v_r_reg[0] ),
        .\tx_pe_data_r_reg[0]_0 (\tx_pe_data_r_reg[0] ),
        .tx_pe_data_v_r_reg_0(tx_pe_data_v_r_reg),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8 tx_err_detect_simplex_i
       (.D(D),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .hard_err_flop_r_reg_0(hard_err_flop_r_reg),
        .hard_err_reset_i(hard_err_reset_i),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9 tx_lane_init_simplex_sm_i
       (.D({tx_lane_init_simplex_sm_i_n_2,send_sp_c}),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .SS(SS),
        .TX_LANE_UP(TX_LANE_UP),
        .lane_up_flop_i_0(lane_up_flop_i),
        .odd_word_r_reg_0(tx_lane_init_simplex_sm_i_n_4),
        .tx_aligned_r(tx_aligned_r),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2
   (TX_LANE_UP,
    \TX_CHAR_IS_K_Buffer_reg[0] ,
    ENABLE_ERR_DETECT,
    hard_err_reset_i,
    D,
    \TX_DATA_Buffer_reg[7] ,
    lane_up_flop_i,
    user_clk,
    SS,
    Q,
    tx_pe_data_v_r_reg,
    gen_cc_r_reg,
    gen_a_r_reg,
    hard_err_flop_r_reg,
    tx_aligned_r,
    \gen_v_r_reg[0] ,
    \gen_r_r_reg[0] ,
    \gen_k_r_reg[0] ,
    \tx_pe_data_r_reg[0] );
  output [0:0]TX_LANE_UP;
  output [1:0]\TX_CHAR_IS_K_Buffer_reg[0] ;
  output ENABLE_ERR_DETECT;
  output hard_err_reset_i;
  output [0:0]D;
  output [15:0]\TX_DATA_Buffer_reg[7] ;
  input lane_up_flop_i;
  input user_clk;
  input [0:0]SS;
  input [0:0]Q;
  input [0:0]tx_pe_data_v_r_reg;
  input gen_cc_r_reg;
  input gen_a_r_reg;
  input hard_err_flop_r_reg;
  input tx_aligned_r;
  input [1:0]\gen_v_r_reg[0] ;
  input [1:0]\gen_r_r_reg[0] ;
  input [1:0]\gen_k_r_reg[0] ;
  input [15:0]\tx_pe_data_r_reg[0] ;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire [0:0]Q;
  wire [0:0]SS;
  wire [1:0]\TX_CHAR_IS_K_Buffer_reg[0] ;
  wire [15:0]\TX_DATA_Buffer_reg[7] ;
  wire [0:0]TX_LANE_UP;
  wire gen_a_r_reg;
  wire gen_cc_r_reg;
  wire [1:0]\gen_k_r_reg[0] ;
  wire [1:0]\gen_r_r_reg[0] ;
  wire [1:0]\gen_v_r_reg[0] ;
  wire hard_err_flop_r_reg;
  wire hard_err_reset_i;
  wire lane_up_flop_i;
  wire send_sp_c;
  wire tx_aligned_r;
  wire tx_lane_init_simplex_sm_i_n_2;
  wire tx_lane_init_simplex_sm_i_n_4;
  wire [15:0]\tx_pe_data_r_reg[0] ;
  wire [0:0]tx_pe_data_v_r_reg;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4 sym_gen_i
       (.D({tx_lane_init_simplex_sm_i_n_2,send_sp_c}),
        .Q(Q),
        .\TX_CHAR_IS_K_Buffer_reg[0]_0 (\TX_CHAR_IS_K_Buffer_reg[0] ),
        .\TX_DATA_Buffer_reg[7]_0 (\TX_DATA_Buffer_reg[7] ),
        .gen_a_r_reg_0(gen_a_r_reg),
        .gen_cc_r_reg_0(gen_cc_r_reg),
        .gen_k_fsm_r_reg_0(tx_lane_init_simplex_sm_i_n_4),
        .\gen_k_r_reg[0]_0 (\gen_k_r_reg[0] ),
        .\gen_r_r_reg[0]_0 (\gen_r_r_reg[0] ),
        .\gen_v_r_reg[0]_0 (\gen_v_r_reg[0] ),
        .\tx_pe_data_r_reg[0]_0 (\tx_pe_data_r_reg[0] ),
        .tx_pe_data_v_r_reg_0(tx_pe_data_v_r_reg),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5 tx_err_detect_simplex_i
       (.D(D),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .hard_err_flop_r_reg_0(hard_err_flop_r_reg),
        .hard_err_reset_i(hard_err_reset_i),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6 tx_lane_init_simplex_sm_i
       (.D({tx_lane_init_simplex_sm_i_n_2,send_sp_c}),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .SS(SS),
        .TX_LANE_UP(TX_LANE_UP),
        .lane_up_flop_i_0(lane_up_flop_i),
        .odd_word_r_reg_0(tx_lane_init_simplex_sm_i_n_4),
        .tx_aligned_r(tx_aligned_r),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3
   (TX_LANE_UP,
    \TX_CHAR_IS_K_Buffer_reg[0] ,
    ENABLE_ERR_DETECT,
    hard_err_reset_i,
    D,
    \TX_DATA_Buffer_reg[7] ,
    lane_up_flop_i,
    user_clk,
    SS,
    Q,
    tx_pe_data_v_r_reg,
    gen_cc_r_reg,
    gen_ecp_i,
    gen_a_r_reg,
    hard_err_flop_r_reg,
    tx_aligned_r,
    \gen_v_r_reg[0] ,
    \gen_r_r_reg[0] ,
    \gen_k_r_reg[0] ,
    \tx_pe_data_r_reg[0] );
  output [0:0]TX_LANE_UP;
  output [1:0]\TX_CHAR_IS_K_Buffer_reg[0] ;
  output ENABLE_ERR_DETECT;
  output hard_err_reset_i;
  output [0:0]D;
  output [15:0]\TX_DATA_Buffer_reg[7] ;
  input lane_up_flop_i;
  input user_clk;
  input [0:0]SS;
  input [0:0]Q;
  input [0:0]tx_pe_data_v_r_reg;
  input gen_cc_r_reg;
  input gen_ecp_i;
  input gen_a_r_reg;
  input hard_err_flop_r_reg;
  input tx_aligned_r;
  input [1:0]\gen_v_r_reg[0] ;
  input [1:0]\gen_r_r_reg[0] ;
  input [1:0]\gen_k_r_reg[0] ;
  input [15:0]\tx_pe_data_r_reg[0] ;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire [0:0]Q;
  wire [0:0]SS;
  wire [1:0]\TX_CHAR_IS_K_Buffer_reg[0] ;
  wire [15:0]\TX_DATA_Buffer_reg[7] ;
  wire [0:0]TX_LANE_UP;
  wire gen_a_r_reg;
  wire gen_cc_r_reg;
  wire gen_ecp_i;
  wire [1:0]\gen_k_r_reg[0] ;
  wire [1:0]\gen_r_r_reg[0] ;
  wire [1:0]\gen_v_r_reg[0] ;
  wire hard_err_flop_r_reg;
  wire hard_err_reset_i;
  wire lane_up_flop_i;
  wire send_sp_c;
  wire tx_aligned_r;
  wire tx_lane_init_simplex_sm_i_n_2;
  wire tx_lane_init_simplex_sm_i_n_4;
  wire [15:0]\tx_pe_data_r_reg[0] ;
  wire [0:0]tx_pe_data_v_r_reg;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_SYM_GEN sym_gen_i
       (.D({tx_lane_init_simplex_sm_i_n_2,send_sp_c}),
        .Q(Q),
        .\TX_CHAR_IS_K_Buffer_reg[0]_0 (\TX_CHAR_IS_K_Buffer_reg[0] ),
        .\TX_DATA_Buffer_reg[7]_0 (\TX_DATA_Buffer_reg[7] ),
        .gen_a_r_reg_0(gen_a_r_reg),
        .gen_cc_r_reg_0(gen_cc_r_reg),
        .gen_ecp_i(gen_ecp_i),
        .gen_k_fsm_r_reg_0(tx_lane_init_simplex_sm_i_n_4),
        .\gen_k_r_reg[0]_0 (\gen_k_r_reg[0] ),
        .\gen_r_r_reg[0]_0 (\gen_r_r_reg[0] ),
        .\gen_v_r_reg[0]_0 (\gen_v_r_reg[0] ),
        .\tx_pe_data_r_reg[0]_0 (\tx_pe_data_r_reg[0] ),
        .tx_pe_data_v_r_reg_0(tx_pe_data_v_r_reg),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX tx_err_detect_simplex_i
       (.D(D),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .hard_err_flop_r_reg_0(hard_err_flop_r_reg),
        .hard_err_reset_i(hard_err_reset_i),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX tx_lane_init_simplex_sm_i
       (.D({tx_lane_init_simplex_sm_i_n_2,send_sp_c}),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .SS(SS),
        .TX_LANE_UP(TX_LANE_UP),
        .lane_up_flop_i_0(lane_up_flop_i),
        .odd_word_r_reg_0(tx_lane_init_simplex_sm_i_n_4),
        .tx_aligned_r(tx_aligned_r),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX
   (CHANNEL_HARD_ERR_Buffer_reg_0,
    reset_channel_i,
    tx_verify_simplex_r_reg,
    tx_bonded1_simplex_r_reg,
    tx_aligned_simplex_r_reg,
    tx_reset_simplex_r_reg,
    simplex_timer_r0,
    POWER_DOWN,
    user_clk,
    tx_verify_simplex_r,
    tx_verify_simplex_r_reg_0,
    tx_bonded1_simplex_r_reg_0,
    tx_verify_simplex_r_reg_1,
    RESET_SYMGEN,
    tx_bonded1_simplex_r,
    tx_bonded1_simplex_r_reg_1,
    tx_bonded1_simplex_r_reg_2,
    tx_aligned_simplex_r,
    tx_aligned_simplex_r_reg_0,
    tx_aligned_simplex_r_reg_1,
    tx_aligned_simplex_r_reg_2,
    tx_reset_simplex_r,
    tx_reset_simplex_r_reg_0,
    simplex_timer_r_reg,
    simplex_timer_r_reg_0_sp_1,
    D,
    TX_LANE_UP);
  output CHANNEL_HARD_ERR_Buffer_reg_0;
  output reset_channel_i;
  output tx_verify_simplex_r_reg;
  output tx_bonded1_simplex_r_reg;
  output tx_aligned_simplex_r_reg;
  output tx_reset_simplex_r_reg;
  output simplex_timer_r0;
  input POWER_DOWN;
  input user_clk;
  input tx_verify_simplex_r;
  input tx_verify_simplex_r_reg_0;
  input tx_bonded1_simplex_r_reg_0;
  input tx_verify_simplex_r_reg_1;
  input RESET_SYMGEN;
  input tx_bonded1_simplex_r;
  input tx_bonded1_simplex_r_reg_1;
  input tx_bonded1_simplex_r_reg_2;
  input tx_aligned_simplex_r;
  input tx_aligned_simplex_r_reg_0;
  input tx_aligned_simplex_r_reg_1;
  input tx_aligned_simplex_r_reg_2;
  input tx_reset_simplex_r;
  input tx_reset_simplex_r_reg_0;
  input [2:0]simplex_timer_r_reg;
  input simplex_timer_r_reg_0_sp_1;
  input [3:0]D;
  input [0:3]TX_LANE_UP;

  wire CHANNEL_HARD_ERR_Buffer_reg_0;
  wire [3:0]D;
  wire POWER_DOWN;
  wire RESET_CHANNEL_Buffer0__0;
  wire RESET_SYMGEN;
  wire [0:3]TX_LANE_UP;
  wire channel_hard_err_c__0;
  wire \hard_err_r_reg_n_0_[0] ;
  wire \hard_err_r_reg_n_0_[3] ;
  wire \lane_up_r_reg_n_0_[0] ;
  wire \lane_up_r_reg_n_0_[2] ;
  wire \lane_up_r_reg_n_0_[3] ;
  wire p_0_in;
  wire p_1_in;
  wire p_2_in;
  wire reset_channel_i;
  wire simplex_timer_r0;
  wire [2:0]simplex_timer_r_reg;
  wire simplex_timer_r_reg_0_sn_1;
  wire tx_aligned_simplex_r;
  wire tx_aligned_simplex_r_reg;
  wire tx_aligned_simplex_r_reg_0;
  wire tx_aligned_simplex_r_reg_1;
  wire tx_aligned_simplex_r_reg_2;
  wire tx_bonded1_simplex_r;
  wire tx_bonded1_simplex_r_reg;
  wire tx_bonded1_simplex_r_reg_0;
  wire tx_bonded1_simplex_r_reg_1;
  wire tx_bonded1_simplex_r_reg_2;
  wire tx_reset_simplex_r;
  wire tx_reset_simplex_r_reg;
  wire tx_reset_simplex_r_reg_0;
  wire tx_verify_simplex_r;
  wire tx_verify_simplex_r_reg;
  wire tx_verify_simplex_r_reg_0;
  wire tx_verify_simplex_r_reg_1;
  wire user_clk;

  assign simplex_timer_r_reg_0_sn_1 = simplex_timer_r_reg_0_sp_1;
  FDRE #(
    .INIT(1'b1)) 
    CHANNEL_HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(channel_hard_err_c__0),
        .Q(CHANNEL_HARD_ERR_Buffer_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    RESET_CHANNEL_Buffer0
       (.I0(\lane_up_r_reg_n_0_[2] ),
        .I1(p_2_in),
        .I2(POWER_DOWN),
        .I3(\lane_up_r_reg_n_0_[3] ),
        .I4(\lane_up_r_reg_n_0_[0] ),
        .O(RESET_CHANNEL_Buffer0__0));
  FDRE #(
    .INIT(1'b1)) 
    RESET_CHANNEL_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RESET_CHANNEL_Buffer0__0),
        .Q(reset_channel_i),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    channel_hard_err_c
       (.I0(\hard_err_r_reg_n_0_[3] ),
        .I1(\hard_err_r_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(p_1_in),
        .O(channel_hard_err_c__0));
  FDRE \hard_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(\hard_err_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \hard_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(p_0_in),
        .R(1'b0));
  FDRE \hard_err_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \hard_err_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\hard_err_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \lane_up_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_LANE_UP[0]),
        .Q(\lane_up_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \lane_up_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_LANE_UP[1]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \lane_up_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_LANE_UP[2]),
        .Q(\lane_up_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \lane_up_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_LANE_UP[3]),
        .Q(\lane_up_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \simplex_timer_r[0]_i_1 
       (.I0(CHANNEL_HARD_ERR_Buffer_reg_0),
        .I1(simplex_timer_r_reg_0_sn_1),
        .O(simplex_timer_r0));
  LUT6 #(
    .INIT(64'h000000000000AAEA)) 
    tx_aligned_simplex_r_i_1
       (.I0(tx_aligned_simplex_r),
        .I1(tx_aligned_simplex_r_reg_0),
        .I2(tx_aligned_simplex_r_reg_1),
        .I3(tx_aligned_simplex_r_reg_2),
        .I4(CHANNEL_HARD_ERR_Buffer_reg_0),
        .I5(RESET_SYMGEN),
        .O(tx_aligned_simplex_r_reg));
  LUT6 #(
    .INIT(64'h000000000000BAAA)) 
    tx_bonded1_simplex_r_i_1
       (.I0(tx_bonded1_simplex_r),
        .I1(tx_bonded1_simplex_r_reg_1),
        .I2(tx_bonded1_simplex_r_reg_2),
        .I3(tx_bonded1_simplex_r_reg_0),
        .I4(CHANNEL_HARD_ERR_Buffer_reg_0),
        .I5(RESET_SYMGEN),
        .O(tx_bonded1_simplex_r_reg));
  LUT6 #(
    .INIT(64'h00000000A8AAAAB8)) 
    tx_reset_simplex_r_i_1
       (.I0(tx_reset_simplex_r),
        .I1(tx_reset_simplex_r_reg_0),
        .I2(simplex_timer_r_reg[0]),
        .I3(simplex_timer_r_reg[1]),
        .I4(simplex_timer_r_reg[2]),
        .I5(simplex_timer_r0),
        .O(tx_reset_simplex_r_reg));
  LUT6 #(
    .INIT(64'h000000000000BAAA)) 
    tx_verify_simplex_r_i_1
       (.I0(tx_verify_simplex_r),
        .I1(tx_verify_simplex_r_reg_0),
        .I2(tx_bonded1_simplex_r_reg_0),
        .I3(tx_verify_simplex_r_reg_1),
        .I4(CHANNEL_HARD_ERR_Buffer_reg_0),
        .I5(RESET_SYMGEN),
        .O(tx_verify_simplex_r_reg));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX
   (TX_CHANNEL_UP,
    RESET,
    reset_lanes_flop_1_i_0,
    reset_lanes_flop_2_i_0,
    reset_lanes_flop_3_i_0,
    gen_ver_i,
    SS,
    reset_lanes_flop_1_i_1,
    reset_lanes_flop_2_i_1,
    reset_lanes_flop_3_i_1,
    tx_channel_up_i_0,
    user_clk,
    tx_verify_simplex_r,
    wait_for_lane_up_r0,
    hard_err_reset_i,
    hard_err_reset_i_0,
    hard_err_reset_i_1,
    hard_err_reset_i_2,
    reset_lanes_flop_3_i_2,
    tx_reset_simplex_r,
    tx_bonded1_simplex_r,
    reset_channel_i);
  output TX_CHANNEL_UP;
  output RESET;
  output reset_lanes_flop_1_i_0;
  output reset_lanes_flop_2_i_0;
  output reset_lanes_flop_3_i_0;
  output gen_ver_i;
  output [0:0]SS;
  output [0:0]reset_lanes_flop_1_i_1;
  output [0:0]reset_lanes_flop_2_i_1;
  output [0:0]reset_lanes_flop_3_i_1;
  output tx_channel_up_i_0;
  input user_clk;
  input tx_verify_simplex_r;
  input wait_for_lane_up_r0;
  input hard_err_reset_i;
  input hard_err_reset_i_0;
  input hard_err_reset_i_1;
  input hard_err_reset_i_2;
  input reset_lanes_flop_3_i_2;
  input tx_reset_simplex_r;
  input tx_bonded1_simplex_r;
  input reset_channel_i;

  wire D;
  wire RESET;
  wire [0:0]SS;
  wire TX_BONDED;
  wire TX_CHANNEL_UP;
  wire bonding_watchdog_r0;
  wire \bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ;
  wire \bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ;
  wire \bonding_watchdog_r_reg[14]_srl15_n_0 ;
  wire \bonding_watchdog_r_reg_n_0_[15] ;
  wire channel_bond_r;
  wire \free_count_r[10]_i_2_n_0 ;
  wire \free_count_r[10]_i_3_n_0 ;
  wire \free_count_r[10]_i_4_n_0 ;
  wire \free_count_r[10]_i_5_n_0 ;
  wire \free_count_r[14]_i_2_n_0 ;
  wire \free_count_r[14]_i_3_n_0 ;
  wire \free_count_r[14]_i_4_n_0 ;
  wire \free_count_r[14]_i_5_n_0 ;
  wire \free_count_r[2]_i_2_n_0 ;
  wire \free_count_r[2]_i_3_n_0 ;
  wire \free_count_r[2]_i_4_n_0 ;
  wire \free_count_r[6]_i_2_n_0 ;
  wire \free_count_r[6]_i_3_n_0 ;
  wire \free_count_r[6]_i_4_n_0 ;
  wire \free_count_r[6]_i_5_n_0 ;
  wire [0:14]free_count_r_reg;
  wire \free_count_r_reg[10]_i_1_n_0 ;
  wire \free_count_r_reg[10]_i_1_n_1 ;
  wire \free_count_r_reg[10]_i_1_n_2 ;
  wire \free_count_r_reg[10]_i_1_n_3 ;
  wire \free_count_r_reg[10]_i_1_n_4 ;
  wire \free_count_r_reg[10]_i_1_n_5 ;
  wire \free_count_r_reg[10]_i_1_n_6 ;
  wire \free_count_r_reg[10]_i_1_n_7 ;
  wire \free_count_r_reg[14]_i_1_n_0 ;
  wire \free_count_r_reg[14]_i_1_n_1 ;
  wire \free_count_r_reg[14]_i_1_n_2 ;
  wire \free_count_r_reg[14]_i_1_n_3 ;
  wire \free_count_r_reg[14]_i_1_n_4 ;
  wire \free_count_r_reg[14]_i_1_n_5 ;
  wire \free_count_r_reg[14]_i_1_n_6 ;
  wire \free_count_r_reg[14]_i_1_n_7 ;
  wire \free_count_r_reg[2]_i_1_n_2 ;
  wire \free_count_r_reg[2]_i_1_n_3 ;
  wire \free_count_r_reg[2]_i_1_n_5 ;
  wire \free_count_r_reg[2]_i_1_n_6 ;
  wire \free_count_r_reg[2]_i_1_n_7 ;
  wire \free_count_r_reg[6]_i_1_n_0 ;
  wire \free_count_r_reg[6]_i_1_n_1 ;
  wire \free_count_r_reg[6]_i_1_n_2 ;
  wire \free_count_r_reg[6]_i_1_n_3 ;
  wire \free_count_r_reg[6]_i_1_n_4 ;
  wire \free_count_r_reg[6]_i_1_n_5 ;
  wire \free_count_r_reg[6]_i_1_n_6 ;
  wire \free_count_r_reg[6]_i_1_n_7 ;
  wire gen_ver_i;
  wire hard_err_reset_i;
  wire hard_err_reset_i_0;
  wire hard_err_reset_i_1;
  wire hard_err_reset_i_2;
  wire next_channel_bond_c;
  wire next_ready_c;
  wire next_verify_c;
  wire ready_r;
  wire reset_channel_i;
  wire reset_lanes_flop_0_i_i_1_n_0;
  wire reset_lanes_flop_0_i_i_2_n_0;
  wire reset_lanes_flop_1_i_0;
  wire [0:0]reset_lanes_flop_1_i_1;
  wire reset_lanes_flop_2_i_0;
  wire [0:0]reset_lanes_flop_2_i_1;
  wire reset_lanes_flop_3_i_0;
  wire [0:0]reset_lanes_flop_3_i_1;
  wire reset_lanes_flop_3_i_2;
  wire tx_bonded1_simplex_r;
  wire tx_bonded_r;
  wire tx_channel_up_i_0;
  wire tx_reset_simplex_r;
  wire tx_verify_r;
  wire tx_verify_simplex_r;
  wire user_clk;
  wire verify_watchdog_r0;
  wire \verify_watchdog_r_reg[14]_srl15_n_0 ;
  wire \verify_watchdog_r_reg_n_0_[15] ;
  wire wait_for_lane_up_r;
  wire wait_for_lane_up_r0;
  wire [3:2]\NLW_free_count_r_reg[2]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_free_count_r_reg[2]_i_1_O_UNCONNECTED ;

  (* srl_bus_name = "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/bonding_watchdog_r_reg " *) 
  (* srl_name = "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/bonding_watchdog_r_reg[14]_srl15 " *) 
  SRL16E \bonding_watchdog_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(bonding_watchdog_r0),
        .CLK(user_clk),
        .D(channel_bond_r),
        .Q(\bonding_watchdog_r_reg[14]_srl15_n_0 ));
  LUT6 #(
    .INIT(64'h00020000FFFFFFFF)) 
    \bonding_watchdog_r_reg[14]_srl15_i_1 
       (.I0(\bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ),
        .I1(free_count_r_reg[12]),
        .I2(free_count_r_reg[13]),
        .I3(free_count_r_reg[14]),
        .I4(\bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ),
        .I5(channel_bond_r),
        .O(bonding_watchdog_r0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \bonding_watchdog_r_reg[14]_srl15_i_2 
       (.I0(free_count_r_reg[3]),
        .I1(free_count_r_reg[2]),
        .I2(free_count_r_reg[5]),
        .I3(free_count_r_reg[4]),
        .I4(free_count_r_reg[0]),
        .I5(free_count_r_reg[1]),
        .O(\bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \bonding_watchdog_r_reg[14]_srl15_i_3 
       (.I0(free_count_r_reg[9]),
        .I1(free_count_r_reg[8]),
        .I2(free_count_r_reg[11]),
        .I3(free_count_r_reg[10]),
        .I4(free_count_r_reg[6]),
        .I5(free_count_r_reg[7]),
        .O(\bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ));
  FDRE \bonding_watchdog_r_reg[15] 
       (.C(user_clk),
        .CE(bonding_watchdog_r0),
        .D(\bonding_watchdog_r_reg[14]_srl15_n_0 ),
        .Q(\bonding_watchdog_r_reg_n_0_[15] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF4)) 
    channel_bond_r_i_1
       (.I0(tx_bonded_r),
        .I1(channel_bond_r),
        .I2(wait_for_lane_up_r),
        .O(next_channel_bond_c));
  FDRE channel_bond_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_channel_bond_c),
        .Q(channel_bond_r),
        .R(wait_for_lane_up_r0));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[10]_i_2 
       (.I0(free_count_r_reg[7]),
        .O(\free_count_r[10]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[10]_i_3 
       (.I0(free_count_r_reg[8]),
        .O(\free_count_r[10]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[10]_i_4 
       (.I0(free_count_r_reg[9]),
        .O(\free_count_r[10]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[10]_i_5 
       (.I0(free_count_r_reg[10]),
        .O(\free_count_r[10]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[14]_i_2 
       (.I0(free_count_r_reg[11]),
        .O(\free_count_r[14]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[14]_i_3 
       (.I0(free_count_r_reg[12]),
        .O(\free_count_r[14]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[14]_i_4 
       (.I0(free_count_r_reg[13]),
        .O(\free_count_r[14]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[14]_i_5 
       (.I0(free_count_r_reg[14]),
        .O(\free_count_r[14]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[2]_i_2 
       (.I0(free_count_r_reg[0]),
        .O(\free_count_r[2]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[2]_i_3 
       (.I0(free_count_r_reg[1]),
        .O(\free_count_r[2]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[2]_i_4 
       (.I0(free_count_r_reg[2]),
        .O(\free_count_r[2]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[6]_i_2 
       (.I0(free_count_r_reg[3]),
        .O(\free_count_r[6]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[6]_i_3 
       (.I0(free_count_r_reg[4]),
        .O(\free_count_r[6]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[6]_i_4 
       (.I0(free_count_r_reg[5]),
        .O(\free_count_r[6]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[6]_i_5 
       (.I0(free_count_r_reg[6]),
        .O(\free_count_r[6]_i_5_n_0 ));
  FDSE \free_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[2]_i_1_n_5 ),
        .Q(free_count_r_reg[0]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[10]_i_1_n_7 ),
        .Q(free_count_r_reg[10]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[10]_i_1 
       (.CI(\free_count_r_reg[14]_i_1_n_0 ),
        .CO({\free_count_r_reg[10]_i_1_n_0 ,\free_count_r_reg[10]_i_1_n_1 ,\free_count_r_reg[10]_i_1_n_2 ,\free_count_r_reg[10]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[10]_i_1_n_4 ,\free_count_r_reg[10]_i_1_n_5 ,\free_count_r_reg[10]_i_1_n_6 ,\free_count_r_reg[10]_i_1_n_7 }),
        .S({\free_count_r[10]_i_2_n_0 ,\free_count_r[10]_i_3_n_0 ,\free_count_r[10]_i_4_n_0 ,\free_count_r[10]_i_5_n_0 }));
  FDSE \free_count_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[14]_i_1_n_4 ),
        .Q(free_count_r_reg[11]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[14]_i_1_n_5 ),
        .Q(free_count_r_reg[12]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[14]_i_1_n_6 ),
        .Q(free_count_r_reg[13]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[14]_i_1_n_7 ),
        .Q(free_count_r_reg[14]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[14]_i_1 
       (.CI(1'b0),
        .CO({\free_count_r_reg[14]_i_1_n_0 ,\free_count_r_reg[14]_i_1_n_1 ,\free_count_r_reg[14]_i_1_n_2 ,\free_count_r_reg[14]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[14]_i_1_n_4 ,\free_count_r_reg[14]_i_1_n_5 ,\free_count_r_reg[14]_i_1_n_6 ,\free_count_r_reg[14]_i_1_n_7 }),
        .S({\free_count_r[14]_i_2_n_0 ,\free_count_r[14]_i_3_n_0 ,\free_count_r[14]_i_4_n_0 ,\free_count_r[14]_i_5_n_0 }));
  FDSE \free_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[2]_i_1_n_6 ),
        .Q(free_count_r_reg[1]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[2]_i_1_n_7 ),
        .Q(free_count_r_reg[2]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[2]_i_1 
       (.CI(\free_count_r_reg[6]_i_1_n_0 ),
        .CO({\NLW_free_count_r_reg[2]_i_1_CO_UNCONNECTED [3:2],\free_count_r_reg[2]_i_1_n_2 ,\free_count_r_reg[2]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b1,1'b1}),
        .O({\NLW_free_count_r_reg[2]_i_1_O_UNCONNECTED [3],\free_count_r_reg[2]_i_1_n_5 ,\free_count_r_reg[2]_i_1_n_6 ,\free_count_r_reg[2]_i_1_n_7 }),
        .S({1'b0,\free_count_r[2]_i_2_n_0 ,\free_count_r[2]_i_3_n_0 ,\free_count_r[2]_i_4_n_0 }));
  FDSE \free_count_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[6]_i_1_n_4 ),
        .Q(free_count_r_reg[3]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[6]_i_1_n_5 ),
        .Q(free_count_r_reg[4]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[6]_i_1_n_6 ),
        .Q(free_count_r_reg[5]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[6]_i_1_n_7 ),
        .Q(free_count_r_reg[6]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[6]_i_1 
       (.CI(\free_count_r_reg[10]_i_1_n_0 ),
        .CO({\free_count_r_reg[6]_i_1_n_0 ,\free_count_r_reg[6]_i_1_n_1 ,\free_count_r_reg[6]_i_1_n_2 ,\free_count_r_reg[6]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[6]_i_1_n_4 ,\free_count_r_reg[6]_i_1_n_5 ,\free_count_r_reg[6]_i_1_n_6 ,\free_count_r_reg[6]_i_1_n_7 }),
        .S({\free_count_r[6]_i_2_n_0 ,\free_count_r[6]_i_3_n_0 ,\free_count_r[6]_i_4_n_0 ,\free_count_r[6]_i_5_n_0 }));
  FDSE \free_count_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[10]_i_1_n_4 ),
        .Q(free_count_r_reg[7]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[10]_i_1_n_5 ),
        .Q(free_count_r_reg[8]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[10]_i_1_n_6 ),
        .Q(free_count_r_reg[9]),
        .S(wait_for_lane_up_r0));
  FDRE ready_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ready_r),
        .Q(D),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF8)) 
    ready_r_i_1__3
       (.I0(gen_ver_i),
        .I1(tx_verify_r),
        .I2(ready_r),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(ready_r),
        .R(wait_for_lane_up_r0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_lanes_flop_0_i_i_1_n_0),
        .Q(RESET),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    reset_lanes_flop_0_i_i_1
       (.I0(reset_lanes_flop_0_i_i_2_n_0),
        .I1(reset_lanes_flop_3_i_2),
        .I2(tx_reset_simplex_r),
        .O(reset_lanes_flop_0_i_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFF222F222F222)) 
    reset_lanes_flop_0_i_i_2
       (.I0(reset_channel_i),
        .I1(wait_for_lane_up_r),
        .I2(\bonding_watchdog_r_reg_n_0_[15] ),
        .I3(channel_bond_r),
        .I4(gen_ver_i),
        .I5(\verify_watchdog_r_reg_n_0_[15] ),
        .O(reset_lanes_flop_0_i_i_2_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_lanes_flop_0_i_i_1_n_0),
        .Q(reset_lanes_flop_1_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_lanes_flop_0_i_i_1_n_0),
        .Q(reset_lanes_flop_2_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_lanes_flop_0_i_i_1_n_0),
        .Q(reset_lanes_flop_3_i_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_r_i_1
       (.I0(RESET),
        .I1(hard_err_reset_i),
        .O(SS));
  LUT2 #(
    .INIT(4'hE)) 
    rst_r_i_1__0
       (.I0(reset_lanes_flop_1_i_0),
        .I1(hard_err_reset_i_0),
        .O(reset_lanes_flop_1_i_1));
  LUT2 #(
    .INIT(4'hE)) 
    rst_r_i_1__1
       (.I0(reset_lanes_flop_2_i_0),
        .I1(hard_err_reset_i_1),
        .O(reset_lanes_flop_2_i_1));
  LUT2 #(
    .INIT(4'hE)) 
    rst_r_i_1__2
       (.I0(reset_lanes_flop_3_i_0),
        .I1(hard_err_reset_i_2),
        .O(reset_lanes_flop_3_i_1));
  LUT2 #(
    .INIT(4'h6)) 
    tx_bonded_r_i_1
       (.I0(tx_verify_simplex_r),
        .I1(tx_bonded1_simplex_r),
        .O(TX_BONDED));
  FDRE #(
    .INIT(1'b1)) 
    tx_bonded_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(TX_BONDED),
        .Q(tx_bonded_r),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    tx_channel_up_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(TX_CHANNEL_UP),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    tx_verify_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_verify_simplex_r),
        .Q(tx_verify_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    ufc_header_r_i_1
       (.I0(TX_CHANNEL_UP),
        .O(tx_channel_up_i_0));
  LUT4 #(
    .INIT(16'hF444)) 
    verify_r_i_1
       (.I0(tx_verify_r),
        .I1(gen_ver_i),
        .I2(channel_bond_r),
        .I3(tx_bonded_r),
        .O(next_verify_c));
  FDRE verify_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_verify_c),
        .Q(gen_ver_i),
        .R(wait_for_lane_up_r0));
  (* srl_bus_name = "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/verify_watchdog_r_reg " *) 
  (* srl_name = "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/verify_watchdog_r_reg[14]_srl15 " *) 
  SRL16E \verify_watchdog_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(verify_watchdog_r0),
        .CLK(user_clk),
        .D(gen_ver_i),
        .Q(\verify_watchdog_r_reg[14]_srl15_n_0 ));
  LUT6 #(
    .INIT(64'h00020000FFFFFFFF)) 
    \verify_watchdog_r_reg[14]_srl15_i_1 
       (.I0(\bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ),
        .I1(free_count_r_reg[12]),
        .I2(free_count_r_reg[13]),
        .I3(free_count_r_reg[14]),
        .I4(\bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ),
        .I5(gen_ver_i),
        .O(verify_watchdog_r0));
  FDRE \verify_watchdog_r_reg[15] 
       (.C(user_clk),
        .CE(verify_watchdog_r0),
        .D(\verify_watchdog_r_reg[14]_srl15_n_0 ),
        .Q(\verify_watchdog_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE wait_for_lane_up_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(wait_for_lane_up_r0),
        .Q(wait_for_lane_up_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX
   (hard_err_reset_i,
    D,
    hard_err_flop_r_reg_0,
    user_clk,
    ENABLE_ERR_DETECT);
  output hard_err_reset_i;
  output [0:0]D;
  input hard_err_flop_r_reg_0;
  input user_clk;
  input ENABLE_ERR_DETECT;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire HARD_ERR_Buffer_i_1__2_n_0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire user_clk;

  LUT2 #(
    .INIT(4'h8)) 
    HARD_ERR_Buffer_i_1__2
       (.I0(hard_err_reset_i),
        .I1(ENABLE_ERR_DETECT),
        .O(HARD_ERR_Buffer_i_1__2_n_0));
  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(HARD_ERR_Buffer_i_1__2_n_0),
        .Q(D),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r_reg_0),
        .Q(hard_err_reset_i),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11
   (hard_err_reset_i,
    D,
    hard_err_flop_r_reg_0,
    user_clk,
    ENABLE_ERR_DETECT);
  output hard_err_reset_i;
  output [0:0]D;
  input hard_err_flop_r_reg_0;
  input user_clk;
  input ENABLE_ERR_DETECT;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire HARD_ERR_Buffer_i_1_n_0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire user_clk;

  LUT2 #(
    .INIT(4'h8)) 
    HARD_ERR_Buffer_i_1
       (.I0(hard_err_reset_i),
        .I1(ENABLE_ERR_DETECT),
        .O(HARD_ERR_Buffer_i_1_n_0));
  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(HARD_ERR_Buffer_i_1_n_0),
        .Q(D),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r_reg_0),
        .Q(hard_err_reset_i),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5
   (hard_err_reset_i,
    D,
    hard_err_flop_r_reg_0,
    user_clk,
    ENABLE_ERR_DETECT);
  output hard_err_reset_i;
  output [0:0]D;
  input hard_err_flop_r_reg_0;
  input user_clk;
  input ENABLE_ERR_DETECT;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire HARD_ERR_Buffer_i_1__1_n_0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire user_clk;

  LUT2 #(
    .INIT(4'h8)) 
    HARD_ERR_Buffer_i_1__1
       (.I0(hard_err_reset_i),
        .I1(ENABLE_ERR_DETECT),
        .O(HARD_ERR_Buffer_i_1__1_n_0));
  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(HARD_ERR_Buffer_i_1__1_n_0),
        .Q(D),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r_reg_0),
        .Q(hard_err_reset_i),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8
   (hard_err_reset_i,
    D,
    hard_err_flop_r_reg_0,
    user_clk,
    ENABLE_ERR_DETECT);
  output hard_err_reset_i;
  output [0:0]D;
  input hard_err_flop_r_reg_0;
  input user_clk;
  input ENABLE_ERR_DETECT;

  wire [0:0]D;
  wire ENABLE_ERR_DETECT;
  wire HARD_ERR_Buffer_i_1__0_n_0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire user_clk;

  LUT2 #(
    .INIT(4'h8)) 
    HARD_ERR_Buffer_i_1__0
       (.I0(hard_err_reset_i),
        .I1(ENABLE_ERR_DETECT),
        .O(HARD_ERR_Buffer_i_1__0_n_0));
  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(HARD_ERR_Buffer_i_1__0_n_0),
        .Q(D),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r_reg_0),
        .Q(hard_err_reset_i),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX
   (TX_CHANNEL_UP,
    RESET,
    reset_lanes_flop_1_i,
    reset_lanes_flop_2_i,
    reset_lanes_flop_3_i,
    gen_v_flop_0_i,
    gen_v_flop_2_i,
    gen_v_flop_4_i,
    gen_v_flop_6_i,
    GEN_A,
    gen_a_flop_1_i,
    gen_a_flop_2_i,
    gen_a_flop_3_i,
    gen_k_flop_0_i,
    gen_k_flop_2_i,
    gen_k_flop_4_i,
    gen_k_flop_6_i,
    gen_r_flop_0_i,
    gen_r_flop_2_i,
    gen_r_flop_4_i,
    gen_r_flop_6_i,
    CHANNEL_HARD_ERR_Buffer_reg,
    reset_channel_i,
    tx_verify_simplex_r_reg,
    tx_bonded1_simplex_r_reg,
    tx_aligned_simplex_r_reg,
    tx_reset_simplex_r_reg,
    simplex_timer_r0,
    SS,
    reset_lanes_flop_1_i_0,
    reset_lanes_flop_2_i_0,
    reset_lanes_flop_3_i_0,
    tx_channel_up_i,
    user_clk,
    RESET_SYMGEN,
    POWER_DOWN,
    tx_verify_simplex_r,
    wait_for_lane_up_r0,
    tx_verify_simplex_r_reg_0,
    tx_bonded1_simplex_r_reg_0,
    tx_verify_simplex_r_reg_1,
    tx_bonded1_simplex_r,
    tx_bonded1_simplex_r_reg_1,
    tx_bonded1_simplex_r_reg_2,
    tx_aligned_simplex_r,
    tx_aligned_simplex_r_reg_0,
    tx_aligned_simplex_r_reg_1,
    tx_aligned_simplex_r_reg_2,
    tx_reset_simplex_r,
    tx_reset_simplex_r_reg_0,
    simplex_timer_r_reg,
    hard_err_reset_i,
    hard_err_reset_i_0,
    hard_err_reset_i_1,
    hard_err_reset_i_2,
    reset_lanes_flop_3_i_1,
    D,
    TX_LANE_UP);
  output TX_CHANNEL_UP;
  output RESET;
  output reset_lanes_flop_1_i;
  output reset_lanes_flop_2_i;
  output reset_lanes_flop_3_i;
  output [1:0]gen_v_flop_0_i;
  output [1:0]gen_v_flop_2_i;
  output [1:0]gen_v_flop_4_i;
  output [1:0]gen_v_flop_6_i;
  output GEN_A;
  output gen_a_flop_1_i;
  output gen_a_flop_2_i;
  output gen_a_flop_3_i;
  output [1:0]gen_k_flop_0_i;
  output [1:0]gen_k_flop_2_i;
  output [1:0]gen_k_flop_4_i;
  output [1:0]gen_k_flop_6_i;
  output [1:0]gen_r_flop_0_i;
  output [1:0]gen_r_flop_2_i;
  output [1:0]gen_r_flop_4_i;
  output [1:0]gen_r_flop_6_i;
  output CHANNEL_HARD_ERR_Buffer_reg;
  output reset_channel_i;
  output tx_verify_simplex_r_reg;
  output tx_bonded1_simplex_r_reg;
  output tx_aligned_simplex_r_reg;
  output tx_reset_simplex_r_reg;
  output simplex_timer_r0;
  output [0:0]SS;
  output [0:0]reset_lanes_flop_1_i_0;
  output [0:0]reset_lanes_flop_2_i_0;
  output [0:0]reset_lanes_flop_3_i_0;
  output tx_channel_up_i;
  input user_clk;
  input RESET_SYMGEN;
  input POWER_DOWN;
  input tx_verify_simplex_r;
  input wait_for_lane_up_r0;
  input tx_verify_simplex_r_reg_0;
  input tx_bonded1_simplex_r_reg_0;
  input tx_verify_simplex_r_reg_1;
  input tx_bonded1_simplex_r;
  input tx_bonded1_simplex_r_reg_1;
  input tx_bonded1_simplex_r_reg_2;
  input tx_aligned_simplex_r;
  input tx_aligned_simplex_r_reg_0;
  input tx_aligned_simplex_r_reg_1;
  input tx_aligned_simplex_r_reg_2;
  input tx_reset_simplex_r;
  input tx_reset_simplex_r_reg_0;
  input [2:0]simplex_timer_r_reg;
  input hard_err_reset_i;
  input hard_err_reset_i_0;
  input hard_err_reset_i_1;
  input hard_err_reset_i_2;
  input reset_lanes_flop_3_i_1;
  input [3:0]D;
  input [0:3]TX_LANE_UP;

  wire CHANNEL_HARD_ERR_Buffer_reg;
  wire [3:0]D;
  wire GEN_A;
  wire POWER_DOWN;
  wire RESET;
  wire RESET_SYMGEN;
  wire [0:0]SS;
  wire TX_CHANNEL_UP;
  wire [0:3]TX_LANE_UP;
  wire gen_a_flop_1_i;
  wire gen_a_flop_2_i;
  wire gen_a_flop_3_i;
  wire [1:0]gen_k_flop_0_i;
  wire [1:0]gen_k_flop_2_i;
  wire [1:0]gen_k_flop_4_i;
  wire [1:0]gen_k_flop_6_i;
  wire [1:0]gen_r_flop_0_i;
  wire [1:0]gen_r_flop_2_i;
  wire [1:0]gen_r_flop_4_i;
  wire [1:0]gen_r_flop_6_i;
  wire [1:0]gen_v_flop_0_i;
  wire [1:0]gen_v_flop_2_i;
  wire [1:0]gen_v_flop_4_i;
  wire [1:0]gen_v_flop_6_i;
  wire gen_ver_i;
  wire hard_err_reset_i;
  wire hard_err_reset_i_0;
  wire hard_err_reset_i_1;
  wire hard_err_reset_i_2;
  wire reset_channel_i;
  wire reset_lanes_flop_1_i;
  wire [0:0]reset_lanes_flop_1_i_0;
  wire reset_lanes_flop_2_i;
  wire [0:0]reset_lanes_flop_2_i_0;
  wire reset_lanes_flop_3_i;
  wire [0:0]reset_lanes_flop_3_i_0;
  wire reset_lanes_flop_3_i_1;
  wire simplex_timer_r0;
  wire [2:0]simplex_timer_r_reg;
  wire tx_aligned_simplex_r;
  wire tx_aligned_simplex_r_reg;
  wire tx_aligned_simplex_r_reg_0;
  wire tx_aligned_simplex_r_reg_1;
  wire tx_aligned_simplex_r_reg_2;
  wire tx_bonded1_simplex_r;
  wire tx_bonded1_simplex_r_reg;
  wire tx_bonded1_simplex_r_reg_0;
  wire tx_bonded1_simplex_r_reg_1;
  wire tx_bonded1_simplex_r_reg_2;
  wire tx_channel_up_i;
  wire tx_reset_simplex_r;
  wire tx_reset_simplex_r_reg;
  wire tx_reset_simplex_r_reg_0;
  wire tx_verify_simplex_r;
  wire tx_verify_simplex_r_reg;
  wire tx_verify_simplex_r_reg_0;
  wire tx_verify_simplex_r_reg_1;
  wire user_clk;
  wire wait_for_lane_up_r0;

  efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN idle_and_ver_gen_i
       (.GEN_A(GEN_A),
        .RESET_SYMGEN(RESET_SYMGEN),
        .\downcounter_r_reg[0]_0 (reset_lanes_flop_3_i_1),
        .gen_a_flop_1_i_0(gen_a_flop_1_i),
        .gen_a_flop_2_i_0(gen_a_flop_2_i),
        .gen_a_flop_3_i_0(gen_a_flop_3_i),
        .gen_k_flop_0_i_0(gen_k_flop_0_i),
        .gen_k_flop_2_i_0(gen_k_flop_2_i),
        .gen_k_flop_4_i_0(gen_k_flop_4_i),
        .gen_k_flop_6_i_0(gen_k_flop_6_i),
        .gen_r_flop_0_i_0(gen_r_flop_0_i),
        .gen_r_flop_2_i_0(gen_r_flop_2_i),
        .gen_r_flop_4_i_0(gen_r_flop_4_i),
        .gen_r_flop_6_i_0(gen_r_flop_6_i),
        .gen_v_flop_0_i_0(gen_v_flop_0_i),
        .gen_v_flop_2_i_0(gen_v_flop_2_i),
        .gen_v_flop_4_i_0(gen_v_flop_4_i),
        .gen_v_flop_6_i_0(gen_v_flop_6_i),
        .gen_ver_i(gen_ver_i),
        .tx_reset_simplex_r(tx_reset_simplex_r),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX tx_channel_err_detect_simplex_i
       (.CHANNEL_HARD_ERR_Buffer_reg_0(CHANNEL_HARD_ERR_Buffer_reg),
        .D(D),
        .POWER_DOWN(POWER_DOWN),
        .RESET_SYMGEN(RESET_SYMGEN),
        .TX_LANE_UP(TX_LANE_UP),
        .reset_channel_i(reset_channel_i),
        .simplex_timer_r0(simplex_timer_r0),
        .simplex_timer_r_reg(simplex_timer_r_reg),
        .simplex_timer_r_reg_0_sp_1(reset_lanes_flop_3_i_1),
        .tx_aligned_simplex_r(tx_aligned_simplex_r),
        .tx_aligned_simplex_r_reg(tx_aligned_simplex_r_reg),
        .tx_aligned_simplex_r_reg_0(tx_aligned_simplex_r_reg_0),
        .tx_aligned_simplex_r_reg_1(tx_aligned_simplex_r_reg_1),
        .tx_aligned_simplex_r_reg_2(tx_aligned_simplex_r_reg_2),
        .tx_bonded1_simplex_r(tx_bonded1_simplex_r),
        .tx_bonded1_simplex_r_reg(tx_bonded1_simplex_r_reg),
        .tx_bonded1_simplex_r_reg_0(tx_bonded1_simplex_r_reg_0),
        .tx_bonded1_simplex_r_reg_1(tx_bonded1_simplex_r_reg_1),
        .tx_bonded1_simplex_r_reg_2(tx_bonded1_simplex_r_reg_2),
        .tx_reset_simplex_r(tx_reset_simplex_r),
        .tx_reset_simplex_r_reg(tx_reset_simplex_r_reg),
        .tx_reset_simplex_r_reg_0(tx_reset_simplex_r_reg_0),
        .tx_verify_simplex_r(tx_verify_simplex_r),
        .tx_verify_simplex_r_reg(tx_verify_simplex_r_reg),
        .tx_verify_simplex_r_reg_0(tx_verify_simplex_r_reg_0),
        .tx_verify_simplex_r_reg_1(tx_verify_simplex_r_reg_1),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX tx_channel_init_sm_simplex_i
       (.RESET(RESET),
        .SS(SS),
        .TX_CHANNEL_UP(TX_CHANNEL_UP),
        .gen_ver_i(gen_ver_i),
        .hard_err_reset_i(hard_err_reset_i),
        .hard_err_reset_i_0(hard_err_reset_i_0),
        .hard_err_reset_i_1(hard_err_reset_i_1),
        .hard_err_reset_i_2(hard_err_reset_i_2),
        .reset_channel_i(reset_channel_i),
        .reset_lanes_flop_1_i_0(reset_lanes_flop_1_i),
        .reset_lanes_flop_1_i_1(reset_lanes_flop_1_i_0),
        .reset_lanes_flop_2_i_0(reset_lanes_flop_2_i),
        .reset_lanes_flop_2_i_1(reset_lanes_flop_2_i_0),
        .reset_lanes_flop_3_i_0(reset_lanes_flop_3_i),
        .reset_lanes_flop_3_i_1(reset_lanes_flop_3_i_0),
        .reset_lanes_flop_3_i_2(reset_lanes_flop_3_i_1),
        .tx_bonded1_simplex_r(tx_bonded1_simplex_r),
        .tx_channel_up_i_0(tx_channel_up_i),
        .tx_reset_simplex_r(tx_reset_simplex_r),
        .tx_verify_simplex_r(tx_verify_simplex_r),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(wait_for_lane_up_r0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX
   (TX_LANE_UP,
    ENABLE_ERR_DETECT,
    D,
    odd_word_r_reg_0,
    lane_up_flop_i_0,
    user_clk,
    SS,
    tx_aligned_r);
  output [0:0]TX_LANE_UP;
  output ENABLE_ERR_DETECT;
  output [1:0]D;
  output odd_word_r_reg_0;
  input lane_up_flop_i_0;
  input user_clk;
  input [0:0]SS;
  input tx_aligned_r;

  wire [1:0]D;
  wire D_0;
  wire ENABLE_ERR_DETECT;
  wire [0:0]SS;
  wire [0:0]TX_LANE_UP;
  wire align_r;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[2] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire gtp_tx_reset_i_3;
  wire lane_up_flop_i_0;
  wire next_align_c;
  wire next_ready_c;
  wire next_rst_c;
  wire odd_word_r;
  wire odd_word_r0;
  wire odd_word_r_reg_0;
  wire [3:0]p_0_in;
  wire std_bool;
  wire tx_aligned_r;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(ENABLE_ERR_DETECT),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_1__2
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(std_bool),
        .I3(gtp_tx_reset_i_3),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \counter1_r[0]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .I3(std_bool),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[1]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[2] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[2]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[3]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(std_bool),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[2] ),
        .R(SS));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT2 #(
    .INIT(4'h2)) 
    gen_k_fsm_r_i_1__2
       (.I0(odd_word_r),
        .I1(D_0),
        .O(odd_word_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_sp_data_r[0]_i_1__2 
       (.I0(D_0),
        .I1(odd_word_r),
        .O(D[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sp_data_r[1]_i_1__2 
       (.I0(D_0),
        .O(D[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(TX_LANE_UP),
        .R(lane_up_flop_i_0));
  LUT1 #(
    .INIT(2'h1)) 
    odd_word_r_i_1__2
       (.I0(odd_word_r),
        .O(odd_word_r0));
  FDRE #(
    .INIT(1'b1)) 
    odd_word_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(odd_word_r0),
        .Q(odd_word_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    ready_r_i_1__2
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(D_0),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D_0),
        .R(SS));
  LUT2 #(
    .INIT(4'h2)) 
    rst_r_i_2__2
       (.I0(gtp_tx_reset_i_3),
        .I1(std_bool),
        .O(next_rst_c));
  FDSE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(gtp_tx_reset_i_3),
        .S(SS));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12
   (TX_LANE_UP,
    ENABLE_ERR_DETECT,
    tx_aligned_r,
    D,
    odd_word_r_reg_0,
    RESET,
    user_clk,
    SS,
    tx_aligned_simplex_r);
  output [0:0]TX_LANE_UP;
  output ENABLE_ERR_DETECT;
  output tx_aligned_r;
  output [1:0]D;
  output odd_word_r_reg_0;
  input RESET;
  input user_clk;
  input [0:0]SS;
  input tx_aligned_simplex_r;

  wire [1:0]D;
  wire D_0;
  wire ENABLE_ERR_DETECT;
  wire RESET;
  wire [0:0]SS;
  wire [0:0]TX_LANE_UP;
  wire align_r;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[2] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire gtp_tx_reset_i_0;
  wire next_align_c;
  wire next_ready_c;
  wire next_rst_c;
  wire odd_word_r;
  wire odd_word_r0;
  wire odd_word_r_reg_0;
  wire [3:0]p_0_in;
  wire std_bool;
  wire tx_aligned_r;
  wire tx_aligned_simplex_r;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(ENABLE_ERR_DETECT),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_1
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(std_bool),
        .I3(gtp_tx_reset_i_0),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \counter1_r[0]_i_1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .I3(std_bool),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[1]_i_1 
       (.I0(\counter1_r_reg_n_0_[2] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[2]_i_1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[3]_i_1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(std_bool),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[2] ),
        .R(SS));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h2)) 
    gen_k_fsm_r_i_1
       (.I0(odd_word_r),
        .I1(D_0),
        .O(odd_word_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_sp_data_r[0]_i_1 
       (.I0(D_0),
        .I1(odd_word_r),
        .O(D[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sp_data_r[1]_i_1 
       (.I0(D_0),
        .O(D[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(TX_LANE_UP),
        .R(RESET));
  LUT1 #(
    .INIT(2'h1)) 
    odd_word_r_i_1
       (.I0(odd_word_r),
        .O(odd_word_r0));
  FDRE #(
    .INIT(1'b1)) 
    odd_word_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(odd_word_r0),
        .Q(odd_word_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    ready_r_i_1
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(D_0),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D_0),
        .R(SS));
  LUT2 #(
    .INIT(4'h2)) 
    rst_r_i_2
       (.I0(gtp_tx_reset_i_0),
        .I1(std_bool),
        .O(next_rst_c));
  FDSE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(gtp_tx_reset_i_0),
        .S(SS));
  FDRE #(
    .INIT(1'b1)) 
    tx_aligned_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_aligned_simplex_r),
        .Q(tx_aligned_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6
   (TX_LANE_UP,
    ENABLE_ERR_DETECT,
    D,
    odd_word_r_reg_0,
    lane_up_flop_i_0,
    user_clk,
    SS,
    tx_aligned_r);
  output [0:0]TX_LANE_UP;
  output ENABLE_ERR_DETECT;
  output [1:0]D;
  output odd_word_r_reg_0;
  input lane_up_flop_i_0;
  input user_clk;
  input [0:0]SS;
  input tx_aligned_r;

  wire [1:0]D;
  wire D_0;
  wire ENABLE_ERR_DETECT;
  wire [0:0]SS;
  wire [0:0]TX_LANE_UP;
  wire align_r;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[2] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire gtp_tx_reset_i_2;
  wire lane_up_flop_i_0;
  wire next_align_c;
  wire next_ready_c;
  wire next_rst_c;
  wire odd_word_r;
  wire odd_word_r0;
  wire odd_word_r_reg_0;
  wire [3:0]p_0_in;
  wire std_bool;
  wire tx_aligned_r;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(ENABLE_ERR_DETECT),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_1__1
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(std_bool),
        .I3(gtp_tx_reset_i_2),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \counter1_r[0]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .I3(std_bool),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[1]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[2] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[2]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[3]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(std_bool),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[2] ),
        .R(SS));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'h2)) 
    gen_k_fsm_r_i_1__1
       (.I0(odd_word_r),
        .I1(D_0),
        .O(odd_word_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_sp_data_r[0]_i_1__1 
       (.I0(D_0),
        .I1(odd_word_r),
        .O(D[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sp_data_r[1]_i_1__1 
       (.I0(D_0),
        .O(D[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(TX_LANE_UP),
        .R(lane_up_flop_i_0));
  LUT1 #(
    .INIT(2'h1)) 
    odd_word_r_i_1__1
       (.I0(odd_word_r),
        .O(odd_word_r0));
  FDRE #(
    .INIT(1'b1)) 
    odd_word_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(odd_word_r0),
        .Q(odd_word_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    ready_r_i_1__1
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(D_0),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D_0),
        .R(SS));
  LUT2 #(
    .INIT(4'h2)) 
    rst_r_i_2__1
       (.I0(gtp_tx_reset_i_2),
        .I1(std_bool),
        .O(next_rst_c));
  FDSE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(gtp_tx_reset_i_2),
        .S(SS));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9
   (TX_LANE_UP,
    ENABLE_ERR_DETECT,
    D,
    odd_word_r_reg_0,
    lane_up_flop_i_0,
    user_clk,
    SS,
    tx_aligned_r);
  output [0:0]TX_LANE_UP;
  output ENABLE_ERR_DETECT;
  output [1:0]D;
  output odd_word_r_reg_0;
  input lane_up_flop_i_0;
  input user_clk;
  input [0:0]SS;
  input tx_aligned_r;

  wire [1:0]D;
  wire D_0;
  wire ENABLE_ERR_DETECT;
  wire [0:0]SS;
  wire [0:0]TX_LANE_UP;
  wire align_r;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[2] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire gtp_tx_reset_i_1;
  wire lane_up_flop_i_0;
  wire next_align_c;
  wire next_ready_c;
  wire next_rst_c;
  wire odd_word_r;
  wire odd_word_r0;
  wire odd_word_r_reg_0;
  wire [3:0]p_0_in;
  wire std_bool;
  wire tx_aligned_r;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(ENABLE_ERR_DETECT),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_1__0
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(std_bool),
        .I3(gtp_tx_reset_i_1),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \counter1_r[0]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .I3(std_bool),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[1]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[2] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[2]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[2] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[3]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(std_bool),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[2] ),
        .R(SS));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h2)) 
    gen_k_fsm_r_i_1__0
       (.I0(odd_word_r),
        .I1(D_0),
        .O(odd_word_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_sp_data_r[0]_i_1__0 
       (.I0(D_0),
        .I1(odd_word_r),
        .O(D[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sp_data_r[1]_i_1__0 
       (.I0(D_0),
        .O(D[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(TX_LANE_UP),
        .R(lane_up_flop_i_0));
  LUT1 #(
    .INIT(2'h1)) 
    odd_word_r_i_1__0
       (.I0(odd_word_r),
        .O(odd_word_r0));
  FDRE #(
    .INIT(1'b1)) 
    odd_word_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(odd_word_r0),
        .Q(odd_word_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    ready_r_i_1__0
       (.I0(tx_aligned_r),
        .I1(align_r),
        .I2(D_0),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D_0),
        .R(SS));
  LUT2 #(
    .INIT(4'h2)) 
    rst_r_i_2__0
       (.I0(gtp_tx_reset_i_1),
        .I1(std_bool),
        .O(next_rst_c));
  FDSE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(gtp_tx_reset_i_1),
        .S(SS));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LL" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LL
   (GEN_CC,
    gen_cc_flop_1_i,
    gen_cc_flop_2_i,
    gen_cc_flop_3_i,
    tx_dst_rdy,
    ufc_header_r_reg,
    gen_scp_i,
    gen_ecp_i,
    gen_suf_i,
    \s_axi_ufc_tx_tdata[2] ,
    \s_axi_ufc_tx_tdata[1] ,
    \s_axi_ufc_tx_tdata[0] ,
    S_AXI_TX_TREADY,
    \ufc_message_count_r_reg[2] ,
    Q,
    \GEN_PAD_Buffer_reg[0] ,
    \TX_PE_DATA_Buffer_reg[0] ,
    user_clk,
    DO_CC_I,
    halt_c_pipeline_r_reg_inv,
    next_ufc_header_c,
    next_ufc_idle_c,
    S_AXI_UFC_TX_MS,
    S_AXI_TX_TVALID,
    S_AXI_TX_TLAST,
    tx_sof_n_pipeline_r_reg,
    S_AXI_TX_TKEEP,
    WARN_CC,
    S_AXI_UFC_TX_REQ,
    S_AXI_TX_TDATA);
  output GEN_CC;
  output gen_cc_flop_1_i;
  output gen_cc_flop_2_i;
  output gen_cc_flop_3_i;
  output tx_dst_rdy;
  output ufc_header_r_reg;
  output gen_scp_i;
  output gen_ecp_i;
  output gen_suf_i;
  output \s_axi_ufc_tx_tdata[2] ;
  output \s_axi_ufc_tx_tdata[1] ;
  output \s_axi_ufc_tx_tdata[0] ;
  output S_AXI_TX_TREADY;
  output \ufc_message_count_r_reg[2] ;
  output [3:0]Q;
  output [3:0]\GEN_PAD_Buffer_reg[0] ;
  output [63:0]\TX_PE_DATA_Buffer_reg[0] ;
  input user_clk;
  input DO_CC_I;
  input halt_c_pipeline_r_reg_inv;
  input next_ufc_header_c;
  input next_ufc_idle_c;
  input [2:0]S_AXI_UFC_TX_MS;
  input S_AXI_TX_TVALID;
  input S_AXI_TX_TLAST;
  input tx_sof_n_pipeline_r_reg;
  input [7:0]S_AXI_TX_TKEEP;
  input WARN_CC;
  input S_AXI_UFC_TX_REQ;
  input [63:0]S_AXI_TX_TDATA;

  wire DO_CC_I;
  wire GEN_CC;
  wire [3:0]\GEN_PAD_Buffer_reg[0] ;
  wire [3:0]Q;
  wire [63:0]S_AXI_TX_TDATA;
  wire [7:0]S_AXI_TX_TKEEP;
  wire S_AXI_TX_TLAST;
  wire S_AXI_TX_TREADY;
  wire S_AXI_TX_TVALID;
  wire [2:0]S_AXI_UFC_TX_MS;
  wire S_AXI_UFC_TX_REQ;
  wire [63:0]\TX_PE_DATA_Buffer_reg[0] ;
  wire UFC_MESSAGE_Buffer0;
  wire WARN_CC;
  wire gen_cc_flop_1_i;
  wire gen_cc_flop_2_i;
  wire gen_cc_flop_3_i;
  wire gen_ecp_i;
  wire gen_scp_i;
  wire gen_suf_i;
  wire halt_c_pipeline_r_reg_inv;
  wire next_ufc_header_c;
  wire next_ufc_idle_c;
  wire \s_axi_ufc_tx_tdata[0] ;
  wire \s_axi_ufc_tx_tdata[1] ;
  wire \s_axi_ufc_tx_tdata[2] ;
  wire tx_dst_rdy;
  wire tx_ll_control_i_n_16;
  wire tx_ll_control_i_n_20;
  wire tx_ll_datapath_i_n_0;
  wire tx_ll_datapath_i_n_1;
  wire [0:0]tx_rem;
  wire tx_sof;
  wire tx_sof_n_pipeline_r_reg;
  wire ufc_header_r_reg;
  wire \ufc_message_count_r_reg[2] ;
  wire [1:2]ufc_message_i;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL tx_ll_control_i
       (.D({tx_ll_control_i_n_16,ufc_message_i[1],ufc_message_i[2],UFC_MESSAGE_Buffer0}),
        .DO_CC_I(DO_CC_I),
        .GEN_CC(GEN_CC),
        .GEN_SUF_Buffer_reg_0(halt_c_pipeline_r_reg_inv),
        .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
        .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
        .S_AXI_TX_TREADY(S_AXI_TX_TREADY),
        .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
        .S_AXI_UFC_TX_MS(S_AXI_UFC_TX_MS),
        .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
        .TX_DST_RDY_N_Buffer_reg_0(tx_dst_rdy),
        .WARN_CC(WARN_CC),
        .do_cc_r_reg_0(tx_ll_control_i_n_20),
        .gen_cc_flop_1_i_0(gen_cc_flop_1_i),
        .gen_cc_flop_2_i_0(gen_cc_flop_2_i),
        .gen_cc_flop_3_i_0(gen_cc_flop_3_i),
        .gen_ecp_i(gen_ecp_i),
        .gen_scp_i(gen_scp_i),
        .gen_suf_i(gen_suf_i),
        .next_ufc_header_c(next_ufc_header_c),
        .next_ufc_idle_c(next_ufc_idle_c),
        .\s_axi_ufc_tx_tdata[0] (\s_axi_ufc_tx_tdata[0] ),
        .\s_axi_ufc_tx_tdata[1] (\s_axi_ufc_tx_tdata[1] ),
        .\s_axi_ufc_tx_tdata[2] (\s_axi_ufc_tx_tdata[2] ),
        .tx_rem(tx_rem),
        .\tx_rem_pipeline_r_reg[0] (tx_ll_datapath_i_n_1),
        .\tx_rem_pipeline_r_reg[0]_0 (tx_ll_datapath_i_n_0),
        .tx_sof(tx_sof),
        .tx_sof_n_pipeline_r_reg(tx_sof_n_pipeline_r_reg),
        .ufc_header_r_reg_0(ufc_header_r_reg),
        .\ufc_message_count_r_reg[2]_0 (\ufc_message_count_r_reg[2] ),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH tx_ll_datapath_i
       (.D(tx_rem),
        .\GEN_PAD_Buffer_reg[0]_0 (\GEN_PAD_Buffer_reg[0] ),
        .Q(Q),
        .S_AXI_TX_TDATA(S_AXI_TX_TDATA),
        .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
        .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
        .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
        .\TX_PE_DATA_Buffer_reg[0]_0 (\TX_PE_DATA_Buffer_reg[0] ),
        .halt_c_pipeline_r_reg_inv_0(halt_c_pipeline_r_reg_inv),
        .halt_c_pipeline_r_reg_inv_1(tx_ll_control_i_n_20),
        .\s_axi_tx_tkeep[4] (tx_ll_datapath_i_n_0),
        .\s_axi_tx_tkeep[5] (tx_ll_datapath_i_n_1),
        .tx_dst_rdy(tx_dst_rdy),
        .tx_sof(tx_sof),
        .\ufc_message_pipeline_r_reg[0]_0 ({tx_ll_control_i_n_16,ufc_message_i[1],ufc_message_i[2],UFC_MESSAGE_Buffer0}),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LL_CONTROL" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL
   (GEN_CC,
    gen_cc_flop_1_i_0,
    gen_cc_flop_2_i_0,
    gen_cc_flop_3_i_0,
    TX_DST_RDY_N_Buffer_reg_0,
    ufc_header_r_reg_0,
    gen_scp_i,
    gen_ecp_i,
    gen_suf_i,
    \s_axi_ufc_tx_tdata[2] ,
    \s_axi_ufc_tx_tdata[1] ,
    \s_axi_ufc_tx_tdata[0] ,
    S_AXI_TX_TREADY,
    \ufc_message_count_r_reg[2]_0 ,
    tx_rem,
    tx_sof,
    D,
    do_cc_r_reg_0,
    user_clk,
    DO_CC_I,
    GEN_SUF_Buffer_reg_0,
    next_ufc_header_c,
    next_ufc_idle_c,
    S_AXI_UFC_TX_MS,
    S_AXI_TX_TLAST,
    tx_sof_n_pipeline_r_reg,
    S_AXI_TX_TVALID,
    \tx_rem_pipeline_r_reg[0] ,
    \tx_rem_pipeline_r_reg[0]_0 ,
    S_AXI_TX_TKEEP,
    WARN_CC,
    S_AXI_UFC_TX_REQ);
  output GEN_CC;
  output gen_cc_flop_1_i_0;
  output gen_cc_flop_2_i_0;
  output gen_cc_flop_3_i_0;
  output TX_DST_RDY_N_Buffer_reg_0;
  output ufc_header_r_reg_0;
  output gen_scp_i;
  output gen_ecp_i;
  output gen_suf_i;
  output \s_axi_ufc_tx_tdata[2] ;
  output \s_axi_ufc_tx_tdata[1] ;
  output \s_axi_ufc_tx_tdata[0] ;
  output S_AXI_TX_TREADY;
  output \ufc_message_count_r_reg[2]_0 ;
  output [0:0]tx_rem;
  output tx_sof;
  output [3:0]D;
  output do_cc_r_reg_0;
  input user_clk;
  input DO_CC_I;
  input GEN_SUF_Buffer_reg_0;
  input next_ufc_header_c;
  input next_ufc_idle_c;
  input [2:0]S_AXI_UFC_TX_MS;
  input S_AXI_TX_TLAST;
  input tx_sof_n_pipeline_r_reg;
  input S_AXI_TX_TVALID;
  input \tx_rem_pipeline_r_reg[0] ;
  input \tx_rem_pipeline_r_reg[0]_0 ;
  input [7:0]S_AXI_TX_TKEEP;
  input WARN_CC;
  input S_AXI_UFC_TX_REQ;

  wire [3:0]D;
  wire DO_CC_I;
  wire D_0;
  wire GEN_CC;
  wire GEN_SUF_Buffer_reg_0;
  wire [7:0]S_AXI_TX_TKEEP;
  wire S_AXI_TX_TLAST;
  wire S_AXI_TX_TREADY;
  wire S_AXI_TX_TVALID;
  wire [2:0]S_AXI_UFC_TX_MS;
  wire S_AXI_UFC_TX_REQ;
  wire TX_DST_RDY_N_Buffer_i_2_n_0;
  wire TX_DST_RDY_N_Buffer_i_3_n_0;
  wire TX_DST_RDY_N_Buffer_i_4_n_0;
  wire TX_DST_RDY_N_Buffer_i_5_n_0;
  wire TX_DST_RDY_N_Buffer_i_6_n_0;
  wire TX_DST_RDY_N_Buffer_reg_0;
  wire WARN_CC;
  wire data_r;
  wire data_to_eof_1_r;
  wire data_to_eof_2_r;
  wire do_cc_r;
  wire do_cc_r_reg_0;
  wire eof_r;
  wire gen_cc_flop_1_i_0;
  wire gen_cc_flop_2_i_0;
  wire gen_cc_flop_3_i_0;
  wire gen_ecp_i;
  wire gen_ecp_pipeline_r;
  wire gen_ecp_pipeline_r0;
  wire gen_scp_i;
  wire gen_scp_pipeline_r;
  wire gen_scp_pipeline_r0;
  wire gen_suf_i;
  wire gen_suf_pipeline_r;
  wire idle_r;
  wire next_data_c;
  wire next_data_to_eof_1_c;
  wire next_eof_c;
  wire next_idle_c;
  wire next_sof_and_eof_c;
  wire next_sof_to_data_c;
  wire next_sof_to_eof_1_c;
  wire next_ufc_header_c;
  wire next_ufc_idle_c;
  wire next_ufc_message1_c;
  wire next_ufc_message2_c;
  wire next_ufc_message3_c;
  wire next_ufc_message4_c;
  wire next_ufc_message5_c;
  wire next_ufc_message6_c;
  wire next_ufc_message7_c;
  wire next_ufc_message8_c;
  wire pdu_ok_c;
  wire \s_axi_ufc_tx_tdata[0] ;
  wire \s_axi_ufc_tx_tdata[1] ;
  wire \s_axi_ufc_tx_tdata[2] ;
  wire sof_and_eof_r;
  wire sof_and_eof_r_i_2_n_0;
  wire sof_to_data_r;
  wire sof_to_eof_1_r;
  wire sof_to_eof_2_r;
  wire suf_delay_1_r;
  wire suf_delay_2_r;
  wire tx_dst_rdy_n_c;
  wire [0:0]tx_rem;
  wire \tx_rem_pipeline_r[0]_i_3_n_0 ;
  wire \tx_rem_pipeline_r[0]_i_5_n_0 ;
  wire \tx_rem_pipeline_r_reg[0] ;
  wire \tx_rem_pipeline_r_reg[0]_0 ;
  wire tx_sof;
  wire tx_sof_n_pipeline_r_reg;
  wire ufc_header_r_i_4_n_0;
  wire ufc_header_r_i_5_n_0;
  wire ufc_header_r_reg_0;
  wire ufc_idle_r;
  wire ufc_message1_r;
  wire ufc_message2_r;
  wire ufc_message3_r;
  wire ufc_message4_r;
  wire ufc_message5_r;
  wire ufc_message6_r;
  wire ufc_message7_r;
  wire ufc_message8_r;
  wire [0:2]ufc_message_count_r;
  wire \ufc_message_count_r[0]_i_1_n_0 ;
  wire \ufc_message_count_r[1]_i_1_n_0 ;
  wire \ufc_message_count_r[2]_i_1_n_0 ;
  wire \ufc_message_count_r_reg[2]_0 ;
  wire user_clk;

  (* srl_bus_name = "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *) 
  (* srl_name = "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[0]_srl4 " *) 
  SRL16E \FC_NB_Buffer_reg[0]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(S_AXI_UFC_TX_MS[2]),
        .Q(\s_axi_ufc_tx_tdata[2] ));
  (* srl_bus_name = "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *) 
  (* srl_name = "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[1]_srl4 " *) 
  SRL16E \FC_NB_Buffer_reg[1]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(S_AXI_UFC_TX_MS[1]),
        .Q(\s_axi_ufc_tx_tdata[1] ));
  (* srl_bus_name = "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg " *) 
  (* srl_name = "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[2]_srl4 " *) 
  SRL16E \FC_NB_Buffer_reg[2]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(S_AXI_UFC_TX_MS[0]),
        .Q(\s_axi_ufc_tx_tdata[0] ));
  FDRE GEN_ECP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_ecp_pipeline_r),
        .Q(gen_ecp_i),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE GEN_SCP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_scp_pipeline_r),
        .Q(gen_scp_i),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE GEN_SUF_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_suf_pipeline_r),
        .Q(gen_suf_i),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT1 #(
    .INIT(2'h1)) 
    S_AXI_TX_TREADY_INST_0
       (.I0(TX_DST_RDY_N_Buffer_reg_0),
        .O(S_AXI_TX_TREADY));
  LUT6 #(
    .INIT(64'hEFEFEFEFFFEFEFEF)) 
    TX_DST_RDY_N_Buffer_i_1
       (.I0(TX_DST_RDY_N_Buffer_i_2_n_0),
        .I1(DO_CC_I),
        .I2(\ufc_message_count_r_reg[2]_0 ),
        .I3(TX_DST_RDY_N_Buffer_i_3_n_0),
        .I4(tx_rem),
        .I5(do_cc_r),
        .O(tx_dst_rdy_n_c));
  LUT6 #(
    .INIT(64'hFFFFFFFFF4F4F444)) 
    TX_DST_RDY_N_Buffer_i_2
       (.I0(WARN_CC),
        .I1(S_AXI_UFC_TX_REQ),
        .I2(do_cc_r),
        .I3(sof_to_eof_1_r),
        .I4(data_to_eof_1_r),
        .I5(TX_DST_RDY_N_Buffer_i_4_n_0),
        .O(TX_DST_RDY_N_Buffer_i_2_n_0));
  LUT6 #(
    .INIT(64'h000088C800000000)) 
    TX_DST_RDY_N_Buffer_i_3
       (.I0(TX_DST_RDY_N_Buffer_i_5_n_0),
        .I1(S_AXI_TX_TLAST),
        .I2(TX_DST_RDY_N_Buffer_i_6_n_0),
        .I3(tx_sof_n_pipeline_r_reg),
        .I4(TX_DST_RDY_N_Buffer_reg_0),
        .I5(S_AXI_TX_TVALID),
        .O(TX_DST_RDY_N_Buffer_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    TX_DST_RDY_N_Buffer_i_4
       (.I0(data_r),
        .I1(sof_to_data_r),
        .I2(ufc_idle_r),
        .I3(ufc_header_r_reg_0),
        .I4(sof_to_eof_1_r),
        .I5(data_to_eof_1_r),
        .O(TX_DST_RDY_N_Buffer_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT2 #(
    .INIT(4'hE)) 
    TX_DST_RDY_N_Buffer_i_5
       (.I0(data_r),
        .I1(sof_to_data_r),
        .O(TX_DST_RDY_N_Buffer_i_5_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    TX_DST_RDY_N_Buffer_i_6
       (.I0(data_to_eof_2_r),
        .I1(eof_r),
        .I2(sof_to_eof_2_r),
        .I3(sof_and_eof_r),
        .I4(idle_r),
        .O(TX_DST_RDY_N_Buffer_i_6_n_0));
  FDSE TX_DST_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_dst_rdy_n_c),
        .Q(TX_DST_RDY_N_Buffer_reg_0),
        .S(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT5 #(
    .INIT(32'hDFDFDF00)) 
    data_r_i_1
       (.I0(S_AXI_TX_TLAST),
        .I1(TX_DST_RDY_N_Buffer_reg_0),
        .I2(S_AXI_TX_TVALID),
        .I3(sof_to_data_r),
        .I4(data_r),
        .O(next_data_c));
  FDRE data_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_data_c),
        .Q(data_r),
        .R(GEN_SUF_Buffer_reg_0));
  LUT6 #(
    .INIT(64'h0000A80000000000)) 
    data_to_eof_1_r_i_1
       (.I0(tx_rem),
        .I1(data_r),
        .I2(sof_to_data_r),
        .I3(S_AXI_TX_TLAST),
        .I4(TX_DST_RDY_N_Buffer_reg_0),
        .I5(S_AXI_TX_TVALID),
        .O(next_data_to_eof_1_c));
  FDRE data_to_eof_1_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_data_to_eof_1_c),
        .Q(data_to_eof_1_r),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE data_to_eof_2_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(data_to_eof_1_r),
        .Q(data_to_eof_2_r),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE do_cc_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(DO_CC_I),
        .Q(do_cc_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    eof_r_i_1
       (.I0(do_cc_r),
        .O(pdu_ok_c));
  LUT6 #(
    .INIT(64'h0000540000000000)) 
    eof_r_i_2
       (.I0(tx_rem),
        .I1(data_r),
        .I2(sof_to_data_r),
        .I3(S_AXI_TX_TLAST),
        .I4(TX_DST_RDY_N_Buffer_reg_0),
        .I5(S_AXI_TX_TVALID),
        .O(next_eof_c));
  FDRE eof_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_eof_c),
        .Q(eof_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_cc_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(GEN_CC),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_cc_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(gen_cc_flop_1_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_cc_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(gen_cc_flop_2_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen_cc_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_0),
        .Q(gen_cc_flop_3_i_0),
        .R(1'b0));
  FDRE gen_cc_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(do_cc_r),
        .Q(D_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT5 #(
    .INIT(32'h0000FFFE)) 
    gen_ecp_pipeline_r_i_1
       (.I0(data_to_eof_2_r),
        .I1(eof_r),
        .I2(sof_to_eof_2_r),
        .I3(sof_and_eof_r),
        .I4(do_cc_r),
        .O(gen_ecp_pipeline_r0));
  FDRE gen_ecp_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_ecp_pipeline_r0),
        .Q(gen_ecp_pipeline_r),
        .R(GEN_SUF_Buffer_reg_0));
  LUT4 #(
    .INIT(16'h0F0E)) 
    gen_scp_pipeline_r_i_1
       (.I0(sof_to_data_r),
        .I1(sof_and_eof_r),
        .I2(do_cc_r),
        .I3(sof_to_eof_1_r),
        .O(gen_scp_pipeline_r0));
  FDRE gen_scp_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gen_scp_pipeline_r0),
        .Q(gen_scp_pipeline_r),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE gen_suf_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(suf_delay_2_r),
        .Q(gen_suf_pipeline_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT1 #(
    .INIT(2'h1)) 
    halt_c_pipeline_r_inv_i_1
       (.I0(do_cc_r),
        .O(do_cc_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000000)) 
    idle_r_i_1
       (.I0(idle_r),
        .I1(sof_and_eof_r),
        .I2(sof_to_eof_2_r),
        .I3(eof_r),
        .I4(data_to_eof_2_r),
        .I5(tx_sof),
        .O(next_idle_c));
  FDSE idle_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_idle_c),
        .Q(idle_r),
        .S(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'h40)) 
    sof_and_eof_r_i_1
       (.I0(tx_rem),
        .I1(S_AXI_TX_TLAST),
        .I2(sof_and_eof_r_i_2_n_0),
        .O(next_sof_and_eof_c));
  LUT6 #(
    .INIT(64'h00000000FFFFFFFE)) 
    sof_and_eof_r_i_2
       (.I0(idle_r),
        .I1(sof_and_eof_r),
        .I2(sof_to_eof_2_r),
        .I3(eof_r),
        .I4(data_to_eof_2_r),
        .I5(tx_sof),
        .O(sof_and_eof_r_i_2_n_0));
  FDRE sof_and_eof_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_sof_and_eof_c),
        .Q(sof_and_eof_r),
        .R(GEN_SUF_Buffer_reg_0));
  LUT2 #(
    .INIT(4'h2)) 
    sof_to_data_r_i_1
       (.I0(sof_and_eof_r_i_2_n_0),
        .I1(S_AXI_TX_TLAST),
        .O(next_sof_to_data_c));
  FDRE sof_to_data_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_sof_to_data_c),
        .Q(sof_to_data_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'h80)) 
    sof_to_eof_1_r_i_1
       (.I0(S_AXI_TX_TLAST),
        .I1(tx_rem),
        .I2(sof_and_eof_r_i_2_n_0),
        .O(next_sof_to_eof_1_c));
  FDRE sof_to_eof_1_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(next_sof_to_eof_1_c),
        .Q(sof_to_eof_1_r),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE sof_to_eof_2_r_reg
       (.C(user_clk),
        .CE(pdu_ok_c),
        .D(sof_to_eof_1_r),
        .Q(sof_to_eof_2_r),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE suf_delay_1_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ufc_header_r_reg_0),
        .Q(suf_delay_1_r),
        .R(GEN_SUF_Buffer_reg_0));
  FDRE suf_delay_2_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(suf_delay_1_r),
        .Q(suf_delay_2_r),
        .R(GEN_SUF_Buffer_reg_0));
  LUT6 #(
    .INIT(64'h107070F1EF8F8F0E)) 
    \tx_rem_pipeline_r[0]_i_1 
       (.I0(\tx_rem_pipeline_r_reg[0] ),
        .I1(\tx_rem_pipeline_r[0]_i_3_n_0 ),
        .I2(\tx_rem_pipeline_r_reg[0]_0 ),
        .I3(S_AXI_TX_TKEEP[1]),
        .I4(S_AXI_TX_TKEEP[2]),
        .I5(\tx_rem_pipeline_r[0]_i_5_n_0 ),
        .O(tx_rem));
  LUT3 #(
    .INIT(8'h96)) 
    \tx_rem_pipeline_r[0]_i_3 
       (.I0(S_AXI_TX_TKEEP[0]),
        .I1(S_AXI_TX_TKEEP[6]),
        .I2(S_AXI_TX_TKEEP[7]),
        .O(\tx_rem_pipeline_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000001700171717)) 
    \tx_rem_pipeline_r[0]_i_5 
       (.I0(S_AXI_TX_TKEEP[3]),
        .I1(S_AXI_TX_TKEEP[4]),
        .I2(S_AXI_TX_TKEEP[5]),
        .I3(S_AXI_TX_TKEEP[0]),
        .I4(S_AXI_TX_TKEEP[7]),
        .I5(S_AXI_TX_TKEEP[6]),
        .O(\tx_rem_pipeline_r[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    tx_sof_n_pipeline_r_i_1
       (.I0(S_AXI_TX_TVALID),
        .I1(TX_DST_RDY_N_Buffer_reg_0),
        .I2(tx_sof_n_pipeline_r_reg),
        .O(tx_sof));
  LUT6 #(
    .INIT(64'hFFFFFFFFAEAAAAAA)) 
    ufc_header_r_i_3
       (.I0(ufc_header_r_i_4_n_0),
        .I1(ufc_message_count_r[2]),
        .I2(ufc_message_count_r[0]),
        .I3(ufc_message4_r),
        .I4(ufc_message_count_r[1]),
        .I5(ufc_header_r_i_5_n_0),
        .O(\ufc_message_count_r_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    ufc_header_r_i_4
       (.I0(ufc_message6_r),
        .I1(ufc_message2_r),
        .I2(ufc_message5_r),
        .I3(ufc_message1_r),
        .I4(ufc_idle_r),
        .O(ufc_header_r_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    ufc_header_r_i_5
       (.I0(ufc_message8_r),
        .I1(ufc_message3_r),
        .I2(ufc_message7_r),
        .O(ufc_header_r_i_5_n_0));
  FDRE ufc_header_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_header_c),
        .Q(ufc_header_r_reg_0),
        .R(GEN_SUF_Buffer_reg_0));
  FDSE ufc_idle_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_idle_c),
        .Q(ufc_idle_r),
        .S(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    ufc_message1_r_i_1
       (.I0(ufc_message_count_r[1]),
        .I1(ufc_message_count_r[2]),
        .I2(ufc_message_count_r[0]),
        .I3(ufc_header_r_reg_0),
        .O(next_ufc_message1_c));
  FDRE ufc_message1_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message1_c),
        .Q(ufc_message1_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    ufc_message2_r_i_1
       (.I0(ufc_message_count_r[1]),
        .I1(ufc_header_r_reg_0),
        .I2(ufc_message_count_r[2]),
        .I3(ufc_message_count_r[0]),
        .O(next_ufc_message2_c));
  FDRE ufc_message2_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message2_c),
        .Q(ufc_message2_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    ufc_message3_r_i_1
       (.I0(ufc_message_count_r[2]),
        .I1(ufc_message_count_r[1]),
        .I2(ufc_message_count_r[0]),
        .I3(ufc_header_r_reg_0),
        .O(next_ufc_message3_c));
  FDRE ufc_message3_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message3_c),
        .Q(ufc_message3_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'hF080)) 
    ufc_message4_r_i_1
       (.I0(ufc_message_count_r[2]),
        .I1(ufc_message_count_r[1]),
        .I2(ufc_header_r_reg_0),
        .I3(ufc_message_count_r[0]),
        .O(next_ufc_message4_c));
  FDRE ufc_message4_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message4_c),
        .Q(ufc_message4_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    ufc_message5_r_i_1
       (.I0(ufc_message_count_r[1]),
        .I1(ufc_message_count_r[2]),
        .I2(ufc_message4_r),
        .I3(ufc_message_count_r[0]),
        .O(next_ufc_message5_c));
  FDRE ufc_message5_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message5_c),
        .Q(ufc_message5_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    ufc_message6_r_i_1
       (.I0(ufc_message_count_r[1]),
        .I1(ufc_message_count_r[2]),
        .I2(ufc_message4_r),
        .I3(ufc_message_count_r[0]),
        .O(next_ufc_message6_c));
  FDRE ufc_message6_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message6_c),
        .Q(ufc_message6_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    ufc_message7_r_i_1
       (.I0(ufc_message_count_r[2]),
        .I1(ufc_message_count_r[0]),
        .I2(ufc_message4_r),
        .I3(ufc_message_count_r[1]),
        .O(next_ufc_message7_c));
  FDRE ufc_message7_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message7_c),
        .Q(ufc_message7_r),
        .R(GEN_SUF_Buffer_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    ufc_message8_r_i_1
       (.I0(ufc_message_count_r[0]),
        .I1(ufc_message_count_r[2]),
        .I2(ufc_message4_r),
        .I3(ufc_message_count_r[1]),
        .O(next_ufc_message8_c));
  FDRE ufc_message8_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ufc_message8_c),
        .Q(ufc_message8_r),
        .R(GEN_SUF_Buffer_reg_0));
  LUT6 #(
    .INIT(64'hFFFBFFFF00080000)) 
    \ufc_message_count_r[0]_i_1 
       (.I0(S_AXI_UFC_TX_MS[2]),
        .I1(\ufc_message_count_r_reg[2]_0 ),
        .I2(DO_CC_I),
        .I3(WARN_CC),
        .I4(S_AXI_UFC_TX_REQ),
        .I5(ufc_message_count_r[0]),
        .O(\ufc_message_count_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBFFFF00080000)) 
    \ufc_message_count_r[1]_i_1 
       (.I0(S_AXI_UFC_TX_MS[1]),
        .I1(\ufc_message_count_r_reg[2]_0 ),
        .I2(DO_CC_I),
        .I3(WARN_CC),
        .I4(S_AXI_UFC_TX_REQ),
        .I5(ufc_message_count_r[1]),
        .O(\ufc_message_count_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBFFFF00080000)) 
    \ufc_message_count_r[2]_i_1 
       (.I0(S_AXI_UFC_TX_MS[0]),
        .I1(\ufc_message_count_r_reg[2]_0 ),
        .I2(DO_CC_I),
        .I3(WARN_CC),
        .I4(S_AXI_UFC_TX_REQ),
        .I5(ufc_message_count_r[2]),
        .O(\ufc_message_count_r[2]_i_1_n_0 ));
  FDRE \ufc_message_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_count_r[0]_i_1_n_0 ),
        .Q(ufc_message_count_r[0]),
        .R(1'b0));
  FDRE \ufc_message_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_count_r[1]_i_1_n_0 ),
        .Q(ufc_message_count_r[1]),
        .R(1'b0));
  FDRE \ufc_message_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_count_r[2]_i_1_n_0 ),
        .Q(ufc_message_count_r[2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ufc_message_pipeline_r[0]_i_1 
       (.I0(ufc_idle_r),
        .I1(ufc_header_r_reg_0),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \ufc_message_pipeline_r[1]_i_1 
       (.I0(ufc_message5_r),
        .I1(ufc_message1_r),
        .I2(ufc_idle_r),
        .I3(ufc_header_r_reg_0),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \ufc_message_pipeline_r[2]_i_1 
       (.I0(ufc_message7_r),
        .I1(ufc_message3_r),
        .I2(ufc_message8_r),
        .I3(ufc_message4_r),
        .O(D[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \ufc_message_pipeline_r[3]_i_1 
       (.I0(ufc_message8_r),
        .I1(ufc_message4_r),
        .O(D[0]));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_TX_LL_DATAPATH" *) 
module efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH
   (\s_axi_tx_tkeep[4] ,
    \s_axi_tx_tkeep[5] ,
    Q,
    \GEN_PAD_Buffer_reg[0]_0 ,
    \TX_PE_DATA_Buffer_reg[0]_0 ,
    halt_c_pipeline_r_reg_inv_0,
    tx_sof,
    user_clk,
    tx_dst_rdy,
    halt_c_pipeline_r_reg_inv_1,
    S_AXI_TX_TVALID,
    D,
    S_AXI_TX_TKEEP,
    S_AXI_TX_TLAST,
    \ufc_message_pipeline_r_reg[0]_0 ,
    S_AXI_TX_TDATA);
  output \s_axi_tx_tkeep[4] ;
  output \s_axi_tx_tkeep[5] ;
  output [3:0]Q;
  output [3:0]\GEN_PAD_Buffer_reg[0]_0 ;
  output [63:0]\TX_PE_DATA_Buffer_reg[0]_0 ;
  input halt_c_pipeline_r_reg_inv_0;
  input tx_sof;
  input user_clk;
  input tx_dst_rdy;
  input halt_c_pipeline_r_reg_inv_1;
  input S_AXI_TX_TVALID;
  input [0:0]D;
  input [7:0]S_AXI_TX_TKEEP;
  input S_AXI_TX_TLAST;
  input [3:0]\ufc_message_pipeline_r_reg[0]_0 ;
  input [63:0]S_AXI_TX_TDATA;

  wire [0:0]D;
  wire [3:0]\GEN_PAD_Buffer_reg[0]_0 ;
  wire [3:0]Q;
  wire [63:0]S_AXI_TX_TDATA;
  wire [7:0]S_AXI_TX_TKEEP;
  wire S_AXI_TX_TLAST;
  wire S_AXI_TX_TVALID;
  wire [63:0]\TX_PE_DATA_Buffer_reg[0]_0 ;
  wire TX_PE_DATA_V_Buffer2;
  wire \gen_pad_r[1]_i_1_n_0 ;
  wire \gen_pad_r[2]_i_1_n_0 ;
  wire \gen_pad_r[3]_i_1_n_0 ;
  wire \gen_pad_r_reg_n_0_[0] ;
  wire \gen_pad_r_reg_n_0_[3] ;
  wire halt_c_pipeline_r_reg_inv_0;
  wire halt_c_pipeline_r_reg_inv_1;
  wire in_frame_r_i_1_n_0;
  wire in_frame_r_reg_n_0;
  wire p_2_in;
  wire p_31_in;
  wire p_3_in;
  wire p_4_in;
  wire p_4_in10_in;
  wire p_5_in;
  wire p_6_in;
  wire p_7_in;
  wire [3:0]p_7_out;
  wire [3:0]p_8_out;
  wire \s_axi_tx_tkeep[4] ;
  wire \s_axi_tx_tkeep[5] ;
  wire storage_pad_r;
  wire storage_pad_r_i_1_n_0;
  wire [0:15]storage_r;
  wire storage_ufc_v_r;
  wire storage_v_r;
  wire \tx_d_pipeline_r_reg_n_0_[0] ;
  wire \tx_d_pipeline_r_reg_n_0_[10] ;
  wire \tx_d_pipeline_r_reg_n_0_[11] ;
  wire \tx_d_pipeline_r_reg_n_0_[12] ;
  wire \tx_d_pipeline_r_reg_n_0_[13] ;
  wire \tx_d_pipeline_r_reg_n_0_[14] ;
  wire \tx_d_pipeline_r_reg_n_0_[15] ;
  wire \tx_d_pipeline_r_reg_n_0_[16] ;
  wire \tx_d_pipeline_r_reg_n_0_[17] ;
  wire \tx_d_pipeline_r_reg_n_0_[18] ;
  wire \tx_d_pipeline_r_reg_n_0_[19] ;
  wire \tx_d_pipeline_r_reg_n_0_[1] ;
  wire \tx_d_pipeline_r_reg_n_0_[20] ;
  wire \tx_d_pipeline_r_reg_n_0_[21] ;
  wire \tx_d_pipeline_r_reg_n_0_[22] ;
  wire \tx_d_pipeline_r_reg_n_0_[23] ;
  wire \tx_d_pipeline_r_reg_n_0_[24] ;
  wire \tx_d_pipeline_r_reg_n_0_[25] ;
  wire \tx_d_pipeline_r_reg_n_0_[26] ;
  wire \tx_d_pipeline_r_reg_n_0_[27] ;
  wire \tx_d_pipeline_r_reg_n_0_[28] ;
  wire \tx_d_pipeline_r_reg_n_0_[29] ;
  wire \tx_d_pipeline_r_reg_n_0_[2] ;
  wire \tx_d_pipeline_r_reg_n_0_[30] ;
  wire \tx_d_pipeline_r_reg_n_0_[31] ;
  wire \tx_d_pipeline_r_reg_n_0_[32] ;
  wire \tx_d_pipeline_r_reg_n_0_[33] ;
  wire \tx_d_pipeline_r_reg_n_0_[34] ;
  wire \tx_d_pipeline_r_reg_n_0_[35] ;
  wire \tx_d_pipeline_r_reg_n_0_[36] ;
  wire \tx_d_pipeline_r_reg_n_0_[37] ;
  wire \tx_d_pipeline_r_reg_n_0_[38] ;
  wire \tx_d_pipeline_r_reg_n_0_[39] ;
  wire \tx_d_pipeline_r_reg_n_0_[3] ;
  wire \tx_d_pipeline_r_reg_n_0_[40] ;
  wire \tx_d_pipeline_r_reg_n_0_[41] ;
  wire \tx_d_pipeline_r_reg_n_0_[42] ;
  wire \tx_d_pipeline_r_reg_n_0_[43] ;
  wire \tx_d_pipeline_r_reg_n_0_[44] ;
  wire \tx_d_pipeline_r_reg_n_0_[45] ;
  wire \tx_d_pipeline_r_reg_n_0_[46] ;
  wire \tx_d_pipeline_r_reg_n_0_[47] ;
  wire \tx_d_pipeline_r_reg_n_0_[48] ;
  wire \tx_d_pipeline_r_reg_n_0_[49] ;
  wire \tx_d_pipeline_r_reg_n_0_[4] ;
  wire \tx_d_pipeline_r_reg_n_0_[50] ;
  wire \tx_d_pipeline_r_reg_n_0_[51] ;
  wire \tx_d_pipeline_r_reg_n_0_[52] ;
  wire \tx_d_pipeline_r_reg_n_0_[53] ;
  wire \tx_d_pipeline_r_reg_n_0_[54] ;
  wire \tx_d_pipeline_r_reg_n_0_[55] ;
  wire \tx_d_pipeline_r_reg_n_0_[56] ;
  wire \tx_d_pipeline_r_reg_n_0_[57] ;
  wire \tx_d_pipeline_r_reg_n_0_[58] ;
  wire \tx_d_pipeline_r_reg_n_0_[59] ;
  wire \tx_d_pipeline_r_reg_n_0_[5] ;
  wire \tx_d_pipeline_r_reg_n_0_[60] ;
  wire \tx_d_pipeline_r_reg_n_0_[61] ;
  wire \tx_d_pipeline_r_reg_n_0_[62] ;
  wire \tx_d_pipeline_r_reg_n_0_[63] ;
  wire \tx_d_pipeline_r_reg_n_0_[6] ;
  wire \tx_d_pipeline_r_reg_n_0_[7] ;
  wire \tx_d_pipeline_r_reg_n_0_[8] ;
  wire \tx_d_pipeline_r_reg_n_0_[9] ;
  wire tx_dst_rdy;
  wire tx_dst_rdy_n_pipeline_r;
  wire tx_eof;
  wire tx_eof_n_pipeline_r;
  wire [0:63]tx_pe_data_r;
  wire \tx_pe_data_v_r[2]_i_1_n_0 ;
  wire \tx_pe_data_v_r_reg_n_0_[0] ;
  wire \tx_pe_data_v_r_reg_n_0_[3] ;
  wire \tx_pe_ufc_v_r_reg_n_0_[3] ;
  wire [1:1]tx_rem;
  wire [0:2]tx_rem_pipeline_r;
  wire \tx_rem_pipeline_r[1]_i_2_n_0 ;
  wire \tx_rem_pipeline_r[2]_i_1_n_0 ;
  wire tx_sof;
  wire tx_sof_n_pipeline_r;
  wire tx_src_rdy;
  wire tx_src_rdy_n_pipeline_r;
  wire [3:0]\ufc_message_pipeline_r_reg[0]_0 ;
  wire \ufc_message_pipeline_r_reg_n_0_[0] ;
  wire \ufc_message_pipeline_r_reg_n_0_[1] ;
  wire \ufc_message_pipeline_r_reg_n_0_[2] ;
  wire \ufc_message_pipeline_r_reg_n_0_[3] ;
  wire user_clk;
  wire [1:3]valid_c;

  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \GEN_PAD_Buffer[0]_i_1 
       (.I0(\gen_pad_r_reg_n_0_[0] ),
        .I1(TX_PE_DATA_V_Buffer2),
        .I2(p_7_in),
        .O(p_8_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \GEN_PAD_Buffer[1]_i_1 
       (.I0(p_6_in),
        .I1(TX_PE_DATA_V_Buffer2),
        .I2(p_5_in),
        .O(p_8_out[2]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \GEN_PAD_Buffer[2]_i_1 
       (.I0(p_4_in),
        .I1(TX_PE_DATA_V_Buffer2),
        .I2(p_3_in),
        .O(p_8_out[1]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \GEN_PAD_Buffer[3]_i_1 
       (.I0(\gen_pad_r_reg_n_0_[3] ),
        .I1(TX_PE_DATA_V_Buffer2),
        .I2(\tx_pe_ufc_v_r_reg_n_0_[3] ),
        .O(p_8_out[0]));
  FDRE \GEN_PAD_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_8_out[3]),
        .Q(\GEN_PAD_Buffer_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \GEN_PAD_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_8_out[2]),
        .Q(\GEN_PAD_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \GEN_PAD_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_8_out[1]),
        .Q(\GEN_PAD_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \GEN_PAD_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_8_out[0]),
        .Q(\GEN_PAD_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[0]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [63]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[10]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [53]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[11]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [52]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[12]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [51]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[13]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [50]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[14]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [49]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[15]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [48]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[16]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [47]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[17]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [46]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[18]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [45]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[19]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [44]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[1]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [62]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[20]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [43]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[21]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [42]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[22]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [41]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[23]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [40]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[24]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [39]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[25]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [38]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[26]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [37]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[27]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [36]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[28]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [35]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[29]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [34]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[2]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [61]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[30]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [33]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[31]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [32]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[32]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [31]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[33]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [30]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[34]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [29]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[35]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [28]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[36]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [27]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[37]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [26]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[38]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [25]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[39]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [24]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[3]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [60]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[40]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [23]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[41]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [22]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[42]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [21]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[43]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [20]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[44]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [19]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[45]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [18]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[46]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [17]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[47]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [16]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[48]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [15]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[49]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [14]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[4]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [59]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[50]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [13]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[51]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [12]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[52]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [11]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[53]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [10]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[54]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [9]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[55]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [8]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[56]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[57]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[58]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[59]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[5]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [58]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[60]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[61]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[62]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[63]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[6]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [57]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[7]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [56]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[8]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [55]),
        .R(1'b0));
  FDRE \TX_PE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_pe_data_r[9]),
        .Q(\TX_PE_DATA_Buffer_reg[0]_0 [54]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_PE_DATA_V_Buffer[0]_i_1 
       (.I0(TX_PE_DATA_V_Buffer2),
        .I1(\tx_pe_data_v_r_reg_n_0_[0] ),
        .I2(p_7_in),
        .O(p_7_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_PE_DATA_V_Buffer[1]_i_1 
       (.I0(TX_PE_DATA_V_Buffer2),
        .I1(p_4_in10_in),
        .I2(p_5_in),
        .O(p_7_out[2]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_PE_DATA_V_Buffer[2]_i_1 
       (.I0(TX_PE_DATA_V_Buffer2),
        .I1(p_2_in),
        .I2(p_3_in),
        .O(p_7_out[1]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \TX_PE_DATA_V_Buffer[3]_i_1 
       (.I0(TX_PE_DATA_V_Buffer2),
        .I1(\tx_pe_data_v_r_reg_n_0_[3] ),
        .I2(\tx_pe_ufc_v_r_reg_n_0_[3] ),
        .O(p_7_out[0]));
  FDRE \TX_PE_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_7_out[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \TX_PE_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_7_out[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \TX_PE_DATA_V_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_7_out[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \TX_PE_DATA_V_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_7_out[0]),
        .Q(Q[0]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_pad_r[1]_i_1 
       (.I0(tx_rem_pipeline_r[0]),
        .I1(tx_rem_pipeline_r[2]),
        .I2(tx_rem_pipeline_r[1]),
        .I3(tx_eof_n_pipeline_r),
        .O(\gen_pad_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \gen_pad_r[2]_i_1 
       (.I0(tx_rem_pipeline_r[0]),
        .I1(tx_rem_pipeline_r[2]),
        .I2(tx_rem_pipeline_r[1]),
        .I3(tx_eof_n_pipeline_r),
        .O(\gen_pad_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \gen_pad_r[3]_i_1 
       (.I0(tx_rem_pipeline_r[1]),
        .I1(tx_rem_pipeline_r[2]),
        .I2(tx_rem_pipeline_r[0]),
        .I3(tx_eof_n_pipeline_r),
        .O(\gen_pad_r[3]_i_1_n_0 ));
  FDRE \gen_pad_r_reg[0] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_pad_r),
        .Q(\gen_pad_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_pad_r_reg[1] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\gen_pad_r[1]_i_1_n_0 ),
        .Q(p_6_in),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  FDRE \gen_pad_r_reg[2] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\gen_pad_r[2]_i_1_n_0 ),
        .Q(p_4_in),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  FDRE \gen_pad_r_reg[3] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\gen_pad_r[3]_i_1_n_0 ),
        .Q(\gen_pad_r_reg_n_0_[3] ),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  (* inverted = "yes" *) 
  FDSE halt_c_pipeline_r_reg_inv
       (.C(user_clk),
        .CE(1'b1),
        .D(halt_c_pipeline_r_reg_inv_1),
        .Q(TX_PE_DATA_V_Buffer2),
        .S(halt_c_pipeline_r_reg_inv_0));
  LUT5 #(
    .INIT(32'hFEFE0010)) 
    in_frame_r_i_1
       (.I0(tx_dst_rdy_n_pipeline_r),
        .I1(tx_src_rdy_n_pipeline_r),
        .I2(tx_eof_n_pipeline_r),
        .I3(tx_sof_n_pipeline_r),
        .I4(in_frame_r_reg_n_0),
        .O(in_frame_r_i_1_n_0));
  FDRE in_frame_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_r_i_1_n_0),
        .Q(in_frame_r_reg_n_0),
        .R(halt_c_pipeline_r_reg_inv_0));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    storage_pad_r_i_1
       (.I0(tx_rem_pipeline_r[2]),
        .I1(tx_rem_pipeline_r[1]),
        .I2(tx_rem_pipeline_r[0]),
        .I3(tx_eof_n_pipeline_r),
        .O(storage_pad_r_i_1_n_0));
  FDRE storage_pad_r_reg
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_pad_r_i_1_n_0),
        .Q(storage_pad_r),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  FDRE \storage_r_reg[0] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[48] ),
        .Q(storage_r[0]),
        .R(1'b0));
  FDRE \storage_r_reg[10] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[58] ),
        .Q(storage_r[10]),
        .R(1'b0));
  FDRE \storage_r_reg[11] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[59] ),
        .Q(storage_r[11]),
        .R(1'b0));
  FDRE \storage_r_reg[12] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[60] ),
        .Q(storage_r[12]),
        .R(1'b0));
  FDRE \storage_r_reg[13] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[61] ),
        .Q(storage_r[13]),
        .R(1'b0));
  FDRE \storage_r_reg[14] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[62] ),
        .Q(storage_r[14]),
        .R(1'b0));
  FDRE \storage_r_reg[15] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[63] ),
        .Q(storage_r[15]),
        .R(1'b0));
  FDRE \storage_r_reg[1] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[49] ),
        .Q(storage_r[1]),
        .R(1'b0));
  FDRE \storage_r_reg[2] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[50] ),
        .Q(storage_r[2]),
        .R(1'b0));
  FDRE \storage_r_reg[3] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[51] ),
        .Q(storage_r[3]),
        .R(1'b0));
  FDRE \storage_r_reg[4] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[52] ),
        .Q(storage_r[4]),
        .R(1'b0));
  FDRE \storage_r_reg[5] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[53] ),
        .Q(storage_r[5]),
        .R(1'b0));
  FDRE \storage_r_reg[6] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[54] ),
        .Q(storage_r[6]),
        .R(1'b0));
  FDRE \storage_r_reg[7] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[55] ),
        .Q(storage_r[7]),
        .R(1'b0));
  FDRE \storage_r_reg[8] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[56] ),
        .Q(storage_r[8]),
        .R(1'b0));
  FDRE \storage_r_reg[9] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[57] ),
        .Q(storage_r[9]),
        .R(1'b0));
  FDRE storage_ufc_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg_n_0_[3] ),
        .Q(storage_ufc_v_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    storage_v_r_i_1
       (.I0(tx_eof_n_pipeline_r),
        .I1(tx_rem_pipeline_r[0]),
        .I2(tx_rem_pipeline_r[1]),
        .O(valid_c[3]));
  FDRE storage_v_r_reg
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(valid_c[3]),
        .Q(storage_v_r),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  FDRE \tx_d_pipeline_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[7]),
        .Q(\tx_d_pipeline_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[13]),
        .Q(\tx_d_pipeline_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[12]),
        .Q(\tx_d_pipeline_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[11]),
        .Q(\tx_d_pipeline_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[10]),
        .Q(\tx_d_pipeline_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[9]),
        .Q(\tx_d_pipeline_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[8]),
        .Q(\tx_d_pipeline_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[23]),
        .Q(\tx_d_pipeline_r_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[22]),
        .Q(\tx_d_pipeline_r_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[21]),
        .Q(\tx_d_pipeline_r_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[20]),
        .Q(\tx_d_pipeline_r_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[6]),
        .Q(\tx_d_pipeline_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[19]),
        .Q(\tx_d_pipeline_r_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[18]),
        .Q(\tx_d_pipeline_r_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[17]),
        .Q(\tx_d_pipeline_r_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[16]),
        .Q(\tx_d_pipeline_r_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[31]),
        .Q(\tx_d_pipeline_r_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[30]),
        .Q(\tx_d_pipeline_r_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[29]),
        .Q(\tx_d_pipeline_r_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[28]),
        .Q(\tx_d_pipeline_r_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[27]),
        .Q(\tx_d_pipeline_r_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[26]),
        .Q(\tx_d_pipeline_r_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[5]),
        .Q(\tx_d_pipeline_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[25]),
        .Q(\tx_d_pipeline_r_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[24]),
        .Q(\tx_d_pipeline_r_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[39]),
        .Q(\tx_d_pipeline_r_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[38]),
        .Q(\tx_d_pipeline_r_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[37]),
        .Q(\tx_d_pipeline_r_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[36]),
        .Q(\tx_d_pipeline_r_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[35]),
        .Q(\tx_d_pipeline_r_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[34]),
        .Q(\tx_d_pipeline_r_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[33]),
        .Q(\tx_d_pipeline_r_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[32]),
        .Q(\tx_d_pipeline_r_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[4]),
        .Q(\tx_d_pipeline_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[47]),
        .Q(\tx_d_pipeline_r_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[46]),
        .Q(\tx_d_pipeline_r_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[45]),
        .Q(\tx_d_pipeline_r_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[44]),
        .Q(\tx_d_pipeline_r_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[43]),
        .Q(\tx_d_pipeline_r_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[42]),
        .Q(\tx_d_pipeline_r_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[41]),
        .Q(\tx_d_pipeline_r_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[40]),
        .Q(\tx_d_pipeline_r_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[55]),
        .Q(\tx_d_pipeline_r_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[54]),
        .Q(\tx_d_pipeline_r_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[3]),
        .Q(\tx_d_pipeline_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[53]),
        .Q(\tx_d_pipeline_r_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[52]),
        .Q(\tx_d_pipeline_r_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[51]),
        .Q(\tx_d_pipeline_r_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[50]),
        .Q(\tx_d_pipeline_r_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[49]),
        .Q(\tx_d_pipeline_r_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[48]),
        .Q(\tx_d_pipeline_r_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[63]),
        .Q(\tx_d_pipeline_r_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[62]),
        .Q(\tx_d_pipeline_r_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[61]),
        .Q(\tx_d_pipeline_r_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[60]),
        .Q(\tx_d_pipeline_r_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[2]),
        .Q(\tx_d_pipeline_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[59]),
        .Q(\tx_d_pipeline_r_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[58]),
        .Q(\tx_d_pipeline_r_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[57]),
        .Q(\tx_d_pipeline_r_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[56]),
        .Q(\tx_d_pipeline_r_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[1]),
        .Q(\tx_d_pipeline_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[0]),
        .Q(\tx_d_pipeline_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[15]),
        .Q(\tx_d_pipeline_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tx_d_pipeline_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(S_AXI_TX_TDATA[14]),
        .Q(\tx_d_pipeline_r_reg_n_0_[9] ),
        .R(1'b0));
  FDSE tx_dst_rdy_n_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_dst_rdy),
        .Q(tx_dst_rdy_n_pipeline_r),
        .S(halt_c_pipeline_r_reg_inv_0));
  LUT1 #(
    .INIT(2'h1)) 
    tx_eof_n_pipeline_r_i_1
       (.I0(S_AXI_TX_TLAST),
        .O(tx_eof));
  FDSE tx_eof_n_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_eof),
        .Q(tx_eof_n_pipeline_r),
        .S(halt_c_pipeline_r_reg_inv_0));
  FDRE \tx_pe_data_r_reg[0] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[0]),
        .Q(tx_pe_data_r[0]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[10]),
        .Q(tx_pe_data_r[10]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[11] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[11]),
        .Q(tx_pe_data_r[11]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[12] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[12]),
        .Q(tx_pe_data_r[12]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[13] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[13]),
        .Q(tx_pe_data_r[13]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[14] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[14]),
        .Q(tx_pe_data_r[14]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[15] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[15]),
        .Q(tx_pe_data_r[15]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[16] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[0] ),
        .Q(tx_pe_data_r[16]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[17] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[1] ),
        .Q(tx_pe_data_r[17]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[18] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[2] ),
        .Q(tx_pe_data_r[18]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[19] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[3] ),
        .Q(tx_pe_data_r[19]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[1] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[1]),
        .Q(tx_pe_data_r[1]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[20] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[4] ),
        .Q(tx_pe_data_r[20]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[21] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[5] ),
        .Q(tx_pe_data_r[21]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[22] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[6] ),
        .Q(tx_pe_data_r[22]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[23] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[7] ),
        .Q(tx_pe_data_r[23]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[24] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[8] ),
        .Q(tx_pe_data_r[24]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[25] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[9] ),
        .Q(tx_pe_data_r[25]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[26] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[10] ),
        .Q(tx_pe_data_r[26]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[27] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[11] ),
        .Q(tx_pe_data_r[27]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[28] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[12] ),
        .Q(tx_pe_data_r[28]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[29] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[13] ),
        .Q(tx_pe_data_r[29]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[2] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[2]),
        .Q(tx_pe_data_r[2]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[30] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[14] ),
        .Q(tx_pe_data_r[30]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[31] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[15] ),
        .Q(tx_pe_data_r[31]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[32] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[16] ),
        .Q(tx_pe_data_r[32]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[33] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[17] ),
        .Q(tx_pe_data_r[33]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[34] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[18] ),
        .Q(tx_pe_data_r[34]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[35] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[19] ),
        .Q(tx_pe_data_r[35]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[36] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[20] ),
        .Q(tx_pe_data_r[36]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[37] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[21] ),
        .Q(tx_pe_data_r[37]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[38] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[22] ),
        .Q(tx_pe_data_r[38]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[39] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[23] ),
        .Q(tx_pe_data_r[39]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[3] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[3]),
        .Q(tx_pe_data_r[3]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[40] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[24] ),
        .Q(tx_pe_data_r[40]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[41] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[25] ),
        .Q(tx_pe_data_r[41]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[42] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[26] ),
        .Q(tx_pe_data_r[42]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[43] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[27] ),
        .Q(tx_pe_data_r[43]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[44] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[28] ),
        .Q(tx_pe_data_r[44]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[45] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[29] ),
        .Q(tx_pe_data_r[45]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[46] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[30] ),
        .Q(tx_pe_data_r[46]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[47] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[31] ),
        .Q(tx_pe_data_r[47]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[48] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[32] ),
        .Q(tx_pe_data_r[48]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[49] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[33] ),
        .Q(tx_pe_data_r[49]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[4] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[4]),
        .Q(tx_pe_data_r[4]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[50] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[34] ),
        .Q(tx_pe_data_r[50]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[51] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[35] ),
        .Q(tx_pe_data_r[51]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[52] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[36] ),
        .Q(tx_pe_data_r[52]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[53] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[37] ),
        .Q(tx_pe_data_r[53]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[54] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[38] ),
        .Q(tx_pe_data_r[54]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[55] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[39] ),
        .Q(tx_pe_data_r[55]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[56] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[40] ),
        .Q(tx_pe_data_r[56]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[57] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[41] ),
        .Q(tx_pe_data_r[57]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[58] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[42] ),
        .Q(tx_pe_data_r[58]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[59] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[43] ),
        .Q(tx_pe_data_r[59]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[5] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[5]),
        .Q(tx_pe_data_r[5]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[60] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[44] ),
        .Q(tx_pe_data_r[60]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[61] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[45] ),
        .Q(tx_pe_data_r[61]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[62] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[46] ),
        .Q(tx_pe_data_r[62]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[63] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(\tx_d_pipeline_r_reg_n_0_[47] ),
        .Q(tx_pe_data_r[63]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[6] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[6]),
        .Q(tx_pe_data_r[6]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[7] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[7]),
        .Q(tx_pe_data_r[7]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[8]),
        .Q(tx_pe_data_r[8]),
        .R(1'b0));
  FDRE \tx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_r[9]),
        .Q(tx_pe_data_r[9]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h1101)) 
    \tx_pe_data_v_r[1]_i_1 
       (.I0(tx_dst_rdy_n_pipeline_r),
        .I1(tx_src_rdy_n_pipeline_r),
        .I2(tx_sof_n_pipeline_r),
        .I3(in_frame_r_reg_n_0),
        .O(p_31_in));
  LUT5 #(
    .INIT(32'hFFF40000)) 
    \tx_pe_data_v_r[2]_i_1 
       (.I0(in_frame_r_reg_n_0),
        .I1(tx_sof_n_pipeline_r),
        .I2(tx_src_rdy_n_pipeline_r),
        .I3(tx_dst_rdy_n_pipeline_r),
        .I4(TX_PE_DATA_V_Buffer2),
        .O(\tx_pe_data_v_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \tx_pe_data_v_r[2]_i_2 
       (.I0(tx_rem_pipeline_r[0]),
        .I1(tx_rem_pipeline_r[1]),
        .I2(tx_eof_n_pipeline_r),
        .O(valid_c[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \tx_pe_data_v_r[3]_i_1 
       (.I0(tx_rem_pipeline_r[0]),
        .I1(tx_eof_n_pipeline_r),
        .O(valid_c[2]));
  FDRE \tx_pe_data_v_r_reg[0] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(storage_v_r),
        .Q(\tx_pe_data_v_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \tx_pe_data_v_r_reg[1] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(p_31_in),
        .Q(p_4_in10_in),
        .R(1'b0));
  FDRE \tx_pe_data_v_r_reg[2] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(valid_c[1]),
        .Q(p_2_in),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  FDRE \tx_pe_data_v_r_reg[3] 
       (.C(user_clk),
        .CE(TX_PE_DATA_V_Buffer2),
        .D(valid_c[2]),
        .Q(\tx_pe_data_v_r_reg_n_0_[3] ),
        .R(\tx_pe_data_v_r[2]_i_1_n_0 ));
  FDRE \tx_pe_ufc_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_ufc_v_r),
        .Q(p_7_in),
        .R(1'b0));
  FDRE \tx_pe_ufc_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg_n_0_[0] ),
        .Q(p_5_in),
        .R(1'b0));
  FDRE \tx_pe_ufc_v_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg_n_0_[1] ),
        .Q(p_3_in),
        .R(1'b0));
  FDRE \tx_pe_ufc_v_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg_n_0_[2] ),
        .Q(\tx_pe_ufc_v_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h96)) 
    \tx_rem_pipeline_r[0]_i_2 
       (.I0(S_AXI_TX_TKEEP[5]),
        .I1(S_AXI_TX_TKEEP[3]),
        .I2(S_AXI_TX_TKEEP[4]),
        .O(\s_axi_tx_tkeep[5] ));
  LUT6 #(
    .INIT(64'h171717E817E8E8E8)) 
    \tx_rem_pipeline_r[0]_i_4 
       (.I0(S_AXI_TX_TKEEP[4]),
        .I1(S_AXI_TX_TKEEP[5]),
        .I2(S_AXI_TX_TKEEP[3]),
        .I3(S_AXI_TX_TKEEP[0]),
        .I4(S_AXI_TX_TKEEP[6]),
        .I5(S_AXI_TX_TKEEP[7]),
        .O(\s_axi_tx_tkeep[4] ));
  LUT4 #(
    .INIT(16'h56A9)) 
    \tx_rem_pipeline_r[1]_i_1 
       (.I0(\tx_rem_pipeline_r[1]_i_2_n_0 ),
        .I1(S_AXI_TX_TKEEP[1]),
        .I2(S_AXI_TX_TKEEP[2]),
        .I3(\s_axi_tx_tkeep[4] ),
        .O(tx_rem));
  LUT6 #(
    .INIT(64'hFF9696FF96000096)) 
    \tx_rem_pipeline_r[1]_i_2 
       (.I0(S_AXI_TX_TKEEP[0]),
        .I1(S_AXI_TX_TKEEP[6]),
        .I2(S_AXI_TX_TKEEP[7]),
        .I3(S_AXI_TX_TKEEP[2]),
        .I4(S_AXI_TX_TKEEP[1]),
        .I5(\s_axi_tx_tkeep[5] ),
        .O(\tx_rem_pipeline_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    \tx_rem_pipeline_r[2]_i_1 
       (.I0(S_AXI_TX_TKEEP[1]),
        .I1(S_AXI_TX_TKEEP[2]),
        .I2(S_AXI_TX_TKEEP[0]),
        .I3(S_AXI_TX_TKEEP[6]),
        .I4(S_AXI_TX_TKEEP[7]),
        .I5(\s_axi_tx_tkeep[5] ),
        .O(\tx_rem_pipeline_r[2]_i_1_n_0 ));
  FDRE \tx_rem_pipeline_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(tx_rem_pipeline_r[0]),
        .R(1'b0));
  FDRE \tx_rem_pipeline_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_rem),
        .Q(tx_rem_pipeline_r[1]),
        .R(1'b0));
  FDRE \tx_rem_pipeline_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tx_rem_pipeline_r[2]_i_1_n_0 ),
        .Q(tx_rem_pipeline_r[2]),
        .R(1'b0));
  FDSE tx_sof_n_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_sof),
        .Q(tx_sof_n_pipeline_r),
        .S(halt_c_pipeline_r_reg_inv_0));
  LUT1 #(
    .INIT(2'h1)) 
    tx_src_rdy_n_pipeline_r_i_1
       (.I0(S_AXI_TX_TVALID),
        .O(tx_src_rdy));
  FDSE tx_src_rdy_n_pipeline_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_src_rdy),
        .Q(tx_src_rdy_n_pipeline_r),
        .S(halt_c_pipeline_r_reg_inv_0));
  FDRE \ufc_message_pipeline_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg[0]_0 [3]),
        .Q(\ufc_message_pipeline_r_reg_n_0_[0] ),
        .R(halt_c_pipeline_r_reg_inv_0));
  FDRE \ufc_message_pipeline_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg[0]_0 [2]),
        .Q(\ufc_message_pipeline_r_reg_n_0_[1] ),
        .R(halt_c_pipeline_r_reg_inv_0));
  FDRE \ufc_message_pipeline_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg[0]_0 [1]),
        .Q(\ufc_message_pipeline_r_reg_n_0_[2] ),
        .R(halt_c_pipeline_r_reg_inv_0));
  FDRE \ufc_message_pipeline_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ufc_message_pipeline_r_reg[0]_0 [0]),
        .Q(\ufc_message_pipeline_r_reg_n_0_[3] ),
        .R(halt_c_pipeline_r_reg_inv_0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync
   (AR,
    GT_RESET,
    init_clk_in);
  output [0:0]AR;
  input GT_RESET;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  assign AR[0] = s_level_out_d3;
  assign p_level_in_int = GT_RESET;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0
   (out,
    TX_SYSTEM_RESET,
    user_clk);
  output out;
  input TX_SYSTEM_RESET;
  input user_clk;

  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  assign p_level_in_int = TX_SYSTEM_RESET;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13
   (reset_time_out_reg,
    E,
    in0,
    init_clk_in,
    reset_time_out,
    \FSM_sequential_tx_state_reg[0] ,
    \FSM_sequential_tx_state_reg[0]_0 ,
    Q,
    reset_time_out_reg_0,
    \FSM_sequential_tx_state_reg[0]_1 ,
    \FSM_sequential_tx_state_reg[0]_2 ,
    \FSM_sequential_tx_state_reg[0]_3 ,
    txresetdone_s3,
    mmcm_lock_reclocked);
  output reset_time_out_reg;
  output [0:0]E;
  input in0;
  input init_clk_in;
  input reset_time_out;
  input \FSM_sequential_tx_state_reg[0] ;
  input \FSM_sequential_tx_state_reg[0]_0 ;
  input [3:0]Q;
  input reset_time_out_reg_0;
  input \FSM_sequential_tx_state_reg[0]_1 ;
  input \FSM_sequential_tx_state_reg[0]_2 ;
  input \FSM_sequential_tx_state_reg[0]_3 ;
  input txresetdone_s3;
  input mmcm_lock_reclocked;

  wire [0:0]E;
  wire \FSM_sequential_tx_state[3]_i_4_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_5_n_0 ;
  wire \FSM_sequential_tx_state_reg[0] ;
  wire \FSM_sequential_tx_state_reg[0]_0 ;
  wire \FSM_sequential_tx_state_reg[0]_1 ;
  wire \FSM_sequential_tx_state_reg[0]_2 ;
  wire \FSM_sequential_tx_state_reg[0]_3 ;
  wire [3:0]Q;
  wire init_clk_in;
  wire mmcm_lock_reclocked;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire reset_time_out;
  wire reset_time_out_0;
  wire reset_time_out_i_3_n_0;
  wire reset_time_out_reg;
  wire reset_time_out_reg_0;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire txresetdone_s3;

  assign p_level_in_int = in0;
  LUT6 #(
    .INIT(64'hFAFAFAFAFFFEFAFA)) 
    \FSM_sequential_tx_state[3]_i_1 
       (.I0(\FSM_sequential_tx_state_reg[0] ),
        .I1(\FSM_sequential_tx_state[3]_i_4_n_0 ),
        .I2(\FSM_sequential_tx_state[3]_i_5_n_0 ),
        .I3(\FSM_sequential_tx_state_reg[0]_0 ),
        .I4(Q[0]),
        .I5(Q[3]),
        .O(E));
  LUT5 #(
    .INIT(32'hB8CCB800)) 
    \FSM_sequential_tx_state[3]_i_4 
       (.I0(txresetdone_s3),
        .I1(Q[2]),
        .I2(s_level_out_d3),
        .I3(Q[1]),
        .I4(mmcm_lock_reclocked),
        .O(\FSM_sequential_tx_state[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0004000400070004)) 
    \FSM_sequential_tx_state[3]_i_5 
       (.I0(\FSM_sequential_tx_state_reg[0]_1 ),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(\FSM_sequential_tx_state_reg[0]_2 ),
        .I4(\FSM_sequential_tx_state_reg[0]_3 ),
        .I5(s_level_out_d3),
        .O(\FSM_sequential_tx_state[3]_i_5_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
  LUT3 #(
    .INIT(8'hB8)) 
    reset_time_out_i_1
       (.I0(reset_time_out_0),
        .I1(reset_time_out_i_3_n_0),
        .I2(reset_time_out),
        .O(reset_time_out_reg));
  LUT6 #(
    .INIT(64'h00AE00AE00AEF0AE)) 
    reset_time_out_i_2
       (.I0(\FSM_sequential_tx_state[3]_i_4_n_0 ),
        .I1(reset_time_out_reg_0),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(reset_time_out_0));
  LUT6 #(
    .INIT(64'h0000FF005555F544)) 
    reset_time_out_i_3
       (.I0(Q[1]),
        .I1(reset_time_out_reg_0),
        .I2(s_level_out_d3),
        .I3(Q[0]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(reset_time_out_i_3_n_0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14
   (init_clk_in);
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(p_level_in_int));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16
   (out,
    SR,
    init_clk_in);
  output out;
  output [0:0]SR;
  input init_clk_in;

  wire [0:0]SR;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  assign out = s_level_out_d3;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(p_level_in_int));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
  LUT1 #(
    .INIT(2'h1)) 
    \mmcm_lock_count[9]_i_1 
       (.I0(s_level_out_d3),
        .O(SR));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2
   (user_clk,
    init_clk_in);
  input user_clk;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(1'b0),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15
   (out,
    txfsm_txresetdone_r,
    user_clk,
    init_clk_in);
  output out;
  input txfsm_txresetdone_r;
  input user_clk;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire txfsm_txresetdone_r;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(txfsm_txresetdone_r),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17
   (out,
    run_phase_alignment_int,
    init_clk_in,
    user_clk);
  output out;
  input run_phase_alignment_int;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire run_phase_alignment_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(run_phase_alignment_int),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18
   (out,
    time_out_wait_bypass,
    user_clk,
    init_clk_in);
  output out;
  input time_out_wait_bypass;
  input user_clk;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire time_out_wait_bypass;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(time_out_wait_bypass),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19
   (out,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0 ,
    tx_fsm_reset_done_int,
    init_clk_in,
    user_clk);
  output out;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0 ;
  input tx_fsm_reset_done_int;
  input init_clk_in;
  input user_clk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0 ;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire tx_fsm_reset_done_int;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(tx_fsm_reset_done_int),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    gt_txresetdone_r_i_1
       (.I0(s_level_out_d3),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23
   (out,
    init_clk_in,
    user_clk);
  output out;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(1'b0),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_cdc_sync" *) 
module efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24
   (out,
    tx_lock_comb_r,
    init_clk_in,
    user_clk);
  output out;
  input tx_lock_comb_r;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_efex_aurora_hub2_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire tx_lock_comb_r;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(tx_lock_comb_r),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_efex_aurora_hub2_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* CC_FREQ_FACTOR = "24" *) (* EXAMPLE_SIMULATION = "0" *) (* ORIG_REF_NAME = "efex_aurora_hub2_core" *) 
(* SIM_GTRESET_SPEEDUP = "FALSE" *) 
module efex_aurora_hub2_efex_aurora_hub2_core
   (S_AXI_TX_TDATA,
    S_AXI_TX_TKEEP,
    S_AXI_TX_TVALID,
    S_AXI_TX_TREADY,
    S_AXI_TX_TLAST,
    S_AXI_UFC_TX_REQ,
    S_AXI_UFC_TX_MS,
    S_AXI_UFC_TX_ACK,
    TXP,
    TXN,
    gt_refclk1,
    TX_HARD_ERR,
    TX_CHANNEL_UP,
    TX_LANE_UP,
    user_clk,
    sync_clk,
    TX_SYSTEM_RESET,
    TX_RESETDONE_OUT,
    POWER_DOWN,
    GT_RESET,
    TX_LOCK,
    init_clk_in,
    PLL_NOT_LOCKED,
    drpclk_in,
    DRPADDR_IN,
    DRPDI_IN,
    DRPDO_OUT,
    DRPEN_IN,
    DRPRDY_OUT,
    DRPWE_IN,
    DRPADDR_IN_LANE1,
    DRPDI_IN_LANE1,
    DRPDO_OUT_LANE1,
    DRPEN_IN_LANE1,
    DRPRDY_OUT_LANE1,
    DRPWE_IN_LANE1,
    DRPADDR_IN_LANE2,
    DRPDI_IN_LANE2,
    DRPDO_OUT_LANE2,
    DRPEN_IN_LANE2,
    DRPRDY_OUT_LANE2,
    DRPWE_IN_LANE2,
    DRPADDR_IN_LANE3,
    DRPDI_IN_LANE3,
    DRPDO_OUT_LANE3,
    DRPEN_IN_LANE3,
    DRPRDY_OUT_LANE3,
    DRPWE_IN_LANE3,
    TX_OUT_CLK,
    gt0_qplllock_in,
    gt0_qpllrefclklost_in,
    gt0_qpllreset_out,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    gt0_cplllock_out,
    gt0_txresetdone_out,
    gt0_txbufstatus_out,
    gt0_txpostcursor_in,
    gt0_txprecursor_in,
    gt0_txchardispmode_in,
    gt0_txchardispval_in,
    gt0_txdiffctrl_in,
    gt0_txmaincursor_in,
    gt0_txpolarity_in,
    gt0_tx_buf_err_out,
    gt0_txprbsforceerr_in,
    gt0_txprbssel_in,
    gt0_txpcsreset_in,
    gt0_txinhibit_in,
    gt0_txpmareset_in,
    gt1_cplllock_out,
    gt1_txresetdone_out,
    gt1_txbufstatus_out,
    gt1_txpostcursor_in,
    gt1_txprecursor_in,
    gt1_txchardispmode_in,
    gt1_txchardispval_in,
    gt1_txdiffctrl_in,
    gt1_txmaincursor_in,
    gt1_txpolarity_in,
    gt1_tx_buf_err_out,
    gt1_txprbsforceerr_in,
    gt1_txprbssel_in,
    gt1_txpcsreset_in,
    gt1_txinhibit_in,
    gt1_txpmareset_in,
    gt2_cplllock_out,
    gt2_txresetdone_out,
    gt2_txbufstatus_out,
    gt2_txpostcursor_in,
    gt2_txprecursor_in,
    gt2_txchardispmode_in,
    gt2_txchardispval_in,
    gt2_txdiffctrl_in,
    gt2_txmaincursor_in,
    gt2_txpolarity_in,
    gt2_tx_buf_err_out,
    gt2_txprbsforceerr_in,
    gt2_txprbssel_in,
    gt2_txpcsreset_in,
    gt2_txinhibit_in,
    gt2_txpmareset_in,
    gt3_cplllock_out,
    gt3_txresetdone_out,
    gt3_txbufstatus_out,
    gt3_txpostcursor_in,
    gt3_txprecursor_in,
    gt3_txchardispmode_in,
    gt3_txchardispval_in,
    gt3_txdiffctrl_in,
    gt3_txmaincursor_in,
    gt3_txpolarity_in,
    gt3_tx_buf_err_out,
    gt3_txprbsforceerr_in,
    gt3_txprbssel_in,
    gt3_txpcsreset_in,
    gt3_txinhibit_in,
    gt3_txpmareset_in,
    sys_reset_out,
    LOOPBACK);
  input [63:0]S_AXI_TX_TDATA;
  input [7:0]S_AXI_TX_TKEEP;
  input S_AXI_TX_TVALID;
  output S_AXI_TX_TREADY;
  input S_AXI_TX_TLAST;
  input S_AXI_UFC_TX_REQ;
  input [2:0]S_AXI_UFC_TX_MS;
  output S_AXI_UFC_TX_ACK;
  output [0:3]TXP;
  output [0:3]TXN;
  input gt_refclk1;
  output TX_HARD_ERR;
  output TX_CHANNEL_UP;
  output [0:3]TX_LANE_UP;
  input user_clk;
  input sync_clk;
  input TX_SYSTEM_RESET;
  output TX_RESETDONE_OUT;
  input POWER_DOWN;
  input GT_RESET;
  output TX_LOCK;
  input init_clk_in;
  input PLL_NOT_LOCKED;
  input drpclk_in;
  input [8:0]DRPADDR_IN;
  input [15:0]DRPDI_IN;
  output [15:0]DRPDO_OUT;
  input DRPEN_IN;
  output DRPRDY_OUT;
  input DRPWE_IN;
  input [8:0]DRPADDR_IN_LANE1;
  input [15:0]DRPDI_IN_LANE1;
  output [15:0]DRPDO_OUT_LANE1;
  input DRPEN_IN_LANE1;
  output DRPRDY_OUT_LANE1;
  input DRPWE_IN_LANE1;
  input [8:0]DRPADDR_IN_LANE2;
  input [15:0]DRPDI_IN_LANE2;
  output [15:0]DRPDO_OUT_LANE2;
  input DRPEN_IN_LANE2;
  output DRPRDY_OUT_LANE2;
  input DRPWE_IN_LANE2;
  input [8:0]DRPADDR_IN_LANE3;
  input [15:0]DRPDI_IN_LANE3;
  output [15:0]DRPDO_OUT_LANE3;
  input DRPEN_IN_LANE3;
  output DRPRDY_OUT_LANE3;
  input DRPWE_IN_LANE3;
  output TX_OUT_CLK;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  output gt0_cplllock_out;
  output gt0_txresetdone_out;
  output [1:0]gt0_txbufstatus_out;
  input [4:0]gt0_txpostcursor_in;
  input [4:0]gt0_txprecursor_in;
  input [1:0]gt0_txchardispmode_in;
  input [1:0]gt0_txchardispval_in;
  input [3:0]gt0_txdiffctrl_in;
  input [6:0]gt0_txmaincursor_in;
  input gt0_txpolarity_in;
  output gt0_tx_buf_err_out;
  input gt0_txprbsforceerr_in;
  input [2:0]gt0_txprbssel_in;
  input gt0_txpcsreset_in;
  input gt0_txinhibit_in;
  input gt0_txpmareset_in;
  output gt1_cplllock_out;
  output gt1_txresetdone_out;
  output [1:0]gt1_txbufstatus_out;
  input [4:0]gt1_txpostcursor_in;
  input [4:0]gt1_txprecursor_in;
  input [1:0]gt1_txchardispmode_in;
  input [1:0]gt1_txchardispval_in;
  input [3:0]gt1_txdiffctrl_in;
  input [6:0]gt1_txmaincursor_in;
  input gt1_txpolarity_in;
  output gt1_tx_buf_err_out;
  input gt1_txprbsforceerr_in;
  input [2:0]gt1_txprbssel_in;
  input gt1_txpcsreset_in;
  input gt1_txinhibit_in;
  input gt1_txpmareset_in;
  output gt2_cplllock_out;
  output gt2_txresetdone_out;
  output [1:0]gt2_txbufstatus_out;
  input [4:0]gt2_txpostcursor_in;
  input [4:0]gt2_txprecursor_in;
  input [1:0]gt2_txchardispmode_in;
  input [1:0]gt2_txchardispval_in;
  input [3:0]gt2_txdiffctrl_in;
  input [6:0]gt2_txmaincursor_in;
  input gt2_txpolarity_in;
  output gt2_tx_buf_err_out;
  input gt2_txprbsforceerr_in;
  input [2:0]gt2_txprbssel_in;
  input gt2_txpcsreset_in;
  input gt2_txinhibit_in;
  input gt2_txpmareset_in;
  output gt3_cplllock_out;
  output gt3_txresetdone_out;
  output [1:0]gt3_txbufstatus_out;
  input [4:0]gt3_txpostcursor_in;
  input [4:0]gt3_txprecursor_in;
  input [1:0]gt3_txchardispmode_in;
  input [1:0]gt3_txchardispval_in;
  input [3:0]gt3_txdiffctrl_in;
  input [6:0]gt3_txmaincursor_in;
  input gt3_txpolarity_in;
  output gt3_tx_buf_err_out;
  input gt3_txprbsforceerr_in;
  input [2:0]gt3_txprbssel_in;
  input gt3_txpcsreset_in;
  input gt3_txinhibit_in;
  input gt3_txpmareset_in;
  output sys_reset_out;
  input [2:0]LOOPBACK;

  wire \<const0> ;
  wire DO_CC_I;
  wire [8:0]DRPADDR_IN;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT;
  wire [15:0]DRPDO_OUT_LANE1;
  wire [15:0]DRPDO_OUT_LANE2;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN;
  wire DRPEN_IN_LANE1;
  wire DRPEN_IN_LANE2;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT;
  wire DRPRDY_OUT_LANE1;
  wire DRPRDY_OUT_LANE2;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN;
  wire DRPWE_IN_LANE1;
  wire DRPWE_IN_LANE2;
  wire DRPWE_IN_LANE3;
  wire ENABLE_ERR_DETECT;
  wire ENABLE_ERR_DETECT_1;
  wire ENABLE_ERR_DETECT_3;
  wire ENABLE_ERR_DETECT_5;
  wire GEN_A;
  wire GEN_CC;
  wire [0:1]GEN_K;
  wire GEN_PAD;
  wire [0:1]GEN_R;
  wire [0:1]GEN_V;
  wire GT_RESET;
  wire HARD_ERR;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire RESET;
  wire RESET_SYMGEN;
  wire [63:0]S_AXI_TX_TDATA;
  wire [7:0]S_AXI_TX_TKEEP;
  wire S_AXI_TX_TLAST;
  wire S_AXI_TX_TREADY;
  wire S_AXI_TX_TVALID;
  wire S_AXI_UFC_TX_ACK;
  wire [2:0]S_AXI_UFC_TX_MS;
  wire S_AXI_UFC_TX_REQ;
  wire [0:3]TXN;
  wire [0:3]TXP;
  wire TX_CHANNEL_UP;
  wire TX_HARD_ERR;
  wire [0:3]TX_LANE_UP;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire [0:15]TX_PE_DATA;
  wire TX_PE_DATA_V;
  wire TX_RESETDONE_OUT;
  wire TX_SYSTEM_RESET;
  wire WARN_CC;
  wire axi_to_ll_pdu_i_n_0;
  wire drpclk_in;
  wire gen_ecp_i;
  wire gen_scp_i;
  wire gen_suf_i;
  wire gt0_cplllock_out;
  wire gt0_tx_buf_err_out;
  wire [0:0]\^gt0_txbufstatus_out ;
  wire [1:0]gt0_txchardispmode_in;
  wire [1:0]gt0_txchardispval_in;
  wire [3:0]gt0_txdiffctrl_in;
  wire gt0_txinhibit_in;
  wire [6:0]gt0_txmaincursor_in;
  wire gt0_txpcsreset_in;
  wire gt0_txpmareset_in;
  wire gt0_txpolarity_in;
  wire [4:0]gt0_txpostcursor_in;
  wire gt0_txprbsforceerr_in;
  wire [2:0]gt0_txprbssel_in;
  wire [4:0]gt0_txprecursor_in;
  wire gt0_txresetdone_out;
  wire gt1_cplllock_out;
  wire gt1_tx_buf_err_out;
  wire [0:0]\^gt1_txbufstatus_out ;
  wire [1:0]gt1_txchardispmode_in;
  wire [1:0]gt1_txchardispval_in;
  wire [3:0]gt1_txdiffctrl_in;
  wire gt1_txinhibit_in;
  wire [6:0]gt1_txmaincursor_in;
  wire gt1_txpcsreset_in;
  wire gt1_txpmareset_in;
  wire gt1_txpolarity_in;
  wire [4:0]gt1_txpostcursor_in;
  wire gt1_txprbsforceerr_in;
  wire [2:0]gt1_txprbssel_in;
  wire [4:0]gt1_txprecursor_in;
  wire gt1_txresetdone_out;
  wire gt2_cplllock_out;
  wire gt2_tx_buf_err_out;
  wire [0:0]\^gt2_txbufstatus_out ;
  wire [1:0]gt2_txchardispmode_in;
  wire [1:0]gt2_txchardispval_in;
  wire [3:0]gt2_txdiffctrl_in;
  wire gt2_txinhibit_in;
  wire [6:0]gt2_txmaincursor_in;
  wire gt2_txpcsreset_in;
  wire gt2_txpmareset_in;
  wire gt2_txpolarity_in;
  wire [4:0]gt2_txpostcursor_in;
  wire gt2_txprbsforceerr_in;
  wire [2:0]gt2_txprbssel_in;
  wire [4:0]gt2_txprecursor_in;
  wire gt2_txresetdone_out;
  wire gt3_cplllock_out;
  wire gt3_tx_buf_err_out;
  wire [0:0]\^gt3_txbufstatus_out ;
  wire [1:0]gt3_txchardispmode_in;
  wire [1:0]gt3_txchardispval_in;
  wire [3:0]gt3_txdiffctrl_in;
  wire gt3_txinhibit_in;
  wire [6:0]gt3_txmaincursor_in;
  wire gt3_txpcsreset_in;
  wire gt3_txpmareset_in;
  wire gt3_txpolarity_in;
  wire [4:0]gt3_txpostcursor_in;
  wire gt3_txprbsforceerr_in;
  wire [2:0]gt3_txprbssel_in;
  wire [4:0]gt3_txprecursor_in;
  wire gt3_txresetdone_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_reset_sync_init_clk;
  wire gt_wrapper_i_n_94;
  wire gt_wrapper_i_n_95;
  wire gt_wrapper_i_n_96;
  wire gt_wrapper_i_n_97;
  wire gt_wrapper_i_n_98;
  wire hard_err_reset_i;
  wire hard_err_reset_i_0;
  wire hard_err_reset_i_2;
  wire hard_err_reset_i_4;
  wire init_clk_in;
  wire new_pkt_r;
  wire reset_channel_i;
  wire reset_sync_user_clk;
  wire sel;
  wire simplex_timer_r0;
  wire \simplex_timer_r[0]_i_4_n_0 ;
  wire [17:0]simplex_timer_r_reg;
  wire \simplex_timer_r_reg[0]_i_3_n_0 ;
  wire \simplex_timer_r_reg[0]_i_3_n_1 ;
  wire \simplex_timer_r_reg[0]_i_3_n_2 ;
  wire \simplex_timer_r_reg[0]_i_3_n_3 ;
  wire \simplex_timer_r_reg[0]_i_3_n_4 ;
  wire \simplex_timer_r_reg[0]_i_3_n_5 ;
  wire \simplex_timer_r_reg[0]_i_3_n_6 ;
  wire \simplex_timer_r_reg[0]_i_3_n_7 ;
  wire \simplex_timer_r_reg[12]_i_1_n_0 ;
  wire \simplex_timer_r_reg[12]_i_1_n_1 ;
  wire \simplex_timer_r_reg[12]_i_1_n_2 ;
  wire \simplex_timer_r_reg[12]_i_1_n_3 ;
  wire \simplex_timer_r_reg[12]_i_1_n_4 ;
  wire \simplex_timer_r_reg[12]_i_1_n_5 ;
  wire \simplex_timer_r_reg[12]_i_1_n_6 ;
  wire \simplex_timer_r_reg[12]_i_1_n_7 ;
  wire \simplex_timer_r_reg[16]_i_1_n_3 ;
  wire \simplex_timer_r_reg[16]_i_1_n_6 ;
  wire \simplex_timer_r_reg[16]_i_1_n_7 ;
  wire \simplex_timer_r_reg[4]_i_1_n_0 ;
  wire \simplex_timer_r_reg[4]_i_1_n_1 ;
  wire \simplex_timer_r_reg[4]_i_1_n_2 ;
  wire \simplex_timer_r_reg[4]_i_1_n_3 ;
  wire \simplex_timer_r_reg[4]_i_1_n_4 ;
  wire \simplex_timer_r_reg[4]_i_1_n_5 ;
  wire \simplex_timer_r_reg[4]_i_1_n_6 ;
  wire \simplex_timer_r_reg[4]_i_1_n_7 ;
  wire \simplex_timer_r_reg[8]_i_1_n_0 ;
  wire \simplex_timer_r_reg[8]_i_1_n_1 ;
  wire \simplex_timer_r_reg[8]_i_1_n_2 ;
  wire \simplex_timer_r_reg[8]_i_1_n_3 ;
  wire \simplex_timer_r_reg[8]_i_1_n_4 ;
  wire \simplex_timer_r_reg[8]_i_1_n_5 ;
  wire \simplex_timer_r_reg[8]_i_1_n_6 ;
  wire \simplex_timer_r_reg[8]_i_1_n_7 ;
  wire sync_clk;
  wire sys_reset_out;
  wire tx_aligned_simplex_r;
  wire tx_aligned_simplex_r_i_2_n_0;
  wire tx_aligned_simplex_r_i_3_n_0;
  wire tx_aligned_simplex_r_i_4_n_0;
  wire tx_aurora_lane_simplex_v5_1_i_n_5;
  wire tx_aurora_lane_simplex_v5_2_i_n_5;
  wire tx_aurora_lane_simplex_v5_3_i_n_5;
  wire tx_bonded1_simplex_r;
  wire tx_bonded1_simplex_r_i_2_n_0;
  wire tx_bonded1_simplex_r_i_3_n_0;
  wire \tx_channel_init_sm_simplex_i/wait_for_lane_up_r0 ;
  wire [1:0]tx_char_is_k_i_0;
  wire [1:0]tx_char_is_k_i_2;
  wire [1:0]tx_char_is_k_i_4;
  wire [1:0]tx_char_is_k_i_6;
  wire [15:0]tx_data_i_0;
  wire [15:0]tx_data_i_16;
  wire [15:0]tx_data_i_32;
  wire [15:0]tx_data_i_48;
  wire tx_dst_rdy;
  wire tx_global_logic_simplex_i_n_10;
  wire tx_global_logic_simplex_i_n_11;
  wire tx_global_logic_simplex_i_n_12;
  wire tx_global_logic_simplex_i_n_14;
  wire tx_global_logic_simplex_i_n_15;
  wire tx_global_logic_simplex_i_n_16;
  wire tx_global_logic_simplex_i_n_19;
  wire tx_global_logic_simplex_i_n_2;
  wire tx_global_logic_simplex_i_n_20;
  wire tx_global_logic_simplex_i_n_21;
  wire tx_global_logic_simplex_i_n_22;
  wire tx_global_logic_simplex_i_n_23;
  wire tx_global_logic_simplex_i_n_24;
  wire tx_global_logic_simplex_i_n_27;
  wire tx_global_logic_simplex_i_n_28;
  wire tx_global_logic_simplex_i_n_29;
  wire tx_global_logic_simplex_i_n_3;
  wire tx_global_logic_simplex_i_n_30;
  wire tx_global_logic_simplex_i_n_31;
  wire tx_global_logic_simplex_i_n_32;
  wire tx_global_logic_simplex_i_n_35;
  wire tx_global_logic_simplex_i_n_36;
  wire tx_global_logic_simplex_i_n_37;
  wire tx_global_logic_simplex_i_n_38;
  wire tx_global_logic_simplex_i_n_4;
  wire tx_global_logic_simplex_i_n_44;
  wire tx_global_logic_simplex_i_n_7;
  wire tx_global_logic_simplex_i_n_8;
  wire tx_global_logic_simplex_i_n_9;
  wire \tx_lane_init_simplex_sm_i/rst_r0 ;
  wire \tx_lane_init_simplex_sm_i/rst_r0_6 ;
  wire \tx_lane_init_simplex_sm_i/rst_r0_7 ;
  wire \tx_lane_init_simplex_sm_i/rst_r0_8 ;
  wire \tx_lane_init_simplex_sm_i/tx_aligned_r ;
  wire \tx_ll_control_i/next_ufc_header_c ;
  wire \tx_ll_control_i/next_ufc_idle_c ;
  wire tx_ll_i_n_1;
  wire tx_ll_i_n_10;
  wire tx_ll_i_n_11;
  wire tx_ll_i_n_13;
  wire tx_ll_i_n_15;
  wire tx_ll_i_n_16;
  wire tx_ll_i_n_17;
  wire tx_ll_i_n_19;
  wire tx_ll_i_n_2;
  wire tx_ll_i_n_20;
  wire tx_ll_i_n_21;
  wire tx_ll_i_n_3;
  wire tx_ll_i_n_38;
  wire tx_ll_i_n_39;
  wire tx_ll_i_n_40;
  wire tx_ll_i_n_41;
  wire tx_ll_i_n_42;
  wire tx_ll_i_n_43;
  wire tx_ll_i_n_44;
  wire tx_ll_i_n_45;
  wire tx_ll_i_n_46;
  wire tx_ll_i_n_47;
  wire tx_ll_i_n_48;
  wire tx_ll_i_n_49;
  wire tx_ll_i_n_50;
  wire tx_ll_i_n_51;
  wire tx_ll_i_n_52;
  wire tx_ll_i_n_53;
  wire tx_ll_i_n_54;
  wire tx_ll_i_n_55;
  wire tx_ll_i_n_56;
  wire tx_ll_i_n_57;
  wire tx_ll_i_n_58;
  wire tx_ll_i_n_59;
  wire tx_ll_i_n_60;
  wire tx_ll_i_n_61;
  wire tx_ll_i_n_62;
  wire tx_ll_i_n_63;
  wire tx_ll_i_n_64;
  wire tx_ll_i_n_65;
  wire tx_ll_i_n_66;
  wire tx_ll_i_n_67;
  wire tx_ll_i_n_68;
  wire tx_ll_i_n_69;
  wire tx_ll_i_n_70;
  wire tx_ll_i_n_71;
  wire tx_ll_i_n_72;
  wire tx_ll_i_n_73;
  wire tx_ll_i_n_74;
  wire tx_ll_i_n_75;
  wire tx_ll_i_n_76;
  wire tx_ll_i_n_77;
  wire tx_ll_i_n_78;
  wire tx_ll_i_n_79;
  wire tx_ll_i_n_80;
  wire tx_ll_i_n_81;
  wire tx_ll_i_n_82;
  wire tx_ll_i_n_83;
  wire tx_ll_i_n_84;
  wire tx_ll_i_n_85;
  wire tx_ll_i_n_9;
  wire tx_reset_simplex_r;
  wire tx_reset_simplex_r_i_2_n_0;
  wire tx_reset_simplex_r_i_3_n_0;
  wire tx_reset_simplex_r_i_4_n_0;
  wire tx_verify_simplex_r;
  wire tx_verify_simplex_r_i_2_n_0;
  wire tx_verify_simplex_r_i_3_n_0;
  wire tx_verify_simplex_r_i_4_n_0;
  wire user_clk;
  wire [3:1]\NLW_simplex_timer_r_reg[16]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_simplex_timer_r_reg[16]_i_1_O_UNCONNECTED ;

  assign gt0_qpllreset_out = \<const0> ;
  assign gt0_txbufstatus_out[1] = gt0_tx_buf_err_out;
  assign gt0_txbufstatus_out[0] = \^gt0_txbufstatus_out [0];
  assign gt1_txbufstatus_out[1] = gt1_tx_buf_err_out;
  assign gt1_txbufstatus_out[0] = \^gt1_txbufstatus_out [0];
  assign gt2_txbufstatus_out[1] = gt2_tx_buf_err_out;
  assign gt2_txbufstatus_out[0] = \^gt2_txbufstatus_out [0];
  assign gt3_txbufstatus_out[1] = gt3_tx_buf_err_out;
  assign gt3_txbufstatus_out[0] = \^gt3_txbufstatus_out [0];
  GND GND
       (.G(\<const0> ));
  efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL axi_to_ll_pdu_i
       (.new_pkt_r(new_pkt_r),
        .new_pkt_r_reg_0(axi_to_ll_pdu_i_n_0),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC core_reset_logic_i
       (.RESET_SYMGEN(RESET_SYMGEN),
        .SYSTEM_RESET_reg_0(sys_reset_out),
        .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
        .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
        .TX_CHANNEL_UP(TX_CHANNEL_UP),
        .TX_LOCK(TX_LOCK),
        .gt_txresetdone_r2_reg_0(gt_wrapper_i_n_98),
        .init_clk_in(init_clk_in),
        .new_pkt_r(new_pkt_r),
        .new_pkt_r_reg(axi_to_ll_pdu_i_n_0),
        .out(reset_sync_user_clk),
        .reset_channel_i(reset_channel_i),
        .tx_dst_rdy(tx_dst_rdy),
        .tx_reset_simplex_r(tx_reset_simplex_r),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(\tx_channel_init_sm_simplex_i/wait_for_lane_up_r0 ));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync gt_reset_cdc_sync
       (.AR(gt_reset_sync_init_clk),
        .GT_RESET(GT_RESET),
        .init_clk_in(init_clk_in));
  efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER gt_wrapper_i
       (.AR(gt_reset_sync_init_clk),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPADDR_IN_LANE1(DRPADDR_IN_LANE1),
        .DRPADDR_IN_LANE2(DRPADDR_IN_LANE2),
        .DRPADDR_IN_LANE3(DRPADDR_IN_LANE3),
        .DRPDI_IN(DRPDI_IN),
        .DRPDI_IN_LANE1(DRPDI_IN_LANE1),
        .DRPDI_IN_LANE2(DRPDI_IN_LANE2),
        .DRPDI_IN_LANE3(DRPDI_IN_LANE3),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPDO_OUT_LANE1(DRPDO_OUT_LANE1),
        .DRPDO_OUT_LANE2(DRPDO_OUT_LANE2),
        .DRPDO_OUT_LANE3(DRPDO_OUT_LANE3),
        .DRPEN_IN(DRPEN_IN),
        .DRPEN_IN_LANE1(DRPEN_IN_LANE1),
        .DRPEN_IN_LANE2(DRPEN_IN_LANE2),
        .DRPEN_IN_LANE3(DRPEN_IN_LANE3),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPRDY_OUT_LANE1(DRPRDY_OUT_LANE1),
        .DRPRDY_OUT_LANE2(DRPRDY_OUT_LANE2),
        .DRPRDY_OUT_LANE3(DRPRDY_OUT_LANE3),
        .DRPWE_IN(DRPWE_IN),
        .DRPWE_IN_LANE1(DRPWE_IN_LANE1),
        .DRPWE_IN_LANE2(DRPWE_IN_LANE2),
        .DRPWE_IN_LANE3(DRPWE_IN_LANE3),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .ENABLE_ERR_DETECT_0(ENABLE_ERR_DETECT_1),
        .ENABLE_ERR_DETECT_1(ENABLE_ERR_DETECT_3),
        .ENABLE_ERR_DETECT_2(ENABLE_ERR_DETECT_5),
        .ENABLE_ERR_DETECT_Buffer_reg(gt_wrapper_i_n_94),
        .ENABLE_ERR_DETECT_Buffer_reg_0(gt_wrapper_i_n_95),
        .ENABLE_ERR_DETECT_Buffer_reg_1(gt_wrapper_i_n_96),
        .ENABLE_ERR_DETECT_Buffer_reg_2(gt_wrapper_i_n_97),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg (gt_wrapper_i_n_98),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .TXCHARISK(tx_char_is_k_i_0),
        .TXDATA(tx_data_i_0),
        .TXN(TXN),
        .TXP(TXP),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .TX_RESETDONE_OUT(TX_RESETDONE_OUT),
        .drpclk_in(drpclk_in),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_txbufstatus_out({gt0_tx_buf_err_out,\^gt0_txbufstatus_out }),
        .gt0_txchardispmode_in(gt0_txchardispmode_in),
        .gt0_txchardispval_in(gt0_txchardispval_in),
        .gt0_txdiffctrl_in(gt0_txdiffctrl_in),
        .gt0_txinhibit_in(gt0_txinhibit_in),
        .gt0_txmaincursor_in(gt0_txmaincursor_in),
        .gt0_txpcsreset_in(gt0_txpcsreset_in),
        .gt0_txpmareset_in(gt0_txpmareset_in),
        .gt0_txpolarity_in(gt0_txpolarity_in),
        .gt0_txpostcursor_in(gt0_txpostcursor_in),
        .gt0_txprbsforceerr_in(gt0_txprbsforceerr_in),
        .gt0_txprbssel_in(gt0_txprbssel_in),
        .gt0_txprecursor_in(gt0_txprecursor_in),
        .gt0_txresetdone_out(gt0_txresetdone_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_cplllock_out_0(tx_data_i_16),
        .gt1_cplllock_out_1(tx_char_is_k_i_2),
        .gt1_txbufstatus_out({gt1_tx_buf_err_out,\^gt1_txbufstatus_out }),
        .gt1_txchardispmode_in(gt1_txchardispmode_in),
        .gt1_txchardispval_in(gt1_txchardispval_in),
        .gt1_txdiffctrl_in(gt1_txdiffctrl_in),
        .gt1_txinhibit_in(gt1_txinhibit_in),
        .gt1_txmaincursor_in(gt1_txmaincursor_in),
        .gt1_txpcsreset_in(gt1_txpcsreset_in),
        .gt1_txpmareset_in(gt1_txpmareset_in),
        .gt1_txpolarity_in(gt1_txpolarity_in),
        .gt1_txpostcursor_in(gt1_txpostcursor_in),
        .gt1_txprbsforceerr_in(gt1_txprbsforceerr_in),
        .gt1_txprbssel_in(gt1_txprbssel_in),
        .gt1_txprecursor_in(gt1_txprecursor_in),
        .gt1_txresetdone_out(gt1_txresetdone_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_cplllock_out_0(tx_data_i_32),
        .gt2_cplllock_out_1(tx_char_is_k_i_4),
        .gt2_txbufstatus_out({gt2_tx_buf_err_out,\^gt2_txbufstatus_out }),
        .gt2_txchardispmode_in(gt2_txchardispmode_in),
        .gt2_txchardispval_in(gt2_txchardispval_in),
        .gt2_txdiffctrl_in(gt2_txdiffctrl_in),
        .gt2_txinhibit_in(gt2_txinhibit_in),
        .gt2_txmaincursor_in(gt2_txmaincursor_in),
        .gt2_txpcsreset_in(gt2_txpcsreset_in),
        .gt2_txpmareset_in(gt2_txpmareset_in),
        .gt2_txpolarity_in(gt2_txpolarity_in),
        .gt2_txpostcursor_in(gt2_txpostcursor_in),
        .gt2_txprbsforceerr_in(gt2_txprbsforceerr_in),
        .gt2_txprbssel_in(gt2_txprbssel_in),
        .gt2_txprecursor_in(gt2_txprecursor_in),
        .gt2_txresetdone_out(gt2_txresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_cplllock_out_0(tx_data_i_48),
        .gt3_cplllock_out_1(tx_char_is_k_i_6),
        .gt3_txbufstatus_out({gt3_tx_buf_err_out,\^gt3_txbufstatus_out }),
        .gt3_txchardispmode_in(gt3_txchardispmode_in),
        .gt3_txchardispval_in(gt3_txchardispval_in),
        .gt3_txdiffctrl_in(gt3_txdiffctrl_in),
        .gt3_txinhibit_in(gt3_txinhibit_in),
        .gt3_txmaincursor_in(gt3_txmaincursor_in),
        .gt3_txpcsreset_in(gt3_txpcsreset_in),
        .gt3_txpmareset_in(gt3_txpmareset_in),
        .gt3_txpolarity_in(gt3_txpolarity_in),
        .gt3_txpostcursor_in(gt3_txpostcursor_in),
        .gt3_txprbsforceerr_in(gt3_txprbsforceerr_in),
        .gt3_txprbssel_in(gt3_txprbssel_in),
        .gt3_txprecursor_in(gt3_txprecursor_in),
        .gt3_txresetdone_out(gt3_txresetdone_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0 reset_sync_user_clk_cdc_sync
       (.TX_SYSTEM_RESET(TX_SYSTEM_RESET),
        .out(reset_sync_user_clk),
        .user_clk(user_clk));
  LUT1 #(
    .INIT(2'h1)) 
    \simplex_timer_r[0]_i_2 
       (.I0(tx_verify_simplex_r),
        .O(sel));
  LUT1 #(
    .INIT(2'h1)) 
    \simplex_timer_r[0]_i_4 
       (.I0(simplex_timer_r_reg[0]),
        .O(\simplex_timer_r[0]_i_4_n_0 ));
  FDRE \simplex_timer_r_reg[0] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[0]_i_3_n_7 ),
        .Q(simplex_timer_r_reg[0]),
        .R(simplex_timer_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \simplex_timer_r_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\simplex_timer_r_reg[0]_i_3_n_0 ,\simplex_timer_r_reg[0]_i_3_n_1 ,\simplex_timer_r_reg[0]_i_3_n_2 ,\simplex_timer_r_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\simplex_timer_r_reg[0]_i_3_n_4 ,\simplex_timer_r_reg[0]_i_3_n_5 ,\simplex_timer_r_reg[0]_i_3_n_6 ,\simplex_timer_r_reg[0]_i_3_n_7 }),
        .S({simplex_timer_r_reg[3:1],\simplex_timer_r[0]_i_4_n_0 }));
  FDRE \simplex_timer_r_reg[10] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[8]_i_1_n_5 ),
        .Q(simplex_timer_r_reg[10]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[11] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[8]_i_1_n_4 ),
        .Q(simplex_timer_r_reg[11]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[12] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[12]_i_1_n_7 ),
        .Q(simplex_timer_r_reg[12]),
        .R(simplex_timer_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \simplex_timer_r_reg[12]_i_1 
       (.CI(\simplex_timer_r_reg[8]_i_1_n_0 ),
        .CO({\simplex_timer_r_reg[12]_i_1_n_0 ,\simplex_timer_r_reg[12]_i_1_n_1 ,\simplex_timer_r_reg[12]_i_1_n_2 ,\simplex_timer_r_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\simplex_timer_r_reg[12]_i_1_n_4 ,\simplex_timer_r_reg[12]_i_1_n_5 ,\simplex_timer_r_reg[12]_i_1_n_6 ,\simplex_timer_r_reg[12]_i_1_n_7 }),
        .S(simplex_timer_r_reg[15:12]));
  FDRE \simplex_timer_r_reg[13] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[12]_i_1_n_6 ),
        .Q(simplex_timer_r_reg[13]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[14] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[12]_i_1_n_5 ),
        .Q(simplex_timer_r_reg[14]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[15] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[12]_i_1_n_4 ),
        .Q(simplex_timer_r_reg[15]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[16] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[16]_i_1_n_7 ),
        .Q(simplex_timer_r_reg[16]),
        .R(simplex_timer_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \simplex_timer_r_reg[16]_i_1 
       (.CI(\simplex_timer_r_reg[12]_i_1_n_0 ),
        .CO({\NLW_simplex_timer_r_reg[16]_i_1_CO_UNCONNECTED [3:1],\simplex_timer_r_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_simplex_timer_r_reg[16]_i_1_O_UNCONNECTED [3:2],\simplex_timer_r_reg[16]_i_1_n_6 ,\simplex_timer_r_reg[16]_i_1_n_7 }),
        .S({1'b0,1'b0,simplex_timer_r_reg[17:16]}));
  FDRE \simplex_timer_r_reg[17] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[16]_i_1_n_6 ),
        .Q(simplex_timer_r_reg[17]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[1] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[0]_i_3_n_6 ),
        .Q(simplex_timer_r_reg[1]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[2] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[0]_i_3_n_5 ),
        .Q(simplex_timer_r_reg[2]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[3] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[0]_i_3_n_4 ),
        .Q(simplex_timer_r_reg[3]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[4] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[4]_i_1_n_7 ),
        .Q(simplex_timer_r_reg[4]),
        .R(simplex_timer_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \simplex_timer_r_reg[4]_i_1 
       (.CI(\simplex_timer_r_reg[0]_i_3_n_0 ),
        .CO({\simplex_timer_r_reg[4]_i_1_n_0 ,\simplex_timer_r_reg[4]_i_1_n_1 ,\simplex_timer_r_reg[4]_i_1_n_2 ,\simplex_timer_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\simplex_timer_r_reg[4]_i_1_n_4 ,\simplex_timer_r_reg[4]_i_1_n_5 ,\simplex_timer_r_reg[4]_i_1_n_6 ,\simplex_timer_r_reg[4]_i_1_n_7 }),
        .S(simplex_timer_r_reg[7:4]));
  FDRE \simplex_timer_r_reg[5] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[4]_i_1_n_6 ),
        .Q(simplex_timer_r_reg[5]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[6] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[4]_i_1_n_5 ),
        .Q(simplex_timer_r_reg[6]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[7] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[4]_i_1_n_4 ),
        .Q(simplex_timer_r_reg[7]),
        .R(simplex_timer_r0));
  FDRE \simplex_timer_r_reg[8] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[8]_i_1_n_7 ),
        .Q(simplex_timer_r_reg[8]),
        .R(simplex_timer_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \simplex_timer_r_reg[8]_i_1 
       (.CI(\simplex_timer_r_reg[4]_i_1_n_0 ),
        .CO({\simplex_timer_r_reg[8]_i_1_n_0 ,\simplex_timer_r_reg[8]_i_1_n_1 ,\simplex_timer_r_reg[8]_i_1_n_2 ,\simplex_timer_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\simplex_timer_r_reg[8]_i_1_n_4 ,\simplex_timer_r_reg[8]_i_1_n_5 ,\simplex_timer_r_reg[8]_i_1_n_6 ,\simplex_timer_r_reg[8]_i_1_n_7 }),
        .S(simplex_timer_r_reg[11:8]));
  FDRE \simplex_timer_r_reg[9] 
       (.C(user_clk),
        .CE(sel),
        .D(\simplex_timer_r_reg[8]_i_1_n_6 ),
        .Q(simplex_timer_r_reg[9]),
        .R(simplex_timer_r0));
  efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE standard_cc_module_i
       (.DO_CC_I(DO_CC_I),
        .DO_CC_reg_0(sys_reset_out),
        .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
        .WARN_CC(WARN_CC),
        .next_ufc_header_c(\tx_ll_control_i/next_ufc_header_c ),
        .next_ufc_idle_c(\tx_ll_control_i/next_ufc_idle_c ),
        .ufc_idle_r_reg(tx_ll_i_n_13),
        .user_clk(user_clk));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    tx_aligned_simplex_r_i_2
       (.I0(simplex_timer_r_reg[11]),
        .I1(simplex_timer_r_reg[13]),
        .I2(simplex_timer_r_reg[8]),
        .I3(simplex_timer_r_reg[10]),
        .I4(simplex_timer_r_reg[17]),
        .I5(simplex_timer_r_reg[14]),
        .O(tx_aligned_simplex_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    tx_aligned_simplex_r_i_3
       (.I0(simplex_timer_r_reg[0]),
        .I1(simplex_timer_r_reg[1]),
        .I2(simplex_timer_r_reg[3]),
        .I3(simplex_timer_r_reg[2]),
        .O(tx_aligned_simplex_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    tx_aligned_simplex_r_i_4
       (.I0(simplex_timer_r_reg[9]),
        .I1(tx_verify_simplex_r_i_2_n_0),
        .I2(simplex_timer_r_reg[12]),
        .O(tx_aligned_simplex_r_i_4_n_0));
  FDRE tx_aligned_simplex_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_global_logic_simplex_i_n_37),
        .Q(tx_aligned_simplex_r),
        .R(1'b0));
  efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5 tx_aurora_lane_simplex_v5_0_i
       (.D(HARD_ERR),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .GEN_A(GEN_A),
        .GEN_CC(GEN_CC),
        .Q(GEN_PAD),
        .RESET(RESET),
        .SS(\tx_lane_init_simplex_sm_i/rst_r0_8 ),
        .TXCHARISK(tx_char_is_k_i_0),
        .TXDATA(tx_data_i_0),
        .TX_LANE_UP(TX_LANE_UP[0]),
        .\fc_nb_r_reg[0] (tx_ll_i_n_9),
        .\fc_nb_r_reg[1] (tx_ll_i_n_10),
        .\fc_nb_r_reg[2] (tx_ll_i_n_11),
        .\gen_k_r_reg[0] ({GEN_K[0],GEN_K[1]}),
        .\gen_r_r_reg[0] ({GEN_R[0],GEN_R[1]}),
        .gen_scp_i(gen_scp_i),
        .gen_suf_i(gen_suf_i),
        .\gen_v_r_reg[0] ({GEN_V[0],GEN_V[1]}),
        .hard_err_flop_r_reg(gt_wrapper_i_n_94),
        .hard_err_reset_i(hard_err_reset_i),
        .tx_aligned_r(\tx_lane_init_simplex_sm_i/tx_aligned_r ),
        .tx_aligned_simplex_r(tx_aligned_simplex_r),
        .\tx_pe_data_r_reg[0] ({TX_PE_DATA[0],TX_PE_DATA[1],TX_PE_DATA[2],TX_PE_DATA[3],TX_PE_DATA[4],TX_PE_DATA[5],TX_PE_DATA[6],TX_PE_DATA[7],TX_PE_DATA[8],TX_PE_DATA[9],TX_PE_DATA[10],TX_PE_DATA[11],TX_PE_DATA[12],TX_PE_DATA[13],TX_PE_DATA[14],TX_PE_DATA[15]}),
        .tx_pe_data_v_r_reg(TX_PE_DATA_V),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1 tx_aurora_lane_simplex_v5_1_i
       (.D(tx_aurora_lane_simplex_v5_1_i_n_5),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT_1),
        .Q(tx_ll_i_n_19),
        .SS(\tx_lane_init_simplex_sm_i/rst_r0_7 ),
        .\TX_CHAR_IS_K_Buffer_reg[0] (tx_char_is_k_i_2),
        .\TX_DATA_Buffer_reg[7] (tx_data_i_16),
        .TX_LANE_UP(TX_LANE_UP[1]),
        .gen_a_r_reg(tx_global_logic_simplex_i_n_14),
        .gen_cc_r_reg(tx_ll_i_n_1),
        .\gen_k_r_reg[0] ({tx_global_logic_simplex_i_n_19,tx_global_logic_simplex_i_n_20}),
        .\gen_r_r_reg[0] ({tx_global_logic_simplex_i_n_27,tx_global_logic_simplex_i_n_28}),
        .\gen_v_r_reg[0] ({tx_global_logic_simplex_i_n_7,tx_global_logic_simplex_i_n_8}),
        .hard_err_flop_r_reg(gt_wrapper_i_n_95),
        .hard_err_reset_i(hard_err_reset_i_0),
        .lane_up_flop_i(tx_global_logic_simplex_i_n_2),
        .tx_aligned_r(\tx_lane_init_simplex_sm_i/tx_aligned_r ),
        .\tx_pe_data_r_reg[0] ({tx_ll_i_n_38,tx_ll_i_n_39,tx_ll_i_n_40,tx_ll_i_n_41,tx_ll_i_n_42,tx_ll_i_n_43,tx_ll_i_n_44,tx_ll_i_n_45,tx_ll_i_n_46,tx_ll_i_n_47,tx_ll_i_n_48,tx_ll_i_n_49,tx_ll_i_n_50,tx_ll_i_n_51,tx_ll_i_n_52,tx_ll_i_n_53}),
        .tx_pe_data_v_r_reg(tx_ll_i_n_15),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2 tx_aurora_lane_simplex_v5_2_i
       (.D(tx_aurora_lane_simplex_v5_2_i_n_5),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT_3),
        .Q(tx_ll_i_n_20),
        .SS(\tx_lane_init_simplex_sm_i/rst_r0_6 ),
        .\TX_CHAR_IS_K_Buffer_reg[0] (tx_char_is_k_i_4),
        .\TX_DATA_Buffer_reg[7] (tx_data_i_32),
        .TX_LANE_UP(TX_LANE_UP[2]),
        .gen_a_r_reg(tx_global_logic_simplex_i_n_15),
        .gen_cc_r_reg(tx_ll_i_n_2),
        .\gen_k_r_reg[0] ({tx_global_logic_simplex_i_n_21,tx_global_logic_simplex_i_n_22}),
        .\gen_r_r_reg[0] ({tx_global_logic_simplex_i_n_29,tx_global_logic_simplex_i_n_30}),
        .\gen_v_r_reg[0] ({tx_global_logic_simplex_i_n_9,tx_global_logic_simplex_i_n_10}),
        .hard_err_flop_r_reg(gt_wrapper_i_n_96),
        .hard_err_reset_i(hard_err_reset_i_2),
        .lane_up_flop_i(tx_global_logic_simplex_i_n_3),
        .tx_aligned_r(\tx_lane_init_simplex_sm_i/tx_aligned_r ),
        .\tx_pe_data_r_reg[0] ({tx_ll_i_n_54,tx_ll_i_n_55,tx_ll_i_n_56,tx_ll_i_n_57,tx_ll_i_n_58,tx_ll_i_n_59,tx_ll_i_n_60,tx_ll_i_n_61,tx_ll_i_n_62,tx_ll_i_n_63,tx_ll_i_n_64,tx_ll_i_n_65,tx_ll_i_n_66,tx_ll_i_n_67,tx_ll_i_n_68,tx_ll_i_n_69}),
        .tx_pe_data_v_r_reg(tx_ll_i_n_16),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3 tx_aurora_lane_simplex_v5_3_i
       (.D(tx_aurora_lane_simplex_v5_3_i_n_5),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT_5),
        .Q(tx_ll_i_n_21),
        .SS(\tx_lane_init_simplex_sm_i/rst_r0 ),
        .\TX_CHAR_IS_K_Buffer_reg[0] (tx_char_is_k_i_6),
        .\TX_DATA_Buffer_reg[7] (tx_data_i_48),
        .TX_LANE_UP(TX_LANE_UP[3]),
        .gen_a_r_reg(tx_global_logic_simplex_i_n_16),
        .gen_cc_r_reg(tx_ll_i_n_3),
        .gen_ecp_i(gen_ecp_i),
        .\gen_k_r_reg[0] ({tx_global_logic_simplex_i_n_23,tx_global_logic_simplex_i_n_24}),
        .\gen_r_r_reg[0] ({tx_global_logic_simplex_i_n_31,tx_global_logic_simplex_i_n_32}),
        .\gen_v_r_reg[0] ({tx_global_logic_simplex_i_n_11,tx_global_logic_simplex_i_n_12}),
        .hard_err_flop_r_reg(gt_wrapper_i_n_97),
        .hard_err_reset_i(hard_err_reset_i_4),
        .lane_up_flop_i(tx_global_logic_simplex_i_n_4),
        .tx_aligned_r(\tx_lane_init_simplex_sm_i/tx_aligned_r ),
        .\tx_pe_data_r_reg[0] ({tx_ll_i_n_70,tx_ll_i_n_71,tx_ll_i_n_72,tx_ll_i_n_73,tx_ll_i_n_74,tx_ll_i_n_75,tx_ll_i_n_76,tx_ll_i_n_77,tx_ll_i_n_78,tx_ll_i_n_79,tx_ll_i_n_80,tx_ll_i_n_81,tx_ll_i_n_82,tx_ll_i_n_83,tx_ll_i_n_84,tx_ll_i_n_85}),
        .tx_pe_data_v_r_reg(tx_ll_i_n_17),
        .user_clk(user_clk));
  LUT2 #(
    .INIT(4'hE)) 
    tx_bonded1_simplex_r_i_2
       (.I0(tx_verify_simplex_r_i_2_n_0),
        .I1(simplex_timer_r_reg[9]),
        .O(tx_bonded1_simplex_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    tx_bonded1_simplex_r_i_3
       (.I0(simplex_timer_r_reg[0]),
        .I1(simplex_timer_r_reg[1]),
        .I2(simplex_timer_r_reg[2]),
        .I3(simplex_timer_r_reg[8]),
        .I4(simplex_timer_r_reg[3]),
        .O(tx_bonded1_simplex_r_i_3_n_0));
  FDRE tx_bonded1_simplex_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_global_logic_simplex_i_n_36),
        .Q(tx_bonded1_simplex_r),
        .R(1'b0));
  efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX tx_global_logic_simplex_i
       (.CHANNEL_HARD_ERR_Buffer_reg(TX_HARD_ERR),
        .D({HARD_ERR,tx_aurora_lane_simplex_v5_1_i_n_5,tx_aurora_lane_simplex_v5_2_i_n_5,tx_aurora_lane_simplex_v5_3_i_n_5}),
        .GEN_A(GEN_A),
        .POWER_DOWN(POWER_DOWN),
        .RESET(RESET),
        .RESET_SYMGEN(RESET_SYMGEN),
        .SS(\tx_lane_init_simplex_sm_i/rst_r0_8 ),
        .TX_CHANNEL_UP(TX_CHANNEL_UP),
        .TX_LANE_UP(TX_LANE_UP),
        .gen_a_flop_1_i(tx_global_logic_simplex_i_n_14),
        .gen_a_flop_2_i(tx_global_logic_simplex_i_n_15),
        .gen_a_flop_3_i(tx_global_logic_simplex_i_n_16),
        .gen_k_flop_0_i({GEN_K[0],GEN_K[1]}),
        .gen_k_flop_2_i({tx_global_logic_simplex_i_n_19,tx_global_logic_simplex_i_n_20}),
        .gen_k_flop_4_i({tx_global_logic_simplex_i_n_21,tx_global_logic_simplex_i_n_22}),
        .gen_k_flop_6_i({tx_global_logic_simplex_i_n_23,tx_global_logic_simplex_i_n_24}),
        .gen_r_flop_0_i({GEN_R[0],GEN_R[1]}),
        .gen_r_flop_2_i({tx_global_logic_simplex_i_n_27,tx_global_logic_simplex_i_n_28}),
        .gen_r_flop_4_i({tx_global_logic_simplex_i_n_29,tx_global_logic_simplex_i_n_30}),
        .gen_r_flop_6_i({tx_global_logic_simplex_i_n_31,tx_global_logic_simplex_i_n_32}),
        .gen_v_flop_0_i({GEN_V[0],GEN_V[1]}),
        .gen_v_flop_2_i({tx_global_logic_simplex_i_n_7,tx_global_logic_simplex_i_n_8}),
        .gen_v_flop_4_i({tx_global_logic_simplex_i_n_9,tx_global_logic_simplex_i_n_10}),
        .gen_v_flop_6_i({tx_global_logic_simplex_i_n_11,tx_global_logic_simplex_i_n_12}),
        .hard_err_reset_i(hard_err_reset_i),
        .hard_err_reset_i_0(hard_err_reset_i_0),
        .hard_err_reset_i_1(hard_err_reset_i_2),
        .hard_err_reset_i_2(hard_err_reset_i_4),
        .reset_channel_i(reset_channel_i),
        .reset_lanes_flop_1_i(tx_global_logic_simplex_i_n_2),
        .reset_lanes_flop_1_i_0(\tx_lane_init_simplex_sm_i/rst_r0_7 ),
        .reset_lanes_flop_2_i(tx_global_logic_simplex_i_n_3),
        .reset_lanes_flop_2_i_0(\tx_lane_init_simplex_sm_i/rst_r0_6 ),
        .reset_lanes_flop_3_i(tx_global_logic_simplex_i_n_4),
        .reset_lanes_flop_3_i_0(\tx_lane_init_simplex_sm_i/rst_r0 ),
        .reset_lanes_flop_3_i_1(sys_reset_out),
        .simplex_timer_r0(simplex_timer_r0),
        .simplex_timer_r_reg(simplex_timer_r_reg[2:0]),
        .tx_aligned_simplex_r(tx_aligned_simplex_r),
        .tx_aligned_simplex_r_reg(tx_global_logic_simplex_i_n_37),
        .tx_aligned_simplex_r_reg_0(tx_aligned_simplex_r_i_2_n_0),
        .tx_aligned_simplex_r_reg_1(tx_aligned_simplex_r_i_3_n_0),
        .tx_aligned_simplex_r_reg_2(tx_aligned_simplex_r_i_4_n_0),
        .tx_bonded1_simplex_r(tx_bonded1_simplex_r),
        .tx_bonded1_simplex_r_reg(tx_global_logic_simplex_i_n_36),
        .tx_bonded1_simplex_r_reg_0(tx_verify_simplex_r_i_3_n_0),
        .tx_bonded1_simplex_r_reg_1(tx_bonded1_simplex_r_i_2_n_0),
        .tx_bonded1_simplex_r_reg_2(tx_bonded1_simplex_r_i_3_n_0),
        .tx_channel_up_i(tx_global_logic_simplex_i_n_44),
        .tx_reset_simplex_r(tx_reset_simplex_r),
        .tx_reset_simplex_r_reg(tx_global_logic_simplex_i_n_38),
        .tx_reset_simplex_r_reg_0(tx_reset_simplex_r_i_2_n_0),
        .tx_verify_simplex_r(tx_verify_simplex_r),
        .tx_verify_simplex_r_reg(tx_global_logic_simplex_i_n_35),
        .tx_verify_simplex_r_reg_0(tx_verify_simplex_r_i_2_n_0),
        .tx_verify_simplex_r_reg_1(tx_verify_simplex_r_i_4_n_0),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(\tx_channel_init_sm_simplex_i/wait_for_lane_up_r0 ));
  efex_aurora_hub2_efex_aurora_hub2_TX_LL tx_ll_i
       (.DO_CC_I(DO_CC_I),
        .GEN_CC(GEN_CC),
        .\GEN_PAD_Buffer_reg[0] ({GEN_PAD,tx_ll_i_n_19,tx_ll_i_n_20,tx_ll_i_n_21}),
        .Q({TX_PE_DATA_V,tx_ll_i_n_15,tx_ll_i_n_16,tx_ll_i_n_17}),
        .S_AXI_TX_TDATA(S_AXI_TX_TDATA),
        .S_AXI_TX_TKEEP(S_AXI_TX_TKEEP),
        .S_AXI_TX_TLAST(S_AXI_TX_TLAST),
        .S_AXI_TX_TREADY(S_AXI_TX_TREADY),
        .S_AXI_TX_TVALID(S_AXI_TX_TVALID),
        .S_AXI_UFC_TX_MS(S_AXI_UFC_TX_MS),
        .S_AXI_UFC_TX_REQ(S_AXI_UFC_TX_REQ),
        .\TX_PE_DATA_Buffer_reg[0] ({TX_PE_DATA[0],TX_PE_DATA[1],TX_PE_DATA[2],TX_PE_DATA[3],TX_PE_DATA[4],TX_PE_DATA[5],TX_PE_DATA[6],TX_PE_DATA[7],TX_PE_DATA[8],TX_PE_DATA[9],TX_PE_DATA[10],TX_PE_DATA[11],TX_PE_DATA[12],TX_PE_DATA[13],TX_PE_DATA[14],TX_PE_DATA[15],tx_ll_i_n_38,tx_ll_i_n_39,tx_ll_i_n_40,tx_ll_i_n_41,tx_ll_i_n_42,tx_ll_i_n_43,tx_ll_i_n_44,tx_ll_i_n_45,tx_ll_i_n_46,tx_ll_i_n_47,tx_ll_i_n_48,tx_ll_i_n_49,tx_ll_i_n_50,tx_ll_i_n_51,tx_ll_i_n_52,tx_ll_i_n_53,tx_ll_i_n_54,tx_ll_i_n_55,tx_ll_i_n_56,tx_ll_i_n_57,tx_ll_i_n_58,tx_ll_i_n_59,tx_ll_i_n_60,tx_ll_i_n_61,tx_ll_i_n_62,tx_ll_i_n_63,tx_ll_i_n_64,tx_ll_i_n_65,tx_ll_i_n_66,tx_ll_i_n_67,tx_ll_i_n_68,tx_ll_i_n_69,tx_ll_i_n_70,tx_ll_i_n_71,tx_ll_i_n_72,tx_ll_i_n_73,tx_ll_i_n_74,tx_ll_i_n_75,tx_ll_i_n_76,tx_ll_i_n_77,tx_ll_i_n_78,tx_ll_i_n_79,tx_ll_i_n_80,tx_ll_i_n_81,tx_ll_i_n_82,tx_ll_i_n_83,tx_ll_i_n_84,tx_ll_i_n_85}),
        .WARN_CC(WARN_CC),
        .gen_cc_flop_1_i(tx_ll_i_n_1),
        .gen_cc_flop_2_i(tx_ll_i_n_2),
        .gen_cc_flop_3_i(tx_ll_i_n_3),
        .gen_ecp_i(gen_ecp_i),
        .gen_scp_i(gen_scp_i),
        .gen_suf_i(gen_suf_i),
        .halt_c_pipeline_r_reg_inv(tx_global_logic_simplex_i_n_44),
        .next_ufc_header_c(\tx_ll_control_i/next_ufc_header_c ),
        .next_ufc_idle_c(\tx_ll_control_i/next_ufc_idle_c ),
        .\s_axi_ufc_tx_tdata[0] (tx_ll_i_n_11),
        .\s_axi_ufc_tx_tdata[1] (tx_ll_i_n_10),
        .\s_axi_ufc_tx_tdata[2] (tx_ll_i_n_9),
        .tx_dst_rdy(tx_dst_rdy),
        .tx_sof_n_pipeline_r_reg(axi_to_ll_pdu_i_n_0),
        .ufc_header_r_reg(S_AXI_UFC_TX_ACK),
        .\ufc_message_count_r_reg[2] (tx_ll_i_n_13),
        .user_clk(user_clk));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    tx_reset_simplex_r_i_2
       (.I0(tx_reset_simplex_r_i_3_n_0),
        .I1(tx_reset_simplex_r_i_4_n_0),
        .I2(simplex_timer_r_reg[12]),
        .I3(tx_verify_simplex_r_i_2_n_0),
        .I4(simplex_timer_r_reg[9]),
        .O(tx_reset_simplex_r_i_2_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    tx_reset_simplex_r_i_3
       (.I0(simplex_timer_r_reg[17]),
        .I1(simplex_timer_r_reg[14]),
        .I2(simplex_timer_r_reg[3]),
        .O(tx_reset_simplex_r_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    tx_reset_simplex_r_i_4
       (.I0(simplex_timer_r_reg[10]),
        .I1(simplex_timer_r_reg[8]),
        .I2(simplex_timer_r_reg[13]),
        .I3(simplex_timer_r_reg[11]),
        .O(tx_reset_simplex_r_i_4_n_0));
  FDRE tx_reset_simplex_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_global_logic_simplex_i_n_38),
        .Q(tx_reset_simplex_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    tx_verify_simplex_r_i_2
       (.I0(simplex_timer_r_reg[15]),
        .I1(simplex_timer_r_reg[16]),
        .I2(simplex_timer_r_reg[6]),
        .I3(simplex_timer_r_reg[7]),
        .I4(simplex_timer_r_reg[5]),
        .I5(simplex_timer_r_reg[4]),
        .O(tx_verify_simplex_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    tx_verify_simplex_r_i_3
       (.I0(simplex_timer_r_reg[12]),
        .I1(simplex_timer_r_reg[13]),
        .I2(simplex_timer_r_reg[10]),
        .I3(simplex_timer_r_reg[11]),
        .I4(simplex_timer_r_reg[17]),
        .I5(simplex_timer_r_reg[14]),
        .O(tx_verify_simplex_r_i_3_n_0));
  LUT6 #(
    .INIT(64'h0080000000000000)) 
    tx_verify_simplex_r_i_4
       (.I0(simplex_timer_r_reg[2]),
        .I1(simplex_timer_r_reg[3]),
        .I2(simplex_timer_r_reg[1]),
        .I3(simplex_timer_r_reg[0]),
        .I4(simplex_timer_r_reg[9]),
        .I5(simplex_timer_r_reg[8]),
        .O(tx_verify_simplex_r_i_4_n_0));
  FDRE tx_verify_simplex_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_global_logic_simplex_i_n_35),
        .Q(tx_verify_simplex_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_gt" *) 
module efex_aurora_hub2_efex_aurora_hub2_gt
   (gt0_cplllock_out,
    DRPRDY_OUT,
    TXN,
    TXP,
    gt0_txresetdone_out,
    DRPDO_OUT,
    gt0_txbufstatus_out,
    ENABLE_ERR_DETECT_Buffer_reg,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt_refclk1,
    gt_tx_reset_i,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    gt_rxdfeagchold_i,
    gt_rxdfelfhold_i,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    POWER_DOWN,
    gt0_txinhibit_in,
    gt0_txpcsreset_in,
    gt0_txpmareset_in,
    gt0_txpolarity_in,
    gt0_txprbsforceerr_in,
    gt_txuserrdy_i,
    DRPDI_IN,
    LOOPBACK,
    gt0_txprbssel_in,
    gt0_txdiffctrl_in,
    RXCHBONDO,
    gt0_txpostcursor_in,
    gt0_txprecursor_in,
    TXDATA,
    gt0_txmaincursor_in,
    gt0_txchardispmode_in,
    gt0_txchardispval_in,
    TXCHARISK,
    DRPADDR_IN,
    flag2_reg_0,
    ENABLE_ERR_DETECT,
    cpll_reset_i);
  output gt0_cplllock_out;
  output DRPRDY_OUT;
  output [0:0]TXN;
  output [0:0]TXP;
  output gt0_txresetdone_out;
  output [15:0]DRPDO_OUT;
  output [1:0]gt0_txbufstatus_out;
  output ENABLE_ERR_DETECT_Buffer_reg;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt_refclk1;
  input gt_tx_reset_i;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  input gt_rxdfeagchold_i;
  input gt_rxdfelfhold_i;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input POWER_DOWN;
  input gt0_txinhibit_in;
  input gt0_txpcsreset_in;
  input gt0_txpmareset_in;
  input gt0_txpolarity_in;
  input gt0_txprbsforceerr_in;
  input gt_txuserrdy_i;
  input [15:0]DRPDI_IN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_txprbssel_in;
  input [3:0]gt0_txdiffctrl_in;
  input [4:0]RXCHBONDO;
  input [4:0]gt0_txpostcursor_in;
  input [4:0]gt0_txprecursor_in;
  input [15:0]TXDATA;
  input [6:0]gt0_txmaincursor_in;
  input [1:0]gt0_txchardispmode_in;
  input [1:0]gt0_txchardispval_in;
  input [1:0]TXCHARISK;
  input [8:0]DRPADDR_IN;
  input flag2_reg_0;
  input ENABLE_ERR_DETECT;
  input cpll_reset_i;

  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDO_OUT;
  wire DRPEN_IN;
  wire DRPRDY_OUT;
  wire DRPWE_IN;
  wire ENABLE_ERR_DETECT;
  wire ENABLE_ERR_DETECT_Buffer_reg;
  wire GT0_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [1:0]TXCHARISK;
  wire [15:0]TXDATA;
  wire [0:0]TXN;
  wire [0:0]TXP;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire flag2;
  wire flag2_i_2_n_0;
  wire flag2_reg_0;
  wire flag_i_1_n_0;
  wire gt0_cplllock_out;
  wire [1:0]gt0_txbufstatus_out;
  wire [1:0]gt0_txchardispmode_in;
  wire [1:0]gt0_txchardispval_in;
  wire [3:0]gt0_txdiffctrl_in;
  wire gt0_txinhibit_in;
  wire [6:0]gt0_txmaincursor_in;
  wire gt0_txpcsreset_in;
  wire gt0_txpmareset_in;
  wire gt0_txpolarity_in;
  wire [4:0]gt0_txpostcursor_in;
  wire gt0_txprbsforceerr_in;
  wire [2:0]gt0_txprbssel_in;
  wire [4:0]gt0_txprecursor_in;
  wire gt0_txresetdone_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_rxdfeagchold_i;
  wire gt_rxdfelfhold_i;
  wire gt_rxuserrdy_i;
  wire gt_tx_reset_i;
  wire gt_txuserrdy_i;
  wire gthe2_i_n_0;
  wire gthe2_i_n_10;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_11;
  wire gthe2_i_n_114;
  wire gthe2_i_n_115;
  wire gthe2_i_n_116;
  wire gthe2_i_n_12;
  wire gthe2_i_n_120;
  wire gthe2_i_n_121;
  wire gthe2_i_n_122;
  wire gthe2_i_n_123;
  wire gthe2_i_n_124;
  wire gthe2_i_n_13;
  wire gthe2_i_n_14;
  wire gthe2_i_n_15;
  wire gthe2_i_n_17;
  wire gthe2_i_n_189;
  wire gthe2_i_n_190;
  wire gthe2_i_n_191;
  wire gthe2_i_n_192;
  wire gthe2_i_n_193;
  wire gthe2_i_n_194;
  wire gthe2_i_n_195;
  wire gthe2_i_n_196;
  wire gthe2_i_n_197;
  wire gthe2_i_n_198;
  wire gthe2_i_n_199;
  wire gthe2_i_n_200;
  wire gthe2_i_n_201;
  wire gthe2_i_n_202;
  wire gthe2_i_n_203;
  wire gthe2_i_n_204;
  wire gthe2_i_n_205;
  wire gthe2_i_n_206;
  wire gthe2_i_n_207;
  wire gthe2_i_n_208;
  wire gthe2_i_n_209;
  wire gthe2_i_n_210;
  wire gthe2_i_n_211;
  wire gthe2_i_n_218;
  wire gthe2_i_n_219;
  wire gthe2_i_n_226;
  wire gthe2_i_n_227;
  wire gthe2_i_n_234;
  wire gthe2_i_n_235;
  wire gthe2_i_n_242;
  wire gthe2_i_n_243;
  wire gthe2_i_n_29;
  wire gthe2_i_n_33;
  wire gthe2_i_n_34;
  wire gthe2_i_n_38;
  wire gthe2_i_n_4;
  wire gthe2_i_n_45;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_57;
  wire gthe2_i_n_58;
  wire gthe2_i_n_59;
  wire gthe2_i_n_60;
  wire gthe2_i_n_61;
  wire gthe2_i_n_62;
  wire gthe2_i_n_63;
  wire gthe2_i_n_64;
  wire gthe2_i_n_65;
  wire gthe2_i_n_66;
  wire gthe2_i_n_67;
  wire gthe2_i_n_68;
  wire gthe2_i_n_69;
  wire gthe2_i_n_70;
  wire gthe2_i_n_71;
  wire init_clk_in;
  wire sync_clk;
  wire user_clk;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_2
       (.I0(ack_flag),
        .O(flag2_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_2_n_0),
        .Q(flag2),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt0_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT0_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT({gthe2_i_n_57,gthe2_i_n_58,gthe2_i_n_59,gthe2_i_n_60,gthe2_i_n_61,gthe2_i_n_62,gthe2_i_n_63,gthe2_i_n_64,gthe2_i_n_65,gthe2_i_n_66,gthe2_i_n_67,gthe2_i_n_68,gthe2_i_n_69,gthe2_i_n_70,gthe2_i_n_71}),
        .DRPADDR(DRPADDR_IN),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN),
        .DRPDO(DRPDO_OUT),
        .DRPEN(DRPEN_IN),
        .DRPRDY(DRPRDY_OUT),
        .DRPWE(DRPWE_IN),
        .EYESCANDATAERROR(gthe2_i_n_4),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(1'b0),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTHRXN(1'b0),
        .GTHRXP(1'b0),
        .GTHTXN(TXN),
        .GTHTXP(TXP),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(1'b0),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(gt_tx_reset_i),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad5_in),
        .QPLLREFCLK(gt_qpllrefclk_quad5_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(1'b0),
        .RXBUFSTATUS({gthe2_i_n_114,gthe2_i_n_115,gthe2_i_n_116}),
        .RXBYTEISALIGNED(gthe2_i_n_10),
        .RXBYTEREALIGN(gthe2_i_n_11),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(gthe2_i_n_14),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_n_218,gthe2_i_n_219}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],gthe2_i_n_226,gthe2_i_n_227}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({gthe2_i_n_120,gthe2_i_n_121,gthe2_i_n_122,gthe2_i_n_123,gthe2_i_n_124}),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gthe2_i_n_17),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],gthe2_i_n_189,gthe2_i_n_190,gthe2_i_n_191,gthe2_i_n_192,gthe2_i_n_193,gthe2_i_n_194,gthe2_i_n_195,gthe2_i_n_196,gthe2_i_n_197,gthe2_i_n_198,gthe2_i_n_199,gthe2_i_n_200,gthe2_i_n_201,gthe2_i_n_202,gthe2_i_n_203,gthe2_i_n_204}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(gt_rxdfeagchold_i),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(gt_rxdfelfhold_i),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(1'b0),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gthe2_i_n_234,gthe2_i_n_235}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(1'b0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(1'b0),
        .RXMONITOROUT({gthe2_i_n_205,gthe2_i_n_206,gthe2_i_n_207,gthe2_i_n_208,gthe2_i_n_209,gthe2_i_n_210,gthe2_i_n_211}),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gthe2_i_n_242,gthe2_i_n_243}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(1'b0),
        .RXPCSRESET(1'b0),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(1'b0),
        .RXPMARESETDONE(gthe2_i_n_33),
        .RXPOLARITY(1'b0),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(gthe2_i_n_34),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gthe2_i_n_38),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(gt0_txbufstatus_out),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt0_txchardispmode_in}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt0_txchardispval_in}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,TXCHARISK}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,TXDATA}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL(gt0_txdiffctrl_in),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(POWER_DOWN),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(gt0_txinhibit_in),
        .TXMAINCURSOR(gt0_txmaincursor_in),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(gthe2_i_n_45),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(gt0_txpcsreset_in),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(gt0_txpmareset_in),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(gt0_txpolarity_in),
        .TXPOSTCURSOR(gt0_txpostcursor_in),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(gt0_txprbsforceerr_in),
        .TXPRBSSEL(gt0_txprbssel_in),
        .TXPRECURSOR(gt0_txprecursor_in),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gt0_txresetdone_out),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(gt_txuserrdy_i),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT2 #(
    .INIT(4'h8)) 
    hard_err_flop_r_i_1
       (.I0(gt0_txbufstatus_out[1]),
        .I1(ENABLE_ERR_DETECT),
        .O(ENABLE_ERR_DETECT_Buffer_reg));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_gt" *) 
module efex_aurora_hub2_efex_aurora_hub2_gt_20
   (gt1_cplllock_out,
    DRPRDY_OUT_LANE1,
    TXN,
    TXP,
    gt1_txresetdone_out,
    DRPDO_OUT_LANE1,
    gt1_txbufstatus_out,
    RXCHBONDO,
    ENABLE_ERR_DETECT_Buffer_reg,
    init_clk_in,
    drpclk_in,
    DRPEN_IN_LANE1,
    DRPWE_IN_LANE1,
    gt_refclk1,
    gt_tx_reset_i,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    gt_rxdfeagchold_i,
    gt_rxdfelfhold_i,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    POWER_DOWN,
    gt1_txinhibit_in,
    gt1_txpcsreset_in,
    gt1_txpmareset_in,
    gt1_txpolarity_in,
    gt1_txprbsforceerr_in,
    gt_txuserrdy_i,
    DRPDI_IN_LANE1,
    LOOPBACK,
    gt1_txprbssel_in,
    gt1_txdiffctrl_in,
    gt1_txpostcursor_in,
    gt1_txprecursor_in,
    gt1_cplllock_out_0,
    gt1_txmaincursor_in,
    gt1_txchardispmode_in,
    gt1_txchardispval_in,
    gt1_cplllock_out_1,
    DRPADDR_IN_LANE1,
    flag2_reg_0,
    ENABLE_ERR_DETECT_0,
    cpll_reset_i);
  output gt1_cplllock_out;
  output DRPRDY_OUT_LANE1;
  output [0:0]TXN;
  output [0:0]TXP;
  output gt1_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE1;
  output [1:0]gt1_txbufstatus_out;
  output [4:0]RXCHBONDO;
  output ENABLE_ERR_DETECT_Buffer_reg;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN_LANE1;
  input DRPWE_IN_LANE1;
  input gt_refclk1;
  input gt_tx_reset_i;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  input gt_rxdfeagchold_i;
  input gt_rxdfelfhold_i;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input POWER_DOWN;
  input gt1_txinhibit_in;
  input gt1_txpcsreset_in;
  input gt1_txpmareset_in;
  input gt1_txpolarity_in;
  input gt1_txprbsforceerr_in;
  input gt_txuserrdy_i;
  input [15:0]DRPDI_IN_LANE1;
  input [2:0]LOOPBACK;
  input [2:0]gt1_txprbssel_in;
  input [3:0]gt1_txdiffctrl_in;
  input [4:0]gt1_txpostcursor_in;
  input [4:0]gt1_txprecursor_in;
  input [15:0]gt1_cplllock_out_0;
  input [6:0]gt1_txmaincursor_in;
  input [1:0]gt1_txchardispmode_in;
  input [1:0]gt1_txchardispval_in;
  input [1:0]gt1_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE1;
  input flag2_reg_0;
  input ENABLE_ERR_DETECT_0;
  input cpll_reset_i;

  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDO_OUT_LANE1;
  wire DRPEN_IN_LANE1;
  wire DRPRDY_OUT_LANE1;
  wire DRPWE_IN_LANE1;
  wire ENABLE_ERR_DETECT_0;
  wire ENABLE_ERR_DETECT_Buffer_reg;
  wire GT1_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]TXN;
  wire [0:0]TXP;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire flag2_i_1_n_0;
  wire flag2_reg_0;
  wire flag2_reg_n_0;
  wire flag_i_1__0_n_0;
  wire gt1_cplllock_out;
  wire [15:0]gt1_cplllock_out_0;
  wire [1:0]gt1_cplllock_out_1;
  wire [1:0]gt1_txbufstatus_out;
  wire [1:0]gt1_txchardispmode_in;
  wire [1:0]gt1_txchardispval_in;
  wire [3:0]gt1_txdiffctrl_in;
  wire gt1_txinhibit_in;
  wire [6:0]gt1_txmaincursor_in;
  wire gt1_txpcsreset_in;
  wire gt1_txpmareset_in;
  wire gt1_txpolarity_in;
  wire [4:0]gt1_txpostcursor_in;
  wire gt1_txprbsforceerr_in;
  wire [2:0]gt1_txprbssel_in;
  wire [4:0]gt1_txprecursor_in;
  wire gt1_txresetdone_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_rxdfeagchold_i;
  wire gt_rxdfelfhold_i;
  wire gt_rxuserrdy_i;
  wire gt_tx_reset_i;
  wire gt_txuserrdy_i;
  wire gthe2_i_n_0;
  wire gthe2_i_n_10;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_11;
  wire gthe2_i_n_114;
  wire gthe2_i_n_115;
  wire gthe2_i_n_116;
  wire gthe2_i_n_12;
  wire gthe2_i_n_13;
  wire gthe2_i_n_14;
  wire gthe2_i_n_15;
  wire gthe2_i_n_17;
  wire gthe2_i_n_189;
  wire gthe2_i_n_190;
  wire gthe2_i_n_191;
  wire gthe2_i_n_192;
  wire gthe2_i_n_193;
  wire gthe2_i_n_194;
  wire gthe2_i_n_195;
  wire gthe2_i_n_196;
  wire gthe2_i_n_197;
  wire gthe2_i_n_198;
  wire gthe2_i_n_199;
  wire gthe2_i_n_200;
  wire gthe2_i_n_201;
  wire gthe2_i_n_202;
  wire gthe2_i_n_203;
  wire gthe2_i_n_204;
  wire gthe2_i_n_205;
  wire gthe2_i_n_206;
  wire gthe2_i_n_207;
  wire gthe2_i_n_208;
  wire gthe2_i_n_209;
  wire gthe2_i_n_210;
  wire gthe2_i_n_211;
  wire gthe2_i_n_218;
  wire gthe2_i_n_219;
  wire gthe2_i_n_226;
  wire gthe2_i_n_227;
  wire gthe2_i_n_234;
  wire gthe2_i_n_235;
  wire gthe2_i_n_242;
  wire gthe2_i_n_243;
  wire gthe2_i_n_29;
  wire gthe2_i_n_33;
  wire gthe2_i_n_34;
  wire gthe2_i_n_38;
  wire gthe2_i_n_4;
  wire gthe2_i_n_45;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_57;
  wire gthe2_i_n_58;
  wire gthe2_i_n_59;
  wire gthe2_i_n_60;
  wire gthe2_i_n_61;
  wire gthe2_i_n_62;
  wire gthe2_i_n_63;
  wire gthe2_i_n_64;
  wire gthe2_i_n_65;
  wire gthe2_i_n_66;
  wire gthe2_i_n_67;
  wire gthe2_i_n_68;
  wire gthe2_i_n_69;
  wire gthe2_i_n_70;
  wire gthe2_i_n_71;
  wire init_clk_in;
  wire sync_clk;
  wire user_clk;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2_reg_n_0),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1
       (.I0(ack_flag),
        .O(flag2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_1_n_0),
        .Q(flag2_reg_n_0),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1__0
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1__0_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt1_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT1_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT({gthe2_i_n_57,gthe2_i_n_58,gthe2_i_n_59,gthe2_i_n_60,gthe2_i_n_61,gthe2_i_n_62,gthe2_i_n_63,gthe2_i_n_64,gthe2_i_n_65,gthe2_i_n_66,gthe2_i_n_67,gthe2_i_n_68,gthe2_i_n_69,gthe2_i_n_70,gthe2_i_n_71}),
        .DRPADDR(DRPADDR_IN_LANE1),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN_LANE1),
        .DRPDO(DRPDO_OUT_LANE1),
        .DRPEN(DRPEN_IN_LANE1),
        .DRPRDY(DRPRDY_OUT_LANE1),
        .DRPWE(DRPWE_IN_LANE1),
        .EYESCANDATAERROR(gthe2_i_n_4),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(1'b0),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTHRXN(1'b0),
        .GTHRXP(1'b0),
        .GTHTXN(TXN),
        .GTHTXP(TXP),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(1'b0),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(gt_tx_reset_i),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad5_in),
        .QPLLREFCLK(gt_qpllrefclk_quad5_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(1'b0),
        .RXBUFSTATUS({gthe2_i_n_114,gthe2_i_n_115,gthe2_i_n_116}),
        .RXBYTEISALIGNED(gthe2_i_n_10),
        .RXBYTEREALIGN(gthe2_i_n_11),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(gthe2_i_n_14),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_n_218,gthe2_i_n_219}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],gthe2_i_n_226,gthe2_i_n_227}),
        .RXCHBONDEN(1'b0),
        .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXCHBONDLEVEL({1'b0,1'b1,1'b0}),
        .RXCHBONDMASTER(1'b1),
        .RXCHBONDO(RXCHBONDO),
        .RXCHBONDSLAVE(1'b0),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gthe2_i_n_17),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],gthe2_i_n_189,gthe2_i_n_190,gthe2_i_n_191,gthe2_i_n_192,gthe2_i_n_193,gthe2_i_n_194,gthe2_i_n_195,gthe2_i_n_196,gthe2_i_n_197,gthe2_i_n_198,gthe2_i_n_199,gthe2_i_n_200,gthe2_i_n_201,gthe2_i_n_202,gthe2_i_n_203,gthe2_i_n_204}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(gt_rxdfeagchold_i),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(gt_rxdfelfhold_i),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(1'b0),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gthe2_i_n_234,gthe2_i_n_235}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(1'b0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(1'b0),
        .RXMONITOROUT({gthe2_i_n_205,gthe2_i_n_206,gthe2_i_n_207,gthe2_i_n_208,gthe2_i_n_209,gthe2_i_n_210,gthe2_i_n_211}),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gthe2_i_n_242,gthe2_i_n_243}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(1'b0),
        .RXPCSRESET(1'b0),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(1'b0),
        .RXPMARESETDONE(gthe2_i_n_33),
        .RXPOLARITY(1'b0),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(gthe2_i_n_34),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gthe2_i_n_38),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(gt1_txbufstatus_out),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt1_txchardispmode_in}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt1_txchardispval_in}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt1_cplllock_out_1}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt1_cplllock_out_0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL(gt1_txdiffctrl_in),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(POWER_DOWN),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(gt1_txinhibit_in),
        .TXMAINCURSOR(gt1_txmaincursor_in),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(gthe2_i_n_45),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(gt1_txpcsreset_in),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(gt1_txpmareset_in),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(gt1_txpolarity_in),
        .TXPOSTCURSOR(gt1_txpostcursor_in),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(gt1_txprbsforceerr_in),
        .TXPRBSSEL(gt1_txprbssel_in),
        .TXPRECURSOR(gt1_txprecursor_in),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gt1_txresetdone_out),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(gt_txuserrdy_i),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT2 #(
    .INIT(4'h8)) 
    hard_err_flop_r_i_1__0
       (.I0(gt1_txbufstatus_out[1]),
        .I1(ENABLE_ERR_DETECT_0),
        .O(ENABLE_ERR_DETECT_Buffer_reg));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_gt" *) 
module efex_aurora_hub2_efex_aurora_hub2_gt_21
   (gt2_cplllock_out,
    DRPRDY_OUT_LANE2,
    TXN,
    TXP,
    TX_OUT_CLK,
    gt2_txresetdone_out,
    DRPDO_OUT_LANE2,
    gt2_txbufstatus_out,
    RXCHBONDO,
    ENABLE_ERR_DETECT_Buffer_reg,
    TX_LOCK,
    init_clk_in,
    drpclk_in,
    DRPEN_IN_LANE2,
    DRPWE_IN_LANE2,
    gt_refclk1,
    gt_tx_reset_i,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    gt_rxdfeagchold_i,
    gt_rxdfelfhold_i,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    POWER_DOWN,
    gt2_txinhibit_in,
    gt2_txpcsreset_in,
    gt2_txpmareset_in,
    gt2_txpolarity_in,
    gt2_txprbsforceerr_in,
    gt_txuserrdy_i,
    DRPDI_IN_LANE2,
    LOOPBACK,
    gt2_txprbssel_in,
    gt2_txdiffctrl_in,
    gt2_cplllock_out_0,
    gt2_txpostcursor_in,
    gt2_txprecursor_in,
    gt2_cplllock_out_1,
    gt2_txmaincursor_in,
    gt2_txchardispmode_in,
    gt2_txchardispval_in,
    gt2_cplllock_out_2,
    DRPADDR_IN_LANE2,
    flag2_reg_0,
    ENABLE_ERR_DETECT_1,
    cpll_reset_i,
    gt3_cplllock_out,
    gt0_cplllock_out,
    gt1_cplllock_out);
  output gt2_cplllock_out;
  output DRPRDY_OUT_LANE2;
  output [0:0]TXN;
  output [0:0]TXP;
  output TX_OUT_CLK;
  output gt2_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE2;
  output [1:0]gt2_txbufstatus_out;
  output [4:0]RXCHBONDO;
  output ENABLE_ERR_DETECT_Buffer_reg;
  output TX_LOCK;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN_LANE2;
  input DRPWE_IN_LANE2;
  input gt_refclk1;
  input gt_tx_reset_i;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  input gt_rxdfeagchold_i;
  input gt_rxdfelfhold_i;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input POWER_DOWN;
  input gt2_txinhibit_in;
  input gt2_txpcsreset_in;
  input gt2_txpmareset_in;
  input gt2_txpolarity_in;
  input gt2_txprbsforceerr_in;
  input gt_txuserrdy_i;
  input [15:0]DRPDI_IN_LANE2;
  input [2:0]LOOPBACK;
  input [2:0]gt2_txprbssel_in;
  input [3:0]gt2_txdiffctrl_in;
  input [4:0]gt2_cplllock_out_0;
  input [4:0]gt2_txpostcursor_in;
  input [4:0]gt2_txprecursor_in;
  input [15:0]gt2_cplllock_out_1;
  input [6:0]gt2_txmaincursor_in;
  input [1:0]gt2_txchardispmode_in;
  input [1:0]gt2_txchardispval_in;
  input [1:0]gt2_cplllock_out_2;
  input [8:0]DRPADDR_IN_LANE2;
  input flag2_reg_0;
  input ENABLE_ERR_DETECT_1;
  input cpll_reset_i;
  input gt3_cplllock_out;
  input gt0_cplllock_out;
  input gt1_cplllock_out;

  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDO_OUT_LANE2;
  wire DRPEN_IN_LANE2;
  wire DRPRDY_OUT_LANE2;
  wire DRPWE_IN_LANE2;
  wire ENABLE_ERR_DETECT_1;
  wire ENABLE_ERR_DETECT_Buffer_reg;
  wire GT2_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]TXN;
  wire [0:0]TXP;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire flag2_i_1__0_n_0;
  wire flag2_reg_0;
  wire flag2_reg_n_0;
  wire flag_i_1__1_n_0;
  wire gt0_cplllock_out;
  wire gt1_cplllock_out;
  wire gt2_cplllock_out;
  wire [4:0]gt2_cplllock_out_0;
  wire [15:0]gt2_cplllock_out_1;
  wire [1:0]gt2_cplllock_out_2;
  wire [1:0]gt2_txbufstatus_out;
  wire [1:0]gt2_txchardispmode_in;
  wire [1:0]gt2_txchardispval_in;
  wire [3:0]gt2_txdiffctrl_in;
  wire gt2_txinhibit_in;
  wire [6:0]gt2_txmaincursor_in;
  wire gt2_txpcsreset_in;
  wire gt2_txpmareset_in;
  wire gt2_txpolarity_in;
  wire [4:0]gt2_txpostcursor_in;
  wire gt2_txprbsforceerr_in;
  wire [2:0]gt2_txprbssel_in;
  wire [4:0]gt2_txprecursor_in;
  wire gt2_txresetdone_out;
  wire gt3_cplllock_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_rxdfeagchold_i;
  wire gt_rxdfelfhold_i;
  wire gt_rxuserrdy_i;
  wire gt_tx_reset_i;
  wire gt_txuserrdy_i;
  wire gthe2_i_n_0;
  wire gthe2_i_n_10;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_11;
  wire gthe2_i_n_114;
  wire gthe2_i_n_115;
  wire gthe2_i_n_116;
  wire gthe2_i_n_12;
  wire gthe2_i_n_13;
  wire gthe2_i_n_14;
  wire gthe2_i_n_15;
  wire gthe2_i_n_17;
  wire gthe2_i_n_189;
  wire gthe2_i_n_190;
  wire gthe2_i_n_191;
  wire gthe2_i_n_192;
  wire gthe2_i_n_193;
  wire gthe2_i_n_194;
  wire gthe2_i_n_195;
  wire gthe2_i_n_196;
  wire gthe2_i_n_197;
  wire gthe2_i_n_198;
  wire gthe2_i_n_199;
  wire gthe2_i_n_200;
  wire gthe2_i_n_201;
  wire gthe2_i_n_202;
  wire gthe2_i_n_203;
  wire gthe2_i_n_204;
  wire gthe2_i_n_205;
  wire gthe2_i_n_206;
  wire gthe2_i_n_207;
  wire gthe2_i_n_208;
  wire gthe2_i_n_209;
  wire gthe2_i_n_210;
  wire gthe2_i_n_211;
  wire gthe2_i_n_218;
  wire gthe2_i_n_219;
  wire gthe2_i_n_226;
  wire gthe2_i_n_227;
  wire gthe2_i_n_234;
  wire gthe2_i_n_235;
  wire gthe2_i_n_242;
  wire gthe2_i_n_243;
  wire gthe2_i_n_29;
  wire gthe2_i_n_33;
  wire gthe2_i_n_34;
  wire gthe2_i_n_38;
  wire gthe2_i_n_4;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_57;
  wire gthe2_i_n_58;
  wire gthe2_i_n_59;
  wire gthe2_i_n_60;
  wire gthe2_i_n_61;
  wire gthe2_i_n_62;
  wire gthe2_i_n_63;
  wire gthe2_i_n_64;
  wire gthe2_i_n_65;
  wire gthe2_i_n_66;
  wire gthe2_i_n_67;
  wire gthe2_i_n_68;
  wire gthe2_i_n_69;
  wire gthe2_i_n_70;
  wire gthe2_i_n_71;
  wire init_clk_in;
  wire sync_clk;
  wire user_clk;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'h8000)) 
    TX_LOCK_INST_0
       (.I0(gt2_cplllock_out),
        .I1(gt3_cplllock_out),
        .I2(gt0_cplllock_out),
        .I3(gt1_cplllock_out),
        .O(TX_LOCK));
  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2_reg_n_0),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1__0
       (.I0(ack_flag),
        .O(flag2_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_1__0_n_0),
        .Q(flag2_reg_n_0),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1__1
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1__1_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt2_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT2_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT({gthe2_i_n_57,gthe2_i_n_58,gthe2_i_n_59,gthe2_i_n_60,gthe2_i_n_61,gthe2_i_n_62,gthe2_i_n_63,gthe2_i_n_64,gthe2_i_n_65,gthe2_i_n_66,gthe2_i_n_67,gthe2_i_n_68,gthe2_i_n_69,gthe2_i_n_70,gthe2_i_n_71}),
        .DRPADDR(DRPADDR_IN_LANE2),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN_LANE2),
        .DRPDO(DRPDO_OUT_LANE2),
        .DRPEN(DRPEN_IN_LANE2),
        .DRPRDY(DRPRDY_OUT_LANE2),
        .DRPWE(DRPWE_IN_LANE2),
        .EYESCANDATAERROR(gthe2_i_n_4),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(1'b0),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTHRXN(1'b0),
        .GTHRXP(1'b0),
        .GTHTXN(TXN),
        .GTHTXP(TXP),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(1'b0),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(gt_tx_reset_i),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad5_in),
        .QPLLREFCLK(gt_qpllrefclk_quad5_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(1'b0),
        .RXBUFSTATUS({gthe2_i_n_114,gthe2_i_n_115,gthe2_i_n_116}),
        .RXBYTEISALIGNED(gthe2_i_n_10),
        .RXBYTEREALIGN(gthe2_i_n_11),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(gthe2_i_n_14),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_n_218,gthe2_i_n_219}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],gthe2_i_n_226,gthe2_i_n_227}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(gt2_cplllock_out_0),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO(RXCHBONDO),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gthe2_i_n_17),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],gthe2_i_n_189,gthe2_i_n_190,gthe2_i_n_191,gthe2_i_n_192,gthe2_i_n_193,gthe2_i_n_194,gthe2_i_n_195,gthe2_i_n_196,gthe2_i_n_197,gthe2_i_n_198,gthe2_i_n_199,gthe2_i_n_200,gthe2_i_n_201,gthe2_i_n_202,gthe2_i_n_203,gthe2_i_n_204}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(gt_rxdfeagchold_i),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(gt_rxdfelfhold_i),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(1'b0),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gthe2_i_n_234,gthe2_i_n_235}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(1'b0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(1'b0),
        .RXMONITOROUT({gthe2_i_n_205,gthe2_i_n_206,gthe2_i_n_207,gthe2_i_n_208,gthe2_i_n_209,gthe2_i_n_210,gthe2_i_n_211}),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gthe2_i_n_242,gthe2_i_n_243}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(1'b0),
        .RXPCSRESET(1'b0),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(1'b0),
        .RXPMARESETDONE(gthe2_i_n_33),
        .RXPOLARITY(1'b0),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(gthe2_i_n_34),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gthe2_i_n_38),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(gt2_txbufstatus_out),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt2_txchardispmode_in}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt2_txchardispval_in}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt2_cplllock_out_2}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt2_cplllock_out_1}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL(gt2_txdiffctrl_in),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(POWER_DOWN),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(gt2_txinhibit_in),
        .TXMAINCURSOR(gt2_txmaincursor_in),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(TX_OUT_CLK),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(gt2_txpcsreset_in),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(gt2_txpmareset_in),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(gt2_txpolarity_in),
        .TXPOSTCURSOR(gt2_txpostcursor_in),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(gt2_txprbsforceerr_in),
        .TXPRBSSEL(gt2_txprbssel_in),
        .TXPRECURSOR(gt2_txprecursor_in),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gt2_txresetdone_out),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(gt_txuserrdy_i),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT2 #(
    .INIT(4'h8)) 
    hard_err_flop_r_i_1__1
       (.I0(gt2_txbufstatus_out[1]),
        .I1(ENABLE_ERR_DETECT_1),
        .O(ENABLE_ERR_DETECT_Buffer_reg));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_gt" *) 
module efex_aurora_hub2_efex_aurora_hub2_gt_22
   (gt3_cplllock_out,
    DRPRDY_OUT_LANE3,
    TXN,
    TXP,
    gt3_txresetdone_out,
    DRPDO_OUT_LANE3,
    gt3_txbufstatus_out,
    ENABLE_ERR_DETECT_Buffer_reg,
    init_clk_in,
    drpclk_in,
    DRPEN_IN_LANE3,
    DRPWE_IN_LANE3,
    gt_refclk1,
    gt_tx_reset_i,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    gt_rxdfeagchold_i,
    gt_rxdfelfhold_i,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    POWER_DOWN,
    gt3_txinhibit_in,
    gt3_txpcsreset_in,
    gt3_txpmareset_in,
    gt3_txpolarity_in,
    gt3_txprbsforceerr_in,
    gt_txuserrdy_i,
    DRPDI_IN_LANE3,
    LOOPBACK,
    gt3_txprbssel_in,
    gt3_txdiffctrl_in,
    RXCHBONDO,
    gt3_txpostcursor_in,
    gt3_txprecursor_in,
    gt3_cplllock_out_0,
    gt3_txmaincursor_in,
    gt3_txchardispmode_in,
    gt3_txchardispval_in,
    gt3_cplllock_out_1,
    DRPADDR_IN_LANE3,
    flag2_reg_0,
    ENABLE_ERR_DETECT_2,
    cpll_reset_i);
  output gt3_cplllock_out;
  output DRPRDY_OUT_LANE3;
  output [0:0]TXN;
  output [0:0]TXP;
  output gt3_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE3;
  output [1:0]gt3_txbufstatus_out;
  output ENABLE_ERR_DETECT_Buffer_reg;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN_LANE3;
  input DRPWE_IN_LANE3;
  input gt_refclk1;
  input gt_tx_reset_i;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  input gt_rxdfeagchold_i;
  input gt_rxdfelfhold_i;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input POWER_DOWN;
  input gt3_txinhibit_in;
  input gt3_txpcsreset_in;
  input gt3_txpmareset_in;
  input gt3_txpolarity_in;
  input gt3_txprbsforceerr_in;
  input gt_txuserrdy_i;
  input [15:0]DRPDI_IN_LANE3;
  input [2:0]LOOPBACK;
  input [2:0]gt3_txprbssel_in;
  input [3:0]gt3_txdiffctrl_in;
  input [4:0]RXCHBONDO;
  input [4:0]gt3_txpostcursor_in;
  input [4:0]gt3_txprecursor_in;
  input [15:0]gt3_cplllock_out_0;
  input [6:0]gt3_txmaincursor_in;
  input [1:0]gt3_txchardispmode_in;
  input [1:0]gt3_txchardispval_in;
  input [1:0]gt3_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE3;
  input flag2_reg_0;
  input ENABLE_ERR_DETECT_2;
  input cpll_reset_i;

  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN_LANE3;
  wire ENABLE_ERR_DETECT_2;
  wire ENABLE_ERR_DETECT_Buffer_reg;
  wire GT3_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]TXN;
  wire [0:0]TXP;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire flag2_i_1__1_n_0;
  wire flag2_reg_0;
  wire flag2_reg_n_0;
  wire flag_i_1__2_n_0;
  wire gt3_cplllock_out;
  wire [15:0]gt3_cplllock_out_0;
  wire [1:0]gt3_cplllock_out_1;
  wire [1:0]gt3_txbufstatus_out;
  wire [1:0]gt3_txchardispmode_in;
  wire [1:0]gt3_txchardispval_in;
  wire [3:0]gt3_txdiffctrl_in;
  wire gt3_txinhibit_in;
  wire [6:0]gt3_txmaincursor_in;
  wire gt3_txpcsreset_in;
  wire gt3_txpmareset_in;
  wire gt3_txpolarity_in;
  wire [4:0]gt3_txpostcursor_in;
  wire gt3_txprbsforceerr_in;
  wire [2:0]gt3_txprbssel_in;
  wire [4:0]gt3_txprecursor_in;
  wire gt3_txresetdone_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_rxdfeagchold_i;
  wire gt_rxdfelfhold_i;
  wire gt_rxuserrdy_i;
  wire gt_tx_reset_i;
  wire gt_txuserrdy_i;
  wire gthe2_i_n_0;
  wire gthe2_i_n_10;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_11;
  wire gthe2_i_n_114;
  wire gthe2_i_n_115;
  wire gthe2_i_n_116;
  wire gthe2_i_n_12;
  wire gthe2_i_n_120;
  wire gthe2_i_n_121;
  wire gthe2_i_n_122;
  wire gthe2_i_n_123;
  wire gthe2_i_n_124;
  wire gthe2_i_n_13;
  wire gthe2_i_n_14;
  wire gthe2_i_n_15;
  wire gthe2_i_n_17;
  wire gthe2_i_n_189;
  wire gthe2_i_n_190;
  wire gthe2_i_n_191;
  wire gthe2_i_n_192;
  wire gthe2_i_n_193;
  wire gthe2_i_n_194;
  wire gthe2_i_n_195;
  wire gthe2_i_n_196;
  wire gthe2_i_n_197;
  wire gthe2_i_n_198;
  wire gthe2_i_n_199;
  wire gthe2_i_n_200;
  wire gthe2_i_n_201;
  wire gthe2_i_n_202;
  wire gthe2_i_n_203;
  wire gthe2_i_n_204;
  wire gthe2_i_n_205;
  wire gthe2_i_n_206;
  wire gthe2_i_n_207;
  wire gthe2_i_n_208;
  wire gthe2_i_n_209;
  wire gthe2_i_n_210;
  wire gthe2_i_n_211;
  wire gthe2_i_n_218;
  wire gthe2_i_n_219;
  wire gthe2_i_n_226;
  wire gthe2_i_n_227;
  wire gthe2_i_n_234;
  wire gthe2_i_n_235;
  wire gthe2_i_n_242;
  wire gthe2_i_n_243;
  wire gthe2_i_n_29;
  wire gthe2_i_n_33;
  wire gthe2_i_n_34;
  wire gthe2_i_n_38;
  wire gthe2_i_n_4;
  wire gthe2_i_n_45;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_57;
  wire gthe2_i_n_58;
  wire gthe2_i_n_59;
  wire gthe2_i_n_60;
  wire gthe2_i_n_61;
  wire gthe2_i_n_62;
  wire gthe2_i_n_63;
  wire gthe2_i_n_64;
  wire gthe2_i_n_65;
  wire gthe2_i_n_66;
  wire gthe2_i_n_67;
  wire gthe2_i_n_68;
  wire gthe2_i_n_69;
  wire gthe2_i_n_70;
  wire gthe2_i_n_71;
  wire init_clk_in;
  wire sync_clk;
  wire user_clk;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2_reg_n_0),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1__1
       (.I0(ack_flag),
        .O(flag2_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_1__1_n_0),
        .Q(flag2_reg_n_0),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1__2
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1__2_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt3_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT3_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT({gthe2_i_n_57,gthe2_i_n_58,gthe2_i_n_59,gthe2_i_n_60,gthe2_i_n_61,gthe2_i_n_62,gthe2_i_n_63,gthe2_i_n_64,gthe2_i_n_65,gthe2_i_n_66,gthe2_i_n_67,gthe2_i_n_68,gthe2_i_n_69,gthe2_i_n_70,gthe2_i_n_71}),
        .DRPADDR(DRPADDR_IN_LANE3),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN_LANE3),
        .DRPDO(DRPDO_OUT_LANE3),
        .DRPEN(DRPEN_IN_LANE3),
        .DRPRDY(DRPRDY_OUT_LANE3),
        .DRPWE(DRPWE_IN_LANE3),
        .EYESCANDATAERROR(gthe2_i_n_4),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(1'b0),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTHRXN(1'b0),
        .GTHRXP(1'b0),
        .GTHTXN(TXN),
        .GTHTXP(TXP),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(1'b0),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(gt_tx_reset_i),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad5_in),
        .QPLLREFCLK(gt_qpllrefclk_quad5_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(1'b0),
        .RXBUFSTATUS({gthe2_i_n_114,gthe2_i_n_115,gthe2_i_n_116}),
        .RXBYTEISALIGNED(gthe2_i_n_10),
        .RXBYTEREALIGN(gthe2_i_n_11),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(gthe2_i_n_14),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_n_218,gthe2_i_n_219}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],gthe2_i_n_226,gthe2_i_n_227}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({gthe2_i_n_120,gthe2_i_n_121,gthe2_i_n_122,gthe2_i_n_123,gthe2_i_n_124}),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gthe2_i_n_17),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],gthe2_i_n_189,gthe2_i_n_190,gthe2_i_n_191,gthe2_i_n_192,gthe2_i_n_193,gthe2_i_n_194,gthe2_i_n_195,gthe2_i_n_196,gthe2_i_n_197,gthe2_i_n_198,gthe2_i_n_199,gthe2_i_n_200,gthe2_i_n_201,gthe2_i_n_202,gthe2_i_n_203,gthe2_i_n_204}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(gt_rxdfeagchold_i),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(gt_rxdfelfhold_i),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(1'b0),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gthe2_i_n_234,gthe2_i_n_235}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(1'b0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(1'b0),
        .RXMONITOROUT({gthe2_i_n_205,gthe2_i_n_206,gthe2_i_n_207,gthe2_i_n_208,gthe2_i_n_209,gthe2_i_n_210,gthe2_i_n_211}),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gthe2_i_n_242,gthe2_i_n_243}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(1'b0),
        .RXPCSRESET(1'b0),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(1'b0),
        .RXPMARESETDONE(gthe2_i_n_33),
        .RXPOLARITY(1'b0),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(gthe2_i_n_34),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gthe2_i_n_38),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(gt3_txbufstatus_out),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt3_txchardispmode_in}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt3_txchardispval_in}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt3_cplllock_out_1}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt3_cplllock_out_0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL(gt3_txdiffctrl_in),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(POWER_DOWN),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(gt3_txinhibit_in),
        .TXMAINCURSOR(gt3_txmaincursor_in),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(gthe2_i_n_45),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(gt3_txpcsreset_in),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(gt3_txpmareset_in),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(gt3_txpolarity_in),
        .TXPOSTCURSOR(gt3_txpostcursor_in),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(gt3_txprbsforceerr_in),
        .TXPRBSSEL(gt3_txprbssel_in),
        .TXPRECURSOR(gt3_txprecursor_in),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gt3_txresetdone_out),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(gt_txuserrdy_i),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT2 #(
    .INIT(4'h8)) 
    hard_err_flop_r_i_1__2
       (.I0(gt3_txbufstatus_out[1]),
        .I1(ENABLE_ERR_DETECT_2),
        .O(ENABLE_ERR_DETECT_Buffer_reg));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_multi_gt" *) 
module efex_aurora_hub2_efex_aurora_hub2_multi_gt
   (gt0_cplllock_out,
    DRPRDY_OUT,
    TXN,
    TXP,
    gt0_txresetdone_out,
    DRPDO_OUT,
    gt0_txbufstatus_out,
    gt1_cplllock_out,
    DRPRDY_OUT_LANE1,
    gt1_txresetdone_out,
    DRPDO_OUT_LANE1,
    gt1_txbufstatus_out,
    gt2_cplllock_out,
    DRPRDY_OUT_LANE2,
    TX_OUT_CLK,
    gt2_txresetdone_out,
    DRPDO_OUT_LANE2,
    gt2_txbufstatus_out,
    gt3_cplllock_out,
    DRPRDY_OUT_LANE3,
    gt3_txresetdone_out,
    DRPDO_OUT_LANE3,
    gt3_txbufstatus_out,
    ENABLE_ERR_DETECT_Buffer_reg,
    ENABLE_ERR_DETECT_Buffer_reg_0,
    ENABLE_ERR_DETECT_Buffer_reg_1,
    ENABLE_ERR_DETECT_Buffer_reg_2,
    TX_LOCK,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt_refclk1,
    gt_tx_reset_i,
    gt_qpllclk_quad5_in,
    gt_qpllrefclk_quad5_in,
    sync_clk,
    user_clk,
    POWER_DOWN,
    gt0_txinhibit_in,
    gt0_txpcsreset_in,
    gt0_txpmareset_in,
    gt0_txpolarity_in,
    gt0_txprbsforceerr_in,
    gt_txuserrdy_i,
    DRPDI_IN,
    LOOPBACK,
    gt0_txprbssel_in,
    gt0_txdiffctrl_in,
    gt0_txpostcursor_in,
    gt0_txprecursor_in,
    TXDATA,
    gt0_txmaincursor_in,
    gt0_txchardispmode_in,
    gt0_txchardispval_in,
    TXCHARISK,
    DRPADDR_IN,
    DRPEN_IN_LANE1,
    DRPWE_IN_LANE1,
    gt1_txinhibit_in,
    gt1_txpcsreset_in,
    gt1_txpmareset_in,
    gt1_txpolarity_in,
    gt1_txprbsforceerr_in,
    DRPDI_IN_LANE1,
    gt1_txprbssel_in,
    gt1_txdiffctrl_in,
    gt1_txpostcursor_in,
    gt1_txprecursor_in,
    gt1_cplllock_out_0,
    gt1_txmaincursor_in,
    gt1_txchardispmode_in,
    gt1_txchardispval_in,
    gt1_cplllock_out_1,
    DRPADDR_IN_LANE1,
    DRPEN_IN_LANE2,
    DRPWE_IN_LANE2,
    gt2_txinhibit_in,
    gt2_txpcsreset_in,
    gt2_txpmareset_in,
    gt2_txpolarity_in,
    gt2_txprbsforceerr_in,
    DRPDI_IN_LANE2,
    gt2_txprbssel_in,
    gt2_txdiffctrl_in,
    gt2_txpostcursor_in,
    gt2_txprecursor_in,
    gt2_cplllock_out_0,
    gt2_txmaincursor_in,
    gt2_txchardispmode_in,
    gt2_txchardispval_in,
    gt2_cplllock_out_1,
    DRPADDR_IN_LANE2,
    DRPEN_IN_LANE3,
    DRPWE_IN_LANE3,
    gt3_txinhibit_in,
    gt3_txpcsreset_in,
    gt3_txpmareset_in,
    gt3_txpolarity_in,
    gt3_txprbsforceerr_in,
    DRPDI_IN_LANE3,
    gt3_txprbssel_in,
    gt3_txdiffctrl_in,
    gt3_txpostcursor_in,
    gt3_txprecursor_in,
    gt3_cplllock_out_0,
    gt3_txmaincursor_in,
    gt3_txchardispmode_in,
    gt3_txchardispval_in,
    gt3_cplllock_out_1,
    DRPADDR_IN_LANE3,
    flag2_reg,
    ENABLE_ERR_DETECT,
    ENABLE_ERR_DETECT_0,
    ENABLE_ERR_DETECT_1,
    ENABLE_ERR_DETECT_2,
    cpll_reset_i);
  output gt0_cplllock_out;
  output DRPRDY_OUT;
  output [0:3]TXN;
  output [0:3]TXP;
  output gt0_txresetdone_out;
  output [15:0]DRPDO_OUT;
  output [1:0]gt0_txbufstatus_out;
  output gt1_cplllock_out;
  output DRPRDY_OUT_LANE1;
  output gt1_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE1;
  output [1:0]gt1_txbufstatus_out;
  output gt2_cplllock_out;
  output DRPRDY_OUT_LANE2;
  output TX_OUT_CLK;
  output gt2_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE2;
  output [1:0]gt2_txbufstatus_out;
  output gt3_cplllock_out;
  output DRPRDY_OUT_LANE3;
  output gt3_txresetdone_out;
  output [15:0]DRPDO_OUT_LANE3;
  output [1:0]gt3_txbufstatus_out;
  output ENABLE_ERR_DETECT_Buffer_reg;
  output ENABLE_ERR_DETECT_Buffer_reg_0;
  output ENABLE_ERR_DETECT_Buffer_reg_1;
  output ENABLE_ERR_DETECT_Buffer_reg_2;
  output TX_LOCK;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt_refclk1;
  input gt_tx_reset_i;
  input gt_qpllclk_quad5_in;
  input gt_qpllrefclk_quad5_in;
  input sync_clk;
  input user_clk;
  input POWER_DOWN;
  input gt0_txinhibit_in;
  input gt0_txpcsreset_in;
  input gt0_txpmareset_in;
  input gt0_txpolarity_in;
  input gt0_txprbsforceerr_in;
  input gt_txuserrdy_i;
  input [15:0]DRPDI_IN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_txprbssel_in;
  input [3:0]gt0_txdiffctrl_in;
  input [4:0]gt0_txpostcursor_in;
  input [4:0]gt0_txprecursor_in;
  input [15:0]TXDATA;
  input [6:0]gt0_txmaincursor_in;
  input [1:0]gt0_txchardispmode_in;
  input [1:0]gt0_txchardispval_in;
  input [1:0]TXCHARISK;
  input [8:0]DRPADDR_IN;
  input DRPEN_IN_LANE1;
  input DRPWE_IN_LANE1;
  input gt1_txinhibit_in;
  input gt1_txpcsreset_in;
  input gt1_txpmareset_in;
  input gt1_txpolarity_in;
  input gt1_txprbsforceerr_in;
  input [15:0]DRPDI_IN_LANE1;
  input [2:0]gt1_txprbssel_in;
  input [3:0]gt1_txdiffctrl_in;
  input [4:0]gt1_txpostcursor_in;
  input [4:0]gt1_txprecursor_in;
  input [15:0]gt1_cplllock_out_0;
  input [6:0]gt1_txmaincursor_in;
  input [1:0]gt1_txchardispmode_in;
  input [1:0]gt1_txchardispval_in;
  input [1:0]gt1_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE1;
  input DRPEN_IN_LANE2;
  input DRPWE_IN_LANE2;
  input gt2_txinhibit_in;
  input gt2_txpcsreset_in;
  input gt2_txpmareset_in;
  input gt2_txpolarity_in;
  input gt2_txprbsforceerr_in;
  input [15:0]DRPDI_IN_LANE2;
  input [2:0]gt2_txprbssel_in;
  input [3:0]gt2_txdiffctrl_in;
  input [4:0]gt2_txpostcursor_in;
  input [4:0]gt2_txprecursor_in;
  input [15:0]gt2_cplllock_out_0;
  input [6:0]gt2_txmaincursor_in;
  input [1:0]gt2_txchardispmode_in;
  input [1:0]gt2_txchardispval_in;
  input [1:0]gt2_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE2;
  input DRPEN_IN_LANE3;
  input DRPWE_IN_LANE3;
  input gt3_txinhibit_in;
  input gt3_txpcsreset_in;
  input gt3_txpmareset_in;
  input gt3_txpolarity_in;
  input gt3_txprbsforceerr_in;
  input [15:0]DRPDI_IN_LANE3;
  input [2:0]gt3_txprbssel_in;
  input [3:0]gt3_txdiffctrl_in;
  input [4:0]gt3_txpostcursor_in;
  input [4:0]gt3_txprecursor_in;
  input [15:0]gt3_cplllock_out_0;
  input [6:0]gt3_txmaincursor_in;
  input [1:0]gt3_txchardispmode_in;
  input [1:0]gt3_txchardispval_in;
  input [1:0]gt3_cplllock_out_1;
  input [8:0]DRPADDR_IN_LANE3;
  input flag2_reg;
  input ENABLE_ERR_DETECT;
  input ENABLE_ERR_DETECT_0;
  input ENABLE_ERR_DETECT_1;
  input ENABLE_ERR_DETECT_2;
  input cpll_reset_i;

  wire [8:0]DRPADDR_IN;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT;
  wire [15:0]DRPDO_OUT_LANE1;
  wire [15:0]DRPDO_OUT_LANE2;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN;
  wire DRPEN_IN_LANE1;
  wire DRPEN_IN_LANE2;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT;
  wire DRPRDY_OUT_LANE1;
  wire DRPRDY_OUT_LANE2;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN;
  wire DRPWE_IN_LANE1;
  wire DRPWE_IN_LANE2;
  wire DRPWE_IN_LANE3;
  wire ENABLE_ERR_DETECT;
  wire ENABLE_ERR_DETECT_0;
  wire ENABLE_ERR_DETECT_1;
  wire ENABLE_ERR_DETECT_2;
  wire ENABLE_ERR_DETECT_Buffer_reg;
  wire ENABLE_ERR_DETECT_Buffer_reg_0;
  wire ENABLE_ERR_DETECT_Buffer_reg_1;
  wire ENABLE_ERR_DETECT_Buffer_reg_2;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [1:0]TXCHARISK;
  wire [15:0]TXDATA;
  wire [0:3]TXN;
  wire [0:3]TXP;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire [4:0]chbondo_LANE1;
  wire [4:0]chbondo_LANE2;
  wire cpll_reset_i;
  wire drpclk_in;
  wire flag2_reg;
  wire gt0_cplllock_out;
  wire [1:0]gt0_txbufstatus_out;
  wire [1:0]gt0_txchardispmode_in;
  wire [1:0]gt0_txchardispval_in;
  wire [3:0]gt0_txdiffctrl_in;
  wire gt0_txinhibit_in;
  wire [6:0]gt0_txmaincursor_in;
  wire gt0_txpcsreset_in;
  wire gt0_txpmareset_in;
  wire gt0_txpolarity_in;
  wire [4:0]gt0_txpostcursor_in;
  wire gt0_txprbsforceerr_in;
  wire [2:0]gt0_txprbssel_in;
  wire [4:0]gt0_txprecursor_in;
  wire gt0_txresetdone_out;
  wire gt1_cplllock_out;
  wire [15:0]gt1_cplllock_out_0;
  wire [1:0]gt1_cplllock_out_1;
  wire [1:0]gt1_txbufstatus_out;
  wire [1:0]gt1_txchardispmode_in;
  wire [1:0]gt1_txchardispval_in;
  wire [3:0]gt1_txdiffctrl_in;
  wire gt1_txinhibit_in;
  wire [6:0]gt1_txmaincursor_in;
  wire gt1_txpcsreset_in;
  wire gt1_txpmareset_in;
  wire gt1_txpolarity_in;
  wire [4:0]gt1_txpostcursor_in;
  wire gt1_txprbsforceerr_in;
  wire [2:0]gt1_txprbssel_in;
  wire [4:0]gt1_txprecursor_in;
  wire gt1_txresetdone_out;
  wire gt2_cplllock_out;
  wire [15:0]gt2_cplllock_out_0;
  wire [1:0]gt2_cplllock_out_1;
  wire [1:0]gt2_txbufstatus_out;
  wire [1:0]gt2_txchardispmode_in;
  wire [1:0]gt2_txchardispval_in;
  wire [3:0]gt2_txdiffctrl_in;
  wire gt2_txinhibit_in;
  wire [6:0]gt2_txmaincursor_in;
  wire gt2_txpcsreset_in;
  wire gt2_txpmareset_in;
  wire gt2_txpolarity_in;
  wire [4:0]gt2_txpostcursor_in;
  wire gt2_txprbsforceerr_in;
  wire [2:0]gt2_txprbssel_in;
  wire [4:0]gt2_txprecursor_in;
  wire gt2_txresetdone_out;
  wire gt3_cplllock_out;
  wire [15:0]gt3_cplllock_out_0;
  wire [1:0]gt3_cplllock_out_1;
  wire [1:0]gt3_txbufstatus_out;
  wire [1:0]gt3_txchardispmode_in;
  wire [1:0]gt3_txchardispval_in;
  wire [3:0]gt3_txdiffctrl_in;
  wire gt3_txinhibit_in;
  wire [6:0]gt3_txmaincursor_in;
  wire gt3_txpcsreset_in;
  wire gt3_txpmareset_in;
  wire gt3_txpolarity_in;
  wire [4:0]gt3_txpostcursor_in;
  wire gt3_txprbsforceerr_in;
  wire [2:0]gt3_txprbssel_in;
  wire [4:0]gt3_txprecursor_in;
  wire gt3_txresetdone_out;
  wire gt_qpllclk_quad5_in;
  wire gt_qpllrefclk_quad5_in;
  wire gt_refclk1;
  wire gt_rxdfeagchold_i;
  wire gt_rxdfelfhold_i;
  wire gt_rxuserrdy_i;
  wire gt_tx_reset_i;
  wire gt_txuserrdy_i;
  wire init_clk_in;
  wire sync_clk;
  wire user_clk;

  efex_aurora_hub2_efex_aurora_hub2_gt gt0_efex_aurora_hub2_i
       (.DRPADDR_IN(DRPADDR_IN),
        .DRPDI_IN(DRPDI_IN),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPEN_IN(DRPEN_IN),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPWE_IN(DRPWE_IN),
        .ENABLE_ERR_DETECT(ENABLE_ERR_DETECT),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE1),
        .TXCHARISK(TXCHARISK),
        .TXDATA(TXDATA),
        .TXN(TXN[0]),
        .TXP(TXP[0]),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .flag2_reg_0(flag2_reg),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_txbufstatus_out(gt0_txbufstatus_out),
        .gt0_txchardispmode_in(gt0_txchardispmode_in),
        .gt0_txchardispval_in(gt0_txchardispval_in),
        .gt0_txdiffctrl_in(gt0_txdiffctrl_in),
        .gt0_txinhibit_in(gt0_txinhibit_in),
        .gt0_txmaincursor_in(gt0_txmaincursor_in),
        .gt0_txpcsreset_in(gt0_txpcsreset_in),
        .gt0_txpmareset_in(gt0_txpmareset_in),
        .gt0_txpolarity_in(gt0_txpolarity_in),
        .gt0_txpostcursor_in(gt0_txpostcursor_in),
        .gt0_txprbsforceerr_in(gt0_txprbsforceerr_in),
        .gt0_txprbssel_in(gt0_txprbssel_in),
        .gt0_txprecursor_in(gt0_txprecursor_in),
        .gt0_txresetdone_out(gt0_txresetdone_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxdfeagchold_i(gt_rxdfeagchold_i),
        .gt_rxdfelfhold_i(gt_rxdfelfhold_i),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gt_tx_reset_i(gt_tx_reset_i),
        .gt_txuserrdy_i(gt_txuserrdy_i),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_gt_20 gt1_efex_aurora_hub2_i
       (.DRPADDR_IN_LANE1(DRPADDR_IN_LANE1),
        .DRPDI_IN_LANE1(DRPDI_IN_LANE1),
        .DRPDO_OUT_LANE1(DRPDO_OUT_LANE1),
        .DRPEN_IN_LANE1(DRPEN_IN_LANE1),
        .DRPRDY_OUT_LANE1(DRPRDY_OUT_LANE1),
        .DRPWE_IN_LANE1(DRPWE_IN_LANE1),
        .ENABLE_ERR_DETECT_0(ENABLE_ERR_DETECT_0),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg_0),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE1),
        .TXN(TXN[1]),
        .TXP(TXP[1]),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .flag2_reg_0(flag2_reg),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_cplllock_out_0(gt1_cplllock_out_0),
        .gt1_cplllock_out_1(gt1_cplllock_out_1),
        .gt1_txbufstatus_out(gt1_txbufstatus_out),
        .gt1_txchardispmode_in(gt1_txchardispmode_in),
        .gt1_txchardispval_in(gt1_txchardispval_in),
        .gt1_txdiffctrl_in(gt1_txdiffctrl_in),
        .gt1_txinhibit_in(gt1_txinhibit_in),
        .gt1_txmaincursor_in(gt1_txmaincursor_in),
        .gt1_txpcsreset_in(gt1_txpcsreset_in),
        .gt1_txpmareset_in(gt1_txpmareset_in),
        .gt1_txpolarity_in(gt1_txpolarity_in),
        .gt1_txpostcursor_in(gt1_txpostcursor_in),
        .gt1_txprbsforceerr_in(gt1_txprbsforceerr_in),
        .gt1_txprbssel_in(gt1_txprbssel_in),
        .gt1_txprecursor_in(gt1_txprecursor_in),
        .gt1_txresetdone_out(gt1_txresetdone_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxdfeagchold_i(gt_rxdfeagchold_i),
        .gt_rxdfelfhold_i(gt_rxdfelfhold_i),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gt_tx_reset_i(gt_tx_reset_i),
        .gt_txuserrdy_i(gt_txuserrdy_i),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_gt_21 gt2_efex_aurora_hub2_i
       (.DRPADDR_IN_LANE2(DRPADDR_IN_LANE2),
        .DRPDI_IN_LANE2(DRPDI_IN_LANE2),
        .DRPDO_OUT_LANE2(DRPDO_OUT_LANE2),
        .DRPEN_IN_LANE2(DRPEN_IN_LANE2),
        .DRPRDY_OUT_LANE2(DRPRDY_OUT_LANE2),
        .DRPWE_IN_LANE2(DRPWE_IN_LANE2),
        .ENABLE_ERR_DETECT_1(ENABLE_ERR_DETECT_1),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg_1),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE2),
        .TXN(TXN[2]),
        .TXP(TXP[2]),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .flag2_reg_0(flag2_reg),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_cplllock_out_0(chbondo_LANE1),
        .gt2_cplllock_out_1(gt2_cplllock_out_0),
        .gt2_cplllock_out_2(gt2_cplllock_out_1),
        .gt2_txbufstatus_out(gt2_txbufstatus_out),
        .gt2_txchardispmode_in(gt2_txchardispmode_in),
        .gt2_txchardispval_in(gt2_txchardispval_in),
        .gt2_txdiffctrl_in(gt2_txdiffctrl_in),
        .gt2_txinhibit_in(gt2_txinhibit_in),
        .gt2_txmaincursor_in(gt2_txmaincursor_in),
        .gt2_txpcsreset_in(gt2_txpcsreset_in),
        .gt2_txpmareset_in(gt2_txpmareset_in),
        .gt2_txpolarity_in(gt2_txpolarity_in),
        .gt2_txpostcursor_in(gt2_txpostcursor_in),
        .gt2_txprbsforceerr_in(gt2_txprbsforceerr_in),
        .gt2_txprbssel_in(gt2_txprbssel_in),
        .gt2_txprecursor_in(gt2_txprecursor_in),
        .gt2_txresetdone_out(gt2_txresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxdfeagchold_i(gt_rxdfeagchold_i),
        .gt_rxdfelfhold_i(gt_rxdfelfhold_i),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gt_tx_reset_i(gt_tx_reset_i),
        .gt_txuserrdy_i(gt_txuserrdy_i),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_gt_22 gt3_efex_aurora_hub2_i
       (.DRPADDR_IN_LANE3(DRPADDR_IN_LANE3),
        .DRPDI_IN_LANE3(DRPDI_IN_LANE3),
        .DRPDO_OUT_LANE3(DRPDO_OUT_LANE3),
        .DRPEN_IN_LANE3(DRPEN_IN_LANE3),
        .DRPRDY_OUT_LANE3(DRPRDY_OUT_LANE3),
        .DRPWE_IN_LANE3(DRPWE_IN_LANE3),
        .ENABLE_ERR_DETECT_2(ENABLE_ERR_DETECT_2),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg_2),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE2),
        .TXN(TXN[3]),
        .TXP(TXP[3]),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .flag2_reg_0(flag2_reg),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_cplllock_out_0(gt3_cplllock_out_0),
        .gt3_cplllock_out_1(gt3_cplllock_out_1),
        .gt3_txbufstatus_out(gt3_txbufstatus_out),
        .gt3_txchardispmode_in(gt3_txchardispmode_in),
        .gt3_txchardispval_in(gt3_txchardispval_in),
        .gt3_txdiffctrl_in(gt3_txdiffctrl_in),
        .gt3_txinhibit_in(gt3_txinhibit_in),
        .gt3_txmaincursor_in(gt3_txmaincursor_in),
        .gt3_txpcsreset_in(gt3_txpcsreset_in),
        .gt3_txpmareset_in(gt3_txpmareset_in),
        .gt3_txpolarity_in(gt3_txpolarity_in),
        .gt3_txpostcursor_in(gt3_txpostcursor_in),
        .gt3_txprbsforceerr_in(gt3_txprbsforceerr_in),
        .gt3_txprbssel_in(gt3_txprbssel_in),
        .gt3_txprecursor_in(gt3_txprecursor_in),
        .gt3_txresetdone_out(gt3_txresetdone_out),
        .gt_qpllclk_quad5_in(gt_qpllclk_quad5_in),
        .gt_qpllrefclk_quad5_in(gt_qpllrefclk_quad5_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxdfeagchold_i(gt_rxdfeagchold_i),
        .gt_rxdfelfhold_i(gt_rxdfelfhold_i),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gt_tx_reset_i(gt_tx_reset_i),
        .gt_txuserrdy_i(gt_txuserrdy_i),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "efex_aurora_hub2_tx_startup_fsm" *) 
module efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm
   (out,
    gt_tx_reset_i,
    cpll_reset_i,
    gt_txuserrdy_i,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ,
    CPLL_RESET_reg_0,
    in0,
    init_clk_in,
    user_clk,
    txfsm_txresetdone_r,
    AR);
  output out;
  output gt_tx_reset_i;
  output cpll_reset_i;
  output gt_txuserrdy_i;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ;
  output CPLL_RESET_reg_0;
  input in0;
  input init_clk_in;
  input user_clk;
  input txfsm_txresetdone_r;
  input [0:0]AR;

  wire [0:0]AR;
  wire CPLL_RESET_i_1_n_0;
  wire CPLL_RESET_reg_0;
  wire \FSM_sequential_tx_state[2]_i_2_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_10_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_3_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_6_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_7_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_8_n_0 ;
  wire \FSM_sequential_tx_state[3]_i_9_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ;
  wire TXUSERRDY_i_1_n_0;
  wire clear;
  wire cpll_reset_i;
  wire gt_tx_reset_i;
  wire gt_txuserrdy_i;
  wire gttxreset_i_i_1_n_0;
  wire in0;
  wire init_clk_in;
  wire init_wait_count;
  wire \init_wait_count[0]_i_1_n_0 ;
  wire \init_wait_count[6]_i_3_n_0 ;
  wire \init_wait_count[6]_i_4_n_0 ;
  wire [6:0]init_wait_count_reg;
  wire init_wait_done_i_1_n_0;
  wire init_wait_done_i_2_n_0;
  wire init_wait_done_reg_n_0;
  wire \mmcm_lock_count[9]_i_2_n_0 ;
  wire \mmcm_lock_count[9]_i_4_n_0 ;
  wire [9:0]mmcm_lock_count_reg;
  wire mmcm_lock_i;
  wire mmcm_lock_reclocked;
  wire mmcm_lock_reclocked_i_1_n_0;
  wire out;
  wire [6:1]p_0_in;
  wire p_0_in_0;
  wire [9:0]p_0_in__0;
  wire pll_reset_asserted_i_1_n_0;
  wire pll_reset_asserted_reg_n_0;
  wire reset_time_out;
  wire run_phase_alignment_int;
  wire run_phase_alignment_int_i_1_n_0;
  wire run_phase_alignment_int_s3;
  wire scndry_out;
  wire sel;
  wire sync_CPLLLOCK_cdc_sync_n_0;
  wire sync_CPLLLOCK_cdc_sync_n_1;
  wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
  wire time_out_2ms_i_1_n_0;
  wire time_out_2ms_i_2_n_0;
  wire time_out_2ms_i_3_n_0;
  wire time_out_2ms_i_4_n_0;
  wire time_out_2ms_i_5_n_0;
  wire time_out_2ms_reg_n_0;
  wire time_out_500us_i_1_n_0;
  wire time_out_500us_i_2_n_0;
  wire time_out_500us_i_3_n_0;
  wire time_out_500us_i_4_n_0;
  wire time_out_500us_reg_n_0;
  wire \time_out_counter[0]_i_1_n_0 ;
  wire \time_out_counter[0]_i_3_n_0 ;
  wire \time_out_counter[0]_i_4_n_0 ;
  wire [18:0]time_out_counter_reg;
  wire \time_out_counter_reg[0]_i_2_n_0 ;
  wire \time_out_counter_reg[0]_i_2_n_1 ;
  wire \time_out_counter_reg[0]_i_2_n_2 ;
  wire \time_out_counter_reg[0]_i_2_n_3 ;
  wire \time_out_counter_reg[0]_i_2_n_4 ;
  wire \time_out_counter_reg[0]_i_2_n_5 ;
  wire \time_out_counter_reg[0]_i_2_n_6 ;
  wire \time_out_counter_reg[0]_i_2_n_7 ;
  wire \time_out_counter_reg[12]_i_1_n_0 ;
  wire \time_out_counter_reg[12]_i_1_n_1 ;
  wire \time_out_counter_reg[12]_i_1_n_2 ;
  wire \time_out_counter_reg[12]_i_1_n_3 ;
  wire \time_out_counter_reg[12]_i_1_n_4 ;
  wire \time_out_counter_reg[12]_i_1_n_5 ;
  wire \time_out_counter_reg[12]_i_1_n_6 ;
  wire \time_out_counter_reg[12]_i_1_n_7 ;
  wire \time_out_counter_reg[16]_i_1_n_2 ;
  wire \time_out_counter_reg[16]_i_1_n_3 ;
  wire \time_out_counter_reg[16]_i_1_n_5 ;
  wire \time_out_counter_reg[16]_i_1_n_6 ;
  wire \time_out_counter_reg[16]_i_1_n_7 ;
  wire \time_out_counter_reg[4]_i_1_n_0 ;
  wire \time_out_counter_reg[4]_i_1_n_1 ;
  wire \time_out_counter_reg[4]_i_1_n_2 ;
  wire \time_out_counter_reg[4]_i_1_n_3 ;
  wire \time_out_counter_reg[4]_i_1_n_4 ;
  wire \time_out_counter_reg[4]_i_1_n_5 ;
  wire \time_out_counter_reg[4]_i_1_n_6 ;
  wire \time_out_counter_reg[4]_i_1_n_7 ;
  wire \time_out_counter_reg[8]_i_1_n_0 ;
  wire \time_out_counter_reg[8]_i_1_n_1 ;
  wire \time_out_counter_reg[8]_i_1_n_2 ;
  wire \time_out_counter_reg[8]_i_1_n_3 ;
  wire \time_out_counter_reg[8]_i_1_n_4 ;
  wire \time_out_counter_reg[8]_i_1_n_5 ;
  wire \time_out_counter_reg[8]_i_1_n_6 ;
  wire \time_out_counter_reg[8]_i_1_n_7 ;
  wire time_out_wait_bypass;
  wire time_out_wait_bypass_i_1_n_0;
  wire time_out_wait_bypass_i_2_n_0;
  wire time_out_wait_bypass_i_3_n_0;
  wire time_out_wait_bypass_i_4_n_0;
  wire time_out_wait_bypass_i_5_n_0;
  wire time_out_wait_bypass_i_6_n_0;
  wire time_out_wait_bypass_s2;
  wire time_out_wait_bypass_s3;
  wire time_tlock_max_i_1_n_0;
  wire time_tlock_max_i_2_n_0;
  wire time_tlock_max_i_3_n_0;
  wire time_tlock_max_reg_n_0;
  wire tx_fsm_reset_done_int;
  wire tx_fsm_reset_done_int_i_1_n_0;
  wire tx_fsm_reset_done_int_s3;
  wire [3:0]tx_state;
  wire [3:0]tx_state__0;
  wire txfsm_txresetdone_r;
  wire txresetdone_s2;
  wire txresetdone_s3;
  wire user_clk;
  wire \wait_bypass_count[0]_i_2_n_0 ;
  wire \wait_bypass_count[0]_i_4_n_0 ;
  wire [15:0]wait_bypass_count_reg;
  wire \wait_bypass_count_reg[0]_i_3_n_0 ;
  wire \wait_bypass_count_reg[0]_i_3_n_1 ;
  wire \wait_bypass_count_reg[0]_i_3_n_2 ;
  wire \wait_bypass_count_reg[0]_i_3_n_3 ;
  wire \wait_bypass_count_reg[0]_i_3_n_4 ;
  wire \wait_bypass_count_reg[0]_i_3_n_5 ;
  wire \wait_bypass_count_reg[0]_i_3_n_6 ;
  wire \wait_bypass_count_reg[0]_i_3_n_7 ;
  wire \wait_bypass_count_reg[12]_i_1_n_1 ;
  wire \wait_bypass_count_reg[12]_i_1_n_2 ;
  wire \wait_bypass_count_reg[12]_i_1_n_3 ;
  wire \wait_bypass_count_reg[12]_i_1_n_4 ;
  wire \wait_bypass_count_reg[12]_i_1_n_5 ;
  wire \wait_bypass_count_reg[12]_i_1_n_6 ;
  wire \wait_bypass_count_reg[12]_i_1_n_7 ;
  wire \wait_bypass_count_reg[4]_i_1_n_0 ;
  wire \wait_bypass_count_reg[4]_i_1_n_1 ;
  wire \wait_bypass_count_reg[4]_i_1_n_2 ;
  wire \wait_bypass_count_reg[4]_i_1_n_3 ;
  wire \wait_bypass_count_reg[4]_i_1_n_4 ;
  wire \wait_bypass_count_reg[4]_i_1_n_5 ;
  wire \wait_bypass_count_reg[4]_i_1_n_6 ;
  wire \wait_bypass_count_reg[4]_i_1_n_7 ;
  wire \wait_bypass_count_reg[8]_i_1_n_0 ;
  wire \wait_bypass_count_reg[8]_i_1_n_1 ;
  wire \wait_bypass_count_reg[8]_i_1_n_2 ;
  wire \wait_bypass_count_reg[8]_i_1_n_3 ;
  wire \wait_bypass_count_reg[8]_i_1_n_4 ;
  wire \wait_bypass_count_reg[8]_i_1_n_5 ;
  wire \wait_bypass_count_reg[8]_i_1_n_6 ;
  wire \wait_bypass_count_reg[8]_i_1_n_7 ;
  wire [6:0]wait_time_cnt0;
  wire \wait_time_cnt[6]_i_1_n_0 ;
  wire \wait_time_cnt[6]_i_4_n_0 ;
  wire [6:0]wait_time_cnt_reg;
  wire [3:2]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFFFFDFF00000100)) 
    CPLL_RESET_i_1
       (.I0(pll_reset_asserted_reg_n_0),
        .I1(tx_state[2]),
        .I2(tx_state[1]),
        .I3(tx_state[0]),
        .I4(tx_state[3]),
        .I5(cpll_reset_i),
        .O(CPLL_RESET_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    CPLL_RESET_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(CPLL_RESET_i_1_n_0),
        .Q(cpll_reset_i),
        .R(AR));
  LUT6 #(
    .INIT(64'hEFEFEFEFEFFFEFEF)) 
    \FSM_sequential_tx_state[0]_i_1 
       (.I0(\FSM_sequential_tx_state[3]_i_6_n_0 ),
        .I1(tx_state[3]),
        .I2(tx_state[0]),
        .I3(\FSM_sequential_tx_state[2]_i_2_n_0 ),
        .I4(tx_state[2]),
        .I5(tx_state[1]),
        .O(tx_state__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'h000F00D0)) 
    \FSM_sequential_tx_state[1]_i_1 
       (.I0(tx_state[2]),
        .I1(\FSM_sequential_tx_state[2]_i_2_n_0 ),
        .I2(tx_state[0]),
        .I3(tx_state[3]),
        .I4(tx_state[1]),
        .O(tx_state__0[1]));
  LUT6 #(
    .INIT(64'h000000000838CCCC)) 
    \FSM_sequential_tx_state[2]_i_1 
       (.I0(\FSM_sequential_tx_state[2]_i_2_n_0 ),
        .I1(tx_state[2]),
        .I2(tx_state[1]),
        .I3(time_out_2ms_reg_n_0),
        .I4(tx_state[0]),
        .I5(tx_state[3]),
        .O(tx_state__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_tx_state[2]_i_2 
       (.I0(time_tlock_max_reg_n_0),
        .I1(reset_time_out),
        .I2(mmcm_lock_reclocked),
        .O(\FSM_sequential_tx_state[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_tx_state[3]_i_10 
       (.I0(tx_state[3]),
        .I1(tx_state[0]),
        .O(\FSM_sequential_tx_state[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h5555555500F30000)) 
    \FSM_sequential_tx_state[3]_i_2 
       (.I0(time_out_wait_bypass_s3),
        .I1(time_out_500us_reg_n_0),
        .I2(reset_time_out),
        .I3(\FSM_sequential_tx_state[3]_i_7_n_0 ),
        .I4(tx_state[0]),
        .I5(tx_state[3]),
        .O(tx_state__0[3]));
  LUT6 #(
    .INIT(64'h0000001100FF00F0)) 
    \FSM_sequential_tx_state[3]_i_3 
       (.I0(wait_time_cnt_reg[6]),
        .I1(\wait_time_cnt[6]_i_4_n_0 ),
        .I2(init_wait_done_reg_n_0),
        .I3(tx_state[0]),
        .I4(tx_state[3]),
        .I5(\FSM_sequential_tx_state[3]_i_8_n_0 ),
        .O(\FSM_sequential_tx_state[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h2020F000)) 
    \FSM_sequential_tx_state[3]_i_6 
       (.I0(time_out_500us_reg_n_0),
        .I1(reset_time_out),
        .I2(tx_state[1]),
        .I3(time_out_2ms_reg_n_0),
        .I4(tx_state[2]),
        .O(\FSM_sequential_tx_state[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_sequential_tx_state[3]_i_7 
       (.I0(tx_state[1]),
        .I1(tx_state[2]),
        .O(\FSM_sequential_tx_state[3]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_tx_state[3]_i_8 
       (.I0(tx_state[1]),
        .I1(tx_state[2]),
        .O(\FSM_sequential_tx_state[3]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_tx_state[3]_i_9 
       (.I0(reset_time_out),
        .I1(time_tlock_max_reg_n_0),
        .O(\FSM_sequential_tx_state[3]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_tx_state_reg[0] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_1),
        .D(tx_state__0[0]),
        .Q(tx_state[0]),
        .R(AR));
  (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_tx_state_reg[1] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_1),
        .D(tx_state__0[1]),
        .Q(tx_state[1]),
        .R(AR));
  (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_tx_state_reg[2] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_1),
        .D(tx_state__0[2]),
        .Q(tx_state[2]),
        .R(AR));
  (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_tx_state_reg[3] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_1),
        .D(tx_state__0[3]),
        .Q(tx_state[3]),
        .R(AR));
  LUT5 #(
    .INIT(32'hFFFB4000)) 
    TXUSERRDY_i_1
       (.I0(tx_state[3]),
        .I1(tx_state[0]),
        .I2(tx_state[1]),
        .I3(tx_state[2]),
        .I4(gt_txuserrdy_i),
        .O(TXUSERRDY_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    TXUSERRDY_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(TXUSERRDY_i_1_n_0),
        .Q(gt_txuserrdy_i),
        .R(AR));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1__2
       (.I0(cpll_reset_i),
        .O(CPLL_RESET_reg_0));
  LUT5 #(
    .INIT(32'hFEFF0004)) 
    gttxreset_i_i_1
       (.I0(tx_state[3]),
        .I1(tx_state[0]),
        .I2(tx_state[1]),
        .I3(tx_state[2]),
        .I4(gt_tx_reset_i),
        .O(gttxreset_i_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gttxreset_i_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gttxreset_i_i_1_n_0),
        .Q(gt_tx_reset_i),
        .R(AR));
  LUT1 #(
    .INIT(2'h1)) 
    \init_wait_count[0]_i_1 
       (.I0(init_wait_count_reg[0]),
        .O(\init_wait_count[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \init_wait_count[1]_i_1 
       (.I0(init_wait_count_reg[0]),
        .I1(init_wait_count_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \init_wait_count[2]_i_1 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \init_wait_count[3]_i_1 
       (.I0(init_wait_count_reg[2]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[1]),
        .I3(init_wait_count_reg[3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \init_wait_count[4]_i_1 
       (.I0(init_wait_count_reg[3]),
        .I1(init_wait_count_reg[1]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[2]),
        .I4(init_wait_count_reg[4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \init_wait_count[5]_i_1 
       (.I0(init_wait_count_reg[4]),
        .I1(init_wait_count_reg[2]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[1]),
        .I4(init_wait_count_reg[3]),
        .I5(init_wait_count_reg[5]),
        .O(p_0_in[5]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFBFFFF)) 
    \init_wait_count[6]_i_1 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[2]),
        .I3(init_wait_count_reg[3]),
        .I4(init_wait_count_reg[4]),
        .I5(\init_wait_count[6]_i_3_n_0 ),
        .O(init_wait_count));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hC6)) 
    \init_wait_count[6]_i_2 
       (.I0(init_wait_count_reg[5]),
        .I1(init_wait_count_reg[6]),
        .I2(\init_wait_count[6]_i_4_n_0 ),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_wait_count[6]_i_3 
       (.I0(init_wait_count_reg[5]),
        .I1(init_wait_count_reg[6]),
        .O(\init_wait_count[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \init_wait_count[6]_i_4 
       (.I0(init_wait_count_reg[3]),
        .I1(init_wait_count_reg[1]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[2]),
        .I4(init_wait_count_reg[4]),
        .O(\init_wait_count[6]_i_4_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[0] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(\init_wait_count[0]_i_1_n_0 ),
        .Q(init_wait_count_reg[0]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[1] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[1]),
        .Q(init_wait_count_reg[1]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[2] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[2]),
        .Q(init_wait_count_reg[2]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[3] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[3]),
        .Q(init_wait_count_reg[3]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[4] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[4]),
        .Q(init_wait_count_reg[4]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[5] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[5]),
        .Q(init_wait_count_reg[5]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[6] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[6]),
        .Q(init_wait_count_reg[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000004)) 
    init_wait_done_i_1
       (.I0(init_wait_count_reg[3]),
        .I1(init_wait_count_reg[4]),
        .I2(init_wait_count_reg[2]),
        .I3(init_wait_done_i_2_n_0),
        .I4(\init_wait_count[6]_i_3_n_0 ),
        .I5(init_wait_done_reg_n_0),
        .O(init_wait_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'hB)) 
    init_wait_done_i_2
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .O(init_wait_done_i_2_n_0));
  FDCE #(
    .INIT(1'b0)) 
    init_wait_done_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(AR),
        .D(init_wait_done_i_1_n_0),
        .Q(init_wait_done_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \mmcm_lock_count[0]_i_1 
       (.I0(mmcm_lock_count_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \mmcm_lock_count[1]_i_1 
       (.I0(mmcm_lock_count_reg[0]),
        .I1(mmcm_lock_count_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \mmcm_lock_count[2]_i_1 
       (.I0(mmcm_lock_count_reg[1]),
        .I1(mmcm_lock_count_reg[0]),
        .I2(mmcm_lock_count_reg[2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \mmcm_lock_count[3]_i_1 
       (.I0(mmcm_lock_count_reg[2]),
        .I1(mmcm_lock_count_reg[0]),
        .I2(mmcm_lock_count_reg[1]),
        .I3(mmcm_lock_count_reg[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \mmcm_lock_count[4]_i_1 
       (.I0(mmcm_lock_count_reg[3]),
        .I1(mmcm_lock_count_reg[1]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[2]),
        .I4(mmcm_lock_count_reg[4]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \mmcm_lock_count[5]_i_1 
       (.I0(mmcm_lock_count_reg[4]),
        .I1(mmcm_lock_count_reg[2]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[1]),
        .I4(mmcm_lock_count_reg[3]),
        .I5(mmcm_lock_count_reg[5]),
        .O(p_0_in__0[5]));
  LUT2 #(
    .INIT(4'h9)) 
    \mmcm_lock_count[6]_i_1 
       (.I0(\mmcm_lock_count[9]_i_4_n_0 ),
        .I1(mmcm_lock_count_reg[6]),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \mmcm_lock_count[7]_i_1 
       (.I0(mmcm_lock_count_reg[6]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[7]),
        .O(p_0_in__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \mmcm_lock_count[8]_i_1 
       (.I0(mmcm_lock_count_reg[7]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[6]),
        .I3(mmcm_lock_count_reg[8]),
        .O(p_0_in__0[8]));
  LUT5 #(
    .INIT(32'hDFFFFFFF)) 
    \mmcm_lock_count[9]_i_2 
       (.I0(mmcm_lock_count_reg[7]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[6]),
        .I3(mmcm_lock_count_reg[8]),
        .I4(mmcm_lock_count_reg[9]),
        .O(\mmcm_lock_count[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \mmcm_lock_count[9]_i_3 
       (.I0(mmcm_lock_count_reg[8]),
        .I1(mmcm_lock_count_reg[6]),
        .I2(\mmcm_lock_count[9]_i_4_n_0 ),
        .I3(mmcm_lock_count_reg[7]),
        .I4(mmcm_lock_count_reg[9]),
        .O(p_0_in__0[9]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \mmcm_lock_count[9]_i_4 
       (.I0(mmcm_lock_count_reg[4]),
        .I1(mmcm_lock_count_reg[2]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[1]),
        .I4(mmcm_lock_count_reg[3]),
        .I5(mmcm_lock_count_reg[5]),
        .O(\mmcm_lock_count[9]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[0] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[0]),
        .Q(mmcm_lock_count_reg[0]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[1] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[1]),
        .Q(mmcm_lock_count_reg[1]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[2] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[2]),
        .Q(mmcm_lock_count_reg[2]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[3] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[3]),
        .Q(mmcm_lock_count_reg[3]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[4] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[4]),
        .Q(mmcm_lock_count_reg[4]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[5] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[5]),
        .Q(mmcm_lock_count_reg[5]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[6] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[6]),
        .Q(mmcm_lock_count_reg[6]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[7] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[7]),
        .Q(mmcm_lock_count_reg[7]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[8] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[8]),
        .Q(mmcm_lock_count_reg[8]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[9] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[9]),
        .Q(mmcm_lock_count_reg[9]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    mmcm_lock_reclocked_i_1
       (.I0(mmcm_lock_reclocked),
        .I1(p_0_in_0),
        .I2(mmcm_lock_i),
        .O(mmcm_lock_reclocked_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    mmcm_lock_reclocked_i_2
       (.I0(mmcm_lock_count_reg[9]),
        .I1(mmcm_lock_count_reg[8]),
        .I2(mmcm_lock_count_reg[6]),
        .I3(\mmcm_lock_count[9]_i_4_n_0 ),
        .I4(mmcm_lock_count_reg[7]),
        .O(p_0_in_0));
  FDRE #(
    .INIT(1'b0)) 
    mmcm_lock_reclocked_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(mmcm_lock_reclocked_i_1_n_0),
        .Q(mmcm_lock_reclocked),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hEF00FF10)) 
    pll_reset_asserted_i_1
       (.I0(tx_state[2]),
        .I1(tx_state[3]),
        .I2(tx_state[0]),
        .I3(pll_reset_asserted_reg_n_0),
        .I4(tx_state[1]),
        .O(pll_reset_asserted_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pll_reset_asserted_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(pll_reset_asserted_i_1_n_0),
        .Q(pll_reset_asserted_reg_n_0),
        .R(AR));
  FDRE #(
    .INIT(1'b0)) 
    reset_time_out_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(sync_CPLLLOCK_cdc_sync_n_0),
        .Q(reset_time_out),
        .R(AR));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'hFFFB0002)) 
    run_phase_alignment_int_i_1
       (.I0(tx_state[3]),
        .I1(tx_state[0]),
        .I2(tx_state[1]),
        .I3(tx_state[2]),
        .I4(run_phase_alignment_int),
        .O(run_phase_alignment_int_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    run_phase_alignment_int_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(run_phase_alignment_int_i_1_n_0),
        .Q(run_phase_alignment_int),
        .R(AR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    run_phase_alignment_int_s3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(scndry_out),
        .Q(run_phase_alignment_int_s3),
        .R(1'b0));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13 sync_CPLLLOCK_cdc_sync
       (.E(sync_CPLLLOCK_cdc_sync_n_1),
        .\FSM_sequential_tx_state_reg[0] (\FSM_sequential_tx_state[3]_i_3_n_0 ),
        .\FSM_sequential_tx_state_reg[0]_0 (\FSM_sequential_tx_state[3]_i_6_n_0 ),
        .\FSM_sequential_tx_state_reg[0]_1 (\FSM_sequential_tx_state[3]_i_9_n_0 ),
        .\FSM_sequential_tx_state_reg[0]_2 (\FSM_sequential_tx_state[3]_i_10_n_0 ),
        .\FSM_sequential_tx_state_reg[0]_3 (pll_reset_asserted_reg_n_0),
        .Q(tx_state),
        .in0(in0),
        .init_clk_in(init_clk_in),
        .mmcm_lock_reclocked(mmcm_lock_reclocked),
        .reset_time_out(reset_time_out),
        .reset_time_out_reg(sync_CPLLLOCK_cdc_sync_n_0),
        .reset_time_out_reg_0(init_wait_done_reg_n_0),
        .txresetdone_s3(txresetdone_s3));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14 sync_QPLLLOCK_cdc_sync
       (.init_clk_in(init_clk_in));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15 sync_TXRESETDONE_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(txresetdone_s2),
        .txfsm_txresetdone_r(txfsm_txresetdone_r),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16 sync_mmcm_lock_reclocked_cdc_sync
       (.SR(sync_mmcm_lock_reclocked_cdc_sync_n_1),
        .init_clk_in(init_clk_in),
        .out(mmcm_lock_i));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17 sync_run_phase_alignment_int_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(scndry_out),
        .run_phase_alignment_int(run_phase_alignment_int),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18 sync_time_out_wait_bypass_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(time_out_wait_bypass_s2),
        .time_out_wait_bypass(time_out_wait_bypass),
        .user_clk(user_clk));
  efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19 sync_tx_fsm_reset_done_int_cdc_sync
       (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg ),
        .init_clk_in(init_clk_in),
        .out(out),
        .tx_fsm_reset_done_int(tx_fsm_reset_done_int),
        .user_clk(user_clk));
  LUT6 #(
    .INIT(64'h00000000AAAAAAEA)) 
    time_out_2ms_i_1
       (.I0(time_out_2ms_reg_n_0),
        .I1(time_out_2ms_i_2_n_0),
        .I2(time_out_2ms_i_3_n_0),
        .I3(time_out_2ms_i_4_n_0),
        .I4(time_out_2ms_i_5_n_0),
        .I5(reset_time_out),
        .O(time_out_2ms_i_1_n_0));
  LUT6 #(
    .INIT(64'h0020000000000000)) 
    time_out_2ms_i_2
       (.I0(time_out_counter_reg[11]),
        .I1(time_out_counter_reg[9]),
        .I2(time_out_counter_reg[4]),
        .I3(time_out_counter_reg[8]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[14]),
        .O(time_out_2ms_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h2)) 
    time_out_2ms_i_3
       (.I0(time_out_counter_reg[1]),
        .I1(time_out_counter_reg[2]),
        .O(time_out_2ms_i_3_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    time_out_2ms_i_4
       (.I0(time_out_counter_reg[0]),
        .I1(time_out_counter_reg[7]),
        .I2(time_out_counter_reg[13]),
        .I3(time_out_counter_reg[6]),
        .I4(time_out_counter_reg[3]),
        .O(time_out_2ms_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    time_out_2ms_i_5
       (.I0(time_out_counter_reg[10]),
        .I1(time_out_counter_reg[12]),
        .I2(time_out_counter_reg[17]),
        .I3(time_out_counter_reg[15]),
        .I4(time_out_counter_reg[5]),
        .I5(time_out_counter_reg[16]),
        .O(time_out_2ms_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_2ms_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_2ms_i_1_n_0),
        .Q(time_out_2ms_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AABAAAAA)) 
    time_out_500us_i_1
       (.I0(time_out_500us_reg_n_0),
        .I1(time_out_500us_i_2_n_0),
        .I2(time_out_500us_i_3_n_0),
        .I3(time_out_2ms_i_4_n_0),
        .I4(time_out_500us_i_4_n_0),
        .I5(reset_time_out),
        .O(time_out_500us_i_1_n_0));
  LUT5 #(
    .INIT(32'hFEFFFFFF)) 
    time_out_500us_i_2
       (.I0(time_out_counter_reg[5]),
        .I1(time_out_counter_reg[15]),
        .I2(time_out_counter_reg[17]),
        .I3(time_out_counter_reg[12]),
        .I4(time_out_counter_reg[10]),
        .O(time_out_500us_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    time_out_500us_i_3
       (.I0(time_out_counter_reg[11]),
        .I1(time_out_counter_reg[14]),
        .I2(time_out_counter_reg[8]),
        .I3(time_out_counter_reg[9]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[16]),
        .O(time_out_500us_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'h04)) 
    time_out_500us_i_4
       (.I0(time_out_counter_reg[4]),
        .I1(time_out_counter_reg[2]),
        .I2(time_out_counter_reg[1]),
        .O(time_out_500us_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_500us_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_500us_i_1_n_0),
        .Q(time_out_500us_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    \time_out_counter[0]_i_1 
       (.I0(\time_out_counter[0]_i_3_n_0 ),
        .I1(time_out_2ms_i_4_n_0),
        .I2(time_out_counter_reg[4]),
        .I3(time_out_counter_reg[2]),
        .I4(time_out_counter_reg[1]),
        .O(\time_out_counter[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF7FFFF)) 
    \time_out_counter[0]_i_3 
       (.I0(time_out_counter_reg[14]),
        .I1(time_out_counter_reg[18]),
        .I2(time_out_counter_reg[8]),
        .I3(time_out_counter_reg[9]),
        .I4(time_out_counter_reg[11]),
        .I5(time_out_2ms_i_5_n_0),
        .O(\time_out_counter[0]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \time_out_counter[0]_i_4 
       (.I0(time_out_counter_reg[0]),
        .O(\time_out_counter[0]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[0] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[0]_i_2_n_7 ),
        .Q(time_out_counter_reg[0]),
        .R(reset_time_out));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }),
        .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[10] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[8]_i_1_n_5 ),
        .Q(time_out_counter_reg[10]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[11] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[8]_i_1_n_4 ),
        .Q(time_out_counter_reg[11]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[12] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[12]_i_1_n_7 ),
        .Q(time_out_counter_reg[12]),
        .R(reset_time_out));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[12]_i_1 
       (.CI(\time_out_counter_reg[8]_i_1_n_0 ),
        .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }),
        .S(time_out_counter_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[13] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[12]_i_1_n_6 ),
        .Q(time_out_counter_reg[13]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[14] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[12]_i_1_n_5 ),
        .Q(time_out_counter_reg[14]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[15] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[12]_i_1_n_4 ),
        .Q(time_out_counter_reg[15]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[16] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[16]_i_1_n_7 ),
        .Q(time_out_counter_reg[16]),
        .R(reset_time_out));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[16]_i_1 
       (.CI(\time_out_counter_reg[12]_i_1_n_0 ),
        .CO({\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1_n_2 ,\time_out_counter_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3],\time_out_counter_reg[16]_i_1_n_5 ,\time_out_counter_reg[16]_i_1_n_6 ,\time_out_counter_reg[16]_i_1_n_7 }),
        .S({1'b0,time_out_counter_reg[18:16]}));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[17] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[16]_i_1_n_6 ),
        .Q(time_out_counter_reg[17]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[18] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[16]_i_1_n_5 ),
        .Q(time_out_counter_reg[18]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[1] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[0]_i_2_n_6 ),
        .Q(time_out_counter_reg[1]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[2] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[0]_i_2_n_5 ),
        .Q(time_out_counter_reg[2]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[3] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[0]_i_2_n_4 ),
        .Q(time_out_counter_reg[3]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[4] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[4]_i_1_n_7 ),
        .Q(time_out_counter_reg[4]),
        .R(reset_time_out));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[4]_i_1 
       (.CI(\time_out_counter_reg[0]_i_2_n_0 ),
        .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }),
        .S(time_out_counter_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[5] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[4]_i_1_n_6 ),
        .Q(time_out_counter_reg[5]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[6] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[4]_i_1_n_5 ),
        .Q(time_out_counter_reg[6]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[7] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[4]_i_1_n_4 ),
        .Q(time_out_counter_reg[7]),
        .R(reset_time_out));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[8] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[8]_i_1_n_7 ),
        .Q(time_out_counter_reg[8]),
        .R(reset_time_out));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[8]_i_1 
       (.CI(\time_out_counter_reg[4]_i_1_n_0 ),
        .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }),
        .S(time_out_counter_reg[11:8]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[9] 
       (.C(init_clk_in),
        .CE(\time_out_counter[0]_i_1_n_0 ),
        .D(\time_out_counter_reg[8]_i_1_n_6 ),
        .Q(time_out_counter_reg[9]),
        .R(reset_time_out));
  LUT4 #(
    .INIT(16'hAB00)) 
    time_out_wait_bypass_i_1
       (.I0(time_out_wait_bypass),
        .I1(time_out_wait_bypass_i_2_n_0),
        .I2(tx_fsm_reset_done_int_s3),
        .I3(run_phase_alignment_int_s3),
        .O(time_out_wait_bypass_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    time_out_wait_bypass_i_2
       (.I0(time_out_wait_bypass_i_3_n_0),
        .I1(time_out_wait_bypass_i_4_n_0),
        .I2(time_out_wait_bypass_i_5_n_0),
        .I3(time_out_wait_bypass_i_6_n_0),
        .O(time_out_wait_bypass_i_2_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    time_out_wait_bypass_i_3
       (.I0(wait_bypass_count_reg[5]),
        .I1(wait_bypass_count_reg[4]),
        .I2(wait_bypass_count_reg[7]),
        .I3(wait_bypass_count_reg[6]),
        .O(time_out_wait_bypass_i_3_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    time_out_wait_bypass_i_4
       (.I0(wait_bypass_count_reg[1]),
        .I1(wait_bypass_count_reg[0]),
        .I2(wait_bypass_count_reg[3]),
        .I3(wait_bypass_count_reg[2]),
        .O(time_out_wait_bypass_i_4_n_0));
  LUT4 #(
    .INIT(16'hEFFF)) 
    time_out_wait_bypass_i_5
       (.I0(wait_bypass_count_reg[13]),
        .I1(wait_bypass_count_reg[12]),
        .I2(wait_bypass_count_reg[15]),
        .I3(wait_bypass_count_reg[14]),
        .O(time_out_wait_bypass_i_5_n_0));
  LUT4 #(
    .INIT(16'hFFDF)) 
    time_out_wait_bypass_i_6
       (.I0(wait_bypass_count_reg[8]),
        .I1(wait_bypass_count_reg[9]),
        .I2(wait_bypass_count_reg[10]),
        .I3(wait_bypass_count_reg[11]),
        .O(time_out_wait_bypass_i_6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_wait_bypass_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(time_out_wait_bypass_i_1_n_0),
        .Q(time_out_wait_bypass),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    time_out_wait_bypass_s3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_wait_bypass_s2),
        .Q(time_out_wait_bypass_s3),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAAEAAA)) 
    time_tlock_max_i_1
       (.I0(time_tlock_max_reg_n_0),
        .I1(time_tlock_max_i_2_n_0),
        .I2(time_tlock_max_i_3_n_0),
        .I3(time_out_counter_reg[0]),
        .I4(time_out_2ms_i_5_n_0),
        .I5(reset_time_out),
        .O(time_tlock_max_i_1_n_0));
  LUT6 #(
    .INIT(64'h0020000000000000)) 
    time_tlock_max_i_2
       (.I0(time_out_counter_reg[3]),
        .I1(time_out_counter_reg[4]),
        .I2(time_out_counter_reg[2]),
        .I3(time_out_counter_reg[1]),
        .I4(time_out_counter_reg[7]),
        .I5(time_out_counter_reg[6]),
        .O(time_tlock_max_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    time_tlock_max_i_3
       (.I0(time_out_counter_reg[13]),
        .I1(time_out_counter_reg[11]),
        .I2(time_out_counter_reg[8]),
        .I3(time_out_counter_reg[9]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[14]),
        .O(time_tlock_max_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_tlock_max_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_tlock_max_i_1_n_0),
        .Q(time_tlock_max_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF0008)) 
    tx_fsm_reset_done_int_i_1
       (.I0(tx_state[0]),
        .I1(tx_state[3]),
        .I2(tx_state[2]),
        .I3(tx_state[1]),
        .I4(tx_fsm_reset_done_int),
        .O(tx_fsm_reset_done_int_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    tx_fsm_reset_done_int_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(tx_fsm_reset_done_int_i_1_n_0),
        .Q(tx_fsm_reset_done_int),
        .R(AR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    tx_fsm_reset_done_int_s3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(out),
        .Q(tx_fsm_reset_done_int_s3),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    txresetdone_s3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(txresetdone_s2),
        .Q(txresetdone_s3),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_bypass_count[0]_i_1 
       (.I0(run_phase_alignment_int_s3),
        .O(clear));
  LUT2 #(
    .INIT(4'h2)) 
    \wait_bypass_count[0]_i_2 
       (.I0(time_out_wait_bypass_i_2_n_0),
        .I1(tx_fsm_reset_done_int_s3),
        .O(\wait_bypass_count[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_bypass_count[0]_i_4 
       (.I0(wait_bypass_count_reg[0]),
        .O(\wait_bypass_count[0]_i_4_n_0 ));
  FDRE \wait_bypass_count_reg[0] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_7 ),
        .Q(wait_bypass_count_reg[0]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }),
        .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_4_n_0 }));
  FDRE \wait_bypass_count_reg[10] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[10]),
        .R(clear));
  FDRE \wait_bypass_count_reg[11] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[11]),
        .R(clear));
  FDRE \wait_bypass_count_reg[12] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[12]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[12]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[12]_i_1 
       (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ),
        .CO({\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED [3],\wait_bypass_count_reg[12]_i_1_n_1 ,\wait_bypass_count_reg[12]_i_1_n_2 ,\wait_bypass_count_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[12]_i_1_n_4 ,\wait_bypass_count_reg[12]_i_1_n_5 ,\wait_bypass_count_reg[12]_i_1_n_6 ,\wait_bypass_count_reg[12]_i_1_n_7 }),
        .S(wait_bypass_count_reg[15:12]));
  FDRE \wait_bypass_count_reg[13] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[12]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[13]),
        .R(clear));
  FDRE \wait_bypass_count_reg[14] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[12]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[14]),
        .R(clear));
  FDRE \wait_bypass_count_reg[15] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[12]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[15]),
        .R(clear));
  FDRE \wait_bypass_count_reg[1] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_6 ),
        .Q(wait_bypass_count_reg[1]),
        .R(clear));
  FDRE \wait_bypass_count_reg[2] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_5 ),
        .Q(wait_bypass_count_reg[2]),
        .R(clear));
  FDRE \wait_bypass_count_reg[3] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_4 ),
        .Q(wait_bypass_count_reg[3]),
        .R(clear));
  FDRE \wait_bypass_count_reg[4] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[4]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[4]_i_1 
       (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ),
        .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }),
        .S(wait_bypass_count_reg[7:4]));
  FDRE \wait_bypass_count_reg[5] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[5]),
        .R(clear));
  FDRE \wait_bypass_count_reg[6] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[6]),
        .R(clear));
  FDRE \wait_bypass_count_reg[7] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[7]),
        .R(clear));
  FDRE \wait_bypass_count_reg[8] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[8]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[8]_i_1 
       (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ),
        .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }),
        .S(wait_bypass_count_reg[11:8]));
  FDRE \wait_bypass_count_reg[9] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[9]),
        .R(clear));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wait_time_cnt[0]_i_1 
       (.I0(wait_time_cnt_reg[0]),
        .O(wait_time_cnt0[0]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_time_cnt[1]_i_1 
       (.I0(wait_time_cnt_reg[1]),
        .I1(wait_time_cnt_reg[0]),
        .O(wait_time_cnt0[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_time_cnt[2]_i_1 
       (.I0(wait_time_cnt_reg[2]),
        .I1(wait_time_cnt_reg[0]),
        .I2(wait_time_cnt_reg[1]),
        .O(wait_time_cnt0[2]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_time_cnt[3]_i_1 
       (.I0(wait_time_cnt_reg[3]),
        .I1(wait_time_cnt_reg[1]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[2]),
        .O(wait_time_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \wait_time_cnt[4]_i_1 
       (.I0(wait_time_cnt_reg[4]),
        .I1(wait_time_cnt_reg[2]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[1]),
        .I4(wait_time_cnt_reg[3]),
        .O(wait_time_cnt0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \wait_time_cnt[5]_i_1 
       (.I0(wait_time_cnt_reg[5]),
        .I1(wait_time_cnt_reg[3]),
        .I2(wait_time_cnt_reg[1]),
        .I3(wait_time_cnt_reg[0]),
        .I4(wait_time_cnt_reg[2]),
        .I5(wait_time_cnt_reg[4]),
        .O(wait_time_cnt0[5]));
  LUT4 #(
    .INIT(16'h0070)) 
    \wait_time_cnt[6]_i_1 
       (.I0(tx_state[2]),
        .I1(tx_state[1]),
        .I2(tx_state[0]),
        .I3(tx_state[3]),
        .O(\wait_time_cnt[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \wait_time_cnt[6]_i_2 
       (.I0(\wait_time_cnt[6]_i_4_n_0 ),
        .I1(wait_time_cnt_reg[6]),
        .O(sel));
  LUT2 #(
    .INIT(4'h9)) 
    \wait_time_cnt[6]_i_3 
       (.I0(wait_time_cnt_reg[6]),
        .I1(\wait_time_cnt[6]_i_4_n_0 ),
        .O(wait_time_cnt0[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wait_time_cnt[6]_i_4 
       (.I0(wait_time_cnt_reg[4]),
        .I1(wait_time_cnt_reg[2]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[1]),
        .I4(wait_time_cnt_reg[3]),
        .I5(wait_time_cnt_reg[5]),
        .O(\wait_time_cnt[6]_i_4_n_0 ));
  FDRE \wait_time_cnt_reg[0] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[0]),
        .Q(wait_time_cnt_reg[0]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[1] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[1]),
        .Q(wait_time_cnt_reg[1]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[2] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[2]),
        .Q(wait_time_cnt_reg[2]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[3] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[3]),
        .Q(wait_time_cnt_reg[3]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[4] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[4]),
        .Q(wait_time_cnt_reg[4]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[5] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[5]),
        .Q(wait_time_cnt_reg[5]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[6] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[6]),
        .Q(wait_time_cnt_reg[6]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
