-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
-- Date        : Sat Mar  8 22:13:41 2025
-- Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit AlmaLinux 9.5 (Teal Serval)
-- Command     : write_vhdl -force -mode funcsim
--               /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_sim_netlist.vhdl
-- Design      : efex_aurora_hub2
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx330tffg1157-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL is
  port (
    new_pkt_r_reg_0 : out STD_LOGIC;
    new_pkt_r : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL : entity is "efex_aurora_hub2_AXI_TO_LL";
end efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL is
begin
new_pkt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => new_pkt_r,
      Q => new_pkt_r_reg_0,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN is
  port (
    gen_v_flop_0_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_v_flop_2_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_v_flop_4_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_v_flop_6_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GEN_A : out STD_LOGIC;
    gen_a_flop_1_i_0 : out STD_LOGIC;
    gen_a_flop_2_i_0 : out STD_LOGIC;
    gen_a_flop_3_i_0 : out STD_LOGIC;
    gen_k_flop_0_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_k_flop_2_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_k_flop_4_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_k_flop_6_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_0_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_2_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_4_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_6_i_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RESET_SYMGEN : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    gen_ver_i : in STD_LOGIC;
    tx_reset_simplex_r : in STD_LOGIC;
    \downcounter_r_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN : entity is "efex_aurora_hub2_IDLE_AND_VER_GEN";
end efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN is
  signal D : STD_LOGIC;
  signal D0_out : STD_LOGIC;
  signal D1_out : STD_LOGIC;
  signal D2_out : STD_LOGIC;
  signal \downcounter_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \downcounter_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \downcounter_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \downcounter_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \downcounter_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \downcounter_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \downcounter_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \downcounter_r_reg_n_0_[3]\ : STD_LOGIC;
  signal gen_k_flop_0_i_i_1_n_0 : STD_LOGIC;
  signal gen_r_flop_0_i_i_1_n_0 : STD_LOGIC;
  signal gen_r_flop_1_i_i_1_n_0 : STD_LOGIC;
  signal gen_v_flop_1_i_i_1_n_0 : STD_LOGIC;
  signal gen_ver_word_2_r_reg_n_0 : STD_LOGIC;
  signal lfsr_last_flop_r : STD_LOGIC;
  signal \lfsr_shift_register_r_reg[2]_srl3_n_0\ : STD_LOGIC;
  signal lfsr_taps_i_i_1_n_0 : STD_LOGIC;
  signal lfsr_taps_r : STD_LOGIC;
  signal prev_cycle_gen_ver_r : STD_LOGIC;
  signal ver_counter_r_0 : STD_LOGIC;
  signal ver_counter_r_1 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of gen_a_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of gen_a_flop_0_i : label is "FD";
  attribute BOX_TYPE of gen_a_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_a_flop_1_i : label is "FD";
  attribute BOX_TYPE of gen_a_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_a_flop_2_i : label is "FD";
  attribute BOX_TYPE of gen_a_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_a_flop_3_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_0_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_1_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_2_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_3_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_4_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_4_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_5_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_5_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_6_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_6_i : label is "FD";
  attribute BOX_TYPE of gen_k_flop_7_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_k_flop_7_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_0_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_1_i : label is "FD";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of gen_r_flop_1_i_i_1 : label is "soft_lutpair41";
  attribute BOX_TYPE of gen_r_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_2_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_3_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_4_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_4_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_5_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_5_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_6_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_6_i : label is "FD";
  attribute BOX_TYPE of gen_r_flop_7_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_r_flop_7_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_0_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_1_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_2_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_3_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_4_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_4_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_5_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_5_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_6_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_6_i : label is "FD";
  attribute BOX_TYPE of gen_v_flop_7_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_v_flop_7_i : label is "FD";
  attribute BOX_TYPE of lfsr_last_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of lfsr_last_flop_i : label is "FDR";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \lfsr_shift_register_r_reg[2]_srl3\ : label is "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/lfsr_shift_register_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \lfsr_shift_register_r_reg[2]_srl3\ : label is "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/lfsr_shift_register_r_reg[2]_srl3 ";
  attribute BOX_TYPE of lfsr_taps_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of lfsr_taps_i : label is "FDR";
  attribute SOFT_HLUTNM of lfsr_taps_i_i_1 : label is "soft_lutpair41";
  attribute BOX_TYPE of ver_counter_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of ver_counter_0_i : label is "SRL16";
  attribute srl_name of ver_counter_0_i : label is "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/ver_counter_0_i ";
  attribute BOX_TYPE of ver_counter_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of ver_counter_1_i : label is "SRL16";
  attribute srl_name of ver_counter_1_i : label is "U0/\tx_global_logic_simplex_i/idle_and_ver_gen_i/ver_counter_1_i ";
begin
\downcounter_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101010101001"
    )
        port map (
      I0 => tx_reset_simplex_r,
      I1 => \downcounter_r_reg[0]_0\,
      I2 => \downcounter_r_reg_n_0_[0]\,
      I3 => \downcounter_r_reg_n_0_[2]\,
      I4 => \downcounter_r_reg_n_0_[1]\,
      I5 => \downcounter_r_reg_n_0_[3]\,
      O => \downcounter_r[0]_i_1_n_0\
    );
\downcounter_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F0C3F0C2"
    )
        port map (
      I0 => \downcounter_r_reg_n_0_[0]\,
      I1 => \downcounter_r_reg_n_0_[2]\,
      I2 => \downcounter_r_reg_n_0_[1]\,
      I3 => \downcounter_r_reg_n_0_[3]\,
      I4 => lfsr_taps_r,
      I5 => RESET_SYMGEN,
      O => \downcounter_r[1]_i_1_n_0\
    );
\downcounter_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CC33CC32"
    )
        port map (
      I0 => \downcounter_r_reg_n_0_[0]\,
      I1 => \downcounter_r_reg_n_0_[2]\,
      I2 => \downcounter_r_reg_n_0_[1]\,
      I3 => \downcounter_r_reg_n_0_[3]\,
      I4 => D,
      I5 => RESET_SYMGEN,
      O => \downcounter_r[2]_i_1_n_0\
    );
\downcounter_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \downcounter_r_reg_n_0_[3]\,
      I1 => RESET_SYMGEN,
      I2 => lfsr_last_flop_r,
      I3 => \downcounter_r_reg_n_0_[1]\,
      I4 => \downcounter_r_reg_n_0_[2]\,
      I5 => \downcounter_r_reg_n_0_[0]\,
      O => \downcounter_r[3]_i_1_n_0\
    );
\downcounter_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \downcounter_r[0]_i_1_n_0\,
      Q => \downcounter_r_reg_n_0_[0]\,
      R => '0'
    );
\downcounter_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \downcounter_r[1]_i_1_n_0\,
      Q => \downcounter_r_reg_n_0_[1]\,
      R => '0'
    );
\downcounter_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \downcounter_r[2]_i_1_n_0\,
      Q => \downcounter_r_reg_n_0_[2]\,
      R => '0'
    );
\downcounter_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \downcounter_r[3]_i_1_n_0\,
      Q => \downcounter_r_reg_n_0_[3]\,
      R => '0'
    );
gen_a_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D2_out,
      Q => GEN_A,
      R => '0'
    );
gen_a_flop_0_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \downcounter_r_reg_n_0_[3]\,
      I1 => \downcounter_r_reg_n_0_[1]\,
      I2 => \downcounter_r_reg_n_0_[2]\,
      I3 => \downcounter_r_reg_n_0_[0]\,
      I4 => ver_counter_r_0,
      O => D2_out
    );
gen_a_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D2_out,
      Q => gen_a_flop_1_i_0,
      R => '0'
    );
gen_a_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D2_out,
      Q => gen_a_flop_2_i_0,
      R => '0'
    );
gen_a_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D2_out,
      Q => gen_a_flop_3_i_0,
      R => '0'
    );
gen_k_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_k_flop_0_i_i_1_n_0,
      Q => gen_k_flop_0_i_0(1),
      R => '0'
    );
gen_k_flop_0_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAA8"
    )
        port map (
      I0 => lfsr_taps_r,
      I1 => \downcounter_r_reg_n_0_[0]\,
      I2 => \downcounter_r_reg_n_0_[2]\,
      I3 => \downcounter_r_reg_n_0_[1]\,
      I4 => \downcounter_r_reg_n_0_[3]\,
      I5 => ver_counter_r_0,
      O => gen_k_flop_0_i_i_1_n_0
    );
gen_k_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => gen_k_flop_0_i_0(0),
      R => '0'
    );
gen_k_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_k_flop_0_i_i_1_n_0,
      Q => gen_k_flop_2_i_0(1),
      R => '0'
    );
gen_k_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => gen_k_flop_2_i_0(0),
      R => '0'
    );
gen_k_flop_4_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_k_flop_0_i_i_1_n_0,
      Q => gen_k_flop_4_i_0(1),
      R => '0'
    );
gen_k_flop_5_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => gen_k_flop_4_i_0(0),
      R => '0'
    );
gen_k_flop_6_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_k_flop_0_i_i_1_n_0,
      Q => gen_k_flop_6_i_0(1),
      R => '0'
    );
gen_k_flop_7_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => gen_k_flop_6_i_0(0),
      R => '0'
    );
gen_r_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_0_i_i_1_n_0,
      Q => gen_r_flop_0_i_0(1),
      R => '0'
    );
gen_r_flop_0_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => lfsr_taps_r,
      I1 => ver_counter_r_0,
      I2 => \downcounter_r_reg_n_0_[3]\,
      I3 => \downcounter_r_reg_n_0_[1]\,
      I4 => \downcounter_r_reg_n_0_[2]\,
      I5 => \downcounter_r_reg_n_0_[0]\,
      O => gen_r_flop_0_i_i_1_n_0
    );
gen_r_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_1_i_i_1_n_0,
      Q => gen_r_flop_0_i_0(0),
      R => '0'
    );
gen_r_flop_1_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D,
      O => gen_r_flop_1_i_i_1_n_0
    );
gen_r_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_0_i_i_1_n_0,
      Q => gen_r_flop_2_i_0(1),
      R => '0'
    );
gen_r_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_1_i_i_1_n_0,
      Q => gen_r_flop_2_i_0(0),
      R => '0'
    );
gen_r_flop_4_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_0_i_i_1_n_0,
      Q => gen_r_flop_4_i_0(1),
      R => '0'
    );
gen_r_flop_5_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_1_i_i_1_n_0,
      Q => gen_r_flop_4_i_0(0),
      R => '0'
    );
gen_r_flop_6_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_0_i_i_1_n_0,
      Q => gen_r_flop_6_i_0(1),
      R => '0'
    );
gen_r_flop_7_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_r_flop_1_i_i_1_n_0,
      Q => gen_r_flop_6_i_0(0),
      R => '0'
    );
gen_v_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D1_out,
      Q => gen_v_flop_0_i_0(1),
      R => '0'
    );
gen_v_flop_0_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen_ver_word_2_r_reg_n_0,
      I1 => gen_ver_i,
      O => D1_out
    );
gen_v_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_v_flop_1_i_i_1_n_0,
      Q => gen_v_flop_0_i_0(0),
      R => '0'
    );
gen_v_flop_1_i_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => ver_counter_r_0,
      I1 => gen_ver_i,
      I2 => gen_ver_word_2_r_reg_n_0,
      O => gen_v_flop_1_i_i_1_n_0
    );
gen_v_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D1_out,
      Q => gen_v_flop_2_i_0(1),
      R => '0'
    );
gen_v_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_v_flop_1_i_i_1_n_0,
      Q => gen_v_flop_2_i_0(0),
      R => '0'
    );
gen_v_flop_4_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D1_out,
      Q => gen_v_flop_4_i_0(1),
      R => '0'
    );
gen_v_flop_5_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_v_flop_1_i_i_1_n_0,
      Q => gen_v_flop_4_i_0(0),
      R => '0'
    );
gen_v_flop_6_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D1_out,
      Q => gen_v_flop_6_i_0(1),
      R => '0'
    );
gen_v_flop_7_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gen_v_flop_1_i_i_1_n_0,
      Q => gen_v_flop_6_i_0(0),
      R => '0'
    );
gen_ver_word_2_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ver_counter_r_0,
      Q => gen_ver_word_2_r_reg_n_0,
      R => '0'
    );
lfsr_last_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => lfsr_last_flop_r,
      R => RESET_SYMGEN
    );
\lfsr_shift_register_r_reg[2]_srl3\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => lfsr_taps_r,
      Q => \lfsr_shift_register_r_reg[2]_srl3_n_0\
    );
\lfsr_shift_register_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \lfsr_shift_register_r_reg[2]_srl3_n_0\,
      Q => D,
      R => '0'
    );
lfsr_taps_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => lfsr_taps_i_i_1_n_0,
      Q => lfsr_taps_r,
      R => RESET_SYMGEN
    );
lfsr_taps_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => lfsr_last_flop_r,
      I1 => D,
      O => lfsr_taps_i_i_1_n_0
    );
prev_cycle_gen_ver_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_ver_i,
      Q => prev_cycle_gen_ver_r,
      R => '0'
    );
ver_counter_0_i: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => user_clk,
      D => D0_out,
      Q => ver_counter_r_1
    );
ver_counter_0_i_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B0"
    )
        port map (
      I0 => gen_ver_word_2_r_reg_n_0,
      I1 => prev_cycle_gen_ver_r,
      I2 => gen_ver_i,
      O => D0_out
    );
ver_counter_1_i: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => user_clk,
      D => ver_counter_r_1,
      Q => ver_counter_r_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE is
  port (
    WARN_CC : out STD_LOGIC;
    DO_CC_I : out STD_LOGIC;
    next_ufc_idle_c : out STD_LOGIC;
    next_ufc_header_c : out STD_LOGIC;
    DO_CC_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    ufc_idle_r_reg : in STD_LOGIC;
    S_AXI_UFC_TX_REQ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE : entity is "efex_aurora_hub2_STANDARD_CC_MODULE";
end efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE is
  signal \^do_cc_i\ : STD_LOGIC;
  signal DO_CC_i_1_n_0 : STD_LOGIC;
  signal DO_CC_i_2_n_0 : STD_LOGIC;
  signal \^warn_cc\ : STD_LOGIC;
  signal WARN_CC_i_1_n_0 : STD_LOGIC;
  signal cc_count_r : STD_LOGIC_VECTOR ( 5 to 5 );
  signal cc_idle_count_done_c : STD_LOGIC;
  signal count_13d_flop_r_reg_r_n_0 : STD_LOGIC;
  signal \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0\ : STD_LOGIC;
  signal \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0\ : STD_LOGIC;
  signal \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0\ : STD_LOGIC;
  signal count_13d_srl_r_reg_gate_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_0_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_1_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_2_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_3_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_4_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_5_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_6_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_7_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_8_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_9_n_0 : STD_LOGIC;
  signal count_13d_srl_r_reg_r_n_0 : STD_LOGIC;
  signal count_16d_flop_r : STD_LOGIC;
  signal count_16d_flop_r_i_1_n_0 : STD_LOGIC;
  signal count_16d_srl_r0 : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \count_16d_srl_r_reg_n_0_[9]\ : STD_LOGIC;
  signal count_24d_flop_r : STD_LOGIC;
  signal count_24d_flop_r_i_1_n_0 : STD_LOGIC;
  signal count_24d_srl_r0 : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[16]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[17]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[18]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[19]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[20]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[21]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[22]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \count_24d_srl_r_reg_n_0_[9]\ : STD_LOGIC;
  signal p_2_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal p_3_out : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_n_0\ : STD_LOGIC;
  signal \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0_n_0\ : STD_LOGIC;
  signal prepare_count_r_reg_gate_n_0 : STD_LOGIC;
  signal reset_r : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8\ : label is "U0/\standard_cc_module_i/count_13d_srl_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8\ : label is "U0/\standard_cc_module_i/count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8 ";
  attribute srl_bus_name of \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r\ : label is "U0/\standard_cc_module_i/prepare_count_r_reg ";
  attribute srl_name of \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r\ : label is "U0/\standard_cc_module_i/prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r ";
begin
  DO_CC_I <= \^do_cc_i\;
  WARN_CC <= \^warn_cc\;
DO_CC_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => cc_count_r(5),
      I1 => p_2_in(0),
      I2 => p_2_in(1),
      I3 => DO_CC_i_2_n_0,
      O => DO_CC_i_1_n_0
    );
DO_CC_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF2"
    )
        port map (
      I0 => reset_r,
      I1 => DO_CC_reg_0,
      I2 => p_2_in(4),
      I3 => p_3_out(5),
      I4 => p_2_in(3),
      I5 => p_2_in(2),
      O => DO_CC_i_2_n_0
    );
DO_CC_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DO_CC_i_1_n_0,
      Q => \^do_cc_i\,
      R => DO_CC_reg_0
    );
WARN_CC_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80FF8080"
    )
        port map (
      I0 => \count_24d_srl_r_reg_n_0_[22]\,
      I1 => \count_16d_srl_r_reg_n_0_[14]\,
      I2 => count_16d_srl_r0,
      I3 => p_3_out(5),
      I4 => \^warn_cc\,
      O => WARN_CC_i_1_n_0
    );
WARN_CC_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => WARN_CC_i_1_n_0,
      Q => \^warn_cc\,
      R => DO_CC_reg_0
    );
\cc_count_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(5),
      Q => p_2_in(4),
      R => DO_CC_reg_0
    );
\cc_count_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_2_in(4),
      Q => p_2_in(3),
      R => DO_CC_reg_0
    );
\cc_count_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_2_in(3),
      Q => p_2_in(2),
      R => DO_CC_reg_0
    );
\cc_count_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_2_in(2),
      Q => p_2_in(1),
      R => DO_CC_reg_0
    );
\cc_count_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_2_in(1),
      Q => p_2_in(0),
      R => DO_CC_reg_0
    );
\cc_count_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_2_in(0),
      Q => cc_count_r(5),
      R => DO_CC_reg_0
    );
count_13d_flop_r_reg_r: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => '1',
      Q => count_13d_flop_r_reg_r_n_0,
      R => DO_CC_reg_0
    );
\count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0\,
      Q => \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0\,
      R => '0'
    );
\count_13d_srl_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_gate_n_0,
      Q => count_16d_srl_r0,
      R => DO_CC_reg_0
    );
\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => user_clk,
      D => \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0\,
      Q => \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_n_0\
    );
\count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => count_16d_srl_r0,
      I1 => reset_r,
      O => \count_13d_srl_r_reg[9]_srl11___standard_cc_module_i_count_13d_srl_r_reg_r_8_i_1_n_0\
    );
count_13d_srl_r_reg_gate: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \count_13d_srl_r_reg[10]_standard_cc_module_i_count_13d_srl_r_reg_r_9_n_0\,
      I1 => count_13d_srl_r_reg_r_9_n_0,
      O => count_13d_srl_r_reg_gate_n_0
    );
count_13d_srl_r_reg_r: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_flop_r_reg_r_n_0,
      Q => count_13d_srl_r_reg_r_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_0: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_n_0,
      Q => count_13d_srl_r_reg_r_0_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_1: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_0_n_0,
      Q => count_13d_srl_r_reg_r_1_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_2: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_1_n_0,
      Q => count_13d_srl_r_reg_r_2_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_3: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_2_n_0,
      Q => count_13d_srl_r_reg_r_3_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_4: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_3_n_0,
      Q => count_13d_srl_r_reg_r_4_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_5: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_4_n_0,
      Q => count_13d_srl_r_reg_r_5_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_6: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_5_n_0,
      Q => count_13d_srl_r_reg_r_6_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_7: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_6_n_0,
      Q => count_13d_srl_r_reg_r_7_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_8: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_7_n_0,
      Q => count_13d_srl_r_reg_r_8_n_0,
      R => DO_CC_reg_0
    );
count_13d_srl_r_reg_r_9: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_13d_srl_r_reg_r_8_n_0,
      Q => count_13d_srl_r_reg_r_9_n_0,
      R => DO_CC_reg_0
    );
count_16d_flop_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBF8"
    )
        port map (
      I0 => \count_16d_srl_r_reg_n_0_[14]\,
      I1 => count_16d_srl_r0,
      I2 => reset_r,
      I3 => count_16d_flop_r,
      O => count_16d_flop_r_i_1_n_0
    );
count_16d_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_16d_flop_r_i_1_n_0,
      Q => count_16d_flop_r,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => count_16d_flop_r,
      Q => \count_16d_srl_r_reg_n_0_[0]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[9]\,
      Q => \count_16d_srl_r_reg_n_0_[10]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[10]\,
      Q => \count_16d_srl_r_reg_n_0_[11]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[11]\,
      Q => \count_16d_srl_r_reg_n_0_[12]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[12]\,
      Q => \count_16d_srl_r_reg_n_0_[13]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[13]\,
      Q => \count_16d_srl_r_reg_n_0_[14]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[0]\,
      Q => \count_16d_srl_r_reg_n_0_[1]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[1]\,
      Q => \count_16d_srl_r_reg_n_0_[2]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[2]\,
      Q => \count_16d_srl_r_reg_n_0_[3]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[3]\,
      Q => \count_16d_srl_r_reg_n_0_[4]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[4]\,
      Q => \count_16d_srl_r_reg_n_0_[5]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[5]\,
      Q => \count_16d_srl_r_reg_n_0_[6]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[6]\,
      Q => \count_16d_srl_r_reg_n_0_[7]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[7]\,
      Q => \count_16d_srl_r_reg_n_0_[8]\,
      R => DO_CC_reg_0
    );
\count_16d_srl_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_16d_srl_r0,
      D => \count_16d_srl_r_reg_n_0_[8]\,
      Q => \count_16d_srl_r_reg_n_0_[9]\,
      R => DO_CC_reg_0
    );
count_24d_flop_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFFF80"
    )
        port map (
      I0 => \count_24d_srl_r_reg_n_0_[22]\,
      I1 => count_16d_srl_r0,
      I2 => \count_16d_srl_r_reg_n_0_[14]\,
      I3 => reset_r,
      I4 => count_24d_flop_r,
      O => count_24d_flop_r_i_1_n_0
    );
count_24d_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => count_24d_flop_r_i_1_n_0,
      Q => count_24d_flop_r,
      R => DO_CC_reg_0
    );
\count_24d_srl_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => count_16d_srl_r0,
      I1 => \count_16d_srl_r_reg_n_0_[14]\,
      O => count_24d_srl_r0
    );
\count_24d_srl_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => count_24d_flop_r,
      Q => \count_24d_srl_r_reg_n_0_[0]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[9]\,
      Q => \count_24d_srl_r_reg_n_0_[10]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[10]\,
      Q => \count_24d_srl_r_reg_n_0_[11]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[11]\,
      Q => \count_24d_srl_r_reg_n_0_[12]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[12]\,
      Q => \count_24d_srl_r_reg_n_0_[13]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[13]\,
      Q => \count_24d_srl_r_reg_n_0_[14]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[14]\,
      Q => \count_24d_srl_r_reg_n_0_[15]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[15]\,
      Q => \count_24d_srl_r_reg_n_0_[16]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[16]\,
      Q => \count_24d_srl_r_reg_n_0_[17]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[17]\,
      Q => \count_24d_srl_r_reg_n_0_[18]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[18]\,
      Q => \count_24d_srl_r_reg_n_0_[19]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[0]\,
      Q => \count_24d_srl_r_reg_n_0_[1]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[19]\,
      Q => \count_24d_srl_r_reg_n_0_[20]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[20]\,
      Q => \count_24d_srl_r_reg_n_0_[21]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[21]\,
      Q => \count_24d_srl_r_reg_n_0_[22]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[1]\,
      Q => \count_24d_srl_r_reg_n_0_[2]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[2]\,
      Q => \count_24d_srl_r_reg_n_0_[3]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[3]\,
      Q => \count_24d_srl_r_reg_n_0_[4]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[4]\,
      Q => \count_24d_srl_r_reg_n_0_[5]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[5]\,
      Q => \count_24d_srl_r_reg_n_0_[6]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[6]\,
      Q => \count_24d_srl_r_reg_n_0_[7]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[7]\,
      Q => \count_24d_srl_r_reg_n_0_[8]\,
      R => DO_CC_reg_0
    );
\count_24d_srl_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => count_24d_srl_r0,
      D => \count_24d_srl_r_reg_n_0_[8]\,
      Q => \count_24d_srl_r_reg_n_0_[9]\,
      R => DO_CC_reg_0
    );
\prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => cc_idle_count_done_c,
      Q => \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_n_0\
    );
\prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => count_16d_srl_r0,
      I1 => \count_16d_srl_r_reg_n_0_[14]\,
      I2 => \count_24d_srl_r_reg_n_0_[22]\,
      O => cc_idle_count_done_c
    );
\prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prepare_count_r_reg[7]_srl2___standard_cc_module_i_count_13d_srl_r_reg_r_n_0\,
      Q => \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0_n_0\,
      R => '0'
    );
\prepare_count_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => prepare_count_r_reg_gate_n_0,
      Q => p_3_out(5),
      R => DO_CC_reg_0
    );
prepare_count_r_reg_gate: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \prepare_count_r_reg[8]_standard_cc_module_i_count_13d_srl_r_reg_r_0_n_0\,
      I1 => count_13d_srl_r_reg_r_0_n_0,
      O => prepare_count_r_reg_gate_n_0
    );
reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DO_CC_reg_0,
      Q => reset_r,
      R => '0'
    );
ufc_header_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => ufc_idle_r_reg,
      I1 => \^do_cc_i\,
      I2 => \^warn_cc\,
      I3 => S_AXI_UFC_TX_REQ,
      O => next_ufc_header_c
    );
ufc_idle_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => ufc_idle_r_reg,
      I1 => \^do_cc_i\,
      I2 => \^warn_cc\,
      I3 => S_AXI_UFC_TX_REQ,
      O => next_ufc_idle_c
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_SYM_GEN is
  port (
    \TX_CHAR_IS_K_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \TX_DATA_Buffer_reg[7]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    tx_pe_data_v_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_k_fsm_r_reg_0 : in STD_LOGIC;
    gen_cc_r_reg_0 : in STD_LOGIC;
    gen_ecp_i : in STD_LOGIC;
    gen_a_r_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_v_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN : entity is "efex_aurora_hub2_SYM_GEN";
end efex_aurora_hub2_efex_aurora_hub2_SYM_GEN;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN is
  signal TX_CHAR_IS_K_Buffer_reg0 : STD_LOGIC;
  signal TX_CHAR_IS_K_Buffer_reg04_out : STD_LOGIC;
  signal \TX_DATA_Buffer[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_3__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_3__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_3__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_4__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_5__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_3__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[9]_i_1__2_n_0\ : STD_LOGIC;
  signal TX_DATA_Buffer_reg0 : STD_LOGIC;
  signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal gen_a_r : STD_LOGIC;
  signal gen_cc_r : STD_LOGIC;
  signal gen_ecp_r : STD_LOGIC;
  signal gen_k_fsm_r : STD_LOGIC;
  signal \gen_k_r_reg_n_0_[1]\ : STD_LOGIC;
  signal gen_pad_r : STD_LOGIC;
  signal \gen_r_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_sp_data_r_reg_n_0_[1]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[9]\ : STD_LOGIC;
  signal tx_pe_data_v_r : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[4]_i_3__0\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[6]_i_2__2\ : label is "soft_lutpair37";
begin
\TX_CHAR_IS_K_Buffer[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCFCCCD"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_cc_r,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => gen_pad_r,
      O => TX_CHAR_IS_K_Buffer_reg0
    );
\TX_CHAR_IS_K_Buffer[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => gen_cc_r,
      I1 => p_2_in,
      I2 => p_0_in1_in,
      I3 => tx_pe_data_v_r,
      O => TX_CHAR_IS_K_Buffer_reg04_out
    );
\TX_CHAR_IS_K_Buffer_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg0,
      Q => \TX_CHAR_IS_K_Buffer_reg[0]_0\(1),
      R => '0'
    );
\TX_CHAR_IS_K_Buffer_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg04_out,
      Q => \TX_CHAR_IS_K_Buffer_reg[0]_0\(0),
      R => '0'
    );
\TX_DATA_Buffer[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002E22"
    )
        port map (
      I0 => gen_cc_r,
      I1 => tx_pe_data_v_r,
      I2 => gen_pad_r,
      I3 => \tx_pe_data_r_reg_n_0_[15]\,
      I4 => gen_ecp_r,
      O => \TX_DATA_Buffer[0]_i_1__2_n_0\
    );
\TX_DATA_Buffer[10]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => data0(2),
      I2 => \TX_DATA_Buffer[12]_i_2__2_n_0\,
      O => \TX_DATA_Buffer[10]_i_1__2_n_0\
    );
\TX_DATA_Buffer[11]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFAEAFAF"
    )
        port map (
      I0 => gen_ecp_r,
      I1 => data0(3),
      I2 => gen_cc_r,
      I3 => gen_k_fsm_r,
      I4 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[11]_i_1__2_n_0\
    );
\TX_DATA_Buffer[12]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => data0(4),
      I2 => \TX_DATA_Buffer[12]_i_2__2_n_0\,
      O => \TX_DATA_Buffer[12]_i_1__2_n_0\
    );
\TX_DATA_Buffer[12]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11111110"
    )
        port map (
      I0 => \TX_DATA_Buffer[15]_i_4__2_n_0\,
      I1 => p_2_in,
      I2 => p_0_in4_in,
      I3 => gen_a_r,
      I4 => p_0_in,
      I5 => \TX_DATA_Buffer[15]_i_3__2_n_0\,
      O => \TX_DATA_Buffer[12]_i_2__2_n_0\
    );
\TX_DATA_Buffer[13]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCF0FCFAFCF0FCFF"
    )
        port map (
      I0 => \TX_DATA_Buffer[13]_i_2__2_n_0\,
      I1 => data0(5),
      I2 => \TX_DATA_Buffer[13]_i_3__0_n_0\,
      I3 => tx_pe_data_v_r,
      I4 => p_0_in1_in,
      I5 => p_0_in,
      O => \TX_DATA_Buffer[13]_i_1__2_n_0\
    );
\TX_DATA_Buffer[13]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      O => \TX_DATA_Buffer[13]_i_2__2_n_0\
    );
\TX_DATA_Buffer[13]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF10"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => tx_pe_data_v_r,
      I2 => p_2_in,
      I3 => gen_k_fsm_r,
      I4 => gen_cc_r,
      I5 => gen_ecp_r,
      O => \TX_DATA_Buffer[13]_i_3__0_n_0\
    );
\TX_DATA_Buffer[14]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEEEFEEE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => gen_ecp_r,
      I2 => data0(6),
      I3 => tx_pe_data_v_r,
      I4 => gen_k_fsm_r,
      I5 => \TX_DATA_Buffer[14]_i_2__2_n_0\,
      O => \TX_DATA_Buffer[14]_i_1__2_n_0\
    );
\TX_DATA_Buffer[14]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000EEEF0000"
    )
        port map (
      I0 => p_2_in,
      I1 => gen_a_r,
      I2 => p_0_in,
      I3 => p_0_in4_in,
      I4 => \TX_DATA_Buffer[14]_i_3__0_n_0\,
      I5 => p_0_in1_in,
      O => \TX_DATA_Buffer[14]_i_2__2_n_0\
    );
\TX_DATA_Buffer[14]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_k_fsm_r,
      O => \TX_DATA_Buffer[14]_i_3__0_n_0\
    );
\TX_DATA_Buffer[15]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \TX_DATA_Buffer[15]_i_3__2_n_0\,
      I1 => \TX_DATA_Buffer[15]_i_4__2_n_0\,
      I2 => p_2_in,
      I3 => p_0_in,
      I4 => gen_a_r,
      I5 => p_0_in4_in,
      O => TX_DATA_Buffer_reg0
    );
\TX_DATA_Buffer[15]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF4FFF0FFF4"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => p_2_in,
      I2 => \TX_DATA_Buffer[15]_i_3__2_n_0\,
      I3 => \TX_DATA_Buffer[15]_i_5__0_n_0\,
      I4 => tx_pe_data_v_r,
      I5 => data0(7),
      O => \TX_DATA_Buffer[15]_i_2__2_n_0\
    );
\TX_DATA_Buffer[15]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => gen_ecp_r,
      I1 => gen_cc_r,
      I2 => gen_k_fsm_r,
      O => \TX_DATA_Buffer[15]_i_3__2_n_0\
    );
\TX_DATA_Buffer[15]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[15]_i_4__2_n_0\
    );
\TX_DATA_Buffer[15]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010001"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in1_in,
      I2 => tx_pe_data_v_r,
      I3 => p_0_in,
      I4 => p_0_in4_in,
      O => \TX_DATA_Buffer[15]_i_5__0_n_0\
    );
\TX_DATA_Buffer[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFCCFFFFCFCCEEEE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => gen_ecp_r,
      I2 => gen_pad_r,
      I3 => \tx_pe_data_r_reg_n_0_[14]\,
      I4 => tx_pe_data_v_r,
      I5 => \gen_sp_data_r_reg_n_0_[1]\,
      O => \TX_DATA_Buffer[1]_i_1__2_n_0\
    );
\TX_DATA_Buffer[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => \tx_pe_data_r_reg_n_0_[13]\,
      I2 => \TX_DATA_Buffer[4]_i_2__2_n_0\,
      O => \TX_DATA_Buffer[2]_i_1__2_n_0\
    );
\TX_DATA_Buffer[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF5FCF5"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \tx_pe_data_r_reg_n_0_[12]\,
      I2 => gen_ecp_r,
      I3 => tx_pe_data_v_r,
      I4 => gen_pad_r,
      O => \TX_DATA_Buffer[3]_i_1__2_n_0\
    );
\TX_DATA_Buffer[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => \tx_pe_data_r_reg_n_0_[11]\,
      I2 => \TX_DATA_Buffer[4]_i_2__2_n_0\,
      O => \TX_DATA_Buffer[4]_i_1__2_n_0\
    );
\TX_DATA_Buffer[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF01010100"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => \gen_sp_data_r_reg_n_0_[1]\,
      I2 => p_3_in,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => \gen_r_r_reg_n_0_[1]\,
      I5 => \TX_DATA_Buffer[4]_i_3__0_n_0\,
      O => \TX_DATA_Buffer[4]_i_2__2_n_0\
    );
\TX_DATA_Buffer[4]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEFC"
    )
        port map (
      I0 => gen_pad_r,
      I1 => gen_ecp_r,
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[4]_i_3__0_n_0\
    );
\TX_DATA_Buffer[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF4FEF4F4"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_cc_r,
      I2 => gen_ecp_r,
      I3 => gen_pad_r,
      I4 => \tx_pe_data_r_reg_n_0_[10]\,
      I5 => \TX_DATA_Buffer[7]_i_4__0_n_0\,
      O => \TX_DATA_Buffer[5]_i_1__2_n_0\
    );
\TX_DATA_Buffer[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0E0E0E0F"
    )
        port map (
      I0 => p_3_in,
      I1 => \gen_sp_data_r_reg_n_0_[1]\,
      I2 => tx_pe_data_v_r,
      I3 => \gen_r_r_reg_n_0_[1]\,
      I4 => \gen_k_r_reg_n_0_[1]\,
      I5 => \TX_DATA_Buffer[6]_i_2__2_n_0\,
      O => \TX_DATA_Buffer[6]_i_1__2_n_0\
    );
\TX_DATA_Buffer[6]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2F2FFF0"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[9]\,
      I1 => gen_pad_r,
      I2 => gen_ecp_r,
      I3 => gen_cc_r,
      I4 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[6]_i_2__2_n_0\
    );
\TX_DATA_Buffer[7]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \TX_DATA_Buffer[7]_i_3__2_n_0\,
      I1 => \gen_k_r_reg_n_0_[1]\,
      I2 => \gen_r_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => \gen_sp_data_r_reg_n_0_[1]\,
      I5 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[7]_i_1__2_n_0\
    );
\TX_DATA_Buffer[7]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCFFEEFFFC"
    )
        port map (
      I0 => gen_pad_r,
      I1 => gen_ecp_r,
      I2 => gen_cc_r,
      I3 => \TX_DATA_Buffer[7]_i_4__0_n_0\,
      I4 => tx_pe_data_v_r,
      I5 => \tx_pe_data_r_reg_n_0_[8]\,
      O => \TX_DATA_Buffer[7]_i_2__2_n_0\
    );
\TX_DATA_Buffer[7]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => gen_cc_r,
      I1 => gen_ecp_r,
      O => \TX_DATA_Buffer[7]_i_3__2_n_0\
    );
\TX_DATA_Buffer[7]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000EF"
    )
        port map (
      I0 => \gen_k_r_reg_n_0_[1]\,
      I1 => p_3_in,
      I2 => \gen_r_r_reg_n_0_[1]\,
      I3 => tx_pe_data_v_r,
      I4 => \gen_sp_data_r_reg_n_0_[1]\,
      O => \TX_DATA_Buffer[7]_i_4__0_n_0\
    );
\TX_DATA_Buffer[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF40"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => tx_pe_data_v_r,
      I2 => data0(0),
      I3 => gen_ecp_r,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[8]_i_1__2_n_0\
    );
\TX_DATA_Buffer[9]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AFAEAAAE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => p_0_in1_in,
      I2 => gen_k_fsm_r,
      I3 => tx_pe_data_v_r,
      I4 => data0(1),
      I5 => gen_ecp_r,
      O => \TX_DATA_Buffer[9]_i_1__2_n_0\
    );
\TX_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[0]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(8),
      R => '0'
    );
\TX_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[10]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(2),
      R => '0'
    );
\TX_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[11]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(3),
      R => '0'
    );
\TX_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[12]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(4),
      R => '0'
    );
\TX_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[13]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(5),
      R => '0'
    );
\TX_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[14]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(6),
      R => '0'
    );
\TX_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[15]_i_2__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(7),
      R => '0'
    );
\TX_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[1]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(9),
      R => '0'
    );
\TX_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[2]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(10),
      R => '0'
    );
\TX_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[3]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(11),
      R => '0'
    );
\TX_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[4]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(12),
      R => '0'
    );
\TX_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[5]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(13),
      R => '0'
    );
\TX_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[6]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(14),
      R => '0'
    );
\TX_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__2_n_0\,
      D => \TX_DATA_Buffer[7]_i_2__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(15),
      R => '0'
    );
\TX_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[8]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(0),
      R => '0'
    );
\TX_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[9]_i_1__2_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(1),
      R => '0'
    );
gen_a_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_a_r_reg_0,
      Q => gen_a_r,
      R => '0'
    );
gen_cc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_cc_r_reg_0,
      Q => gen_cc_r,
      R => '0'
    );
gen_ecp_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_ecp_i,
      Q => gen_ecp_r,
      R => '0'
    );
gen_k_fsm_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_k_fsm_r_reg_0,
      Q => gen_k_fsm_r,
      R => '0'
    );
\gen_k_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(1),
      Q => p_0_in4_in,
      R => '0'
    );
\gen_k_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(0),
      Q => \gen_k_r_reg_n_0_[1]\,
      R => '0'
    );
gen_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => gen_pad_r,
      R => '0'
    );
\gen_r_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(1),
      Q => p_0_in,
      R => '0'
    );
\gen_r_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(0),
      Q => \gen_r_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_sp_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => p_0_in1_in,
      R => '0'
    );
\gen_sp_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \gen_sp_data_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(1),
      Q => p_2_in,
      R => '0'
    );
\gen_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(0),
      Q => p_3_in,
      R => '0'
    );
\tx_pe_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(15),
      Q => data0(7),
      R => '0'
    );
\tx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(5),
      Q => \tx_pe_data_r_reg_n_0_[10]\,
      R => '0'
    );
\tx_pe_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(4),
      Q => \tx_pe_data_r_reg_n_0_[11]\,
      R => '0'
    );
\tx_pe_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(3),
      Q => \tx_pe_data_r_reg_n_0_[12]\,
      R => '0'
    );
\tx_pe_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(2),
      Q => \tx_pe_data_r_reg_n_0_[13]\,
      R => '0'
    );
\tx_pe_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(1),
      Q => \tx_pe_data_r_reg_n_0_[14]\,
      R => '0'
    );
\tx_pe_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(0),
      Q => \tx_pe_data_r_reg_n_0_[15]\,
      R => '0'
    );
\tx_pe_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(14),
      Q => data0(6),
      R => '0'
    );
\tx_pe_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(13),
      Q => data0(5),
      R => '0'
    );
\tx_pe_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(12),
      Q => data0(4),
      R => '0'
    );
\tx_pe_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(11),
      Q => data0(3),
      R => '0'
    );
\tx_pe_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(10),
      Q => data0(2),
      R => '0'
    );
\tx_pe_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(9),
      Q => data0(1),
      R => '0'
    );
\tx_pe_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(8),
      Q => data0(0),
      R => '0'
    );
\tx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(7),
      Q => \tx_pe_data_r_reg_n_0_[8]\,
      R => '0'
    );
\tx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(6),
      Q => \tx_pe_data_r_reg_n_0_[9]\,
      R => '0'
    );
tx_pe_data_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_v_r_reg_0(0),
      Q => tx_pe_data_v_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10 is
  port (
    TXCHARISK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    tx_pe_data_v_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_k_fsm_r_reg_0 : in STD_LOGIC;
    GEN_CC : in STD_LOGIC;
    gen_suf_i : in STD_LOGIC;
    gen_scp_i : in STD_LOGIC;
    GEN_A : in STD_LOGIC;
    \fc_nb_r_reg[0]_0\ : in STD_LOGIC;
    \fc_nb_r_reg[1]_0\ : in STD_LOGIC;
    \fc_nb_r_reg[2]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_v_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10 : entity is "efex_aurora_hub2_SYM_GEN";
end efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10 is
  signal TX_CHAR_IS_K_Buffer_reg0 : STD_LOGIC;
  signal TX_CHAR_IS_K_Buffer_reg04_out : STD_LOGIC;
  signal \TX_DATA_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[10]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[11]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_4_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_5_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_6_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[2]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[2]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[2]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[5]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_4_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_4_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_5_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[8]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[9]_i_1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[9]_i_2_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[9]_i_3_n_0\ : STD_LOGIC;
  signal TX_DATA_Buffer_reg0 : STD_LOGIC;
  signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal fc_nb_r : STD_LOGIC_VECTOR ( 0 to 2 );
  signal gen_a_r : STD_LOGIC;
  signal gen_cc_r : STD_LOGIC;
  signal gen_k_fsm_r : STD_LOGIC;
  signal \gen_k_r_reg_n_0_[1]\ : STD_LOGIC;
  signal gen_pad_r : STD_LOGIC;
  signal \gen_r_r_reg_n_0_[1]\ : STD_LOGIC;
  signal gen_scp_r : STD_LOGIC;
  signal \gen_sp_data_r_reg_n_0_[1]\ : STD_LOGIC;
  signal gen_suf_r : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[9]\ : STD_LOGIC;
  signal tx_pe_data_v_r : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[14]_i_2\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[14]_i_3\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[15]_i_6\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[6]_i_4\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[9]_i_2\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[9]_i_3\ : label is "soft_lutpair16";
begin
\TX_CHAR_IS_K_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCCCCFCCCD"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_cc_r,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => gen_pad_r,
      I5 => gen_suf_r,
      O => TX_CHAR_IS_K_Buffer_reg0
    );
\TX_CHAR_IS_K_Buffer[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => p_2_in,
      I2 => p_0_in1_in,
      I3 => gen_cc_r,
      O => TX_CHAR_IS_K_Buffer_reg04_out
    );
\TX_CHAR_IS_K_Buffer_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg0,
      Q => TXCHARISK(1),
      R => '0'
    );
\TX_CHAR_IS_K_Buffer_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg04_out,
      Q => TXCHARISK(0),
      R => '0'
    );
\TX_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F2F2F0F0FFF0"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[15]\,
      I1 => gen_pad_r,
      I2 => gen_scp_r,
      I3 => gen_cc_r,
      I4 => gen_suf_r,
      I5 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[0]_i_1_n_0\
    );
\TX_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \TX_DATA_Buffer[12]_i_2_n_0\,
      I1 => tx_pe_data_v_r,
      I2 => data0(2),
      O => \TX_DATA_Buffer[10]_i_1_n_0\
    );
\TX_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0FFF0FFFFFFFD"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => data0(3),
      I2 => gen_suf_r,
      I3 => gen_scp_r,
      I4 => gen_k_fsm_r,
      I5 => gen_cc_r,
      O => \TX_DATA_Buffer[11]_i_1_n_0\
    );
\TX_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \TX_DATA_Buffer[12]_i_2_n_0\,
      I1 => tx_pe_data_v_r,
      I2 => data0(4),
      O => \TX_DATA_Buffer[12]_i_1_n_0\
    );
\TX_DATA_Buffer[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEFEEEEEEEE"
    )
        port map (
      I0 => \TX_DATA_Buffer[13]_i_3_n_0\,
      I1 => \TX_DATA_Buffer[4]_i_3_n_0\,
      I2 => tx_pe_data_v_r,
      I3 => p_2_in,
      I4 => p_0_in1_in,
      I5 => \TX_DATA_Buffer[15]_i_3_n_0\,
      O => \TX_DATA_Buffer[12]_i_2_n_0\
    );
\TX_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F0F0F0FFF8"
    )
        port map (
      I0 => data0(5),
      I1 => tx_pe_data_v_r,
      I2 => \TX_DATA_Buffer[13]_i_2_n_0\,
      I3 => \TX_DATA_Buffer[13]_i_3_n_0\,
      I4 => gen_scp_r,
      I5 => gen_suf_r,
      O => \TX_DATA_Buffer[13]_i_1_n_0\
    );
\TX_DATA_Buffer[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111011111111"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => \TX_DATA_Buffer[15]_i_4_n_0\,
      I2 => gen_a_r,
      I3 => p_0_in4_in,
      I4 => p_2_in,
      I5 => p_0_in,
      O => \TX_DATA_Buffer[13]_i_2_n_0\
    );
\TX_DATA_Buffer[13]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => gen_cc_r,
      O => \TX_DATA_Buffer[13]_i_3_n_0\
    );
\TX_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00AB00AA"
    )
        port map (
      I0 => gen_cc_r,
      I1 => gen_k_fsm_r,
      I2 => tx_pe_data_v_r,
      I3 => gen_suf_r,
      I4 => \TX_DATA_Buffer[14]_i_2_n_0\,
      I5 => \TX_DATA_Buffer[14]_i_3_n_0\,
      O => \TX_DATA_Buffer[14]_i_1_n_0\
    );
\TX_DATA_Buffer[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFAB"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_0_in,
      I3 => p_0_in1_in,
      I4 => p_2_in,
      O => \TX_DATA_Buffer[14]_i_2_n_0\
    );
\TX_DATA_Buffer[14]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0020"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_suf_r,
      I2 => data0(6),
      I3 => gen_k_fsm_r,
      I4 => gen_scp_r,
      O => \TX_DATA_Buffer[14]_i_3_n_0\
    );
\TX_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_2_in,
      I1 => p_0_in1_in,
      I2 => \TX_DATA_Buffer[15]_i_3_n_0\,
      I3 => \TX_DATA_Buffer[15]_i_4_n_0\,
      I4 => gen_k_fsm_r,
      I5 => gen_cc_r,
      O => TX_DATA_Buffer_reg0
    );
\TX_DATA_Buffer[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF54"
    )
        port map (
      I0 => gen_scp_r,
      I1 => gen_k_fsm_r,
      I2 => gen_cc_r,
      I3 => \TX_DATA_Buffer[15]_i_5_n_0\,
      O => \TX_DATA_Buffer[15]_i_2_n_0\
    );
\TX_DATA_Buffer[15]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => p_0_in4_in,
      I1 => gen_a_r,
      I2 => p_0_in,
      O => \TX_DATA_Buffer[15]_i_3_n_0\
    );
\TX_DATA_Buffer[15]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => gen_suf_r,
      I1 => tx_pe_data_v_r,
      I2 => gen_scp_r,
      O => \TX_DATA_Buffer[15]_i_4_n_0\
    );
\TX_DATA_Buffer[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF0000BA10"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => p_0_in1_in,
      I2 => \TX_DATA_Buffer[15]_i_6_n_0\,
      I3 => data0(7),
      I4 => gen_scp_r,
      I5 => gen_suf_r,
      O => \TX_DATA_Buffer[15]_i_5_n_0\
    );
\TX_DATA_Buffer[15]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF45"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_0_in,
      I3 => p_2_in,
      O => \TX_DATA_Buffer[15]_i_6_n_0\
    );
\TX_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAFFAAAABAAA"
    )
        port map (
      I0 => \TX_DATA_Buffer[6]_i_4_n_0\,
      I1 => gen_pad_r,
      I2 => \tx_pe_data_r_reg_n_0_[14]\,
      I3 => tx_pe_data_v_r,
      I4 => gen_suf_r,
      I5 => \gen_sp_data_r_reg_n_0_[1]\,
      O => \TX_DATA_Buffer[1]_i_1_n_0\
    );
\TX_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000C0A"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \tx_pe_data_r_reg_n_0_[13]\,
      I2 => gen_scp_r,
      I3 => tx_pe_data_v_r,
      I4 => gen_suf_r,
      I5 => \TX_DATA_Buffer[2]_i_2_n_0\,
      O => \TX_DATA_Buffer[2]_i_1_n_0\
    );
\TX_DATA_Buffer[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008F8F8F88"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \TX_DATA_Buffer[2]_i_3_n_0\,
      I2 => \TX_DATA_Buffer[7]_i_3_n_0\,
      I3 => \gen_r_r_reg_n_0_[1]\,
      I4 => \gen_k_r_reg_n_0_[1]\,
      I5 => gen_scp_r,
      O => \TX_DATA_Buffer[2]_i_2_n_0\
    );
\TX_DATA_Buffer[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_suf_r,
      O => \TX_DATA_Buffer[2]_i_3_n_0\
    );
\TX_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFF0F5F0FCF0F5"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \tx_pe_data_r_reg_n_0_[12]\,
      I2 => gen_scp_r,
      I3 => gen_suf_r,
      I4 => tx_pe_data_v_r,
      I5 => gen_pad_r,
      O => \TX_DATA_Buffer[3]_i_1_n_0\
    );
\TX_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF5FCFCFFF5"
    )
        port map (
      I0 => \TX_DATA_Buffer[4]_i_2_n_0\,
      I1 => gen_pad_r,
      I2 => \TX_DATA_Buffer[4]_i_3_n_0\,
      I3 => gen_cc_r,
      I4 => tx_pe_data_v_r,
      I5 => \tx_pe_data_r_reg_n_0_[11]\,
      O => \TX_DATA_Buffer[4]_i_1_n_0\
    );
\TX_DATA_Buffer[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEEF"
    )
        port map (
      I0 => p_3_in,
      I1 => \gen_sp_data_r_reg_n_0_[1]\,
      I2 => \gen_r_r_reg_n_0_[1]\,
      I3 => \gen_k_r_reg_n_0_[1]\,
      O => \TX_DATA_Buffer[4]_i_2_n_0\
    );
\TX_DATA_Buffer[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => gen_suf_r,
      I1 => gen_scp_r,
      O => \TX_DATA_Buffer[4]_i_3_n_0\
    );
\TX_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBAAAAAAABAAA"
    )
        port map (
      I0 => \TX_DATA_Buffer[7]_i_4_n_0\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \tx_pe_data_r_reg_n_0_[10]\,
      I4 => gen_suf_r,
      I5 => fc_nb_r(2),
      O => \TX_DATA_Buffer[5]_i_1_n_0\
    );
\TX_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFF8F8F8"
    )
        port map (
      I0 => fc_nb_r(1),
      I1 => gen_suf_r,
      I2 => \TX_DATA_Buffer[6]_i_2_n_0\,
      I3 => \tx_pe_data_r_reg_n_0_[9]\,
      I4 => \TX_DATA_Buffer[6]_i_3_n_0\,
      I5 => \TX_DATA_Buffer[6]_i_4_n_0\,
      O => \TX_DATA_Buffer[6]_i_1_n_0\
    );
\TX_DATA_Buffer[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFF1"
    )
        port map (
      I0 => \gen_k_r_reg_n_0_[1]\,
      I1 => \gen_r_r_reg_n_0_[1]\,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => gen_suf_r,
      I5 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[6]_i_2_n_0\
    );
\TX_DATA_Buffer[6]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => gen_suf_r,
      I1 => tx_pe_data_v_r,
      I2 => gen_pad_r,
      O => \TX_DATA_Buffer[6]_i_3_n_0\
    );
\TX_DATA_Buffer[6]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF10"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_suf_r,
      I2 => gen_cc_r,
      I3 => gen_scp_r,
      O => \TX_DATA_Buffer[6]_i_4_n_0\
    );
\TX_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TX_DATA_Buffer[7]_i_3_n_0\,
      I1 => \gen_k_r_reg_n_0_[1]\,
      I2 => \gen_r_r_reg_n_0_[1]\,
      I3 => gen_scp_r,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[7]_i_1_n_0\
    );
\TX_DATA_Buffer[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFFCF0FCFAFCF0"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[8]\,
      I1 => fc_nb_r(0),
      I2 => \TX_DATA_Buffer[7]_i_4_n_0\,
      I3 => gen_suf_r,
      I4 => tx_pe_data_v_r,
      I5 => gen_pad_r,
      O => \TX_DATA_Buffer[7]_i_2_n_0\
    );
\TX_DATA_Buffer[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_sp_data_r_reg_n_0_[1]\,
      I1 => tx_pe_data_v_r,
      I2 => gen_suf_r,
      I3 => p_3_in,
      O => \TX_DATA_Buffer[7]_i_3_n_0\
    );
\TX_DATA_Buffer[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11111101"
    )
        port map (
      I0 => \TX_DATA_Buffer[7]_i_5_n_0\,
      I1 => \gen_sp_data_r_reg_n_0_[1]\,
      I2 => \gen_r_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => \gen_k_r_reg_n_0_[1]\,
      I5 => \TX_DATA_Buffer[6]_i_4_n_0\,
      O => \TX_DATA_Buffer[7]_i_4_n_0\
    );
\TX_DATA_Buffer[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => gen_suf_r,
      O => \TX_DATA_Buffer[7]_i_5_n_0\
    );
\TX_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF00000008"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => data0(0),
      I2 => gen_k_fsm_r,
      I3 => gen_suf_r,
      I4 => gen_scp_r,
      I5 => gen_cc_r,
      O => \TX_DATA_Buffer[8]_i_1_n_0\
    );
\TX_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBAABAAABAAABA"
    )
        port map (
      I0 => \TX_DATA_Buffer[9]_i_2_n_0\,
      I1 => gen_k_fsm_r,
      I2 => p_0_in1_in,
      I3 => \TX_DATA_Buffer[15]_i_4_n_0\,
      I4 => data0(1),
      I5 => \TX_DATA_Buffer[9]_i_3_n_0\,
      O => \TX_DATA_Buffer[9]_i_1_n_0\
    );
\TX_DATA_Buffer[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => gen_cc_r,
      I1 => gen_scp_r,
      I2 => gen_suf_r,
      O => \TX_DATA_Buffer[9]_i_2_n_0\
    );
\TX_DATA_Buffer[9]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => gen_suf_r,
      I1 => tx_pe_data_v_r,
      I2 => gen_scp_r,
      O => \TX_DATA_Buffer[9]_i_3_n_0\
    );
\TX_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[0]_i_1_n_0\,
      Q => TXDATA(8),
      R => '0'
    );
\TX_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[10]_i_1_n_0\,
      Q => TXDATA(2),
      R => '0'
    );
\TX_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[11]_i_1_n_0\,
      Q => TXDATA(3),
      R => '0'
    );
\TX_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[12]_i_1_n_0\,
      Q => TXDATA(4),
      R => '0'
    );
\TX_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[13]_i_1_n_0\,
      Q => TXDATA(5),
      R => '0'
    );
\TX_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[14]_i_1_n_0\,
      Q => TXDATA(6),
      R => '0'
    );
\TX_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[15]_i_2_n_0\,
      Q => TXDATA(7),
      R => '0'
    );
\TX_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[1]_i_1_n_0\,
      Q => TXDATA(9),
      R => '0'
    );
\TX_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[2]_i_1_n_0\,
      Q => TXDATA(10),
      R => '0'
    );
\TX_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[3]_i_1_n_0\,
      Q => TXDATA(11),
      R => '0'
    );
\TX_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[4]_i_1_n_0\,
      Q => TXDATA(12),
      R => '0'
    );
\TX_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[5]_i_1_n_0\,
      Q => TXDATA(13),
      R => '0'
    );
\TX_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[6]_i_1_n_0\,
      Q => TXDATA(14),
      R => '0'
    );
\TX_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1_n_0\,
      D => \TX_DATA_Buffer[7]_i_2_n_0\,
      Q => TXDATA(15),
      R => '0'
    );
\TX_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[8]_i_1_n_0\,
      Q => TXDATA(0),
      R => '0'
    );
\TX_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[9]_i_1_n_0\,
      Q => TXDATA(1),
      R => '0'
    );
\fc_nb_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \fc_nb_r_reg[0]_0\,
      Q => fc_nb_r(0),
      R => '0'
    );
\fc_nb_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \fc_nb_r_reg[1]_0\,
      Q => fc_nb_r(1),
      R => '0'
    );
\fc_nb_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \fc_nb_r_reg[2]_0\,
      Q => fc_nb_r(2),
      R => '0'
    );
gen_a_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => GEN_A,
      Q => gen_a_r,
      R => '0'
    );
gen_cc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => GEN_CC,
      Q => gen_cc_r,
      R => '0'
    );
gen_k_fsm_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_k_fsm_r_reg_0,
      Q => gen_k_fsm_r,
      R => '0'
    );
\gen_k_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(1),
      Q => p_0_in4_in,
      R => '0'
    );
\gen_k_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(0),
      Q => \gen_k_r_reg_n_0_[1]\,
      R => '0'
    );
gen_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => gen_pad_r,
      R => '0'
    );
\gen_r_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(1),
      Q => p_0_in,
      R => '0'
    );
\gen_r_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(0),
      Q => \gen_r_r_reg_n_0_[1]\,
      R => '0'
    );
gen_scp_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_scp_i,
      Q => gen_scp_r,
      R => '0'
    );
\gen_sp_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => p_0_in1_in,
      R => '0'
    );
\gen_sp_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \gen_sp_data_r_reg_n_0_[1]\,
      R => '0'
    );
gen_suf_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_suf_i,
      Q => gen_suf_r,
      R => '0'
    );
\gen_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(1),
      Q => p_2_in,
      R => '0'
    );
\gen_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(0),
      Q => p_3_in,
      R => '0'
    );
\tx_pe_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(15),
      Q => data0(7),
      R => '0'
    );
\tx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(5),
      Q => \tx_pe_data_r_reg_n_0_[10]\,
      R => '0'
    );
\tx_pe_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(4),
      Q => \tx_pe_data_r_reg_n_0_[11]\,
      R => '0'
    );
\tx_pe_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(3),
      Q => \tx_pe_data_r_reg_n_0_[12]\,
      R => '0'
    );
\tx_pe_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(2),
      Q => \tx_pe_data_r_reg_n_0_[13]\,
      R => '0'
    );
\tx_pe_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(1),
      Q => \tx_pe_data_r_reg_n_0_[14]\,
      R => '0'
    );
\tx_pe_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(0),
      Q => \tx_pe_data_r_reg_n_0_[15]\,
      R => '0'
    );
\tx_pe_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(14),
      Q => data0(6),
      R => '0'
    );
\tx_pe_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(13),
      Q => data0(5),
      R => '0'
    );
\tx_pe_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(12),
      Q => data0(4),
      R => '0'
    );
\tx_pe_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(11),
      Q => data0(3),
      R => '0'
    );
\tx_pe_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(10),
      Q => data0(2),
      R => '0'
    );
\tx_pe_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(9),
      Q => data0(1),
      R => '0'
    );
\tx_pe_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(8),
      Q => data0(0),
      R => '0'
    );
\tx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(7),
      Q => \tx_pe_data_r_reg_n_0_[8]\,
      R => '0'
    );
\tx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(6),
      Q => \tx_pe_data_r_reg_n_0_[9]\,
      R => '0'
    );
tx_pe_data_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_v_r_reg_0(0),
      Q => tx_pe_data_v_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4 is
  port (
    \TX_CHAR_IS_K_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \TX_DATA_Buffer_reg[7]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    tx_pe_data_v_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_k_fsm_r_reg_0 : in STD_LOGIC;
    gen_cc_r_reg_0 : in STD_LOGIC;
    gen_a_r_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_v_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4 : entity is "efex_aurora_hub2_SYM_GEN";
end efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4 is
  signal TX_CHAR_IS_K_Buffer_reg0 : STD_LOGIC;
  signal TX_CHAR_IS_K_Buffer_reg04_out : STD_LOGIC;
  signal \TX_DATA_Buffer[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_3__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_3__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_4__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[9]_i_1__1_n_0\ : STD_LOGIC;
  signal TX_DATA_Buffer_reg0 : STD_LOGIC;
  signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal gen_a_r : STD_LOGIC;
  signal gen_cc_r : STD_LOGIC;
  signal gen_k_fsm_r : STD_LOGIC;
  signal \gen_k_r_reg_n_0_[1]\ : STD_LOGIC;
  signal gen_pad_r : STD_LOGIC;
  signal \gen_r_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_sp_data_r_reg_n_0_[1]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[9]\ : STD_LOGIC;
  signal tx_pe_data_v_r : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[0]_i_1__1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[11]_i_1__1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[2]_i_1__1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[3]_i_1__1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[4]_i_1__1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[4]_i_2__1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[5]_i_1__1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[7]_i_2__1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[7]_i_3__1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[8]_i_1__1\ : label is "soft_lutpair32";
begin
\TX_CHAR_IS_K_Buffer[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF000B"
    )
        port map (
      I0 => gen_pad_r,
      I1 => tx_pe_data_v_r,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => gen_cc_r,
      O => TX_CHAR_IS_K_Buffer_reg0
    );
\TX_CHAR_IS_K_Buffer[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => p_2_in,
      I2 => p_0_in1_in,
      I3 => gen_cc_r,
      O => TX_CHAR_IS_K_Buffer_reg04_out
    );
\TX_CHAR_IS_K_Buffer_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg0,
      Q => \TX_CHAR_IS_K_Buffer_reg[0]_0\(1),
      R => '0'
    );
\TX_CHAR_IS_K_Buffer_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg04_out,
      Q => \TX_CHAR_IS_K_Buffer_reg[0]_0\(0),
      R => '0'
    );
\TX_DATA_Buffer[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44F0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[15]\,
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[0]_i_1__1_n_0\
    );
\TX_DATA_Buffer[10]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFE00"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(2),
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      I4 => \TX_DATA_Buffer[12]_i_2__1_n_0\,
      O => \TX_DATA_Buffer[10]_i_1__1_n_0\
    );
\TX_DATA_Buffer[11]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EF"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(3),
      I2 => tx_pe_data_v_r,
      I3 => gen_cc_r,
      O => \TX_DATA_Buffer[11]_i_1__1_n_0\
    );
\TX_DATA_Buffer[12]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFE00"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(4),
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      I4 => \TX_DATA_Buffer[12]_i_2__1_n_0\,
      O => \TX_DATA_Buffer[12]_i_1__1_n_0\
    );
\TX_DATA_Buffer[12]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF0F0F0E2"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => p_0_in,
      I2 => \TX_DATA_Buffer[12]_i_3__0_n_0\,
      I3 => p_0_in4_in,
      I4 => gen_a_r,
      I5 => gen_cc_r,
      O => \TX_DATA_Buffer[12]_i_2__1_n_0\
    );
\TX_DATA_Buffer[12]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => p_2_in,
      I1 => gen_k_fsm_r,
      I2 => p_0_in1_in,
      O => \TX_DATA_Buffer[12]_i_3__0_n_0\
    );
\TX_DATA_Buffer[13]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFE0"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(5),
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[13]_i_2__1_n_0\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[13]_i_1__1_n_0\
    );
\TX_DATA_Buffer[13]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFFEFF"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_2_in,
      I3 => p_0_in,
      I4 => gen_k_fsm_r,
      I5 => p_0_in1_in,
      O => \TX_DATA_Buffer[13]_i_2__1_n_0\
    );
\TX_DATA_Buffer[14]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4F40"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(6),
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[14]_i_2__1_n_0\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[14]_i_1__1_n_0\
    );
\TX_DATA_Buffer[14]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFAFFFB"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_2_in,
      I3 => p_0_in1_in,
      I4 => p_0_in,
      I5 => gen_k_fsm_r,
      O => \TX_DATA_Buffer[14]_i_2__1_n_0\
    );
\TX_DATA_Buffer[15]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \TX_DATA_Buffer[15]_i_3__1_n_0\,
      I2 => tx_pe_data_v_r,
      O => TX_DATA_Buffer_reg0
    );
\TX_DATA_Buffer[15]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFE0"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(7),
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[15]_i_4__1_n_0\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[15]_i_2__1_n_0\
    );
\TX_DATA_Buffer[15]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_0_in4_in,
      I1 => p_2_in,
      I2 => p_0_in1_in,
      I3 => gen_k_fsm_r,
      I4 => p_0_in,
      I5 => gen_a_r,
      O => \TX_DATA_Buffer[15]_i_3__1_n_0\
    );
\TX_DATA_Buffer[15]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFF4F5"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_2_in,
      I3 => p_0_in,
      I4 => gen_k_fsm_r,
      I5 => p_0_in1_in,
      O => \TX_DATA_Buffer[15]_i_4__1_n_0\
    );
\TX_DATA_Buffer[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2F2F2F20"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[14]\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \gen_sp_data_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[1]_i_1__1_n_0\
    );
\TX_DATA_Buffer[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[13]\,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[4]_i_2__1_n_0\,
      O => \TX_DATA_Buffer[2]_i_1__1_n_0\
    );
\TX_DATA_Buffer[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E0EF"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[12]\,
      I2 => tx_pe_data_v_r,
      I3 => gen_cc_r,
      O => \TX_DATA_Buffer[3]_i_1__1_n_0\
    );
\TX_DATA_Buffer[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[11]\,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[4]_i_2__1_n_0\,
      O => \TX_DATA_Buffer[4]_i_1__1_n_0\
    );
\TX_DATA_Buffer[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0302"
    )
        port map (
      I0 => \gen_r_r_reg_n_0_[1]\,
      I1 => p_3_in,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[4]_i_2__1_n_0\
    );
\TX_DATA_Buffer[5]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[10]\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[7]_i_3__1_n_0\,
      O => \TX_DATA_Buffer[5]_i_1__1_n_0\
    );
\TX_DATA_Buffer[6]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[9]\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[6]_i_2__1_n_0\,
      O => \TX_DATA_Buffer[6]_i_1__1_n_0\
    );
\TX_DATA_Buffer[6]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFCFD"
    )
        port map (
      I0 => \gen_r_r_reg_n_0_[1]\,
      I1 => \gen_sp_data_r_reg_n_0_[1]\,
      I2 => p_3_in,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[6]_i_2__1_n_0\
    );
\TX_DATA_Buffer[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \gen_r_r_reg_n_0_[1]\,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => \gen_k_r_reg_n_0_[1]\,
      I5 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[7]_i_1__1_n_0\
    );
\TX_DATA_Buffer[7]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[8]\,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[7]_i_3__1_n_0\,
      O => \TX_DATA_Buffer[7]_i_2__1_n_0\
    );
\TX_DATA_Buffer[7]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF5551"
    )
        port map (
      I0 => \gen_sp_data_r_reg_n_0_[1]\,
      I1 => \gen_r_r_reg_n_0_[1]\,
      I2 => p_3_in,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[7]_i_3__1_n_0\
    );
\TX_DATA_Buffer[8]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF40"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(0),
      I2 => tx_pe_data_v_r,
      I3 => gen_cc_r,
      O => \TX_DATA_Buffer[8]_i_1__1_n_0\
    );
\TX_DATA_Buffer[9]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0B08"
    )
        port map (
      I0 => data0(1),
      I1 => tx_pe_data_v_r,
      I2 => gen_k_fsm_r,
      I3 => p_0_in1_in,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[9]_i_1__1_n_0\
    );
\TX_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[0]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(8),
      R => '0'
    );
\TX_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[10]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(2),
      R => '0'
    );
\TX_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[11]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(3),
      R => '0'
    );
\TX_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[12]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(4),
      R => '0'
    );
\TX_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[13]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(5),
      R => '0'
    );
\TX_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[14]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(6),
      R => '0'
    );
\TX_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[15]_i_2__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(7),
      R => '0'
    );
\TX_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[1]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(9),
      R => '0'
    );
\TX_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[2]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(10),
      R => '0'
    );
\TX_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[3]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(11),
      R => '0'
    );
\TX_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[4]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(12),
      R => '0'
    );
\TX_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[5]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(13),
      R => '0'
    );
\TX_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[6]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(14),
      R => '0'
    );
\TX_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__1_n_0\,
      D => \TX_DATA_Buffer[7]_i_2__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(15),
      R => '0'
    );
\TX_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[8]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(0),
      R => '0'
    );
\TX_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[9]_i_1__1_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(1),
      R => '0'
    );
gen_a_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_a_r_reg_0,
      Q => gen_a_r,
      R => '0'
    );
gen_cc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_cc_r_reg_0,
      Q => gen_cc_r,
      R => '0'
    );
gen_k_fsm_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_k_fsm_r_reg_0,
      Q => gen_k_fsm_r,
      R => '0'
    );
\gen_k_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(1),
      Q => p_0_in4_in,
      R => '0'
    );
\gen_k_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(0),
      Q => \gen_k_r_reg_n_0_[1]\,
      R => '0'
    );
gen_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => gen_pad_r,
      R => '0'
    );
\gen_r_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(1),
      Q => p_0_in,
      R => '0'
    );
\gen_r_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(0),
      Q => \gen_r_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_sp_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => p_0_in1_in,
      R => '0'
    );
\gen_sp_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \gen_sp_data_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(1),
      Q => p_2_in,
      R => '0'
    );
\gen_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(0),
      Q => p_3_in,
      R => '0'
    );
\tx_pe_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(15),
      Q => data0(7),
      R => '0'
    );
\tx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(5),
      Q => \tx_pe_data_r_reg_n_0_[10]\,
      R => '0'
    );
\tx_pe_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(4),
      Q => \tx_pe_data_r_reg_n_0_[11]\,
      R => '0'
    );
\tx_pe_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(3),
      Q => \tx_pe_data_r_reg_n_0_[12]\,
      R => '0'
    );
\tx_pe_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(2),
      Q => \tx_pe_data_r_reg_n_0_[13]\,
      R => '0'
    );
\tx_pe_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(1),
      Q => \tx_pe_data_r_reg_n_0_[14]\,
      R => '0'
    );
\tx_pe_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(0),
      Q => \tx_pe_data_r_reg_n_0_[15]\,
      R => '0'
    );
\tx_pe_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(14),
      Q => data0(6),
      R => '0'
    );
\tx_pe_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(13),
      Q => data0(5),
      R => '0'
    );
\tx_pe_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(12),
      Q => data0(4),
      R => '0'
    );
\tx_pe_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(11),
      Q => data0(3),
      R => '0'
    );
\tx_pe_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(10),
      Q => data0(2),
      R => '0'
    );
\tx_pe_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(9),
      Q => data0(1),
      R => '0'
    );
\tx_pe_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(8),
      Q => data0(0),
      R => '0'
    );
\tx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(7),
      Q => \tx_pe_data_r_reg_n_0_[8]\,
      R => '0'
    );
\tx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(6),
      Q => \tx_pe_data_r_reg_n_0_[9]\,
      R => '0'
    );
tx_pe_data_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_v_r_reg_0(0),
      Q => tx_pe_data_v_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7 is
  port (
    \TX_CHAR_IS_K_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \TX_DATA_Buffer_reg[7]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    tx_pe_data_v_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_k_fsm_r_reg_0 : in STD_LOGIC;
    gen_cc_r_reg_0 : in STD_LOGIC;
    gen_a_r_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_v_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7 : entity is "efex_aurora_hub2_SYM_GEN";
end efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7 is
  signal TX_CHAR_IS_K_Buffer_reg0 : STD_LOGIC;
  signal TX_CHAR_IS_K_Buffer_reg04_out : STD_LOGIC;
  signal \TX_DATA_Buffer[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[12]_i_3_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_3__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[15]_i_4__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \TX_DATA_Buffer[9]_i_1__0_n_0\ : STD_LOGIC;
  signal TX_DATA_Buffer_reg0 : STD_LOGIC;
  signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal gen_a_r : STD_LOGIC;
  signal gen_cc_r : STD_LOGIC;
  signal gen_k_fsm_r : STD_LOGIC;
  signal \gen_k_r_reg_n_0_[1]\ : STD_LOGIC;
  signal gen_pad_r : STD_LOGIC;
  signal \gen_r_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_sp_data_r_reg_n_0_[1]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_pe_data_r_reg_n_0_[9]\ : STD_LOGIC;
  signal tx_pe_data_v_r : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[0]_i_1__0\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[11]_i_1__0\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[2]_i_1__0\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[3]_i_1__0\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[4]_i_1__0\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[4]_i_2__0\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[5]_i_1__0\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[7]_i_2__0\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[7]_i_3__0\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \TX_DATA_Buffer[8]_i_1__0\ : label is "soft_lutpair24";
begin
\TX_CHAR_IS_K_Buffer[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF000B"
    )
        port map (
      I0 => gen_pad_r,
      I1 => tx_pe_data_v_r,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => gen_cc_r,
      O => TX_CHAR_IS_K_Buffer_reg0
    );
\TX_CHAR_IS_K_Buffer[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => tx_pe_data_v_r,
      I1 => p_2_in,
      I2 => p_0_in1_in,
      I3 => gen_cc_r,
      O => TX_CHAR_IS_K_Buffer_reg04_out
    );
\TX_CHAR_IS_K_Buffer_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg0,
      Q => \TX_CHAR_IS_K_Buffer_reg[0]_0\(1),
      R => '0'
    );
\TX_CHAR_IS_K_Buffer_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_CHAR_IS_K_Buffer_reg04_out,
      Q => \TX_CHAR_IS_K_Buffer_reg[0]_0\(0),
      R => '0'
    );
\TX_DATA_Buffer[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44F0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[15]\,
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[0]_i_1__0_n_0\
    );
\TX_DATA_Buffer[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFE00"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(2),
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      I4 => \TX_DATA_Buffer[12]_i_2__0_n_0\,
      O => \TX_DATA_Buffer[10]_i_1__0_n_0\
    );
\TX_DATA_Buffer[11]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EF"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(3),
      I2 => tx_pe_data_v_r,
      I3 => gen_cc_r,
      O => \TX_DATA_Buffer[11]_i_1__0_n_0\
    );
\TX_DATA_Buffer[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFE00"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(4),
      I2 => gen_cc_r,
      I3 => tx_pe_data_v_r,
      I4 => \TX_DATA_Buffer[12]_i_2__0_n_0\,
      O => \TX_DATA_Buffer[12]_i_1__0_n_0\
    );
\TX_DATA_Buffer[12]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF0F0F0E2"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => p_0_in,
      I2 => \TX_DATA_Buffer[12]_i_3_n_0\,
      I3 => p_0_in4_in,
      I4 => gen_a_r,
      I5 => gen_cc_r,
      O => \TX_DATA_Buffer[12]_i_2__0_n_0\
    );
\TX_DATA_Buffer[12]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => p_2_in,
      I1 => gen_k_fsm_r,
      I2 => p_0_in1_in,
      O => \TX_DATA_Buffer[12]_i_3_n_0\
    );
\TX_DATA_Buffer[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFE0"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(5),
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[13]_i_2__0_n_0\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[13]_i_1__0_n_0\
    );
\TX_DATA_Buffer[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFFEFF"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_2_in,
      I3 => p_0_in,
      I4 => gen_k_fsm_r,
      I5 => p_0_in1_in,
      O => \TX_DATA_Buffer[13]_i_2__0_n_0\
    );
\TX_DATA_Buffer[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4F40"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(6),
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[14]_i_2__0_n_0\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[14]_i_1__0_n_0\
    );
\TX_DATA_Buffer[14]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFAFFFB"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_2_in,
      I3 => p_0_in1_in,
      I4 => p_0_in,
      I5 => gen_k_fsm_r,
      O => \TX_DATA_Buffer[14]_i_2__0_n_0\
    );
\TX_DATA_Buffer[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \TX_DATA_Buffer[15]_i_3__0_n_0\,
      I2 => tx_pe_data_v_r,
      O => TX_DATA_Buffer_reg0
    );
\TX_DATA_Buffer[15]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFE0"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(7),
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[15]_i_4__0_n_0\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[15]_i_2__0_n_0\
    );
\TX_DATA_Buffer[15]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_0_in4_in,
      I1 => p_2_in,
      I2 => p_0_in1_in,
      I3 => gen_k_fsm_r,
      I4 => p_0_in,
      I5 => gen_a_r,
      O => \TX_DATA_Buffer[15]_i_3__0_n_0\
    );
\TX_DATA_Buffer[15]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFF4F5"
    )
        port map (
      I0 => gen_a_r,
      I1 => p_0_in4_in,
      I2 => p_2_in,
      I3 => p_0_in,
      I4 => gen_k_fsm_r,
      I5 => p_0_in1_in,
      O => \TX_DATA_Buffer[15]_i_4__0_n_0\
    );
\TX_DATA_Buffer[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2F2F2F20"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[14]\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \gen_sp_data_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[1]_i_1__0_n_0\
    );
\TX_DATA_Buffer[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[13]\,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[4]_i_2__0_n_0\,
      O => \TX_DATA_Buffer[2]_i_1__0_n_0\
    );
\TX_DATA_Buffer[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E0EF"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[12]\,
      I2 => tx_pe_data_v_r,
      I3 => gen_cc_r,
      O => \TX_DATA_Buffer[3]_i_1__0_n_0\
    );
\TX_DATA_Buffer[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[11]\,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[4]_i_2__0_n_0\,
      O => \TX_DATA_Buffer[4]_i_1__0_n_0\
    );
\TX_DATA_Buffer[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0302"
    )
        port map (
      I0 => \gen_r_r_reg_n_0_[1]\,
      I1 => p_3_in,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[4]_i_2__0_n_0\
    );
\TX_DATA_Buffer[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[10]\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[7]_i_3__0_n_0\,
      O => \TX_DATA_Buffer[5]_i_1__0_n_0\
    );
\TX_DATA_Buffer[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \tx_pe_data_r_reg_n_0_[9]\,
      I1 => gen_pad_r,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[6]_i_2__0_n_0\,
      O => \TX_DATA_Buffer[6]_i_1__0_n_0\
    );
\TX_DATA_Buffer[6]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFCFD"
    )
        port map (
      I0 => \gen_r_r_reg_n_0_[1]\,
      I1 => \gen_sp_data_r_reg_n_0_[1]\,
      I2 => p_3_in,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[6]_i_2__0_n_0\
    );
\TX_DATA_Buffer[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => gen_cc_r,
      I1 => \gen_r_r_reg_n_0_[1]\,
      I2 => \gen_sp_data_r_reg_n_0_[1]\,
      I3 => p_3_in,
      I4 => \gen_k_r_reg_n_0_[1]\,
      I5 => tx_pe_data_v_r,
      O => \TX_DATA_Buffer[7]_i_1__0_n_0\
    );
\TX_DATA_Buffer[7]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => gen_pad_r,
      I1 => \tx_pe_data_r_reg_n_0_[8]\,
      I2 => tx_pe_data_v_r,
      I3 => \TX_DATA_Buffer[7]_i_3__0_n_0\,
      O => \TX_DATA_Buffer[7]_i_2__0_n_0\
    );
\TX_DATA_Buffer[7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF5551"
    )
        port map (
      I0 => \gen_sp_data_r_reg_n_0_[1]\,
      I1 => \gen_r_r_reg_n_0_[1]\,
      I2 => p_3_in,
      I3 => \gen_k_r_reg_n_0_[1]\,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[7]_i_3__0_n_0\
    );
\TX_DATA_Buffer[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF40"
    )
        port map (
      I0 => gen_k_fsm_r,
      I1 => data0(0),
      I2 => tx_pe_data_v_r,
      I3 => gen_cc_r,
      O => \TX_DATA_Buffer[8]_i_1__0_n_0\
    );
\TX_DATA_Buffer[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0B08"
    )
        port map (
      I0 => data0(1),
      I1 => tx_pe_data_v_r,
      I2 => gen_k_fsm_r,
      I3 => p_0_in1_in,
      I4 => gen_cc_r,
      O => \TX_DATA_Buffer[9]_i_1__0_n_0\
    );
\TX_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[0]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(8),
      R => '0'
    );
\TX_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[10]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(2),
      R => '0'
    );
\TX_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[11]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(3),
      R => '0'
    );
\TX_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[12]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(4),
      R => '0'
    );
\TX_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[13]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(5),
      R => '0'
    );
\TX_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[14]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(6),
      R => '0'
    );
\TX_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[15]_i_2__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(7),
      R => '0'
    );
\TX_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[1]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(9),
      R => '0'
    );
\TX_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[2]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(10),
      R => '0'
    );
\TX_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[3]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(11),
      R => '0'
    );
\TX_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[4]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(12),
      R => '0'
    );
\TX_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[5]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(13),
      R => '0'
    );
\TX_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[6]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(14),
      R => '0'
    );
\TX_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \TX_DATA_Buffer[7]_i_1__0_n_0\,
      D => \TX_DATA_Buffer[7]_i_2__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(15),
      R => '0'
    );
\TX_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[8]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(0),
      R => '0'
    );
\TX_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_DATA_Buffer_reg0,
      D => \TX_DATA_Buffer[9]_i_1__0_n_0\,
      Q => \TX_DATA_Buffer_reg[7]_0\(1),
      R => '0'
    );
gen_a_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_a_r_reg_0,
      Q => gen_a_r,
      R => '0'
    );
gen_cc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_cc_r_reg_0,
      Q => gen_cc_r,
      R => '0'
    );
gen_k_fsm_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_k_fsm_r_reg_0,
      Q => gen_k_fsm_r,
      R => '0'
    );
\gen_k_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(1),
      Q => p_0_in4_in,
      R => '0'
    );
\gen_k_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_k_r_reg[0]_0\(0),
      Q => \gen_k_r_reg_n_0_[1]\,
      R => '0'
    );
gen_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => gen_pad_r,
      R => '0'
    );
\gen_r_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(1),
      Q => p_0_in,
      R => '0'
    );
\gen_r_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_r_r_reg[0]_0\(0),
      Q => \gen_r_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_sp_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => p_0_in1_in,
      R => '0'
    );
\gen_sp_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \gen_sp_data_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(1),
      Q => p_2_in,
      R => '0'
    );
\gen_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \gen_v_r_reg[0]_0\(0),
      Q => p_3_in,
      R => '0'
    );
\tx_pe_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(15),
      Q => data0(7),
      R => '0'
    );
\tx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(5),
      Q => \tx_pe_data_r_reg_n_0_[10]\,
      R => '0'
    );
\tx_pe_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(4),
      Q => \tx_pe_data_r_reg_n_0_[11]\,
      R => '0'
    );
\tx_pe_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(3),
      Q => \tx_pe_data_r_reg_n_0_[12]\,
      R => '0'
    );
\tx_pe_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(2),
      Q => \tx_pe_data_r_reg_n_0_[13]\,
      R => '0'
    );
\tx_pe_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(1),
      Q => \tx_pe_data_r_reg_n_0_[14]\,
      R => '0'
    );
\tx_pe_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(0),
      Q => \tx_pe_data_r_reg_n_0_[15]\,
      R => '0'
    );
\tx_pe_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(14),
      Q => data0(6),
      R => '0'
    );
\tx_pe_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(13),
      Q => data0(5),
      R => '0'
    );
\tx_pe_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(12),
      Q => data0(4),
      R => '0'
    );
\tx_pe_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(11),
      Q => data0(3),
      R => '0'
    );
\tx_pe_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(10),
      Q => data0(2),
      R => '0'
    );
\tx_pe_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(9),
      Q => data0(1),
      R => '0'
    );
\tx_pe_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(8),
      Q => data0(0),
      R => '0'
    );
\tx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(7),
      Q => \tx_pe_data_r_reg_n_0_[8]\,
      R => '0'
    );
\tx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_pe_data_r_reg[0]_0\(6),
      Q => \tx_pe_data_r_reg_n_0_[9]\,
      R => '0'
    );
tx_pe_data_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_v_r_reg_0(0),
      Q => tx_pe_data_v_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX is
  port (
    CHANNEL_HARD_ERR_Buffer_reg_0 : out STD_LOGIC;
    reset_channel_i : out STD_LOGIC;
    tx_verify_simplex_r_reg : out STD_LOGIC;
    tx_bonded1_simplex_r_reg : out STD_LOGIC;
    tx_aligned_simplex_r_reg : out STD_LOGIC;
    tx_reset_simplex_r_reg : out STD_LOGIC;
    simplex_timer_r0 : out STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    tx_verify_simplex_r : in STD_LOGIC;
    tx_verify_simplex_r_reg_0 : in STD_LOGIC;
    tx_bonded1_simplex_r_reg_0 : in STD_LOGIC;
    tx_verify_simplex_r_reg_1 : in STD_LOGIC;
    RESET_SYMGEN : in STD_LOGIC;
    tx_bonded1_simplex_r : in STD_LOGIC;
    tx_bonded1_simplex_r_reg_1 : in STD_LOGIC;
    tx_bonded1_simplex_r_reg_2 : in STD_LOGIC;
    tx_aligned_simplex_r : in STD_LOGIC;
    tx_aligned_simplex_r_reg_0 : in STD_LOGIC;
    tx_aligned_simplex_r_reg_1 : in STD_LOGIC;
    tx_aligned_simplex_r_reg_2 : in STD_LOGIC;
    tx_reset_simplex_r : in STD_LOGIC;
    tx_reset_simplex_r_reg_0 : in STD_LOGIC;
    simplex_timer_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    simplex_timer_r_reg_0_sp_1 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    TX_LANE_UP : in STD_LOGIC_VECTOR ( 0 to 3 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX : entity is "efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX is
  signal \^channel_hard_err_buffer_reg_0\ : STD_LOGIC;
  signal \RESET_CHANNEL_Buffer0__0\ : STD_LOGIC;
  signal \channel_hard_err_c__0\ : STD_LOGIC;
  signal \hard_err_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \hard_err_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \lane_up_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \lane_up_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \lane_up_r_reg_n_0_[3]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal \^simplex_timer_r0\ : STD_LOGIC;
  signal simplex_timer_r_reg_0_sn_1 : STD_LOGIC;
begin
  CHANNEL_HARD_ERR_Buffer_reg_0 <= \^channel_hard_err_buffer_reg_0\;
  simplex_timer_r0 <= \^simplex_timer_r0\;
  simplex_timer_r_reg_0_sn_1 <= simplex_timer_r_reg_0_sp_1;
CHANNEL_HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \channel_hard_err_c__0\,
      Q => \^channel_hard_err_buffer_reg_0\,
      R => '0'
    );
RESET_CHANNEL_Buffer0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
        port map (
      I0 => \lane_up_r_reg_n_0_[2]\,
      I1 => p_2_in,
      I2 => POWER_DOWN,
      I3 => \lane_up_r_reg_n_0_[3]\,
      I4 => \lane_up_r_reg_n_0_[0]\,
      O => \RESET_CHANNEL_Buffer0__0\
    );
RESET_CHANNEL_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \RESET_CHANNEL_Buffer0__0\,
      Q => reset_channel_i,
      R => '0'
    );
channel_hard_err_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \hard_err_r_reg_n_0_[3]\,
      I1 => \hard_err_r_reg_n_0_[0]\,
      I2 => p_0_in,
      I3 => p_1_in,
      O => \channel_hard_err_c__0\
    );
\hard_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => \hard_err_r_reg_n_0_[0]\,
      R => '0'
    );
\hard_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => p_0_in,
      R => '0'
    );
\hard_err_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => p_1_in,
      R => '0'
    );
\hard_err_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \hard_err_r_reg_n_0_[3]\,
      R => '0'
    );
\lane_up_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => TX_LANE_UP(0),
      Q => \lane_up_r_reg_n_0_[0]\,
      R => '0'
    );
\lane_up_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => TX_LANE_UP(1),
      Q => p_2_in,
      R => '0'
    );
\lane_up_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => TX_LANE_UP(2),
      Q => \lane_up_r_reg_n_0_[2]\,
      R => '0'
    );
\lane_up_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => TX_LANE_UP(3),
      Q => \lane_up_r_reg_n_0_[3]\,
      R => '0'
    );
\simplex_timer_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^channel_hard_err_buffer_reg_0\,
      I1 => simplex_timer_r_reg_0_sn_1,
      O => \^simplex_timer_r0\
    );
tx_aligned_simplex_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AAEA"
    )
        port map (
      I0 => tx_aligned_simplex_r,
      I1 => tx_aligned_simplex_r_reg_0,
      I2 => tx_aligned_simplex_r_reg_1,
      I3 => tx_aligned_simplex_r_reg_2,
      I4 => \^channel_hard_err_buffer_reg_0\,
      I5 => RESET_SYMGEN,
      O => tx_aligned_simplex_r_reg
    );
tx_bonded1_simplex_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000BAAA"
    )
        port map (
      I0 => tx_bonded1_simplex_r,
      I1 => tx_bonded1_simplex_r_reg_1,
      I2 => tx_bonded1_simplex_r_reg_2,
      I3 => tx_bonded1_simplex_r_reg_0,
      I4 => \^channel_hard_err_buffer_reg_0\,
      I5 => RESET_SYMGEN,
      O => tx_bonded1_simplex_r_reg
    );
tx_reset_simplex_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A8AAAAB8"
    )
        port map (
      I0 => tx_reset_simplex_r,
      I1 => tx_reset_simplex_r_reg_0,
      I2 => simplex_timer_r_reg(0),
      I3 => simplex_timer_r_reg(1),
      I4 => simplex_timer_r_reg(2),
      I5 => \^simplex_timer_r0\,
      O => tx_reset_simplex_r_reg
    );
tx_verify_simplex_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000BAAA"
    )
        port map (
      I0 => tx_verify_simplex_r,
      I1 => tx_verify_simplex_r_reg_0,
      I2 => tx_bonded1_simplex_r_reg_0,
      I3 => tx_verify_simplex_r_reg_1,
      I4 => \^channel_hard_err_buffer_reg_0\,
      I5 => RESET_SYMGEN,
      O => tx_verify_simplex_r_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX is
  port (
    TX_CHANNEL_UP : out STD_LOGIC;
    RESET : out STD_LOGIC;
    reset_lanes_flop_1_i_0 : out STD_LOGIC;
    reset_lanes_flop_2_i_0 : out STD_LOGIC;
    reset_lanes_flop_3_i_0 : out STD_LOGIC;
    gen_ver_i : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_1_i_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_2_i_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_3_i_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    tx_channel_up_i_0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    tx_verify_simplex_r : in STD_LOGIC;
    wait_for_lane_up_r0 : in STD_LOGIC;
    hard_err_reset_i : in STD_LOGIC;
    hard_err_reset_i_0 : in STD_LOGIC;
    hard_err_reset_i_1 : in STD_LOGIC;
    hard_err_reset_i_2 : in STD_LOGIC;
    reset_lanes_flop_3_i_2 : in STD_LOGIC;
    tx_reset_simplex_r : in STD_LOGIC;
    tx_bonded1_simplex_r : in STD_LOGIC;
    reset_channel_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX : entity is "efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX is
  signal D : STD_LOGIC;
  signal \^reset\ : STD_LOGIC;
  signal TX_BONDED : STD_LOGIC;
  signal \^tx_channel_up\ : STD_LOGIC;
  signal bonding_watchdog_r0 : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg_n_0_[15]\ : STD_LOGIC;
  signal channel_bond_r : STD_LOGIC;
  signal \free_count_r[10]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[10]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[10]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[10]_i_5_n_0\ : STD_LOGIC;
  signal \free_count_r[14]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[14]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[14]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[14]_i_5_n_0\ : STD_LOGIC;
  signal \free_count_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[6]_i_5_n_0\ : STD_LOGIC;
  signal free_count_r_reg : STD_LOGIC_VECTOR ( 0 to 14 );
  signal \free_count_r_reg[10]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[10]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[14]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[2]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[2]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[2]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[2]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[2]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[6]_i_1_n_7\ : STD_LOGIC;
  signal \^gen_ver_i\ : STD_LOGIC;
  signal next_channel_bond_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_verify_c : STD_LOGIC;
  signal ready_r : STD_LOGIC;
  signal reset_lanes_flop_0_i_i_1_n_0 : STD_LOGIC;
  signal reset_lanes_flop_0_i_i_2_n_0 : STD_LOGIC;
  signal \^reset_lanes_flop_1_i_0\ : STD_LOGIC;
  signal \^reset_lanes_flop_2_i_0\ : STD_LOGIC;
  signal \^reset_lanes_flop_3_i_0\ : STD_LOGIC;
  signal tx_bonded_r : STD_LOGIC;
  signal tx_verify_r : STD_LOGIC;
  signal verify_watchdog_r0 : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg_n_0_[15]\ : STD_LOGIC;
  signal wait_for_lane_up_r : STD_LOGIC;
  signal \NLW_free_count_r_reg[2]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_free_count_r_reg[2]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute srl_bus_name : string;
  attribute srl_bus_name of \bonding_watchdog_r_reg[14]_srl15\ : label is "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/bonding_watchdog_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \bonding_watchdog_r_reg[14]_srl15\ : label is "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/bonding_watchdog_r_reg[14]_srl15 ";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \free_count_r_reg[10]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \free_count_r_reg[14]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \free_count_r_reg[2]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \free_count_r_reg[6]_i_1\ : label is 11;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of reset_lanes_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_0_i : label is "FD";
  attribute BOX_TYPE of reset_lanes_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_1_i : label is "FD";
  attribute BOX_TYPE of reset_lanes_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_2_i : label is "FD";
  attribute BOX_TYPE of reset_lanes_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_3_i : label is "FD";
  attribute BOX_TYPE of tx_channel_up_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of tx_channel_up_i : label is "FD";
  attribute srl_bus_name of \verify_watchdog_r_reg[14]_srl15\ : label is "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/verify_watchdog_r_reg ";
  attribute srl_name of \verify_watchdog_r_reg[14]_srl15\ : label is "U0/\tx_global_logic_simplex_i/tx_channel_init_sm_simplex_i/verify_watchdog_r_reg[14]_srl15 ";
begin
  RESET <= \^reset\;
  TX_CHANNEL_UP <= \^tx_channel_up\;
  gen_ver_i <= \^gen_ver_i\;
  reset_lanes_flop_1_i_0 <= \^reset_lanes_flop_1_i_0\;
  reset_lanes_flop_2_i_0 <= \^reset_lanes_flop_2_i_0\;
  reset_lanes_flop_3_i_0 <= \^reset_lanes_flop_3_i_0\;
\bonding_watchdog_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => bonding_watchdog_r0,
      CLK => user_clk,
      D => channel_bond_r,
      Q => \bonding_watchdog_r_reg[14]_srl15_n_0\
    );
\bonding_watchdog_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020000FFFFFFFF"
    )
        port map (
      I0 => \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\,
      I1 => free_count_r_reg(12),
      I2 => free_count_r_reg(13),
      I3 => free_count_r_reg(14),
      I4 => \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\,
      I5 => channel_bond_r,
      O => bonding_watchdog_r0
    );
\bonding_watchdog_r_reg[14]_srl15_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => free_count_r_reg(3),
      I1 => free_count_r_reg(2),
      I2 => free_count_r_reg(5),
      I3 => free_count_r_reg(4),
      I4 => free_count_r_reg(0),
      I5 => free_count_r_reg(1),
      O => \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\
    );
\bonding_watchdog_r_reg[14]_srl15_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => free_count_r_reg(9),
      I1 => free_count_r_reg(8),
      I2 => free_count_r_reg(11),
      I3 => free_count_r_reg(10),
      I4 => free_count_r_reg(6),
      I5 => free_count_r_reg(7),
      O => \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\
    );
\bonding_watchdog_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => bonding_watchdog_r0,
      D => \bonding_watchdog_r_reg[14]_srl15_n_0\,
      Q => \bonding_watchdog_r_reg_n_0_[15]\,
      R => '0'
    );
channel_bond_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => tx_bonded_r,
      I1 => channel_bond_r,
      I2 => wait_for_lane_up_r,
      O => next_channel_bond_c
    );
channel_bond_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_channel_bond_c,
      Q => channel_bond_r,
      R => wait_for_lane_up_r0
    );
\free_count_r[10]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(7),
      O => \free_count_r[10]_i_2_n_0\
    );
\free_count_r[10]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(8),
      O => \free_count_r[10]_i_3_n_0\
    );
\free_count_r[10]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(9),
      O => \free_count_r[10]_i_4_n_0\
    );
\free_count_r[10]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(10),
      O => \free_count_r[10]_i_5_n_0\
    );
\free_count_r[14]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(11),
      O => \free_count_r[14]_i_2_n_0\
    );
\free_count_r[14]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(12),
      O => \free_count_r[14]_i_3_n_0\
    );
\free_count_r[14]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(13),
      O => \free_count_r[14]_i_4_n_0\
    );
\free_count_r[14]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(14),
      O => \free_count_r[14]_i_5_n_0\
    );
\free_count_r[2]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(0),
      O => \free_count_r[2]_i_2_n_0\
    );
\free_count_r[2]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(1),
      O => \free_count_r[2]_i_3_n_0\
    );
\free_count_r[2]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(2),
      O => \free_count_r[2]_i_4_n_0\
    );
\free_count_r[6]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(3),
      O => \free_count_r[6]_i_2_n_0\
    );
\free_count_r[6]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(4),
      O => \free_count_r[6]_i_3_n_0\
    );
\free_count_r[6]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(5),
      O => \free_count_r[6]_i_4_n_0\
    );
\free_count_r[6]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(6),
      O => \free_count_r[6]_i_5_n_0\
    );
\free_count_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[2]_i_1_n_5\,
      Q => free_count_r_reg(0),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[10]_i_1_n_7\,
      Q => free_count_r_reg(10),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[10]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[14]_i_1_n_0\,
      CO(3) => \free_count_r_reg[10]_i_1_n_0\,
      CO(2) => \free_count_r_reg[10]_i_1_n_1\,
      CO(1) => \free_count_r_reg[10]_i_1_n_2\,
      CO(0) => \free_count_r_reg[10]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[10]_i_1_n_4\,
      O(2) => \free_count_r_reg[10]_i_1_n_5\,
      O(1) => \free_count_r_reg[10]_i_1_n_6\,
      O(0) => \free_count_r_reg[10]_i_1_n_7\,
      S(3) => \free_count_r[10]_i_2_n_0\,
      S(2) => \free_count_r[10]_i_3_n_0\,
      S(1) => \free_count_r[10]_i_4_n_0\,
      S(0) => \free_count_r[10]_i_5_n_0\
    );
\free_count_r_reg[11]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[14]_i_1_n_4\,
      Q => free_count_r_reg(11),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[12]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[14]_i_1_n_5\,
      Q => free_count_r_reg(12),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[13]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[14]_i_1_n_6\,
      Q => free_count_r_reg(13),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[14]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[14]_i_1_n_7\,
      Q => free_count_r_reg(14),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[14]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \free_count_r_reg[14]_i_1_n_0\,
      CO(2) => \free_count_r_reg[14]_i_1_n_1\,
      CO(1) => \free_count_r_reg[14]_i_1_n_2\,
      CO(0) => \free_count_r_reg[14]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[14]_i_1_n_4\,
      O(2) => \free_count_r_reg[14]_i_1_n_5\,
      O(1) => \free_count_r_reg[14]_i_1_n_6\,
      O(0) => \free_count_r_reg[14]_i_1_n_7\,
      S(3) => \free_count_r[14]_i_2_n_0\,
      S(2) => \free_count_r[14]_i_3_n_0\,
      S(1) => \free_count_r[14]_i_4_n_0\,
      S(0) => \free_count_r[14]_i_5_n_0\
    );
\free_count_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[2]_i_1_n_6\,
      Q => free_count_r_reg(1),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[2]_i_1_n_7\,
      Q => free_count_r_reg(2),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[2]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[6]_i_1_n_0\,
      CO(3 downto 2) => \NLW_free_count_r_reg[2]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \free_count_r_reg[2]_i_1_n_2\,
      CO(0) => \free_count_r_reg[2]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0011",
      O(3) => \NLW_free_count_r_reg[2]_i_1_O_UNCONNECTED\(3),
      O(2) => \free_count_r_reg[2]_i_1_n_5\,
      O(1) => \free_count_r_reg[2]_i_1_n_6\,
      O(0) => \free_count_r_reg[2]_i_1_n_7\,
      S(3) => '0',
      S(2) => \free_count_r[2]_i_2_n_0\,
      S(1) => \free_count_r[2]_i_3_n_0\,
      S(0) => \free_count_r[2]_i_4_n_0\
    );
\free_count_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[6]_i_1_n_4\,
      Q => free_count_r_reg(3),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[6]_i_1_n_5\,
      Q => free_count_r_reg(4),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[6]_i_1_n_6\,
      Q => free_count_r_reg(5),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[6]_i_1_n_7\,
      Q => free_count_r_reg(6),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[6]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[10]_i_1_n_0\,
      CO(3) => \free_count_r_reg[6]_i_1_n_0\,
      CO(2) => \free_count_r_reg[6]_i_1_n_1\,
      CO(1) => \free_count_r_reg[6]_i_1_n_2\,
      CO(0) => \free_count_r_reg[6]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[6]_i_1_n_4\,
      O(2) => \free_count_r_reg[6]_i_1_n_5\,
      O(1) => \free_count_r_reg[6]_i_1_n_6\,
      O(0) => \free_count_r_reg[6]_i_1_n_7\,
      S(3) => \free_count_r[6]_i_2_n_0\,
      S(2) => \free_count_r[6]_i_3_n_0\,
      S(1) => \free_count_r[6]_i_4_n_0\,
      S(0) => \free_count_r[6]_i_5_n_0\
    );
\free_count_r_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[10]_i_1_n_4\,
      Q => free_count_r_reg(7),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[10]_i_1_n_5\,
      Q => free_count_r_reg(8),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[9]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[10]_i_1_n_6\,
      Q => free_count_r_reg(9),
      S => wait_for_lane_up_r0
    );
ready_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ready_r,
      Q => D,
      R => '0'
    );
\ready_r_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^gen_ver_i\,
      I1 => tx_verify_r,
      I2 => ready_r,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => ready_r,
      R => wait_for_lane_up_r0
    );
reset_lanes_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => reset_lanes_flop_0_i_i_1_n_0,
      Q => \^reset\,
      R => '0'
    );
reset_lanes_flop_0_i_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => reset_lanes_flop_0_i_i_2_n_0,
      I1 => reset_lanes_flop_3_i_2,
      I2 => tx_reset_simplex_r,
      O => reset_lanes_flop_0_i_i_1_n_0
    );
reset_lanes_flop_0_i_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF222F222F222"
    )
        port map (
      I0 => reset_channel_i,
      I1 => wait_for_lane_up_r,
      I2 => \bonding_watchdog_r_reg_n_0_[15]\,
      I3 => channel_bond_r,
      I4 => \^gen_ver_i\,
      I5 => \verify_watchdog_r_reg_n_0_[15]\,
      O => reset_lanes_flop_0_i_i_2_n_0
    );
reset_lanes_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => reset_lanes_flop_0_i_i_1_n_0,
      Q => \^reset_lanes_flop_1_i_0\,
      R => '0'
    );
reset_lanes_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => reset_lanes_flop_0_i_i_1_n_0,
      Q => \^reset_lanes_flop_2_i_0\,
      R => '0'
    );
reset_lanes_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => reset_lanes_flop_0_i_i_1_n_0,
      Q => \^reset_lanes_flop_3_i_0\,
      R => '0'
    );
rst_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset\,
      I1 => hard_err_reset_i,
      O => SS(0)
    );
\rst_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_lanes_flop_1_i_0\,
      I1 => hard_err_reset_i_0,
      O => reset_lanes_flop_1_i_1(0)
    );
\rst_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_lanes_flop_2_i_0\,
      I1 => hard_err_reset_i_1,
      O => reset_lanes_flop_2_i_1(0)
    );
\rst_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_lanes_flop_3_i_0\,
      I1 => hard_err_reset_i_2,
      O => reset_lanes_flop_3_i_1(0)
    );
tx_bonded_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => tx_verify_simplex_r,
      I1 => tx_bonded1_simplex_r,
      O => TX_BONDED
    );
tx_bonded_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => TX_BONDED,
      Q => tx_bonded_r,
      R => '0'
    );
tx_channel_up_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => \^tx_channel_up\,
      R => '0'
    );
tx_verify_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tx_verify_simplex_r,
      Q => tx_verify_r,
      R => '0'
    );
ufc_header_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^tx_channel_up\,
      O => tx_channel_up_i_0
    );
verify_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => tx_verify_r,
      I1 => \^gen_ver_i\,
      I2 => channel_bond_r,
      I3 => tx_bonded_r,
      O => next_verify_c
    );
verify_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_verify_c,
      Q => \^gen_ver_i\,
      R => wait_for_lane_up_r0
    );
\verify_watchdog_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => verify_watchdog_r0,
      CLK => user_clk,
      D => \^gen_ver_i\,
      Q => \verify_watchdog_r_reg[14]_srl15_n_0\
    );
\verify_watchdog_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020000FFFFFFFF"
    )
        port map (
      I0 => \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\,
      I1 => free_count_r_reg(12),
      I2 => free_count_r_reg(13),
      I3 => free_count_r_reg(14),
      I4 => \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\,
      I5 => \^gen_ver_i\,
      O => verify_watchdog_r0
    );
\verify_watchdog_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => verify_watchdog_r0,
      D => \verify_watchdog_r_reg[14]_srl15_n_0\,
      Q => \verify_watchdog_r_reg_n_0_[15]\,
      R => '0'
    );
wait_for_lane_up_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => wait_for_lane_up_r0,
      Q => wait_for_lane_up_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX is
  port (
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    ENABLE_ERR_DETECT : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX : entity is "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX is
  signal \HARD_ERR_Buffer_i_1__2_n_0\ : STD_LOGIC;
  signal \^hard_err_reset_i\ : STD_LOGIC;
begin
  hard_err_reset_i <= \^hard_err_reset_i\;
\HARD_ERR_Buffer_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^hard_err_reset_i\,
      I1 => ENABLE_ERR_DETECT,
      O => \HARD_ERR_Buffer_i_1__2_n_0\
    );
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \HARD_ERR_Buffer_i_1__2_n_0\,
      Q => D(0),
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r_reg_0,
      Q => \^hard_err_reset_i\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11 is
  port (
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    ENABLE_ERR_DETECT : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11 : entity is "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11 is
  signal HARD_ERR_Buffer_i_1_n_0 : STD_LOGIC;
  signal \^hard_err_reset_i\ : STD_LOGIC;
begin
  hard_err_reset_i <= \^hard_err_reset_i\;
HARD_ERR_Buffer_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^hard_err_reset_i\,
      I1 => ENABLE_ERR_DETECT,
      O => HARD_ERR_Buffer_i_1_n_0
    );
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => HARD_ERR_Buffer_i_1_n_0,
      Q => D(0),
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r_reg_0,
      Q => \^hard_err_reset_i\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5 is
  port (
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    ENABLE_ERR_DETECT : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5 : entity is "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5 is
  signal \HARD_ERR_Buffer_i_1__1_n_0\ : STD_LOGIC;
  signal \^hard_err_reset_i\ : STD_LOGIC;
begin
  hard_err_reset_i <= \^hard_err_reset_i\;
\HARD_ERR_Buffer_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^hard_err_reset_i\,
      I1 => ENABLE_ERR_DETECT,
      O => \HARD_ERR_Buffer_i_1__1_n_0\
    );
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \HARD_ERR_Buffer_i_1__1_n_0\,
      Q => D(0),
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r_reg_0,
      Q => \^hard_err_reset_i\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8 is
  port (
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    ENABLE_ERR_DETECT : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8 : entity is "efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8 is
  signal \HARD_ERR_Buffer_i_1__0_n_0\ : STD_LOGIC;
  signal \^hard_err_reset_i\ : STD_LOGIC;
begin
  hard_err_reset_i <= \^hard_err_reset_i\;
\HARD_ERR_Buffer_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^hard_err_reset_i\,
      I1 => ENABLE_ERR_DETECT,
      O => \HARD_ERR_Buffer_i_1__0_n_0\
    );
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \HARD_ERR_Buffer_i_1__0_n_0\,
      Q => D(0),
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r_reg_0,
      Q => \^hard_err_reset_i\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    odd_word_r_reg_0 : out STD_LOGIC;
    lane_up_flop_i_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_aligned_r : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX : entity is "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX is
  signal D_0 : STD_LOGIC;
  signal align_r : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal gtp_tx_reset_i_3 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal odd_word_r : STD_LOGIC;
  signal odd_word_r0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal std_bool : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \align_r_i_1__2\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \counter1_r[0]_i_1__2\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \counter1_r[1]_i_1__2\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \gen_k_fsm_r_i_1__2\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \gen_sp_data_r[0]_i_1__2\ : label is "soft_lutpair40";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute SOFT_HLUTNM of \ready_r_i_1__2\ : label is "soft_lutpair39";
begin
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => ENABLE_ERR_DETECT,
      R => '0'
    );
\align_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => tx_aligned_r,
      I1 => align_r,
      I2 => std_bool,
      I3 => gtp_tx_reset_i_3,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => align_r,
      R => SS(0)
    );
\counter1_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      I3 => std_bool,
      O => p_0_in(3)
    );
\counter1_r[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[2]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(2)
    );
\counter1_r[2]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      O => p_0_in(1)
    );
\counter1_r[3]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => std_bool,
      R => SS(0)
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[1]\,
      R => SS(0)
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[2]\,
      R => SS(0)
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[3]\,
      S => SS(0)
    );
\gen_k_fsm_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => odd_word_r,
      I1 => D_0,
      O => odd_word_r_reg_0
    );
\gen_sp_data_r[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      I1 => odd_word_r,
      O => D(1)
    );
\gen_sp_data_r[1]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      O => D(0)
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => TX_LANE_UP(0),
      R => lane_up_flop_i_0
    );
\odd_word_r_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => odd_word_r,
      O => odd_word_r0
    );
odd_word_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => odd_word_r0,
      Q => odd_word_r,
      R => '0'
    );
\ready_r_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_aligned_r,
      I1 => align_r,
      I2 => D_0,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D_0,
      R => SS(0)
    );
\rst_r_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gtp_tx_reset_i_3,
      I1 => std_bool,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => gtp_tx_reset_i_3,
      S => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    tx_aligned_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    odd_word_r_reg_0 : out STD_LOGIC;
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_aligned_simplex_r : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12 : entity is "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12 is
  signal D_0 : STD_LOGIC;
  signal align_r : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal gtp_tx_reset_i_0 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal odd_word_r : STD_LOGIC;
  signal odd_word_r0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal std_bool : STD_LOGIC;
  signal \^tx_aligned_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of align_r_i_1 : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \counter1_r[0]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \counter1_r[1]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of gen_k_fsm_r_i_1 : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \gen_sp_data_r[0]_i_1\ : label is "soft_lutpair20";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute SOFT_HLUTNM of ready_r_i_1 : label is "soft_lutpair19";
begin
  tx_aligned_r <= \^tx_aligned_r\;
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => ENABLE_ERR_DETECT,
      R => '0'
    );
align_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => \^tx_aligned_r\,
      I1 => align_r,
      I2 => std_bool,
      I3 => gtp_tx_reset_i_0,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => align_r,
      R => SS(0)
    );
\counter1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      I3 => std_bool,
      O => p_0_in(3)
    );
\counter1_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[2]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(2)
    );
\counter1_r[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      O => p_0_in(1)
    );
\counter1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => std_bool,
      R => SS(0)
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[1]\,
      R => SS(0)
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[2]\,
      R => SS(0)
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[3]\,
      S => SS(0)
    );
gen_k_fsm_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => odd_word_r,
      I1 => D_0,
      O => odd_word_r_reg_0
    );
\gen_sp_data_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      I1 => odd_word_r,
      O => D(1)
    );
\gen_sp_data_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      O => D(0)
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => TX_LANE_UP(0),
      R => RESET
    );
odd_word_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => odd_word_r,
      O => odd_word_r0
    );
odd_word_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => odd_word_r0,
      Q => odd_word_r,
      R => '0'
    );
ready_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^tx_aligned_r\,
      I1 => align_r,
      I2 => D_0,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D_0,
      R => SS(0)
    );
rst_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gtp_tx_reset_i_0,
      I1 => std_bool,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => gtp_tx_reset_i_0,
      S => SS(0)
    );
tx_aligned_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tx_aligned_simplex_r,
      Q => \^tx_aligned_r\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    odd_word_r_reg_0 : out STD_LOGIC;
    lane_up_flop_i_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_aligned_r : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6 : entity is "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6 is
  signal D_0 : STD_LOGIC;
  signal align_r : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal gtp_tx_reset_i_2 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal odd_word_r : STD_LOGIC;
  signal odd_word_r0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal std_bool : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \align_r_i_1__1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \counter1_r[0]_i_1__1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \counter1_r[1]_i_1__1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \gen_k_fsm_r_i_1__1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \gen_sp_data_r[0]_i_1__1\ : label is "soft_lutpair36";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute SOFT_HLUTNM of \ready_r_i_1__1\ : label is "soft_lutpair35";
begin
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => ENABLE_ERR_DETECT,
      R => '0'
    );
\align_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => tx_aligned_r,
      I1 => align_r,
      I2 => std_bool,
      I3 => gtp_tx_reset_i_2,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => align_r,
      R => SS(0)
    );
\counter1_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      I3 => std_bool,
      O => p_0_in(3)
    );
\counter1_r[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[2]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(2)
    );
\counter1_r[2]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      O => p_0_in(1)
    );
\counter1_r[3]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => std_bool,
      R => SS(0)
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[1]\,
      R => SS(0)
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[2]\,
      R => SS(0)
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[3]\,
      S => SS(0)
    );
\gen_k_fsm_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => odd_word_r,
      I1 => D_0,
      O => odd_word_r_reg_0
    );
\gen_sp_data_r[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      I1 => odd_word_r,
      O => D(1)
    );
\gen_sp_data_r[1]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      O => D(0)
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => TX_LANE_UP(0),
      R => lane_up_flop_i_0
    );
\odd_word_r_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => odd_word_r,
      O => odd_word_r0
    );
odd_word_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => odd_word_r0,
      Q => odd_word_r,
      R => '0'
    );
\ready_r_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_aligned_r,
      I1 => align_r,
      I2 => D_0,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D_0,
      R => SS(0)
    );
\rst_r_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gtp_tx_reset_i_2,
      I1 => std_bool,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => gtp_tx_reset_i_2,
      S => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    odd_word_r_reg_0 : out STD_LOGIC;
    lane_up_flop_i_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_aligned_r : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9 : entity is "efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9 is
  signal D_0 : STD_LOGIC;
  signal align_r : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal gtp_tx_reset_i_1 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal odd_word_r : STD_LOGIC;
  signal odd_word_r0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal std_bool : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \align_r_i_1__0\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \counter1_r[0]_i_1__0\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \counter1_r[1]_i_1__0\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \gen_k_fsm_r_i_1__0\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \gen_sp_data_r[0]_i_1__0\ : label is "soft_lutpair28";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute SOFT_HLUTNM of \ready_r_i_1__0\ : label is "soft_lutpair27";
begin
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => ENABLE_ERR_DETECT,
      R => '0'
    );
\align_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => tx_aligned_r,
      I1 => align_r,
      I2 => std_bool,
      I3 => gtp_tx_reset_i_1,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => align_r,
      R => SS(0)
    );
\counter1_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      I3 => std_bool,
      O => p_0_in(3)
    );
\counter1_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[2]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(2)
    );
\counter1_r[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[2]\,
      O => p_0_in(1)
    );
\counter1_r[3]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => std_bool,
      R => SS(0)
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[1]\,
      R => SS(0)
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[2]\,
      R => SS(0)
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[3]\,
      S => SS(0)
    );
\gen_k_fsm_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => odd_word_r,
      I1 => D_0,
      O => odd_word_r_reg_0
    );
\gen_sp_data_r[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      I1 => odd_word_r,
      O => D(1)
    );
\gen_sp_data_r[1]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D_0,
      O => D(0)
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => TX_LANE_UP(0),
      R => lane_up_flop_i_0
    );
\odd_word_r_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => odd_word_r,
      O => odd_word_r0
    );
odd_word_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => odd_word_r0,
      Q => odd_word_r,
      R => '0'
    );
\ready_r_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => tx_aligned_r,
      I1 => align_r,
      I2 => D_0,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D_0,
      R => SS(0)
    );
\rst_r_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gtp_tx_reset_i_1,
      I1 => std_bool,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => gtp_tx_reset_i_1,
      S => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL is
  port (
    GEN_CC : out STD_LOGIC;
    gen_cc_flop_1_i_0 : out STD_LOGIC;
    gen_cc_flop_2_i_0 : out STD_LOGIC;
    gen_cc_flop_3_i_0 : out STD_LOGIC;
    TX_DST_RDY_N_Buffer_reg_0 : out STD_LOGIC;
    ufc_header_r_reg_0 : out STD_LOGIC;
    gen_scp_i : out STD_LOGIC;
    gen_ecp_i : out STD_LOGIC;
    gen_suf_i : out STD_LOGIC;
    \s_axi_ufc_tx_tdata[2]\ : out STD_LOGIC;
    \s_axi_ufc_tx_tdata[1]\ : out STD_LOGIC;
    \s_axi_ufc_tx_tdata[0]\ : out STD_LOGIC;
    S_AXI_TX_TREADY : out STD_LOGIC;
    \ufc_message_count_r_reg[2]_0\ : out STD_LOGIC;
    tx_rem : out STD_LOGIC_VECTOR ( 0 to 0 );
    tx_sof : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    do_cc_r_reg_0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    DO_CC_I : in STD_LOGIC;
    GEN_SUF_Buffer_reg_0 : in STD_LOGIC;
    next_ufc_header_c : in STD_LOGIC;
    next_ufc_idle_c : in STD_LOGIC;
    S_AXI_UFC_TX_MS : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S_AXI_TX_TLAST : in STD_LOGIC;
    tx_sof_n_pipeline_r_reg : in STD_LOGIC;
    S_AXI_TX_TVALID : in STD_LOGIC;
    \tx_rem_pipeline_r_reg[0]\ : in STD_LOGIC;
    \tx_rem_pipeline_r_reg[0]_0\ : in STD_LOGIC;
    S_AXI_TX_TKEEP : in STD_LOGIC_VECTOR ( 7 downto 0 );
    WARN_CC : in STD_LOGIC;
    S_AXI_UFC_TX_REQ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL : entity is "efex_aurora_hub2_TX_LL_CONTROL";
end efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL is
  signal D_0 : STD_LOGIC;
  signal TX_DST_RDY_N_Buffer_i_2_n_0 : STD_LOGIC;
  signal TX_DST_RDY_N_Buffer_i_3_n_0 : STD_LOGIC;
  signal TX_DST_RDY_N_Buffer_i_4_n_0 : STD_LOGIC;
  signal TX_DST_RDY_N_Buffer_i_5_n_0 : STD_LOGIC;
  signal TX_DST_RDY_N_Buffer_i_6_n_0 : STD_LOGIC;
  signal \^tx_dst_rdy_n_buffer_reg_0\ : STD_LOGIC;
  signal data_r : STD_LOGIC;
  signal data_to_eof_1_r : STD_LOGIC;
  signal data_to_eof_2_r : STD_LOGIC;
  signal do_cc_r : STD_LOGIC;
  signal eof_r : STD_LOGIC;
  signal gen_ecp_pipeline_r : STD_LOGIC;
  signal gen_ecp_pipeline_r0 : STD_LOGIC;
  signal gen_scp_pipeline_r : STD_LOGIC;
  signal gen_scp_pipeline_r0 : STD_LOGIC;
  signal gen_suf_pipeline_r : STD_LOGIC;
  signal idle_r : STD_LOGIC;
  signal next_data_c : STD_LOGIC;
  signal next_data_to_eof_1_c : STD_LOGIC;
  signal next_eof_c : STD_LOGIC;
  signal next_idle_c : STD_LOGIC;
  signal next_sof_and_eof_c : STD_LOGIC;
  signal next_sof_to_data_c : STD_LOGIC;
  signal next_sof_to_eof_1_c : STD_LOGIC;
  signal next_ufc_message1_c : STD_LOGIC;
  signal next_ufc_message2_c : STD_LOGIC;
  signal next_ufc_message3_c : STD_LOGIC;
  signal next_ufc_message4_c : STD_LOGIC;
  signal next_ufc_message5_c : STD_LOGIC;
  signal next_ufc_message6_c : STD_LOGIC;
  signal next_ufc_message7_c : STD_LOGIC;
  signal next_ufc_message8_c : STD_LOGIC;
  signal pdu_ok_c : STD_LOGIC;
  signal sof_and_eof_r : STD_LOGIC;
  signal sof_and_eof_r_i_2_n_0 : STD_LOGIC;
  signal sof_to_data_r : STD_LOGIC;
  signal sof_to_eof_1_r : STD_LOGIC;
  signal sof_to_eof_2_r : STD_LOGIC;
  signal suf_delay_1_r : STD_LOGIC;
  signal suf_delay_2_r : STD_LOGIC;
  signal tx_dst_rdy_n_c : STD_LOGIC;
  signal \^tx_rem\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \tx_rem_pipeline_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \tx_rem_pipeline_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \^tx_sof\ : STD_LOGIC;
  signal ufc_header_r_i_4_n_0 : STD_LOGIC;
  signal ufc_header_r_i_5_n_0 : STD_LOGIC;
  signal \^ufc_header_r_reg_0\ : STD_LOGIC;
  signal ufc_idle_r : STD_LOGIC;
  signal ufc_message1_r : STD_LOGIC;
  signal ufc_message2_r : STD_LOGIC;
  signal ufc_message3_r : STD_LOGIC;
  signal ufc_message4_r : STD_LOGIC;
  signal ufc_message5_r : STD_LOGIC;
  signal ufc_message6_r : STD_LOGIC;
  signal ufc_message7_r : STD_LOGIC;
  signal ufc_message8_r : STD_LOGIC;
  signal ufc_message_count_r : STD_LOGIC_VECTOR ( 0 to 2 );
  signal \ufc_message_count_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \ufc_message_count_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \ufc_message_count_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \^ufc_message_count_r_reg[2]_0\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \FC_NB_Buffer_reg[0]_srl4\ : label is "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg ";
  attribute srl_name : string;
  attribute srl_name of \FC_NB_Buffer_reg[0]_srl4\ : label is "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[0]_srl4 ";
  attribute srl_bus_name of \FC_NB_Buffer_reg[1]_srl4\ : label is "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg ";
  attribute srl_name of \FC_NB_Buffer_reg[1]_srl4\ : label is "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[1]_srl4 ";
  attribute srl_bus_name of \FC_NB_Buffer_reg[2]_srl4\ : label is "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg ";
  attribute srl_name of \FC_NB_Buffer_reg[2]_srl4\ : label is "U0/\tx_ll_i/tx_ll_control_i/FC_NB_Buffer_reg[2]_srl4 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of S_AXI_TX_TREADY_INST_0 : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of TX_DST_RDY_N_Buffer_i_5 : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of data_r_i_1 : label is "soft_lutpair42";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of gen_cc_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of gen_cc_flop_0_i : label is "FDR";
  attribute BOX_TYPE of gen_cc_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_cc_flop_1_i : label is "FDR";
  attribute BOX_TYPE of gen_cc_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_cc_flop_2_i : label is "FDR";
  attribute BOX_TYPE of gen_cc_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gen_cc_flop_3_i : label is "FDR";
  attribute SOFT_HLUTNM of gen_ecp_pipeline_r_i_1 : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of halt_c_pipeline_r_inv_i_1 : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of sof_and_eof_r_i_1 : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of sof_to_eof_1_r_i_1 : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of tx_sof_n_pipeline_r_i_1 : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of ufc_header_r_i_5 : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of ufc_message1_r_i_1 : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of ufc_message2_r_i_1 : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of ufc_message3_r_i_1 : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of ufc_message4_r_i_1 : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of ufc_message5_r_i_1 : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of ufc_message6_r_i_1 : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of ufc_message7_r_i_1 : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of ufc_message8_r_i_1 : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \ufc_message_pipeline_r[0]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \ufc_message_pipeline_r[1]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \ufc_message_pipeline_r[2]_i_1\ : label is "soft_lutpair49";
begin
  TX_DST_RDY_N_Buffer_reg_0 <= \^tx_dst_rdy_n_buffer_reg_0\;
  tx_rem(0) <= \^tx_rem\(0);
  tx_sof <= \^tx_sof\;
  ufc_header_r_reg_0 <= \^ufc_header_r_reg_0\;
  \ufc_message_count_r_reg[2]_0\ <= \^ufc_message_count_r_reg[2]_0\;
\FC_NB_Buffer_reg[0]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => S_AXI_UFC_TX_MS(2),
      Q => \s_axi_ufc_tx_tdata[2]\
    );
\FC_NB_Buffer_reg[1]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => S_AXI_UFC_TX_MS(1),
      Q => \s_axi_ufc_tx_tdata[1]\
    );
\FC_NB_Buffer_reg[2]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => S_AXI_UFC_TX_MS(0),
      Q => \s_axi_ufc_tx_tdata[0]\
    );
GEN_ECP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_ecp_pipeline_r,
      Q => gen_ecp_i,
      R => GEN_SUF_Buffer_reg_0
    );
GEN_SCP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_scp_pipeline_r,
      Q => gen_scp_i,
      R => GEN_SUF_Buffer_reg_0
    );
GEN_SUF_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_suf_pipeline_r,
      Q => gen_suf_i,
      R => GEN_SUF_Buffer_reg_0
    );
S_AXI_TX_TREADY_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^tx_dst_rdy_n_buffer_reg_0\,
      O => S_AXI_TX_TREADY
    );
TX_DST_RDY_N_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEFEFFFEFEFEF"
    )
        port map (
      I0 => TX_DST_RDY_N_Buffer_i_2_n_0,
      I1 => DO_CC_I,
      I2 => \^ufc_message_count_r_reg[2]_0\,
      I3 => TX_DST_RDY_N_Buffer_i_3_n_0,
      I4 => \^tx_rem\(0),
      I5 => do_cc_r,
      O => tx_dst_rdy_n_c
    );
TX_DST_RDY_N_Buffer_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF4F4F444"
    )
        port map (
      I0 => WARN_CC,
      I1 => S_AXI_UFC_TX_REQ,
      I2 => do_cc_r,
      I3 => sof_to_eof_1_r,
      I4 => data_to_eof_1_r,
      I5 => TX_DST_RDY_N_Buffer_i_4_n_0,
      O => TX_DST_RDY_N_Buffer_i_2_n_0
    );
TX_DST_RDY_N_Buffer_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000088C800000000"
    )
        port map (
      I0 => TX_DST_RDY_N_Buffer_i_5_n_0,
      I1 => S_AXI_TX_TLAST,
      I2 => TX_DST_RDY_N_Buffer_i_6_n_0,
      I3 => tx_sof_n_pipeline_r_reg,
      I4 => \^tx_dst_rdy_n_buffer_reg_0\,
      I5 => S_AXI_TX_TVALID,
      O => TX_DST_RDY_N_Buffer_i_3_n_0
    );
TX_DST_RDY_N_Buffer_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => data_r,
      I1 => sof_to_data_r,
      I2 => ufc_idle_r,
      I3 => \^ufc_header_r_reg_0\,
      I4 => sof_to_eof_1_r,
      I5 => data_to_eof_1_r,
      O => TX_DST_RDY_N_Buffer_i_4_n_0
    );
TX_DST_RDY_N_Buffer_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => data_r,
      I1 => sof_to_data_r,
      O => TX_DST_RDY_N_Buffer_i_5_n_0
    );
TX_DST_RDY_N_Buffer_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => data_to_eof_2_r,
      I1 => eof_r,
      I2 => sof_to_eof_2_r,
      I3 => sof_and_eof_r,
      I4 => idle_r,
      O => TX_DST_RDY_N_Buffer_i_6_n_0
    );
TX_DST_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_dst_rdy_n_c,
      Q => \^tx_dst_rdy_n_buffer_reg_0\,
      S => GEN_SUF_Buffer_reg_0
    );
data_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFDFDF00"
    )
        port map (
      I0 => S_AXI_TX_TLAST,
      I1 => \^tx_dst_rdy_n_buffer_reg_0\,
      I2 => S_AXI_TX_TVALID,
      I3 => sof_to_data_r,
      I4 => data_r,
      O => next_data_c
    );
data_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_data_c,
      Q => data_r,
      R => GEN_SUF_Buffer_reg_0
    );
data_to_eof_1_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A80000000000"
    )
        port map (
      I0 => \^tx_rem\(0),
      I1 => data_r,
      I2 => sof_to_data_r,
      I3 => S_AXI_TX_TLAST,
      I4 => \^tx_dst_rdy_n_buffer_reg_0\,
      I5 => S_AXI_TX_TVALID,
      O => next_data_to_eof_1_c
    );
data_to_eof_1_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_data_to_eof_1_c,
      Q => data_to_eof_1_r,
      R => GEN_SUF_Buffer_reg_0
    );
data_to_eof_2_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => data_to_eof_1_r,
      Q => data_to_eof_2_r,
      R => GEN_SUF_Buffer_reg_0
    );
do_cc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DO_CC_I,
      Q => do_cc_r,
      R => '0'
    );
eof_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => do_cc_r,
      O => pdu_ok_c
    );
eof_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000540000000000"
    )
        port map (
      I0 => \^tx_rem\(0),
      I1 => data_r,
      I2 => sof_to_data_r,
      I3 => S_AXI_TX_TLAST,
      I4 => \^tx_dst_rdy_n_buffer_reg_0\,
      I5 => S_AXI_TX_TVALID,
      O => next_eof_c
    );
eof_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_eof_c,
      Q => eof_r,
      R => GEN_SUF_Buffer_reg_0
    );
gen_cc_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => GEN_CC,
      R => '0'
    );
gen_cc_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => gen_cc_flop_1_i_0,
      R => '0'
    );
gen_cc_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => gen_cc_flop_2_i_0,
      R => '0'
    );
gen_cc_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_0,
      Q => gen_cc_flop_3_i_0,
      R => '0'
    );
gen_cc_pipeline_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => do_cc_r,
      Q => D_0,
      R => '0'
    );
gen_ecp_pipeline_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFFE"
    )
        port map (
      I0 => data_to_eof_2_r,
      I1 => eof_r,
      I2 => sof_to_eof_2_r,
      I3 => sof_and_eof_r,
      I4 => do_cc_r,
      O => gen_ecp_pipeline_r0
    );
gen_ecp_pipeline_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_ecp_pipeline_r0,
      Q => gen_ecp_pipeline_r,
      R => GEN_SUF_Buffer_reg_0
    );
gen_scp_pipeline_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0E"
    )
        port map (
      I0 => sof_to_data_r,
      I1 => sof_and_eof_r,
      I2 => do_cc_r,
      I3 => sof_to_eof_1_r,
      O => gen_scp_pipeline_r0
    );
gen_scp_pipeline_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gen_scp_pipeline_r0,
      Q => gen_scp_pipeline_r,
      R => GEN_SUF_Buffer_reg_0
    );
gen_suf_pipeline_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => suf_delay_2_r,
      Q => gen_suf_pipeline_r,
      R => GEN_SUF_Buffer_reg_0
    );
halt_c_pipeline_r_inv_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => do_cc_r,
      O => do_cc_r_reg_0
    );
idle_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000000"
    )
        port map (
      I0 => idle_r,
      I1 => sof_and_eof_r,
      I2 => sof_to_eof_2_r,
      I3 => eof_r,
      I4 => data_to_eof_2_r,
      I5 => \^tx_sof\,
      O => next_idle_c
    );
idle_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_idle_c,
      Q => idle_r,
      S => GEN_SUF_Buffer_reg_0
    );
sof_and_eof_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^tx_rem\(0),
      I1 => S_AXI_TX_TLAST,
      I2 => sof_and_eof_r_i_2_n_0,
      O => next_sof_and_eof_c
    );
sof_and_eof_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFFE"
    )
        port map (
      I0 => idle_r,
      I1 => sof_and_eof_r,
      I2 => sof_to_eof_2_r,
      I3 => eof_r,
      I4 => data_to_eof_2_r,
      I5 => \^tx_sof\,
      O => sof_and_eof_r_i_2_n_0
    );
sof_and_eof_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_sof_and_eof_c,
      Q => sof_and_eof_r,
      R => GEN_SUF_Buffer_reg_0
    );
sof_to_data_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sof_and_eof_r_i_2_n_0,
      I1 => S_AXI_TX_TLAST,
      O => next_sof_to_data_c
    );
sof_to_data_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_sof_to_data_c,
      Q => sof_to_data_r,
      R => GEN_SUF_Buffer_reg_0
    );
sof_to_eof_1_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => S_AXI_TX_TLAST,
      I1 => \^tx_rem\(0),
      I2 => sof_and_eof_r_i_2_n_0,
      O => next_sof_to_eof_1_c
    );
sof_to_eof_1_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => next_sof_to_eof_1_c,
      Q => sof_to_eof_1_r,
      R => GEN_SUF_Buffer_reg_0
    );
sof_to_eof_2_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pdu_ok_c,
      D => sof_to_eof_1_r,
      Q => sof_to_eof_2_r,
      R => GEN_SUF_Buffer_reg_0
    );
suf_delay_1_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \^ufc_header_r_reg_0\,
      Q => suf_delay_1_r,
      R => GEN_SUF_Buffer_reg_0
    );
suf_delay_2_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => suf_delay_1_r,
      Q => suf_delay_2_r,
      R => GEN_SUF_Buffer_reg_0
    );
\tx_rem_pipeline_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"107070F1EF8F8F0E"
    )
        port map (
      I0 => \tx_rem_pipeline_r_reg[0]\,
      I1 => \tx_rem_pipeline_r[0]_i_3_n_0\,
      I2 => \tx_rem_pipeline_r_reg[0]_0\,
      I3 => S_AXI_TX_TKEEP(1),
      I4 => S_AXI_TX_TKEEP(2),
      I5 => \tx_rem_pipeline_r[0]_i_5_n_0\,
      O => \^tx_rem\(0)
    );
\tx_rem_pipeline_r[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => S_AXI_TX_TKEEP(0),
      I1 => S_AXI_TX_TKEEP(6),
      I2 => S_AXI_TX_TKEEP(7),
      O => \tx_rem_pipeline_r[0]_i_3_n_0\
    );
\tx_rem_pipeline_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001700171717"
    )
        port map (
      I0 => S_AXI_TX_TKEEP(3),
      I1 => S_AXI_TX_TKEEP(4),
      I2 => S_AXI_TX_TKEEP(5),
      I3 => S_AXI_TX_TKEEP(0),
      I4 => S_AXI_TX_TKEEP(7),
      I5 => S_AXI_TX_TKEEP(6),
      O => \tx_rem_pipeline_r[0]_i_5_n_0\
    );
tx_sof_n_pipeline_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => S_AXI_TX_TVALID,
      I1 => \^tx_dst_rdy_n_buffer_reg_0\,
      I2 => tx_sof_n_pipeline_r_reg,
      O => \^tx_sof\
    );
ufc_header_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAEAAAAAA"
    )
        port map (
      I0 => ufc_header_r_i_4_n_0,
      I1 => ufc_message_count_r(2),
      I2 => ufc_message_count_r(0),
      I3 => ufc_message4_r,
      I4 => ufc_message_count_r(1),
      I5 => ufc_header_r_i_5_n_0,
      O => \^ufc_message_count_r_reg[2]_0\
    );
ufc_header_r_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => ufc_message6_r,
      I1 => ufc_message2_r,
      I2 => ufc_message5_r,
      I3 => ufc_message1_r,
      I4 => ufc_idle_r,
      O => ufc_header_r_i_4_n_0
    );
ufc_header_r_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => ufc_message8_r,
      I1 => ufc_message3_r,
      I2 => ufc_message7_r,
      O => ufc_header_r_i_5_n_0
    );
ufc_header_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_header_c,
      Q => \^ufc_header_r_reg_0\,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_idle_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_idle_c,
      Q => ufc_idle_r,
      S => GEN_SUF_Buffer_reg_0
    );
ufc_message1_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => ufc_message_count_r(1),
      I1 => ufc_message_count_r(2),
      I2 => ufc_message_count_r(0),
      I3 => \^ufc_header_r_reg_0\,
      O => next_ufc_message1_c
    );
ufc_message1_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message1_c,
      Q => ufc_message1_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message2_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => ufc_message_count_r(1),
      I1 => \^ufc_header_r_reg_0\,
      I2 => ufc_message_count_r(2),
      I3 => ufc_message_count_r(0),
      O => next_ufc_message2_c
    );
ufc_message2_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message2_c,
      Q => ufc_message2_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message3_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => ufc_message_count_r(2),
      I1 => ufc_message_count_r(1),
      I2 => ufc_message_count_r(0),
      I3 => \^ufc_header_r_reg_0\,
      O => next_ufc_message3_c
    );
ufc_message3_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message3_c,
      Q => ufc_message3_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message4_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F080"
    )
        port map (
      I0 => ufc_message_count_r(2),
      I1 => ufc_message_count_r(1),
      I2 => \^ufc_header_r_reg_0\,
      I3 => ufc_message_count_r(0),
      O => next_ufc_message4_c
    );
ufc_message4_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message4_c,
      Q => ufc_message4_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message5_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => ufc_message_count_r(1),
      I1 => ufc_message_count_r(2),
      I2 => ufc_message4_r,
      I3 => ufc_message_count_r(0),
      O => next_ufc_message5_c
    );
ufc_message5_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message5_c,
      Q => ufc_message5_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message6_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => ufc_message_count_r(1),
      I1 => ufc_message_count_r(2),
      I2 => ufc_message4_r,
      I3 => ufc_message_count_r(0),
      O => next_ufc_message6_c
    );
ufc_message6_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message6_c,
      Q => ufc_message6_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message7_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => ufc_message_count_r(2),
      I1 => ufc_message_count_r(0),
      I2 => ufc_message4_r,
      I3 => ufc_message_count_r(1),
      O => next_ufc_message7_c
    );
ufc_message7_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message7_c,
      Q => ufc_message7_r,
      R => GEN_SUF_Buffer_reg_0
    );
ufc_message8_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => ufc_message_count_r(0),
      I1 => ufc_message_count_r(2),
      I2 => ufc_message4_r,
      I3 => ufc_message_count_r(1),
      O => next_ufc_message8_c
    );
ufc_message8_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ufc_message8_c,
      Q => ufc_message8_r,
      R => GEN_SUF_Buffer_reg_0
    );
\ufc_message_count_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBFFFF00080000"
    )
        port map (
      I0 => S_AXI_UFC_TX_MS(2),
      I1 => \^ufc_message_count_r_reg[2]_0\,
      I2 => DO_CC_I,
      I3 => WARN_CC,
      I4 => S_AXI_UFC_TX_REQ,
      I5 => ufc_message_count_r(0),
      O => \ufc_message_count_r[0]_i_1_n_0\
    );
\ufc_message_count_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBFFFF00080000"
    )
        port map (
      I0 => S_AXI_UFC_TX_MS(1),
      I1 => \^ufc_message_count_r_reg[2]_0\,
      I2 => DO_CC_I,
      I3 => WARN_CC,
      I4 => S_AXI_UFC_TX_REQ,
      I5 => ufc_message_count_r(1),
      O => \ufc_message_count_r[1]_i_1_n_0\
    );
\ufc_message_count_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBFFFF00080000"
    )
        port map (
      I0 => S_AXI_UFC_TX_MS(0),
      I1 => \^ufc_message_count_r_reg[2]_0\,
      I2 => DO_CC_I,
      I3 => WARN_CC,
      I4 => S_AXI_UFC_TX_REQ,
      I5 => ufc_message_count_r(2),
      O => \ufc_message_count_r[2]_i_1_n_0\
    );
\ufc_message_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_count_r[0]_i_1_n_0\,
      Q => ufc_message_count_r(0),
      R => '0'
    );
\ufc_message_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_count_r[1]_i_1_n_0\,
      Q => ufc_message_count_r(1),
      R => '0'
    );
\ufc_message_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_count_r[2]_i_1_n_0\,
      Q => ufc_message_count_r(2),
      R => '0'
    );
\ufc_message_pipeline_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ufc_idle_r,
      I1 => \^ufc_header_r_reg_0\,
      O => D(3)
    );
\ufc_message_pipeline_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ufc_message5_r,
      I1 => ufc_message1_r,
      I2 => ufc_idle_r,
      I3 => \^ufc_header_r_reg_0\,
      O => D(2)
    );
\ufc_message_pipeline_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => ufc_message7_r,
      I1 => ufc_message3_r,
      I2 => ufc_message8_r,
      I3 => ufc_message4_r,
      O => D(1)
    );
\ufc_message_pipeline_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ufc_message8_r,
      I1 => ufc_message4_r,
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH is
  port (
    \s_axi_tx_tkeep[4]\ : out STD_LOGIC;
    \s_axi_tx_tkeep[5]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \GEN_PAD_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \TX_PE_DATA_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    halt_c_pipeline_r_reg_inv_0 : in STD_LOGIC;
    tx_sof : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    tx_dst_rdy : in STD_LOGIC;
    halt_c_pipeline_r_reg_inv_1 : in STD_LOGIC;
    S_AXI_TX_TVALID : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_AXI_TX_TKEEP : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S_AXI_TX_TLAST : in STD_LOGIC;
    \ufc_message_pipeline_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S_AXI_TX_TDATA : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH : entity is "efex_aurora_hub2_TX_LL_DATAPATH";
end efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH is
  signal TX_PE_DATA_V_Buffer2 : STD_LOGIC;
  signal \gen_pad_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pad_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pad_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pad_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_pad_r_reg_n_0_[3]\ : STD_LOGIC;
  signal in_frame_r_i_1_n_0 : STD_LOGIC;
  signal in_frame_r_reg_n_0 : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_31_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal p_4_in : STD_LOGIC;
  signal p_4_in10_in : STD_LOGIC;
  signal p_5_in : STD_LOGIC;
  signal p_6_in : STD_LOGIC;
  signal p_7_in : STD_LOGIC;
  signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^s_axi_tx_tkeep[4]\ : STD_LOGIC;
  signal \^s_axi_tx_tkeep[5]\ : STD_LOGIC;
  signal storage_pad_r : STD_LOGIC;
  signal storage_pad_r_i_1_n_0 : STD_LOGIC;
  signal storage_r : STD_LOGIC_VECTOR ( 0 to 15 );
  signal storage_ufc_v_r : STD_LOGIC;
  signal storage_v_r : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[16]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[17]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[18]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[19]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[20]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[21]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[22]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[23]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[24]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[25]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[26]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[27]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[28]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[29]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[30]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[31]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[32]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[33]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[34]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[35]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[36]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[37]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[38]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[39]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[40]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[41]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[42]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[43]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[44]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[45]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[46]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[47]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[48]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[49]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[50]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[51]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[52]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[53]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[54]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[55]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[56]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[57]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[58]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[59]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[60]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[61]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[62]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[63]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_d_pipeline_r_reg_n_0_[9]\ : STD_LOGIC;
  signal tx_dst_rdy_n_pipeline_r : STD_LOGIC;
  signal tx_eof : STD_LOGIC;
  signal tx_eof_n_pipeline_r : STD_LOGIC;
  signal tx_pe_data_r : STD_LOGIC_VECTOR ( 0 to 63 );
  signal \tx_pe_data_v_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \tx_pe_data_v_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_pe_data_v_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_pe_ufc_v_r_reg_n_0_[3]\ : STD_LOGIC;
  signal tx_rem : STD_LOGIC_VECTOR ( 1 to 1 );
  signal tx_rem_pipeline_r : STD_LOGIC_VECTOR ( 0 to 2 );
  signal \tx_rem_pipeline_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \tx_rem_pipeline_r[2]_i_1_n_0\ : STD_LOGIC;
  signal tx_sof_n_pipeline_r : STD_LOGIC;
  signal tx_src_rdy : STD_LOGIC;
  signal tx_src_rdy_n_pipeline_r : STD_LOGIC;
  signal \ufc_message_pipeline_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \ufc_message_pipeline_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \ufc_message_pipeline_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \ufc_message_pipeline_r_reg_n_0_[3]\ : STD_LOGIC;
  signal valid_c : STD_LOGIC_VECTOR ( 1 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \GEN_PAD_Buffer[0]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \GEN_PAD_Buffer[1]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \GEN_PAD_Buffer[2]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \GEN_PAD_Buffer[3]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \TX_PE_DATA_V_Buffer[0]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \TX_PE_DATA_V_Buffer[1]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \TX_PE_DATA_V_Buffer[2]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \TX_PE_DATA_V_Buffer[3]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \gen_pad_r[1]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \gen_pad_r[2]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \gen_pad_r[3]_i_1\ : label is "soft_lutpair52";
  attribute inverted : string;
  attribute inverted of halt_c_pipeline_r_reg_inv : label is "yes";
  attribute SOFT_HLUTNM of storage_pad_r_i_1 : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of storage_v_r_i_1 : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \tx_pe_data_v_r[2]_i_2\ : label is "soft_lutpair58";
begin
  \s_axi_tx_tkeep[4]\ <= \^s_axi_tx_tkeep[4]\;
  \s_axi_tx_tkeep[5]\ <= \^s_axi_tx_tkeep[5]\;
\GEN_PAD_Buffer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \gen_pad_r_reg_n_0_[0]\,
      I1 => TX_PE_DATA_V_Buffer2,
      I2 => p_7_in,
      O => p_8_out(3)
    );
\GEN_PAD_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_6_in,
      I1 => TX_PE_DATA_V_Buffer2,
      I2 => p_5_in,
      O => p_8_out(2)
    );
\GEN_PAD_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_4_in,
      I1 => TX_PE_DATA_V_Buffer2,
      I2 => p_3_in,
      O => p_8_out(1)
    );
\GEN_PAD_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \gen_pad_r_reg_n_0_[3]\,
      I1 => TX_PE_DATA_V_Buffer2,
      I2 => \tx_pe_ufc_v_r_reg_n_0_[3]\,
      O => p_8_out(0)
    );
\GEN_PAD_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_8_out(3),
      Q => \GEN_PAD_Buffer_reg[0]_0\(3),
      R => '0'
    );
\GEN_PAD_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_8_out(2),
      Q => \GEN_PAD_Buffer_reg[0]_0\(2),
      R => '0'
    );
\GEN_PAD_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_8_out(1),
      Q => \GEN_PAD_Buffer_reg[0]_0\(1),
      R => '0'
    );
\GEN_PAD_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_8_out(0),
      Q => \GEN_PAD_Buffer_reg[0]_0\(0),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(0),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(63),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(10),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(53),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(11),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(52),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(12),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(51),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(13),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(50),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(14),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(49),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(15),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(48),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(16),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(47),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(17),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(46),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(18),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(45),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(19),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(44),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(1),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(62),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(20),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(43),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(21),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(42),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(22),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(41),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(23),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(40),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(24),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(39),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(25),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(38),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(26),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(37),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(27),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(36),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(28),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(35),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(29),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(34),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(2),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(61),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(30),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(33),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(31),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(32),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(32),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(31),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(33),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(30),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(34),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(29),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(35),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(28),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(36),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(27),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(37),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(26),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(38),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(25),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(39),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(24),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(3),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(60),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(40),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(23),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(41),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(22),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(42),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(21),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(43),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(20),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(44),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(19),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(45),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(18),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(46),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(17),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(47),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(16),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(48),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(15),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(49),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(14),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(4),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(59),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(50),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(13),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(51),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(12),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(52),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(11),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(53),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(10),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(54),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(9),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(55),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(8),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(56),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(7),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(57),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(6),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(58),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(5),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(59),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(4),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(5),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(58),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(60),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(3),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(61),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(2),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(62),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(1),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(63),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(0),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(6),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(57),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(7),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(56),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(8),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(55),
      R => '0'
    );
\TX_PE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_pe_data_r(9),
      Q => \TX_PE_DATA_Buffer_reg[0]_0\(54),
      R => '0'
    );
\TX_PE_DATA_V_Buffer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => TX_PE_DATA_V_Buffer2,
      I1 => \tx_pe_data_v_r_reg_n_0_[0]\,
      I2 => p_7_in,
      O => p_7_out(3)
    );
\TX_PE_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => TX_PE_DATA_V_Buffer2,
      I1 => p_4_in10_in,
      I2 => p_5_in,
      O => p_7_out(2)
    );
\TX_PE_DATA_V_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => TX_PE_DATA_V_Buffer2,
      I1 => p_2_in,
      I2 => p_3_in,
      O => p_7_out(1)
    );
\TX_PE_DATA_V_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => TX_PE_DATA_V_Buffer2,
      I1 => \tx_pe_data_v_r_reg_n_0_[3]\,
      I2 => \tx_pe_ufc_v_r_reg_n_0_[3]\,
      O => p_7_out(0)
    );
\TX_PE_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_7_out(3),
      Q => Q(3),
      R => '0'
    );
\TX_PE_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_7_out(2),
      Q => Q(2),
      R => '0'
    );
\TX_PE_DATA_V_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_7_out(1),
      Q => Q(1),
      R => '0'
    );
\TX_PE_DATA_V_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_7_out(0),
      Q => Q(0),
      R => '0'
    );
\gen_pad_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => tx_rem_pipeline_r(0),
      I1 => tx_rem_pipeline_r(2),
      I2 => tx_rem_pipeline_r(1),
      I3 => tx_eof_n_pipeline_r,
      O => \gen_pad_r[1]_i_1_n_0\
    );
\gen_pad_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => tx_rem_pipeline_r(0),
      I1 => tx_rem_pipeline_r(2),
      I2 => tx_rem_pipeline_r(1),
      I3 => tx_eof_n_pipeline_r,
      O => \gen_pad_r[2]_i_1_n_0\
    );
\gen_pad_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => tx_rem_pipeline_r(1),
      I1 => tx_rem_pipeline_r(2),
      I2 => tx_rem_pipeline_r(0),
      I3 => tx_eof_n_pipeline_r,
      O => \gen_pad_r[3]_i_1_n_0\
    );
\gen_pad_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_pad_r,
      Q => \gen_pad_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_pad_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \gen_pad_r[1]_i_1_n_0\,
      Q => p_6_in,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\gen_pad_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \gen_pad_r[2]_i_1_n_0\,
      Q => p_4_in,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\gen_pad_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \gen_pad_r[3]_i_1_n_0\,
      Q => \gen_pad_r_reg_n_0_[3]\,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
halt_c_pipeline_r_reg_inv: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => halt_c_pipeline_r_reg_inv_1,
      Q => TX_PE_DATA_V_Buffer2,
      S => halt_c_pipeline_r_reg_inv_0
    );
in_frame_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFE0010"
    )
        port map (
      I0 => tx_dst_rdy_n_pipeline_r,
      I1 => tx_src_rdy_n_pipeline_r,
      I2 => tx_eof_n_pipeline_r,
      I3 => tx_sof_n_pipeline_r,
      I4 => in_frame_r_reg_n_0,
      O => in_frame_r_i_1_n_0
    );
in_frame_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_r_i_1_n_0,
      Q => in_frame_r_reg_n_0,
      R => halt_c_pipeline_r_reg_inv_0
    );
storage_pad_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => tx_rem_pipeline_r(2),
      I1 => tx_rem_pipeline_r(1),
      I2 => tx_rem_pipeline_r(0),
      I3 => tx_eof_n_pipeline_r,
      O => storage_pad_r_i_1_n_0
    );
storage_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_pad_r_i_1_n_0,
      Q => storage_pad_r,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\storage_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[48]\,
      Q => storage_r(0),
      R => '0'
    );
\storage_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[58]\,
      Q => storage_r(10),
      R => '0'
    );
\storage_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[59]\,
      Q => storage_r(11),
      R => '0'
    );
\storage_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[60]\,
      Q => storage_r(12),
      R => '0'
    );
\storage_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[61]\,
      Q => storage_r(13),
      R => '0'
    );
\storage_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[62]\,
      Q => storage_r(14),
      R => '0'
    );
\storage_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[63]\,
      Q => storage_r(15),
      R => '0'
    );
\storage_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[49]\,
      Q => storage_r(1),
      R => '0'
    );
\storage_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[50]\,
      Q => storage_r(2),
      R => '0'
    );
\storage_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[51]\,
      Q => storage_r(3),
      R => '0'
    );
\storage_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[52]\,
      Q => storage_r(4),
      R => '0'
    );
\storage_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[53]\,
      Q => storage_r(5),
      R => '0'
    );
\storage_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[54]\,
      Q => storage_r(6),
      R => '0'
    );
\storage_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[55]\,
      Q => storage_r(7),
      R => '0'
    );
\storage_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[56]\,
      Q => storage_r(8),
      R => '0'
    );
\storage_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[57]\,
      Q => storage_r(9),
      R => '0'
    );
storage_ufc_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg_n_0_[3]\,
      Q => storage_ufc_v_r,
      R => '0'
    );
storage_v_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => tx_eof_n_pipeline_r,
      I1 => tx_rem_pipeline_r(0),
      I2 => tx_rem_pipeline_r(1),
      O => valid_c(3)
    );
storage_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => valid_c(3),
      Q => storage_v_r,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\tx_d_pipeline_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(7),
      Q => \tx_d_pipeline_r_reg_n_0_[0]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(13),
      Q => \tx_d_pipeline_r_reg_n_0_[10]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(12),
      Q => \tx_d_pipeline_r_reg_n_0_[11]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(11),
      Q => \tx_d_pipeline_r_reg_n_0_[12]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(10),
      Q => \tx_d_pipeline_r_reg_n_0_[13]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(9),
      Q => \tx_d_pipeline_r_reg_n_0_[14]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(8),
      Q => \tx_d_pipeline_r_reg_n_0_[15]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(23),
      Q => \tx_d_pipeline_r_reg_n_0_[16]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(22),
      Q => \tx_d_pipeline_r_reg_n_0_[17]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(21),
      Q => \tx_d_pipeline_r_reg_n_0_[18]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(20),
      Q => \tx_d_pipeline_r_reg_n_0_[19]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(6),
      Q => \tx_d_pipeline_r_reg_n_0_[1]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(19),
      Q => \tx_d_pipeline_r_reg_n_0_[20]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(18),
      Q => \tx_d_pipeline_r_reg_n_0_[21]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(17),
      Q => \tx_d_pipeline_r_reg_n_0_[22]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(16),
      Q => \tx_d_pipeline_r_reg_n_0_[23]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(31),
      Q => \tx_d_pipeline_r_reg_n_0_[24]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(30),
      Q => \tx_d_pipeline_r_reg_n_0_[25]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(29),
      Q => \tx_d_pipeline_r_reg_n_0_[26]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(28),
      Q => \tx_d_pipeline_r_reg_n_0_[27]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(27),
      Q => \tx_d_pipeline_r_reg_n_0_[28]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(26),
      Q => \tx_d_pipeline_r_reg_n_0_[29]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(5),
      Q => \tx_d_pipeline_r_reg_n_0_[2]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(25),
      Q => \tx_d_pipeline_r_reg_n_0_[30]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(24),
      Q => \tx_d_pipeline_r_reg_n_0_[31]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(39),
      Q => \tx_d_pipeline_r_reg_n_0_[32]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(38),
      Q => \tx_d_pipeline_r_reg_n_0_[33]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(37),
      Q => \tx_d_pipeline_r_reg_n_0_[34]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(36),
      Q => \tx_d_pipeline_r_reg_n_0_[35]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(35),
      Q => \tx_d_pipeline_r_reg_n_0_[36]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(34),
      Q => \tx_d_pipeline_r_reg_n_0_[37]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(33),
      Q => \tx_d_pipeline_r_reg_n_0_[38]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(32),
      Q => \tx_d_pipeline_r_reg_n_0_[39]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(4),
      Q => \tx_d_pipeline_r_reg_n_0_[3]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(47),
      Q => \tx_d_pipeline_r_reg_n_0_[40]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(46),
      Q => \tx_d_pipeline_r_reg_n_0_[41]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(45),
      Q => \tx_d_pipeline_r_reg_n_0_[42]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(44),
      Q => \tx_d_pipeline_r_reg_n_0_[43]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(43),
      Q => \tx_d_pipeline_r_reg_n_0_[44]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(42),
      Q => \tx_d_pipeline_r_reg_n_0_[45]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(41),
      Q => \tx_d_pipeline_r_reg_n_0_[46]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(40),
      Q => \tx_d_pipeline_r_reg_n_0_[47]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(55),
      Q => \tx_d_pipeline_r_reg_n_0_[48]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(54),
      Q => \tx_d_pipeline_r_reg_n_0_[49]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(3),
      Q => \tx_d_pipeline_r_reg_n_0_[4]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(53),
      Q => \tx_d_pipeline_r_reg_n_0_[50]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(52),
      Q => \tx_d_pipeline_r_reg_n_0_[51]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(51),
      Q => \tx_d_pipeline_r_reg_n_0_[52]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(50),
      Q => \tx_d_pipeline_r_reg_n_0_[53]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(49),
      Q => \tx_d_pipeline_r_reg_n_0_[54]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(48),
      Q => \tx_d_pipeline_r_reg_n_0_[55]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(63),
      Q => \tx_d_pipeline_r_reg_n_0_[56]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(62),
      Q => \tx_d_pipeline_r_reg_n_0_[57]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(61),
      Q => \tx_d_pipeline_r_reg_n_0_[58]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(60),
      Q => \tx_d_pipeline_r_reg_n_0_[59]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(2),
      Q => \tx_d_pipeline_r_reg_n_0_[5]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(59),
      Q => \tx_d_pipeline_r_reg_n_0_[60]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(58),
      Q => \tx_d_pipeline_r_reg_n_0_[61]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(57),
      Q => \tx_d_pipeline_r_reg_n_0_[62]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(56),
      Q => \tx_d_pipeline_r_reg_n_0_[63]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(1),
      Q => \tx_d_pipeline_r_reg_n_0_[6]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(0),
      Q => \tx_d_pipeline_r_reg_n_0_[7]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(15),
      Q => \tx_d_pipeline_r_reg_n_0_[8]\,
      R => '0'
    );
\tx_d_pipeline_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => S_AXI_TX_TDATA(14),
      Q => \tx_d_pipeline_r_reg_n_0_[9]\,
      R => '0'
    );
tx_dst_rdy_n_pipeline_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_dst_rdy,
      Q => tx_dst_rdy_n_pipeline_r,
      S => halt_c_pipeline_r_reg_inv_0
    );
tx_eof_n_pipeline_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => S_AXI_TX_TLAST,
      O => tx_eof
    );
tx_eof_n_pipeline_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_eof,
      Q => tx_eof_n_pipeline_r,
      S => halt_c_pipeline_r_reg_inv_0
    );
\tx_pe_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(0),
      Q => tx_pe_data_r(0),
      R => '0'
    );
\tx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(10),
      Q => tx_pe_data_r(10),
      R => '0'
    );
\tx_pe_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(11),
      Q => tx_pe_data_r(11),
      R => '0'
    );
\tx_pe_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(12),
      Q => tx_pe_data_r(12),
      R => '0'
    );
\tx_pe_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(13),
      Q => tx_pe_data_r(13),
      R => '0'
    );
\tx_pe_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(14),
      Q => tx_pe_data_r(14),
      R => '0'
    );
\tx_pe_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(15),
      Q => tx_pe_data_r(15),
      R => '0'
    );
\tx_pe_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[0]\,
      Q => tx_pe_data_r(16),
      R => '0'
    );
\tx_pe_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[1]\,
      Q => tx_pe_data_r(17),
      R => '0'
    );
\tx_pe_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[2]\,
      Q => tx_pe_data_r(18),
      R => '0'
    );
\tx_pe_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[3]\,
      Q => tx_pe_data_r(19),
      R => '0'
    );
\tx_pe_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(1),
      Q => tx_pe_data_r(1),
      R => '0'
    );
\tx_pe_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[4]\,
      Q => tx_pe_data_r(20),
      R => '0'
    );
\tx_pe_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[5]\,
      Q => tx_pe_data_r(21),
      R => '0'
    );
\tx_pe_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[6]\,
      Q => tx_pe_data_r(22),
      R => '0'
    );
\tx_pe_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[7]\,
      Q => tx_pe_data_r(23),
      R => '0'
    );
\tx_pe_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[8]\,
      Q => tx_pe_data_r(24),
      R => '0'
    );
\tx_pe_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[9]\,
      Q => tx_pe_data_r(25),
      R => '0'
    );
\tx_pe_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[10]\,
      Q => tx_pe_data_r(26),
      R => '0'
    );
\tx_pe_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[11]\,
      Q => tx_pe_data_r(27),
      R => '0'
    );
\tx_pe_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[12]\,
      Q => tx_pe_data_r(28),
      R => '0'
    );
\tx_pe_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[13]\,
      Q => tx_pe_data_r(29),
      R => '0'
    );
\tx_pe_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(2),
      Q => tx_pe_data_r(2),
      R => '0'
    );
\tx_pe_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[14]\,
      Q => tx_pe_data_r(30),
      R => '0'
    );
\tx_pe_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[15]\,
      Q => tx_pe_data_r(31),
      R => '0'
    );
\tx_pe_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[16]\,
      Q => tx_pe_data_r(32),
      R => '0'
    );
\tx_pe_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[17]\,
      Q => tx_pe_data_r(33),
      R => '0'
    );
\tx_pe_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[18]\,
      Q => tx_pe_data_r(34),
      R => '0'
    );
\tx_pe_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[19]\,
      Q => tx_pe_data_r(35),
      R => '0'
    );
\tx_pe_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[20]\,
      Q => tx_pe_data_r(36),
      R => '0'
    );
\tx_pe_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[21]\,
      Q => tx_pe_data_r(37),
      R => '0'
    );
\tx_pe_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[22]\,
      Q => tx_pe_data_r(38),
      R => '0'
    );
\tx_pe_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[23]\,
      Q => tx_pe_data_r(39),
      R => '0'
    );
\tx_pe_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(3),
      Q => tx_pe_data_r(3),
      R => '0'
    );
\tx_pe_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[24]\,
      Q => tx_pe_data_r(40),
      R => '0'
    );
\tx_pe_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[25]\,
      Q => tx_pe_data_r(41),
      R => '0'
    );
\tx_pe_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[26]\,
      Q => tx_pe_data_r(42),
      R => '0'
    );
\tx_pe_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[27]\,
      Q => tx_pe_data_r(43),
      R => '0'
    );
\tx_pe_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[28]\,
      Q => tx_pe_data_r(44),
      R => '0'
    );
\tx_pe_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[29]\,
      Q => tx_pe_data_r(45),
      R => '0'
    );
\tx_pe_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[30]\,
      Q => tx_pe_data_r(46),
      R => '0'
    );
\tx_pe_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[31]\,
      Q => tx_pe_data_r(47),
      R => '0'
    );
\tx_pe_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[32]\,
      Q => tx_pe_data_r(48),
      R => '0'
    );
\tx_pe_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[33]\,
      Q => tx_pe_data_r(49),
      R => '0'
    );
\tx_pe_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(4),
      Q => tx_pe_data_r(4),
      R => '0'
    );
\tx_pe_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[34]\,
      Q => tx_pe_data_r(50),
      R => '0'
    );
\tx_pe_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[35]\,
      Q => tx_pe_data_r(51),
      R => '0'
    );
\tx_pe_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[36]\,
      Q => tx_pe_data_r(52),
      R => '0'
    );
\tx_pe_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[37]\,
      Q => tx_pe_data_r(53),
      R => '0'
    );
\tx_pe_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[38]\,
      Q => tx_pe_data_r(54),
      R => '0'
    );
\tx_pe_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[39]\,
      Q => tx_pe_data_r(55),
      R => '0'
    );
\tx_pe_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[40]\,
      Q => tx_pe_data_r(56),
      R => '0'
    );
\tx_pe_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[41]\,
      Q => tx_pe_data_r(57),
      R => '0'
    );
\tx_pe_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[42]\,
      Q => tx_pe_data_r(58),
      R => '0'
    );
\tx_pe_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[43]\,
      Q => tx_pe_data_r(59),
      R => '0'
    );
\tx_pe_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(5),
      Q => tx_pe_data_r(5),
      R => '0'
    );
\tx_pe_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[44]\,
      Q => tx_pe_data_r(60),
      R => '0'
    );
\tx_pe_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[45]\,
      Q => tx_pe_data_r(61),
      R => '0'
    );
\tx_pe_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[46]\,
      Q => tx_pe_data_r(62),
      R => '0'
    );
\tx_pe_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => \tx_d_pipeline_r_reg_n_0_[47]\,
      Q => tx_pe_data_r(63),
      R => '0'
    );
\tx_pe_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(6),
      Q => tx_pe_data_r(6),
      R => '0'
    );
\tx_pe_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(7),
      Q => tx_pe_data_r(7),
      R => '0'
    );
\tx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(8),
      Q => tx_pe_data_r(8),
      R => '0'
    );
\tx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_r(9),
      Q => tx_pe_data_r(9),
      R => '0'
    );
\tx_pe_data_v_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1101"
    )
        port map (
      I0 => tx_dst_rdy_n_pipeline_r,
      I1 => tx_src_rdy_n_pipeline_r,
      I2 => tx_sof_n_pipeline_r,
      I3 => in_frame_r_reg_n_0,
      O => p_31_in
    );
\tx_pe_data_v_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF40000"
    )
        port map (
      I0 => in_frame_r_reg_n_0,
      I1 => tx_sof_n_pipeline_r,
      I2 => tx_src_rdy_n_pipeline_r,
      I3 => tx_dst_rdy_n_pipeline_r,
      I4 => TX_PE_DATA_V_Buffer2,
      O => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\tx_pe_data_v_r[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => tx_rem_pipeline_r(0),
      I1 => tx_rem_pipeline_r(1),
      I2 => tx_eof_n_pipeline_r,
      O => valid_c(1)
    );
\tx_pe_data_v_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_rem_pipeline_r(0),
      I1 => tx_eof_n_pipeline_r,
      O => valid_c(2)
    );
\tx_pe_data_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => storage_v_r,
      Q => \tx_pe_data_v_r_reg_n_0_[0]\,
      R => '0'
    );
\tx_pe_data_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => p_31_in,
      Q => p_4_in10_in,
      R => '0'
    );
\tx_pe_data_v_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => valid_c(1),
      Q => p_2_in,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\tx_pe_data_v_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => TX_PE_DATA_V_Buffer2,
      D => valid_c(2),
      Q => \tx_pe_data_v_r_reg_n_0_[3]\,
      R => \tx_pe_data_v_r[2]_i_1_n_0\
    );
\tx_pe_ufc_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_ufc_v_r,
      Q => p_7_in,
      R => '0'
    );
\tx_pe_ufc_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg_n_0_[0]\,
      Q => p_5_in,
      R => '0'
    );
\tx_pe_ufc_v_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg_n_0_[1]\,
      Q => p_3_in,
      R => '0'
    );
\tx_pe_ufc_v_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg_n_0_[2]\,
      Q => \tx_pe_ufc_v_r_reg_n_0_[3]\,
      R => '0'
    );
\tx_rem_pipeline_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => S_AXI_TX_TKEEP(5),
      I1 => S_AXI_TX_TKEEP(3),
      I2 => S_AXI_TX_TKEEP(4),
      O => \^s_axi_tx_tkeep[5]\
    );
\tx_rem_pipeline_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"171717E817E8E8E8"
    )
        port map (
      I0 => S_AXI_TX_TKEEP(4),
      I1 => S_AXI_TX_TKEEP(5),
      I2 => S_AXI_TX_TKEEP(3),
      I3 => S_AXI_TX_TKEEP(0),
      I4 => S_AXI_TX_TKEEP(6),
      I5 => S_AXI_TX_TKEEP(7),
      O => \^s_axi_tx_tkeep[4]\
    );
\tx_rem_pipeline_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A9"
    )
        port map (
      I0 => \tx_rem_pipeline_r[1]_i_2_n_0\,
      I1 => S_AXI_TX_TKEEP(1),
      I2 => S_AXI_TX_TKEEP(2),
      I3 => \^s_axi_tx_tkeep[4]\,
      O => tx_rem(1)
    );
\tx_rem_pipeline_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF9696FF96000096"
    )
        port map (
      I0 => S_AXI_TX_TKEEP(0),
      I1 => S_AXI_TX_TKEEP(6),
      I2 => S_AXI_TX_TKEEP(7),
      I3 => S_AXI_TX_TKEEP(2),
      I4 => S_AXI_TX_TKEEP(1),
      I5 => \^s_axi_tx_tkeep[5]\,
      O => \tx_rem_pipeline_r[1]_i_2_n_0\
    );
\tx_rem_pipeline_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => S_AXI_TX_TKEEP(1),
      I1 => S_AXI_TX_TKEEP(2),
      I2 => S_AXI_TX_TKEEP(0),
      I3 => S_AXI_TX_TKEEP(6),
      I4 => S_AXI_TX_TKEEP(7),
      I5 => \^s_axi_tx_tkeep[5]\,
      O => \tx_rem_pipeline_r[2]_i_1_n_0\
    );
\tx_rem_pipeline_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => tx_rem_pipeline_r(0),
      R => '0'
    );
\tx_rem_pipeline_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_rem(1),
      Q => tx_rem_pipeline_r(1),
      R => '0'
    );
\tx_rem_pipeline_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \tx_rem_pipeline_r[2]_i_1_n_0\,
      Q => tx_rem_pipeline_r(2),
      R => '0'
    );
tx_sof_n_pipeline_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_sof,
      Q => tx_sof_n_pipeline_r,
      S => halt_c_pipeline_r_reg_inv_0
    );
tx_src_rdy_n_pipeline_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => S_AXI_TX_TVALID,
      O => tx_src_rdy
    );
tx_src_rdy_n_pipeline_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_src_rdy,
      Q => tx_src_rdy_n_pipeline_r,
      S => halt_c_pipeline_r_reg_inv_0
    );
\ufc_message_pipeline_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg[0]_0\(3),
      Q => \ufc_message_pipeline_r_reg_n_0_[0]\,
      R => halt_c_pipeline_r_reg_inv_0
    );
\ufc_message_pipeline_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg[0]_0\(2),
      Q => \ufc_message_pipeline_r_reg_n_0_[1]\,
      R => halt_c_pipeline_r_reg_inv_0
    );
\ufc_message_pipeline_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg[0]_0\(1),
      Q => \ufc_message_pipeline_r_reg_n_0_[2]\,
      R => halt_c_pipeline_r_reg_inv_0
    );
\ufc_message_pipeline_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ufc_message_pipeline_r_reg[0]_0\(0),
      Q => \ufc_message_pipeline_r_reg_n_0_[3]\,
      R => halt_c_pipeline_r_reg_inv_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_cdc_sync is
  port (
    AR : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_RESET : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_cdc_sync : entity is "efex_aurora_hub2_cdc_sync";
end efex_aurora_hub2_efex_aurora_hub2_cdc_sync;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_cdc_sync is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  AR(0) <= s_level_out_d3;
  p_level_in_int <= GT_RESET;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0 is
  port (
    \out\ : out STD_LOGIC;
    TX_SYSTEM_RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0 : entity is "efex_aurora_hub2_cdc_sync";
end efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
  p_level_in_int <= TX_SYSTEM_RESET;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13 is
  port (
    reset_time_out_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    reset_time_out : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    reset_time_out_reg_0 : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_3\ : in STD_LOGIC;
    txresetdone_s3 : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13 : entity is "efex_aurora_hub2_cdc_sync";
end efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13 is
  signal \FSM_sequential_tx_state[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_5_n_0\ : STD_LOGIC;
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal reset_time_out_0 : STD_LOGIC;
  signal reset_time_out_i_3_n_0 : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  p_level_in_int <= in0;
\FSM_sequential_tx_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFAFAFAFFFEFAFA"
    )
        port map (
      I0 => \FSM_sequential_tx_state_reg[0]\,
      I1 => \FSM_sequential_tx_state[3]_i_4_n_0\,
      I2 => \FSM_sequential_tx_state[3]_i_5_n_0\,
      I3 => \FSM_sequential_tx_state_reg[0]_0\,
      I4 => Q(0),
      I5 => Q(3),
      O => E(0)
    );
\FSM_sequential_tx_state[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8CCB800"
    )
        port map (
      I0 => txresetdone_s3,
      I1 => Q(2),
      I2 => s_level_out_d3,
      I3 => Q(1),
      I4 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[3]_i_4_n_0\
    );
\FSM_sequential_tx_state[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000400070004"
    )
        port map (
      I0 => \FSM_sequential_tx_state_reg[0]_1\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => \FSM_sequential_tx_state_reg[0]_2\,
      I4 => \FSM_sequential_tx_state_reg[0]_3\,
      I5 => s_level_out_d3,
      O => \FSM_sequential_tx_state[3]_i_5_n_0\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
reset_time_out_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => reset_time_out_0,
      I1 => reset_time_out_i_3_n_0,
      I2 => reset_time_out,
      O => reset_time_out_reg
    );
reset_time_out_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AE00AE00AEF0AE"
    )
        port map (
      I0 => \FSM_sequential_tx_state[3]_i_4_n_0\,
      I1 => reset_time_out_reg_0,
      I2 => Q(0),
      I3 => Q(3),
      I4 => Q(2),
      I5 => Q(1),
      O => reset_time_out_0
    );
reset_time_out_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF005555F544"
    )
        port map (
      I0 => Q(1),
      I1 => reset_time_out_reg_0,
      I2 => s_level_out_d3,
      I3 => Q(0),
      I4 => Q(3),
      I5 => Q(2),
      O => reset_time_out_i_3_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14 is
  port (
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14 : entity is "efex_aurora_hub2_cdc_sync";
end efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => p_level_in_int
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16 is
  port (
    \out\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16 : entity is "efex_aurora_hub2_cdc_sync";
end efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => p_level_in_int
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
\mmcm_lock_count[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => s_level_out_d3,
      O => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2\ is
  port (
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => '0',
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15\ is
  port (
    \out\ : out STD_LOGIC;
    txfsm_txresetdone_r : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => txfsm_txresetdone_r,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17\ is
  port (
    \out\ : out STD_LOGIC;
    run_phase_alignment_int : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => run_phase_alignment_int,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18\ is
  port (
    \out\ : out STD_LOGIC;
    time_out_wait_bypass : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => time_out_wait_bypass,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19\ is
  port (
    \out\ : out STD_LOGIC;
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0\ : out STD_LOGIC;
    tx_fsm_reset_done_int : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => tx_fsm_reset_done_int,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
gt_txresetdone_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => s_level_out_d3,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0\
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23\ is
  port (
    \out\ : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => '0',
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24\ is
  port (
    \out\ : out STD_LOGIC;
    tx_lock_comb_r : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24\ : entity is "efex_aurora_hub2_cdc_sync";
end \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24\;

architecture STRUCTURE of \efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_efex_aurora_hub2_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_efex_aurora_hub2_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => tx_lock_comb_r,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_efex_aurora_hub2_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_efex_aurora_hub2_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_efex_aurora_hub2_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_gt is
  port (
    gt0_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    TXN : out STD_LOGIC_VECTOR ( 0 to 0 );
    TXP : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_tx_reset_i : in STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    gt_rxdfeagchold_i : in STD_LOGIC;
    gt_rxdfelfhold_i : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    gt0_txinhibit_in : in STD_LOGIC;
    gt0_txpcsreset_in : in STD_LOGIC;
    gt0_txpmareset_in : in STD_LOGIC;
    gt0_txpolarity_in : in STD_LOGIC;
    gt0_txprbsforceerr_in : in STD_LOGIC;
    gt_txuserrdy_i : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    TXCHARISK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    ENABLE_ERR_DETECT : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_gt : entity is "efex_aurora_hub2_gt";
end efex_aurora_hub2_efex_aurora_hub2_gt;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_gt is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT0_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal flag2 : STD_LOGIC;
  signal flag2_i_2_n_0 : STD_LOGIC;
  signal flag_i_1_n_0 : STD_LOGIC;
  signal \^gt0_txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_10 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_11 : STD_LOGIC;
  signal gthe2_i_n_114 : STD_LOGIC;
  signal gthe2_i_n_115 : STD_LOGIC;
  signal gthe2_i_n_116 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_120 : STD_LOGIC;
  signal gthe2_i_n_121 : STD_LOGIC;
  signal gthe2_i_n_122 : STD_LOGIC;
  signal gthe2_i_n_123 : STD_LOGIC;
  signal gthe2_i_n_124 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_14 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_17 : STD_LOGIC;
  signal gthe2_i_n_189 : STD_LOGIC;
  signal gthe2_i_n_190 : STD_LOGIC;
  signal gthe2_i_n_191 : STD_LOGIC;
  signal gthe2_i_n_192 : STD_LOGIC;
  signal gthe2_i_n_193 : STD_LOGIC;
  signal gthe2_i_n_194 : STD_LOGIC;
  signal gthe2_i_n_195 : STD_LOGIC;
  signal gthe2_i_n_196 : STD_LOGIC;
  signal gthe2_i_n_197 : STD_LOGIC;
  signal gthe2_i_n_198 : STD_LOGIC;
  signal gthe2_i_n_199 : STD_LOGIC;
  signal gthe2_i_n_200 : STD_LOGIC;
  signal gthe2_i_n_201 : STD_LOGIC;
  signal gthe2_i_n_202 : STD_LOGIC;
  signal gthe2_i_n_203 : STD_LOGIC;
  signal gthe2_i_n_204 : STD_LOGIC;
  signal gthe2_i_n_205 : STD_LOGIC;
  signal gthe2_i_n_206 : STD_LOGIC;
  signal gthe2_i_n_207 : STD_LOGIC;
  signal gthe2_i_n_208 : STD_LOGIC;
  signal gthe2_i_n_209 : STD_LOGIC;
  signal gthe2_i_n_210 : STD_LOGIC;
  signal gthe2_i_n_211 : STD_LOGIC;
  signal gthe2_i_n_218 : STD_LOGIC;
  signal gthe2_i_n_219 : STD_LOGIC;
  signal gthe2_i_n_226 : STD_LOGIC;
  signal gthe2_i_n_227 : STD_LOGIC;
  signal gthe2_i_n_234 : STD_LOGIC;
  signal gthe2_i_n_235 : STD_LOGIC;
  signal gthe2_i_n_242 : STD_LOGIC;
  signal gthe2_i_n_243 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_34 : STD_LOGIC;
  signal gthe2_i_n_38 : STD_LOGIC;
  signal gthe2_i_n_4 : STD_LOGIC;
  signal gthe2_i_n_45 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_57 : STD_LOGIC;
  signal gthe2_i_n_58 : STD_LOGIC;
  signal gthe2_i_n_59 : STD_LOGIC;
  signal gthe2_i_n_60 : STD_LOGIC;
  signal gthe2_i_n_61 : STD_LOGIC;
  signal gthe2_i_n_62 : STD_LOGIC;
  signal gthe2_i_n_63 : STD_LOGIC;
  signal gthe2_i_n_64 : STD_LOGIC;
  signal gthe2_i_n_65 : STD_LOGIC;
  signal gthe2_i_n_66 : STD_LOGIC;
  signal gthe2_i_n_67 : STD_LOGIC;
  signal gthe2_i_n_68 : STD_LOGIC;
  signal gthe2_i_n_69 : STD_LOGIC;
  signal gthe2_i_n_70 : STD_LOGIC;
  signal gthe2_i_n_71 : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt0_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt0_txbufstatus_out(1 downto 0) <= \^gt0_txbufstatus_out\(1 downto 0);
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
flag2_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => flag2_i_2_n_0
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag2_i_2_n_0,
      Q => flag2,
      R => flag2_reg_0
    );
flag_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => flag_i_1_n_0
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag_i_1_n_0,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => gt0_cplllock_out,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT0_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14) => gthe2_i_n_57,
      DMONITOROUT(13) => gthe2_i_n_58,
      DMONITOROUT(12) => gthe2_i_n_59,
      DMONITOROUT(11) => gthe2_i_n_60,
      DMONITOROUT(10) => gthe2_i_n_61,
      DMONITOROUT(9) => gthe2_i_n_62,
      DMONITOROUT(8) => gthe2_i_n_63,
      DMONITOROUT(7) => gthe2_i_n_64,
      DMONITOROUT(6) => gthe2_i_n_65,
      DMONITOROUT(5) => gthe2_i_n_66,
      DMONITOROUT(4) => gthe2_i_n_67,
      DMONITOROUT(3) => gthe2_i_n_68,
      DMONITOROUT(2) => gthe2_i_n_69,
      DMONITOROUT(1) => gthe2_i_n_70,
      DMONITOROUT(0) => gthe2_i_n_71,
      DRPADDR(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN => DRPEN_IN,
      DRPRDY => DRPRDY_OUT,
      DRPWE => DRPWE_IN,
      EYESCANDATAERROR => gthe2_i_n_4,
      EYESCANMODE => '0',
      EYESCANRESET => '0',
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTHRXN => '0',
      GTHRXP => '0',
      GTHTXN => TXN(0),
      GTHTXP => TXP(0),
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => gt_tx_reset_i,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad5_in,
      QPLLREFCLK => gt_qpllrefclk_quad5_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2) => gthe2_i_n_114,
      RXBUFSTATUS(1) => gthe2_i_n_115,
      RXBUFSTATUS(0) => gthe2_i_n_116,
      RXBYTEISALIGNED => gthe2_i_n_10,
      RXBYTEREALIGN => gthe2_i_n_11,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => gthe2_i_n_14,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1) => gthe2_i_n_218,
      RXCHARISCOMMA(0) => gthe2_i_n_219,
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1) => gthe2_i_n_226,
      RXCHARISK(0) => gthe2_i_n_227,
      RXCHBONDEN => '1',
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"001",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => gthe2_i_n_120,
      RXCHBONDO(3) => gthe2_i_n_121,
      RXCHBONDO(2) => gthe2_i_n_122,
      RXCHBONDO(1) => gthe2_i_n_123,
      RXCHBONDO(0) => gthe2_i_n_124,
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gthe2_i_n_17,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15) => gthe2_i_n_189,
      RXDATA(14) => gthe2_i_n_190,
      RXDATA(13) => gthe2_i_n_191,
      RXDATA(12) => gthe2_i_n_192,
      RXDATA(11) => gthe2_i_n_193,
      RXDATA(10) => gthe2_i_n_194,
      RXDATA(9) => gthe2_i_n_195,
      RXDATA(8) => gthe2_i_n_196,
      RXDATA(7) => gthe2_i_n_197,
      RXDATA(6) => gthe2_i_n_198,
      RXDATA(5) => gthe2_i_n_199,
      RXDATA(4) => gthe2_i_n_200,
      RXDATA(3) => gthe2_i_n_201,
      RXDATA(2) => gthe2_i_n_202,
      RXDATA(1) => gthe2_i_n_203,
      RXDATA(0) => gthe2_i_n_204,
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => gt_rxdfeagchold_i,
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => gt_rxdfelfhold_i,
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1) => gthe2_i_n_234,
      RXDISPERR(0) => gthe2_i_n_235,
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '0',
      RXMONITOROUT(6) => gthe2_i_n_205,
      RXMONITOROUT(5) => gthe2_i_n_206,
      RXMONITOROUT(4) => gthe2_i_n_207,
      RXMONITOROUT(3) => gthe2_i_n_208,
      RXMONITOROUT(2) => gthe2_i_n_209,
      RXMONITOROUT(1) => gthe2_i_n_210,
      RXMONITOROUT(0) => gthe2_i_n_211,
      RXMONITORSEL(1 downto 0) => B"00",
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1) => gthe2_i_n_242,
      RXNOTINTABLE(0) => gthe2_i_n_243,
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '0',
      RXPCSRESET => '0',
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => gthe2_i_n_34,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gthe2_i_n_38,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \^gt0_txbufstatus_out\(1 downto 0),
      TXCHARDISPMODE(7 downto 2) => B"000000",
      TXCHARDISPMODE(1 downto 0) => gt0_txchardispmode_in(1 downto 0),
      TXCHARDISPVAL(7 downto 2) => B"000000",
      TXCHARDISPVAL(1 downto 0) => gt0_txchardispval_in(1 downto 0),
      TXCHARISK(7 downto 2) => B"000000",
      TXCHARISK(1 downto 0) => TXCHARISK(1 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000",
      TXDATA(15 downto 0) => TXDATA(15 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => gt0_txdiffctrl_in(3 downto 0),
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => POWER_DOWN,
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => gt0_txinhibit_in,
      TXMAINCURSOR(6 downto 0) => gt0_txmaincursor_in(6 downto 0),
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gthe2_i_n_45,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => gt0_txpcsreset_in,
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => gt0_txpmareset_in,
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => gt0_txpolarity_in,
      TXPOSTCURSOR(4 downto 0) => gt0_txpostcursor_in(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => gt0_txprbsforceerr_in,
      TXPRBSSEL(2 downto 0) => gt0_txprbssel_in(2 downto 0),
      TXPRECURSOR(4 downto 0) => gt0_txprecursor_in(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt0_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => gt_txuserrdy_i,
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
hard_err_flop_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt0_txbufstatus_out\(1),
      I1 => ENABLE_ERR_DETECT,
      O => ENABLE_ERR_DETECT_Buffer_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_gt_20 is
  port (
    gt1_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    TXN : out STD_LOGIC_VECTOR ( 0 to 0 );
    TXP : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt1_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 );
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_tx_reset_i : in STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    gt_rxdfeagchold_i : in STD_LOGIC;
    gt_rxdfelfhold_i : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    gt1_txinhibit_in : in STD_LOGIC;
    gt1_txpcsreset_in : in STD_LOGIC;
    gt1_txpmareset_in : in STD_LOGIC;
    gt1_txpolarity_in : in STD_LOGIC;
    gt1_txprbsforceerr_in : in STD_LOGIC;
    gt_txuserrdy_i : in STD_LOGIC;
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    ENABLE_ERR_DETECT_0 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_gt_20 : entity is "efex_aurora_hub2_gt";
end efex_aurora_hub2_efex_aurora_hub2_gt_20;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_gt_20 is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT1_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal flag2_i_1_n_0 : STD_LOGIC;
  signal flag2_reg_n_0 : STD_LOGIC;
  signal \flag_i_1__0_n_0\ : STD_LOGIC;
  signal \^gt1_txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_10 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_11 : STD_LOGIC;
  signal gthe2_i_n_114 : STD_LOGIC;
  signal gthe2_i_n_115 : STD_LOGIC;
  signal gthe2_i_n_116 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_14 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_17 : STD_LOGIC;
  signal gthe2_i_n_189 : STD_LOGIC;
  signal gthe2_i_n_190 : STD_LOGIC;
  signal gthe2_i_n_191 : STD_LOGIC;
  signal gthe2_i_n_192 : STD_LOGIC;
  signal gthe2_i_n_193 : STD_LOGIC;
  signal gthe2_i_n_194 : STD_LOGIC;
  signal gthe2_i_n_195 : STD_LOGIC;
  signal gthe2_i_n_196 : STD_LOGIC;
  signal gthe2_i_n_197 : STD_LOGIC;
  signal gthe2_i_n_198 : STD_LOGIC;
  signal gthe2_i_n_199 : STD_LOGIC;
  signal gthe2_i_n_200 : STD_LOGIC;
  signal gthe2_i_n_201 : STD_LOGIC;
  signal gthe2_i_n_202 : STD_LOGIC;
  signal gthe2_i_n_203 : STD_LOGIC;
  signal gthe2_i_n_204 : STD_LOGIC;
  signal gthe2_i_n_205 : STD_LOGIC;
  signal gthe2_i_n_206 : STD_LOGIC;
  signal gthe2_i_n_207 : STD_LOGIC;
  signal gthe2_i_n_208 : STD_LOGIC;
  signal gthe2_i_n_209 : STD_LOGIC;
  signal gthe2_i_n_210 : STD_LOGIC;
  signal gthe2_i_n_211 : STD_LOGIC;
  signal gthe2_i_n_218 : STD_LOGIC;
  signal gthe2_i_n_219 : STD_LOGIC;
  signal gthe2_i_n_226 : STD_LOGIC;
  signal gthe2_i_n_227 : STD_LOGIC;
  signal gthe2_i_n_234 : STD_LOGIC;
  signal gthe2_i_n_235 : STD_LOGIC;
  signal gthe2_i_n_242 : STD_LOGIC;
  signal gthe2_i_n_243 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_34 : STD_LOGIC;
  signal gthe2_i_n_38 : STD_LOGIC;
  signal gthe2_i_n_4 : STD_LOGIC;
  signal gthe2_i_n_45 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_57 : STD_LOGIC;
  signal gthe2_i_n_58 : STD_LOGIC;
  signal gthe2_i_n_59 : STD_LOGIC;
  signal gthe2_i_n_60 : STD_LOGIC;
  signal gthe2_i_n_61 : STD_LOGIC;
  signal gthe2_i_n_62 : STD_LOGIC;
  signal gthe2_i_n_63 : STD_LOGIC;
  signal gthe2_i_n_64 : STD_LOGIC;
  signal gthe2_i_n_65 : STD_LOGIC;
  signal gthe2_i_n_66 : STD_LOGIC;
  signal gthe2_i_n_67 : STD_LOGIC;
  signal gthe2_i_n_68 : STD_LOGIC;
  signal gthe2_i_n_69 : STD_LOGIC;
  signal gthe2_i_n_70 : STD_LOGIC;
  signal gthe2_i_n_71 : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt1_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt1_txbufstatus_out(1 downto 0) <= \^gt1_txbufstatus_out\(1 downto 0);
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2_reg_n_0,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
flag2_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => flag2_i_1_n_0
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag2_i_1_n_0,
      Q => flag2_reg_n_0,
      R => flag2_reg_0
    );
\flag_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => \flag_i_1__0_n_0\
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag_i_1__0_n_0\,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => gt1_cplllock_out,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT1_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14) => gthe2_i_n_57,
      DMONITOROUT(13) => gthe2_i_n_58,
      DMONITOROUT(12) => gthe2_i_n_59,
      DMONITOROUT(11) => gthe2_i_n_60,
      DMONITOROUT(10) => gthe2_i_n_61,
      DMONITOROUT(9) => gthe2_i_n_62,
      DMONITOROUT(8) => gthe2_i_n_63,
      DMONITOROUT(7) => gthe2_i_n_64,
      DMONITOROUT(6) => gthe2_i_n_65,
      DMONITOROUT(5) => gthe2_i_n_66,
      DMONITOROUT(4) => gthe2_i_n_67,
      DMONITOROUT(3) => gthe2_i_n_68,
      DMONITOROUT(2) => gthe2_i_n_69,
      DMONITOROUT(1) => gthe2_i_n_70,
      DMONITOROUT(0) => gthe2_i_n_71,
      DRPADDR(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPEN => DRPEN_IN_LANE1,
      DRPRDY => DRPRDY_OUT_LANE1,
      DRPWE => DRPWE_IN_LANE1,
      EYESCANDATAERROR => gthe2_i_n_4,
      EYESCANMODE => '0',
      EYESCANRESET => '0',
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTHRXN => '0',
      GTHRXP => '0',
      GTHTXN => TXN(0),
      GTHTXP => TXP(0),
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => gt_tx_reset_i,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad5_in,
      QPLLREFCLK => gt_qpllrefclk_quad5_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2) => gthe2_i_n_114,
      RXBUFSTATUS(1) => gthe2_i_n_115,
      RXBUFSTATUS(0) => gthe2_i_n_116,
      RXBYTEISALIGNED => gthe2_i_n_10,
      RXBYTEREALIGN => gthe2_i_n_11,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => gthe2_i_n_14,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1) => gthe2_i_n_218,
      RXCHARISCOMMA(0) => gthe2_i_n_219,
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1) => gthe2_i_n_226,
      RXCHARISK(0) => gthe2_i_n_227,
      RXCHBONDEN => '0',
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"010",
      RXCHBONDMASTER => '1',
      RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gthe2_i_n_17,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15) => gthe2_i_n_189,
      RXDATA(14) => gthe2_i_n_190,
      RXDATA(13) => gthe2_i_n_191,
      RXDATA(12) => gthe2_i_n_192,
      RXDATA(11) => gthe2_i_n_193,
      RXDATA(10) => gthe2_i_n_194,
      RXDATA(9) => gthe2_i_n_195,
      RXDATA(8) => gthe2_i_n_196,
      RXDATA(7) => gthe2_i_n_197,
      RXDATA(6) => gthe2_i_n_198,
      RXDATA(5) => gthe2_i_n_199,
      RXDATA(4) => gthe2_i_n_200,
      RXDATA(3) => gthe2_i_n_201,
      RXDATA(2) => gthe2_i_n_202,
      RXDATA(1) => gthe2_i_n_203,
      RXDATA(0) => gthe2_i_n_204,
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => gt_rxdfeagchold_i,
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => gt_rxdfelfhold_i,
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1) => gthe2_i_n_234,
      RXDISPERR(0) => gthe2_i_n_235,
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '0',
      RXMONITOROUT(6) => gthe2_i_n_205,
      RXMONITOROUT(5) => gthe2_i_n_206,
      RXMONITOROUT(4) => gthe2_i_n_207,
      RXMONITOROUT(3) => gthe2_i_n_208,
      RXMONITOROUT(2) => gthe2_i_n_209,
      RXMONITOROUT(1) => gthe2_i_n_210,
      RXMONITOROUT(0) => gthe2_i_n_211,
      RXMONITORSEL(1 downto 0) => B"00",
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1) => gthe2_i_n_242,
      RXNOTINTABLE(0) => gthe2_i_n_243,
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '0',
      RXPCSRESET => '0',
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => gthe2_i_n_34,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gthe2_i_n_38,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \^gt1_txbufstatus_out\(1 downto 0),
      TXCHARDISPMODE(7 downto 2) => B"000000",
      TXCHARDISPMODE(1 downto 0) => gt1_txchardispmode_in(1 downto 0),
      TXCHARDISPVAL(7 downto 2) => B"000000",
      TXCHARDISPVAL(1 downto 0) => gt1_txchardispval_in(1 downto 0),
      TXCHARISK(7 downto 2) => B"000000",
      TXCHARISK(1 downto 0) => gt1_cplllock_out_1(1 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000",
      TXDATA(15 downto 0) => gt1_cplllock_out_0(15 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => gt1_txdiffctrl_in(3 downto 0),
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => POWER_DOWN,
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => gt1_txinhibit_in,
      TXMAINCURSOR(6 downto 0) => gt1_txmaincursor_in(6 downto 0),
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gthe2_i_n_45,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => gt1_txpcsreset_in,
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => gt1_txpmareset_in,
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => gt1_txpolarity_in,
      TXPOSTCURSOR(4 downto 0) => gt1_txpostcursor_in(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => gt1_txprbsforceerr_in,
      TXPRBSSEL(2 downto 0) => gt1_txprbssel_in(2 downto 0),
      TXPRECURSOR(4 downto 0) => gt1_txprecursor_in(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt1_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => gt_txuserrdy_i,
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
\hard_err_flop_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt1_txbufstatus_out\(1),
      I1 => ENABLE_ERR_DETECT_0,
      O => ENABLE_ERR_DETECT_Buffer_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_gt_21 is
  port (
    gt2_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    TXN : out STD_LOGIC_VECTOR ( 0 to 0 );
    TXP : out STD_LOGIC_VECTOR ( 0 to 0 );
    TX_OUT_CLK : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 );
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_tx_reset_i : in STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    gt_rxdfeagchold_i : in STD_LOGIC;
    gt_rxdfelfhold_i : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    gt2_txinhibit_in : in STD_LOGIC;
    gt2_txpcsreset_in : in STD_LOGIC;
    gt2_txpmareset_in : in STD_LOGIC;
    gt2_txpolarity_in : in STD_LOGIC;
    gt2_txprbsforceerr_in : in STD_LOGIC;
    gt_txuserrdy_i : in STD_LOGIC;
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_cplllock_out_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_cplllock_out_1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    ENABLE_ERR_DETECT_1 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC;
    gt3_cplllock_out : in STD_LOGIC;
    gt0_cplllock_out : in STD_LOGIC;
    gt1_cplllock_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_gt_21 : entity is "efex_aurora_hub2_gt";
end efex_aurora_hub2_efex_aurora_hub2_gt_21;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_gt_21 is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT2_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal \flag2_i_1__0_n_0\ : STD_LOGIC;
  signal flag2_reg_n_0 : STD_LOGIC;
  signal \flag_i_1__1_n_0\ : STD_LOGIC;
  signal \^gt2_cplllock_out\ : STD_LOGIC;
  signal \^gt2_txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_10 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_11 : STD_LOGIC;
  signal gthe2_i_n_114 : STD_LOGIC;
  signal gthe2_i_n_115 : STD_LOGIC;
  signal gthe2_i_n_116 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_14 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_17 : STD_LOGIC;
  signal gthe2_i_n_189 : STD_LOGIC;
  signal gthe2_i_n_190 : STD_LOGIC;
  signal gthe2_i_n_191 : STD_LOGIC;
  signal gthe2_i_n_192 : STD_LOGIC;
  signal gthe2_i_n_193 : STD_LOGIC;
  signal gthe2_i_n_194 : STD_LOGIC;
  signal gthe2_i_n_195 : STD_LOGIC;
  signal gthe2_i_n_196 : STD_LOGIC;
  signal gthe2_i_n_197 : STD_LOGIC;
  signal gthe2_i_n_198 : STD_LOGIC;
  signal gthe2_i_n_199 : STD_LOGIC;
  signal gthe2_i_n_200 : STD_LOGIC;
  signal gthe2_i_n_201 : STD_LOGIC;
  signal gthe2_i_n_202 : STD_LOGIC;
  signal gthe2_i_n_203 : STD_LOGIC;
  signal gthe2_i_n_204 : STD_LOGIC;
  signal gthe2_i_n_205 : STD_LOGIC;
  signal gthe2_i_n_206 : STD_LOGIC;
  signal gthe2_i_n_207 : STD_LOGIC;
  signal gthe2_i_n_208 : STD_LOGIC;
  signal gthe2_i_n_209 : STD_LOGIC;
  signal gthe2_i_n_210 : STD_LOGIC;
  signal gthe2_i_n_211 : STD_LOGIC;
  signal gthe2_i_n_218 : STD_LOGIC;
  signal gthe2_i_n_219 : STD_LOGIC;
  signal gthe2_i_n_226 : STD_LOGIC;
  signal gthe2_i_n_227 : STD_LOGIC;
  signal gthe2_i_n_234 : STD_LOGIC;
  signal gthe2_i_n_235 : STD_LOGIC;
  signal gthe2_i_n_242 : STD_LOGIC;
  signal gthe2_i_n_243 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_34 : STD_LOGIC;
  signal gthe2_i_n_38 : STD_LOGIC;
  signal gthe2_i_n_4 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_57 : STD_LOGIC;
  signal gthe2_i_n_58 : STD_LOGIC;
  signal gthe2_i_n_59 : STD_LOGIC;
  signal gthe2_i_n_60 : STD_LOGIC;
  signal gthe2_i_n_61 : STD_LOGIC;
  signal gthe2_i_n_62 : STD_LOGIC;
  signal gthe2_i_n_63 : STD_LOGIC;
  signal gthe2_i_n_64 : STD_LOGIC;
  signal gthe2_i_n_65 : STD_LOGIC;
  signal gthe2_i_n_66 : STD_LOGIC;
  signal gthe2_i_n_67 : STD_LOGIC;
  signal gthe2_i_n_68 : STD_LOGIC;
  signal gthe2_i_n_69 : STD_LOGIC;
  signal gthe2_i_n_70 : STD_LOGIC;
  signal gthe2_i_n_71 : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt2_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt2_cplllock_out <= \^gt2_cplllock_out\;
  gt2_txbufstatus_out(1 downto 0) <= \^gt2_txbufstatus_out\(1 downto 0);
TX_LOCK_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^gt2_cplllock_out\,
      I1 => gt3_cplllock_out,
      I2 => gt0_cplllock_out,
      I3 => gt1_cplllock_out,
      O => TX_LOCK
    );
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2_reg_n_0,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
\flag2_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => \flag2_i_1__0_n_0\
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag2_i_1__0_n_0\,
      Q => flag2_reg_n_0,
      R => flag2_reg_0
    );
\flag_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => \flag_i_1__1_n_0\
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag_i_1__1_n_0\,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => \^gt2_cplllock_out\,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT2_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14) => gthe2_i_n_57,
      DMONITOROUT(13) => gthe2_i_n_58,
      DMONITOROUT(12) => gthe2_i_n_59,
      DMONITOROUT(11) => gthe2_i_n_60,
      DMONITOROUT(10) => gthe2_i_n_61,
      DMONITOROUT(9) => gthe2_i_n_62,
      DMONITOROUT(8) => gthe2_i_n_63,
      DMONITOROUT(7) => gthe2_i_n_64,
      DMONITOROUT(6) => gthe2_i_n_65,
      DMONITOROUT(5) => gthe2_i_n_66,
      DMONITOROUT(4) => gthe2_i_n_67,
      DMONITOROUT(3) => gthe2_i_n_68,
      DMONITOROUT(2) => gthe2_i_n_69,
      DMONITOROUT(1) => gthe2_i_n_70,
      DMONITOROUT(0) => gthe2_i_n_71,
      DRPADDR(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPEN => DRPEN_IN_LANE2,
      DRPRDY => DRPRDY_OUT_LANE2,
      DRPWE => DRPWE_IN_LANE2,
      EYESCANDATAERROR => gthe2_i_n_4,
      EYESCANMODE => '0',
      EYESCANRESET => '0',
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTHRXN => '0',
      GTHRXP => '0',
      GTHTXN => TXN(0),
      GTHTXP => TXP(0),
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => gt_tx_reset_i,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad5_in,
      QPLLREFCLK => gt_qpllrefclk_quad5_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2) => gthe2_i_n_114,
      RXBUFSTATUS(1) => gthe2_i_n_115,
      RXBUFSTATUS(0) => gthe2_i_n_116,
      RXBYTEISALIGNED => gthe2_i_n_10,
      RXBYTEREALIGN => gthe2_i_n_11,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => gthe2_i_n_14,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1) => gthe2_i_n_218,
      RXCHARISCOMMA(0) => gthe2_i_n_219,
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1) => gthe2_i_n_226,
      RXCHARISK(0) => gthe2_i_n_227,
      RXCHBONDEN => '1',
      RXCHBONDI(4 downto 0) => gt2_cplllock_out_0(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"001",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gthe2_i_n_17,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15) => gthe2_i_n_189,
      RXDATA(14) => gthe2_i_n_190,
      RXDATA(13) => gthe2_i_n_191,
      RXDATA(12) => gthe2_i_n_192,
      RXDATA(11) => gthe2_i_n_193,
      RXDATA(10) => gthe2_i_n_194,
      RXDATA(9) => gthe2_i_n_195,
      RXDATA(8) => gthe2_i_n_196,
      RXDATA(7) => gthe2_i_n_197,
      RXDATA(6) => gthe2_i_n_198,
      RXDATA(5) => gthe2_i_n_199,
      RXDATA(4) => gthe2_i_n_200,
      RXDATA(3) => gthe2_i_n_201,
      RXDATA(2) => gthe2_i_n_202,
      RXDATA(1) => gthe2_i_n_203,
      RXDATA(0) => gthe2_i_n_204,
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => gt_rxdfeagchold_i,
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => gt_rxdfelfhold_i,
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1) => gthe2_i_n_234,
      RXDISPERR(0) => gthe2_i_n_235,
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '0',
      RXMONITOROUT(6) => gthe2_i_n_205,
      RXMONITOROUT(5) => gthe2_i_n_206,
      RXMONITOROUT(4) => gthe2_i_n_207,
      RXMONITOROUT(3) => gthe2_i_n_208,
      RXMONITOROUT(2) => gthe2_i_n_209,
      RXMONITOROUT(1) => gthe2_i_n_210,
      RXMONITOROUT(0) => gthe2_i_n_211,
      RXMONITORSEL(1 downto 0) => B"00",
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1) => gthe2_i_n_242,
      RXNOTINTABLE(0) => gthe2_i_n_243,
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '0',
      RXPCSRESET => '0',
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => gthe2_i_n_34,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gthe2_i_n_38,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \^gt2_txbufstatus_out\(1 downto 0),
      TXCHARDISPMODE(7 downto 2) => B"000000",
      TXCHARDISPMODE(1 downto 0) => gt2_txchardispmode_in(1 downto 0),
      TXCHARDISPVAL(7 downto 2) => B"000000",
      TXCHARDISPVAL(1 downto 0) => gt2_txchardispval_in(1 downto 0),
      TXCHARISK(7 downto 2) => B"000000",
      TXCHARISK(1 downto 0) => gt2_cplllock_out_2(1 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000",
      TXDATA(15 downto 0) => gt2_cplllock_out_1(15 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => gt2_txdiffctrl_in(3 downto 0),
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => POWER_DOWN,
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => gt2_txinhibit_in,
      TXMAINCURSOR(6 downto 0) => gt2_txmaincursor_in(6 downto 0),
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => TX_OUT_CLK,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => gt2_txpcsreset_in,
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => gt2_txpmareset_in,
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => gt2_txpolarity_in,
      TXPOSTCURSOR(4 downto 0) => gt2_txpostcursor_in(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => gt2_txprbsforceerr_in,
      TXPRBSSEL(2 downto 0) => gt2_txprbssel_in(2 downto 0),
      TXPRECURSOR(4 downto 0) => gt2_txprecursor_in(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt2_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => gt_txuserrdy_i,
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
\hard_err_flop_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt2_txbufstatus_out\(1),
      I1 => ENABLE_ERR_DETECT_1,
      O => ENABLE_ERR_DETECT_Buffer_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_gt_22 is
  port (
    gt3_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    TXN : out STD_LOGIC_VECTOR ( 0 to 0 );
    TXP : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt3_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_tx_reset_i : in STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    gt_rxdfeagchold_i : in STD_LOGIC;
    gt_rxdfelfhold_i : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    gt3_txinhibit_in : in STD_LOGIC;
    gt3_txpcsreset_in : in STD_LOGIC;
    gt3_txpmareset_in : in STD_LOGIC;
    gt3_txpolarity_in : in STD_LOGIC;
    gt3_txprbsforceerr_in : in STD_LOGIC;
    gt_txuserrdy_i : in STD_LOGIC;
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    ENABLE_ERR_DETECT_2 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_gt_22 : entity is "efex_aurora_hub2_gt";
end efex_aurora_hub2_efex_aurora_hub2_gt_22;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_gt_22 is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT3_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal \flag2_i_1__1_n_0\ : STD_LOGIC;
  signal flag2_reg_n_0 : STD_LOGIC;
  signal \flag_i_1__2_n_0\ : STD_LOGIC;
  signal \^gt3_txbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_10 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_11 : STD_LOGIC;
  signal gthe2_i_n_114 : STD_LOGIC;
  signal gthe2_i_n_115 : STD_LOGIC;
  signal gthe2_i_n_116 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_120 : STD_LOGIC;
  signal gthe2_i_n_121 : STD_LOGIC;
  signal gthe2_i_n_122 : STD_LOGIC;
  signal gthe2_i_n_123 : STD_LOGIC;
  signal gthe2_i_n_124 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_14 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_17 : STD_LOGIC;
  signal gthe2_i_n_189 : STD_LOGIC;
  signal gthe2_i_n_190 : STD_LOGIC;
  signal gthe2_i_n_191 : STD_LOGIC;
  signal gthe2_i_n_192 : STD_LOGIC;
  signal gthe2_i_n_193 : STD_LOGIC;
  signal gthe2_i_n_194 : STD_LOGIC;
  signal gthe2_i_n_195 : STD_LOGIC;
  signal gthe2_i_n_196 : STD_LOGIC;
  signal gthe2_i_n_197 : STD_LOGIC;
  signal gthe2_i_n_198 : STD_LOGIC;
  signal gthe2_i_n_199 : STD_LOGIC;
  signal gthe2_i_n_200 : STD_LOGIC;
  signal gthe2_i_n_201 : STD_LOGIC;
  signal gthe2_i_n_202 : STD_LOGIC;
  signal gthe2_i_n_203 : STD_LOGIC;
  signal gthe2_i_n_204 : STD_LOGIC;
  signal gthe2_i_n_205 : STD_LOGIC;
  signal gthe2_i_n_206 : STD_LOGIC;
  signal gthe2_i_n_207 : STD_LOGIC;
  signal gthe2_i_n_208 : STD_LOGIC;
  signal gthe2_i_n_209 : STD_LOGIC;
  signal gthe2_i_n_210 : STD_LOGIC;
  signal gthe2_i_n_211 : STD_LOGIC;
  signal gthe2_i_n_218 : STD_LOGIC;
  signal gthe2_i_n_219 : STD_LOGIC;
  signal gthe2_i_n_226 : STD_LOGIC;
  signal gthe2_i_n_227 : STD_LOGIC;
  signal gthe2_i_n_234 : STD_LOGIC;
  signal gthe2_i_n_235 : STD_LOGIC;
  signal gthe2_i_n_242 : STD_LOGIC;
  signal gthe2_i_n_243 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_34 : STD_LOGIC;
  signal gthe2_i_n_38 : STD_LOGIC;
  signal gthe2_i_n_4 : STD_LOGIC;
  signal gthe2_i_n_45 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_57 : STD_LOGIC;
  signal gthe2_i_n_58 : STD_LOGIC;
  signal gthe2_i_n_59 : STD_LOGIC;
  signal gthe2_i_n_60 : STD_LOGIC;
  signal gthe2_i_n_61 : STD_LOGIC;
  signal gthe2_i_n_62 : STD_LOGIC;
  signal gthe2_i_n_63 : STD_LOGIC;
  signal gthe2_i_n_64 : STD_LOGIC;
  signal gthe2_i_n_65 : STD_LOGIC;
  signal gthe2_i_n_66 : STD_LOGIC;
  signal gthe2_i_n_67 : STD_LOGIC;
  signal gthe2_i_n_68 : STD_LOGIC;
  signal gthe2_i_n_69 : STD_LOGIC;
  signal gthe2_i_n_70 : STD_LOGIC;
  signal gthe2_i_n_71 : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/efex_aurora_hub2_multi_gt_i/gt3_efex_aurora_hub2_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt3_txbufstatus_out(1 downto 0) <= \^gt3_txbufstatus_out\(1 downto 0);
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2_reg_n_0,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
\flag2_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => \flag2_i_1__1_n_0\
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag2_i_1__1_n_0\,
      Q => flag2_reg_n_0,
      R => flag2_reg_0
    );
\flag_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => \flag_i_1__2_n_0\
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag_i_1__2_n_0\,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => gt3_cplllock_out,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT3_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14) => gthe2_i_n_57,
      DMONITOROUT(13) => gthe2_i_n_58,
      DMONITOROUT(12) => gthe2_i_n_59,
      DMONITOROUT(11) => gthe2_i_n_60,
      DMONITOROUT(10) => gthe2_i_n_61,
      DMONITOROUT(9) => gthe2_i_n_62,
      DMONITOROUT(8) => gthe2_i_n_63,
      DMONITOROUT(7) => gthe2_i_n_64,
      DMONITOROUT(6) => gthe2_i_n_65,
      DMONITOROUT(5) => gthe2_i_n_66,
      DMONITOROUT(4) => gthe2_i_n_67,
      DMONITOROUT(3) => gthe2_i_n_68,
      DMONITOROUT(2) => gthe2_i_n_69,
      DMONITOROUT(1) => gthe2_i_n_70,
      DMONITOROUT(0) => gthe2_i_n_71,
      DRPADDR(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN => DRPEN_IN_LANE3,
      DRPRDY => DRPRDY_OUT_LANE3,
      DRPWE => DRPWE_IN_LANE3,
      EYESCANDATAERROR => gthe2_i_n_4,
      EYESCANMODE => '0',
      EYESCANRESET => '0',
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTHRXN => '0',
      GTHRXP => '0',
      GTHTXN => TXN(0),
      GTHTXP => TXP(0),
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => gt_tx_reset_i,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad5_in,
      QPLLREFCLK => gt_qpllrefclk_quad5_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2) => gthe2_i_n_114,
      RXBUFSTATUS(1) => gthe2_i_n_115,
      RXBUFSTATUS(0) => gthe2_i_n_116,
      RXBYTEISALIGNED => gthe2_i_n_10,
      RXBYTEREALIGN => gthe2_i_n_11,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => gthe2_i_n_14,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1) => gthe2_i_n_218,
      RXCHARISCOMMA(0) => gthe2_i_n_219,
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1) => gthe2_i_n_226,
      RXCHARISK(0) => gthe2_i_n_227,
      RXCHBONDEN => '1',
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => gthe2_i_n_120,
      RXCHBONDO(3) => gthe2_i_n_121,
      RXCHBONDO(2) => gthe2_i_n_122,
      RXCHBONDO(1) => gthe2_i_n_123,
      RXCHBONDO(0) => gthe2_i_n_124,
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gthe2_i_n_17,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15) => gthe2_i_n_189,
      RXDATA(14) => gthe2_i_n_190,
      RXDATA(13) => gthe2_i_n_191,
      RXDATA(12) => gthe2_i_n_192,
      RXDATA(11) => gthe2_i_n_193,
      RXDATA(10) => gthe2_i_n_194,
      RXDATA(9) => gthe2_i_n_195,
      RXDATA(8) => gthe2_i_n_196,
      RXDATA(7) => gthe2_i_n_197,
      RXDATA(6) => gthe2_i_n_198,
      RXDATA(5) => gthe2_i_n_199,
      RXDATA(4) => gthe2_i_n_200,
      RXDATA(3) => gthe2_i_n_201,
      RXDATA(2) => gthe2_i_n_202,
      RXDATA(1) => gthe2_i_n_203,
      RXDATA(0) => gthe2_i_n_204,
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => gt_rxdfeagchold_i,
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => gt_rxdfelfhold_i,
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1) => gthe2_i_n_234,
      RXDISPERR(0) => gthe2_i_n_235,
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '0',
      RXMONITOROUT(6) => gthe2_i_n_205,
      RXMONITOROUT(5) => gthe2_i_n_206,
      RXMONITOROUT(4) => gthe2_i_n_207,
      RXMONITOROUT(3) => gthe2_i_n_208,
      RXMONITOROUT(2) => gthe2_i_n_209,
      RXMONITOROUT(1) => gthe2_i_n_210,
      RXMONITOROUT(0) => gthe2_i_n_211,
      RXMONITORSEL(1 downto 0) => B"00",
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1) => gthe2_i_n_242,
      RXNOTINTABLE(0) => gthe2_i_n_243,
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '0',
      RXPCSRESET => '0',
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => gthe2_i_n_34,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gthe2_i_n_38,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \^gt3_txbufstatus_out\(1 downto 0),
      TXCHARDISPMODE(7 downto 2) => B"000000",
      TXCHARDISPMODE(1 downto 0) => gt3_txchardispmode_in(1 downto 0),
      TXCHARDISPVAL(7 downto 2) => B"000000",
      TXCHARDISPVAL(1 downto 0) => gt3_txchardispval_in(1 downto 0),
      TXCHARISK(7 downto 2) => B"000000",
      TXCHARISK(1 downto 0) => gt3_cplllock_out_1(1 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000",
      TXDATA(15 downto 0) => gt3_cplllock_out_0(15 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => gt3_txdiffctrl_in(3 downto 0),
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => POWER_DOWN,
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => gt3_txinhibit_in,
      TXMAINCURSOR(6 downto 0) => gt3_txmaincursor_in(6 downto 0),
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gthe2_i_n_45,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => gt3_txpcsreset_in,
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => gt3_txpmareset_in,
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => gt3_txpolarity_in,
      TXPOSTCURSOR(4 downto 0) => gt3_txpostcursor_in(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => gt3_txprbsforceerr_in,
      TXPRBSSEL(2 downto 0) => gt3_txprbssel_in(2 downto 0),
      TXPRECURSOR(4 downto 0) => gt3_txprecursor_in(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt3_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => gt_txuserrdy_i,
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
\hard_err_flop_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt3_txbufstatus_out\(1),
      I1 => ENABLE_ERR_DETECT_2,
      O => ENABLE_ERR_DETECT_Buffer_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC is
  port (
    SYSTEM_RESET_reg_0 : out STD_LOGIC;
    wait_for_lane_up_r0 : out STD_LOGIC;
    new_pkt_r : out STD_LOGIC;
    RESET_SYMGEN : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    TX_LOCK : in STD_LOGIC;
    gt_txresetdone_r2_reg_0 : in STD_LOGIC;
    tx_reset_simplex_r : in STD_LOGIC;
    reset_channel_i : in STD_LOGIC;
    TX_CHANNEL_UP : in STD_LOGIC;
    S_AXI_TX_TLAST : in STD_LOGIC;
    S_AXI_TX_TVALID : in STD_LOGIC;
    tx_dst_rdy : in STD_LOGIC;
    new_pkt_r_reg : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC : entity is "efex_aurora_hub2_RESET_LOGIC";
end efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC is
  signal \^reset_symgen\ : STD_LOGIC;
  signal SYSTEM_RESET0_n_0 : STD_LOGIC;
  signal \^system_reset_reg_0\ : STD_LOGIC;
  signal gt_txresetdone_r : STD_LOGIC;
  signal gt_txresetdone_r2 : STD_LOGIC;
  signal gt_txresetdone_r3 : STD_LOGIC;
  signal scndry_out : STD_LOGIC;
  signal tx_lock_comb_r : STD_LOGIC;
  signal tx_lock_sync : STD_LOGIC;
begin
  RESET_SYMGEN <= \^reset_symgen\;
  SYSTEM_RESET_reg_0 <= \^system_reset_reg_0\;
SYSTEM_RESET0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => tx_lock_sync,
      I1 => \out\,
      I2 => gt_txresetdone_r3,
      I3 => scndry_out,
      O => SYSTEM_RESET0_n_0
    );
SYSTEM_RESET_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => SYSTEM_RESET0_n_0,
      Q => \^system_reset_reg_0\,
      R => '0'
    );
gt_txresetdone_r2_reg: unisim.vcomponents.FDCE
     port map (
      C => user_clk,
      CE => '1',
      CLR => gt_txresetdone_r2_reg_0,
      D => gt_txresetdone_r,
      Q => gt_txresetdone_r2
    );
gt_txresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt_txresetdone_r2,
      Q => gt_txresetdone_r3,
      R => '0'
    );
gt_txresetdone_r_reg: unisim.vcomponents.FDCE
     port map (
      C => user_clk,
      CE => '1',
      CLR => gt_txresetdone_r2_reg_0,
      D => '1',
      Q => gt_txresetdone_r
    );
lfsr_last_flop_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_reset_simplex_r,
      I1 => \^system_reset_reg_0\,
      O => \^reset_symgen\
    );
link_reset_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23\
     port map (
      init_clk_in => init_clk_in,
      \out\ => scndry_out,
      user_clk => user_clk
    );
new_pkt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444044400000400"
    )
        port map (
      I0 => \^reset_symgen\,
      I1 => TX_CHANNEL_UP,
      I2 => S_AXI_TX_TLAST,
      I3 => S_AXI_TX_TVALID,
      I4 => tx_dst_rdy,
      I5 => new_pkt_r_reg,
      O => new_pkt_r
    );
tx_lock_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24\
     port map (
      init_clk_in => init_clk_in,
      \out\ => tx_lock_sync,
      tx_lock_comb_r => tx_lock_comb_r,
      user_clk => user_clk
    );
tx_lock_comb_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => TX_LOCK,
      Q => tx_lock_comb_r,
      R => '0'
    );
wait_for_lane_up_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^system_reset_reg_0\,
      I1 => tx_reset_simplex_r,
      I2 => reset_channel_i,
      O => wait_for_lane_up_r0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    TXCHARISK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    tx_aligned_r : out STD_LOGIC;
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_pe_data_v_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    GEN_CC : in STD_LOGIC;
    gen_suf_i : in STD_LOGIC;
    gen_scp_i : in STD_LOGIC;
    GEN_A : in STD_LOGIC;
    tx_aligned_simplex_r : in STD_LOGIC;
    hard_err_flop_r_reg : in STD_LOGIC;
    \fc_nb_r_reg[0]\ : in STD_LOGIC;
    \fc_nb_r_reg[1]\ : in STD_LOGIC;
    \fc_nb_r_reg[2]\ : in STD_LOGIC;
    \gen_v_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5 : entity is "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5";
end efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5 is
  signal \^enable_err_detect\ : STD_LOGIC;
  signal send_sp_c : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_3 : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_5 : STD_LOGIC;
begin
  ENABLE_ERR_DETECT <= \^enable_err_detect\;
sym_gen_i: entity work.efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_3,
      D(0) => send_sp_c,
      GEN_A => GEN_A,
      GEN_CC => GEN_CC,
      Q(0) => Q(0),
      TXCHARISK(1 downto 0) => TXCHARISK(1 downto 0),
      TXDATA(15 downto 0) => TXDATA(15 downto 0),
      \fc_nb_r_reg[0]_0\ => \fc_nb_r_reg[0]\,
      \fc_nb_r_reg[1]_0\ => \fc_nb_r_reg[1]\,
      \fc_nb_r_reg[2]_0\ => \fc_nb_r_reg[2]\,
      gen_k_fsm_r_reg_0 => tx_lane_init_simplex_sm_i_n_5,
      \gen_k_r_reg[0]_0\(1 downto 0) => \gen_k_r_reg[0]\(1 downto 0),
      \gen_r_r_reg[0]_0\(1 downto 0) => \gen_r_r_reg[0]\(1 downto 0),
      gen_scp_i => gen_scp_i,
      gen_suf_i => gen_suf_i,
      \gen_v_r_reg[0]_0\(1 downto 0) => \gen_v_r_reg[0]\(1 downto 0),
      \tx_pe_data_r_reg[0]_0\(15 downto 0) => \tx_pe_data_r_reg[0]\(15 downto 0),
      tx_pe_data_v_r_reg_0(0) => tx_pe_data_v_r_reg(0),
      user_clk => user_clk
    );
tx_err_detect_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11
     port map (
      D(0) => D(0),
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      hard_err_flop_r_reg_0 => hard_err_flop_r_reg,
      hard_err_reset_i => hard_err_reset_i,
      user_clk => user_clk
    );
tx_lane_init_simplex_sm_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_3,
      D(0) => send_sp_c,
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      RESET => RESET,
      SS(0) => SS(0),
      TX_LANE_UP(0) => TX_LANE_UP(0),
      odd_word_r_reg_0 => tx_lane_init_simplex_sm_i_n_5,
      tx_aligned_r => tx_aligned_r,
      tx_aligned_simplex_r => tx_aligned_simplex_r,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TX_CHAR_IS_K_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TX_DATA_Buffer_reg[7]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    lane_up_flop_i : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_pe_data_v_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_cc_r_reg : in STD_LOGIC;
    gen_a_r_reg : in STD_LOGIC;
    hard_err_flop_r_reg : in STD_LOGIC;
    tx_aligned_r : in STD_LOGIC;
    \gen_v_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1 : entity is "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5";
end efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1 is
  signal \^enable_err_detect\ : STD_LOGIC;
  signal send_sp_c : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_2 : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_4 : STD_LOGIC;
begin
  ENABLE_ERR_DETECT <= \^enable_err_detect\;
sym_gen_i: entity work.efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_2,
      D(0) => send_sp_c,
      Q(0) => Q(0),
      \TX_CHAR_IS_K_Buffer_reg[0]_0\(1 downto 0) => \TX_CHAR_IS_K_Buffer_reg[0]\(1 downto 0),
      \TX_DATA_Buffer_reg[7]_0\(15 downto 0) => \TX_DATA_Buffer_reg[7]\(15 downto 0),
      gen_a_r_reg_0 => gen_a_r_reg,
      gen_cc_r_reg_0 => gen_cc_r_reg,
      gen_k_fsm_r_reg_0 => tx_lane_init_simplex_sm_i_n_4,
      \gen_k_r_reg[0]_0\(1 downto 0) => \gen_k_r_reg[0]\(1 downto 0),
      \gen_r_r_reg[0]_0\(1 downto 0) => \gen_r_r_reg[0]\(1 downto 0),
      \gen_v_r_reg[0]_0\(1 downto 0) => \gen_v_r_reg[0]\(1 downto 0),
      \tx_pe_data_r_reg[0]_0\(15 downto 0) => \tx_pe_data_r_reg[0]\(15 downto 0),
      tx_pe_data_v_r_reg_0(0) => tx_pe_data_v_r_reg(0),
      user_clk => user_clk
    );
tx_err_detect_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8
     port map (
      D(0) => D(0),
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      hard_err_flop_r_reg_0 => hard_err_flop_r_reg,
      hard_err_reset_i => hard_err_reset_i,
      user_clk => user_clk
    );
tx_lane_init_simplex_sm_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_2,
      D(0) => send_sp_c,
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      SS(0) => SS(0),
      TX_LANE_UP(0) => TX_LANE_UP(0),
      lane_up_flop_i_0 => lane_up_flop_i,
      odd_word_r_reg_0 => tx_lane_init_simplex_sm_i_n_4,
      tx_aligned_r => tx_aligned_r,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TX_CHAR_IS_K_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TX_DATA_Buffer_reg[7]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    lane_up_flop_i : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_pe_data_v_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_cc_r_reg : in STD_LOGIC;
    gen_a_r_reg : in STD_LOGIC;
    hard_err_flop_r_reg : in STD_LOGIC;
    tx_aligned_r : in STD_LOGIC;
    \gen_v_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2 : entity is "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5";
end efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2 is
  signal \^enable_err_detect\ : STD_LOGIC;
  signal send_sp_c : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_2 : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_4 : STD_LOGIC;
begin
  ENABLE_ERR_DETECT <= \^enable_err_detect\;
sym_gen_i: entity work.efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_2,
      D(0) => send_sp_c,
      Q(0) => Q(0),
      \TX_CHAR_IS_K_Buffer_reg[0]_0\(1 downto 0) => \TX_CHAR_IS_K_Buffer_reg[0]\(1 downto 0),
      \TX_DATA_Buffer_reg[7]_0\(15 downto 0) => \TX_DATA_Buffer_reg[7]\(15 downto 0),
      gen_a_r_reg_0 => gen_a_r_reg,
      gen_cc_r_reg_0 => gen_cc_r_reg,
      gen_k_fsm_r_reg_0 => tx_lane_init_simplex_sm_i_n_4,
      \gen_k_r_reg[0]_0\(1 downto 0) => \gen_k_r_reg[0]\(1 downto 0),
      \gen_r_r_reg[0]_0\(1 downto 0) => \gen_r_r_reg[0]\(1 downto 0),
      \gen_v_r_reg[0]_0\(1 downto 0) => \gen_v_r_reg[0]\(1 downto 0),
      \tx_pe_data_r_reg[0]_0\(15 downto 0) => \tx_pe_data_r_reg[0]\(15 downto 0),
      tx_pe_data_v_r_reg_0(0) => tx_pe_data_v_r_reg(0),
      user_clk => user_clk
    );
tx_err_detect_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5
     port map (
      D(0) => D(0),
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      hard_err_flop_r_reg_0 => hard_err_flop_r_reg,
      hard_err_reset_i => hard_err_reset_i,
      user_clk => user_clk
    );
tx_lane_init_simplex_sm_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_2,
      D(0) => send_sp_c,
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      SS(0) => SS(0),
      TX_LANE_UP(0) => TX_LANE_UP(0),
      lane_up_flop_i_0 => lane_up_flop_i,
      odd_word_r_reg_0 => tx_lane_init_simplex_sm_i_n_4,
      tx_aligned_r => tx_aligned_r,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3 is
  port (
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TX_CHAR_IS_K_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT : out STD_LOGIC;
    hard_err_reset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TX_DATA_Buffer_reg[7]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    lane_up_flop_i : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_pe_data_v_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    gen_cc_r_reg : in STD_LOGIC;
    gen_ecp_i : in STD_LOGIC;
    gen_a_r_reg : in STD_LOGIC;
    hard_err_flop_r_reg : in STD_LOGIC;
    tx_aligned_r : in STD_LOGIC;
    \gen_v_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_r_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_k_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tx_pe_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3 : entity is "efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5";
end efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3 is
  signal \^enable_err_detect\ : STD_LOGIC;
  signal send_sp_c : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_2 : STD_LOGIC;
  signal tx_lane_init_simplex_sm_i_n_4 : STD_LOGIC;
begin
  ENABLE_ERR_DETECT <= \^enable_err_detect\;
sym_gen_i: entity work.efex_aurora_hub2_efex_aurora_hub2_SYM_GEN
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_2,
      D(0) => send_sp_c,
      Q(0) => Q(0),
      \TX_CHAR_IS_K_Buffer_reg[0]_0\(1 downto 0) => \TX_CHAR_IS_K_Buffer_reg[0]\(1 downto 0),
      \TX_DATA_Buffer_reg[7]_0\(15 downto 0) => \TX_DATA_Buffer_reg[7]\(15 downto 0),
      gen_a_r_reg_0 => gen_a_r_reg,
      gen_cc_r_reg_0 => gen_cc_r_reg,
      gen_ecp_i => gen_ecp_i,
      gen_k_fsm_r_reg_0 => tx_lane_init_simplex_sm_i_n_4,
      \gen_k_r_reg[0]_0\(1 downto 0) => \gen_k_r_reg[0]\(1 downto 0),
      \gen_r_r_reg[0]_0\(1 downto 0) => \gen_r_r_reg[0]\(1 downto 0),
      \gen_v_r_reg[0]_0\(1 downto 0) => \gen_v_r_reg[0]\(1 downto 0),
      \tx_pe_data_r_reg[0]_0\(15 downto 0) => \tx_pe_data_r_reg[0]\(15 downto 0),
      tx_pe_data_v_r_reg_0(0) => tx_pe_data_v_r_reg(0),
      user_clk => user_clk
    );
tx_err_detect_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX
     port map (
      D(0) => D(0),
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      hard_err_flop_r_reg_0 => hard_err_flop_r_reg,
      hard_err_reset_i => hard_err_reset_i,
      user_clk => user_clk
    );
tx_lane_init_simplex_sm_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX
     port map (
      D(1) => tx_lane_init_simplex_sm_i_n_2,
      D(0) => send_sp_c,
      ENABLE_ERR_DETECT => \^enable_err_detect\,
      SS(0) => SS(0),
      TX_LANE_UP(0) => TX_LANE_UP(0),
      lane_up_flop_i_0 => lane_up_flop_i,
      odd_word_r_reg_0 => tx_lane_init_simplex_sm_i_n_4,
      tx_aligned_r => tx_aligned_r,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX is
  port (
    TX_CHANNEL_UP : out STD_LOGIC;
    RESET : out STD_LOGIC;
    reset_lanes_flop_1_i : out STD_LOGIC;
    reset_lanes_flop_2_i : out STD_LOGIC;
    reset_lanes_flop_3_i : out STD_LOGIC;
    gen_v_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_v_flop_2_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_v_flop_4_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_v_flop_6_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GEN_A : out STD_LOGIC;
    gen_a_flop_1_i : out STD_LOGIC;
    gen_a_flop_2_i : out STD_LOGIC;
    gen_a_flop_3_i : out STD_LOGIC;
    gen_k_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_k_flop_2_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_k_flop_4_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_k_flop_6_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_2_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_4_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen_r_flop_6_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
    CHANNEL_HARD_ERR_Buffer_reg : out STD_LOGIC;
    reset_channel_i : out STD_LOGIC;
    tx_verify_simplex_r_reg : out STD_LOGIC;
    tx_bonded1_simplex_r_reg : out STD_LOGIC;
    tx_aligned_simplex_r_reg : out STD_LOGIC;
    tx_reset_simplex_r_reg : out STD_LOGIC;
    simplex_timer_r0 : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_1_i_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_2_i_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_3_i_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    tx_channel_up_i : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    RESET_SYMGEN : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    tx_verify_simplex_r : in STD_LOGIC;
    wait_for_lane_up_r0 : in STD_LOGIC;
    tx_verify_simplex_r_reg_0 : in STD_LOGIC;
    tx_bonded1_simplex_r_reg_0 : in STD_LOGIC;
    tx_verify_simplex_r_reg_1 : in STD_LOGIC;
    tx_bonded1_simplex_r : in STD_LOGIC;
    tx_bonded1_simplex_r_reg_1 : in STD_LOGIC;
    tx_bonded1_simplex_r_reg_2 : in STD_LOGIC;
    tx_aligned_simplex_r : in STD_LOGIC;
    tx_aligned_simplex_r_reg_0 : in STD_LOGIC;
    tx_aligned_simplex_r_reg_1 : in STD_LOGIC;
    tx_aligned_simplex_r_reg_2 : in STD_LOGIC;
    tx_reset_simplex_r : in STD_LOGIC;
    tx_reset_simplex_r_reg_0 : in STD_LOGIC;
    simplex_timer_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    hard_err_reset_i : in STD_LOGIC;
    hard_err_reset_i_0 : in STD_LOGIC;
    hard_err_reset_i_1 : in STD_LOGIC;
    hard_err_reset_i_2 : in STD_LOGIC;
    reset_lanes_flop_3_i_1 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    TX_LANE_UP : in STD_LOGIC_VECTOR ( 0 to 3 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX : entity is "efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX";
end efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX is
  signal gen_ver_i : STD_LOGIC;
  signal \^reset_channel_i\ : STD_LOGIC;
begin
  reset_channel_i <= \^reset_channel_i\;
idle_and_ver_gen_i: entity work.efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN
     port map (
      GEN_A => GEN_A,
      RESET_SYMGEN => RESET_SYMGEN,
      \downcounter_r_reg[0]_0\ => reset_lanes_flop_3_i_1,
      gen_a_flop_1_i_0 => gen_a_flop_1_i,
      gen_a_flop_2_i_0 => gen_a_flop_2_i,
      gen_a_flop_3_i_0 => gen_a_flop_3_i,
      gen_k_flop_0_i_0(1 downto 0) => gen_k_flop_0_i(1 downto 0),
      gen_k_flop_2_i_0(1 downto 0) => gen_k_flop_2_i(1 downto 0),
      gen_k_flop_4_i_0(1 downto 0) => gen_k_flop_4_i(1 downto 0),
      gen_k_flop_6_i_0(1 downto 0) => gen_k_flop_6_i(1 downto 0),
      gen_r_flop_0_i_0(1 downto 0) => gen_r_flop_0_i(1 downto 0),
      gen_r_flop_2_i_0(1 downto 0) => gen_r_flop_2_i(1 downto 0),
      gen_r_flop_4_i_0(1 downto 0) => gen_r_flop_4_i(1 downto 0),
      gen_r_flop_6_i_0(1 downto 0) => gen_r_flop_6_i(1 downto 0),
      gen_v_flop_0_i_0(1 downto 0) => gen_v_flop_0_i(1 downto 0),
      gen_v_flop_2_i_0(1 downto 0) => gen_v_flop_2_i(1 downto 0),
      gen_v_flop_4_i_0(1 downto 0) => gen_v_flop_4_i(1 downto 0),
      gen_v_flop_6_i_0(1 downto 0) => gen_v_flop_6_i(1 downto 0),
      gen_ver_i => gen_ver_i,
      tx_reset_simplex_r => tx_reset_simplex_r,
      user_clk => user_clk
    );
tx_channel_err_detect_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX
     port map (
      CHANNEL_HARD_ERR_Buffer_reg_0 => CHANNEL_HARD_ERR_Buffer_reg,
      D(3 downto 0) => D(3 downto 0),
      POWER_DOWN => POWER_DOWN,
      RESET_SYMGEN => RESET_SYMGEN,
      TX_LANE_UP(0 to 3) => TX_LANE_UP(0 to 3),
      reset_channel_i => \^reset_channel_i\,
      simplex_timer_r0 => simplex_timer_r0,
      simplex_timer_r_reg(2 downto 0) => simplex_timer_r_reg(2 downto 0),
      simplex_timer_r_reg_0_sp_1 => reset_lanes_flop_3_i_1,
      tx_aligned_simplex_r => tx_aligned_simplex_r,
      tx_aligned_simplex_r_reg => tx_aligned_simplex_r_reg,
      tx_aligned_simplex_r_reg_0 => tx_aligned_simplex_r_reg_0,
      tx_aligned_simplex_r_reg_1 => tx_aligned_simplex_r_reg_1,
      tx_aligned_simplex_r_reg_2 => tx_aligned_simplex_r_reg_2,
      tx_bonded1_simplex_r => tx_bonded1_simplex_r,
      tx_bonded1_simplex_r_reg => tx_bonded1_simplex_r_reg,
      tx_bonded1_simplex_r_reg_0 => tx_bonded1_simplex_r_reg_0,
      tx_bonded1_simplex_r_reg_1 => tx_bonded1_simplex_r_reg_1,
      tx_bonded1_simplex_r_reg_2 => tx_bonded1_simplex_r_reg_2,
      tx_reset_simplex_r => tx_reset_simplex_r,
      tx_reset_simplex_r_reg => tx_reset_simplex_r_reg,
      tx_reset_simplex_r_reg_0 => tx_reset_simplex_r_reg_0,
      tx_verify_simplex_r => tx_verify_simplex_r,
      tx_verify_simplex_r_reg => tx_verify_simplex_r_reg,
      tx_verify_simplex_r_reg_0 => tx_verify_simplex_r_reg_0,
      tx_verify_simplex_r_reg_1 => tx_verify_simplex_r_reg_1,
      user_clk => user_clk
    );
tx_channel_init_sm_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX
     port map (
      RESET => RESET,
      SS(0) => SS(0),
      TX_CHANNEL_UP => TX_CHANNEL_UP,
      gen_ver_i => gen_ver_i,
      hard_err_reset_i => hard_err_reset_i,
      hard_err_reset_i_0 => hard_err_reset_i_0,
      hard_err_reset_i_1 => hard_err_reset_i_1,
      hard_err_reset_i_2 => hard_err_reset_i_2,
      reset_channel_i => \^reset_channel_i\,
      reset_lanes_flop_1_i_0 => reset_lanes_flop_1_i,
      reset_lanes_flop_1_i_1(0) => reset_lanes_flop_1_i_0(0),
      reset_lanes_flop_2_i_0 => reset_lanes_flop_2_i,
      reset_lanes_flop_2_i_1(0) => reset_lanes_flop_2_i_0(0),
      reset_lanes_flop_3_i_0 => reset_lanes_flop_3_i,
      reset_lanes_flop_3_i_1(0) => reset_lanes_flop_3_i_0(0),
      reset_lanes_flop_3_i_2 => reset_lanes_flop_3_i_1,
      tx_bonded1_simplex_r => tx_bonded1_simplex_r,
      tx_channel_up_i_0 => tx_channel_up_i,
      tx_reset_simplex_r => tx_reset_simplex_r,
      tx_verify_simplex_r => tx_verify_simplex_r,
      user_clk => user_clk,
      wait_for_lane_up_r0 => wait_for_lane_up_r0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_TX_LL is
  port (
    GEN_CC : out STD_LOGIC;
    gen_cc_flop_1_i : out STD_LOGIC;
    gen_cc_flop_2_i : out STD_LOGIC;
    gen_cc_flop_3_i : out STD_LOGIC;
    tx_dst_rdy : out STD_LOGIC;
    ufc_header_r_reg : out STD_LOGIC;
    gen_scp_i : out STD_LOGIC;
    gen_ecp_i : out STD_LOGIC;
    gen_suf_i : out STD_LOGIC;
    \s_axi_ufc_tx_tdata[2]\ : out STD_LOGIC;
    \s_axi_ufc_tx_tdata[1]\ : out STD_LOGIC;
    \s_axi_ufc_tx_tdata[0]\ : out STD_LOGIC;
    S_AXI_TX_TREADY : out STD_LOGIC;
    \ufc_message_count_r_reg[2]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \GEN_PAD_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \TX_PE_DATA_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk : in STD_LOGIC;
    DO_CC_I : in STD_LOGIC;
    halt_c_pipeline_r_reg_inv : in STD_LOGIC;
    next_ufc_header_c : in STD_LOGIC;
    next_ufc_idle_c : in STD_LOGIC;
    S_AXI_UFC_TX_MS : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S_AXI_TX_TVALID : in STD_LOGIC;
    S_AXI_TX_TLAST : in STD_LOGIC;
    tx_sof_n_pipeline_r_reg : in STD_LOGIC;
    S_AXI_TX_TKEEP : in STD_LOGIC_VECTOR ( 7 downto 0 );
    WARN_CC : in STD_LOGIC;
    S_AXI_UFC_TX_REQ : in STD_LOGIC;
    S_AXI_TX_TDATA : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_TX_LL : entity is "efex_aurora_hub2_TX_LL";
end efex_aurora_hub2_efex_aurora_hub2_TX_LL;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_TX_LL is
  signal UFC_MESSAGE_Buffer0 : STD_LOGIC;
  signal \^tx_dst_rdy\ : STD_LOGIC;
  signal tx_ll_control_i_n_16 : STD_LOGIC;
  signal tx_ll_control_i_n_20 : STD_LOGIC;
  signal tx_ll_datapath_i_n_0 : STD_LOGIC;
  signal tx_ll_datapath_i_n_1 : STD_LOGIC;
  signal tx_rem : STD_LOGIC_VECTOR ( 0 to 0 );
  signal tx_sof : STD_LOGIC;
  signal ufc_message_i : STD_LOGIC_VECTOR ( 1 to 2 );
begin
  tx_dst_rdy <= \^tx_dst_rdy\;
tx_ll_control_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL
     port map (
      D(3) => tx_ll_control_i_n_16,
      D(2) => ufc_message_i(1),
      D(1) => ufc_message_i(2),
      D(0) => UFC_MESSAGE_Buffer0,
      DO_CC_I => DO_CC_I,
      GEN_CC => GEN_CC,
      GEN_SUF_Buffer_reg_0 => halt_c_pipeline_r_reg_inv,
      S_AXI_TX_TKEEP(7 downto 0) => S_AXI_TX_TKEEP(7 downto 0),
      S_AXI_TX_TLAST => S_AXI_TX_TLAST,
      S_AXI_TX_TREADY => S_AXI_TX_TREADY,
      S_AXI_TX_TVALID => S_AXI_TX_TVALID,
      S_AXI_UFC_TX_MS(2 downto 0) => S_AXI_UFC_TX_MS(2 downto 0),
      S_AXI_UFC_TX_REQ => S_AXI_UFC_TX_REQ,
      TX_DST_RDY_N_Buffer_reg_0 => \^tx_dst_rdy\,
      WARN_CC => WARN_CC,
      do_cc_r_reg_0 => tx_ll_control_i_n_20,
      gen_cc_flop_1_i_0 => gen_cc_flop_1_i,
      gen_cc_flop_2_i_0 => gen_cc_flop_2_i,
      gen_cc_flop_3_i_0 => gen_cc_flop_3_i,
      gen_ecp_i => gen_ecp_i,
      gen_scp_i => gen_scp_i,
      gen_suf_i => gen_suf_i,
      next_ufc_header_c => next_ufc_header_c,
      next_ufc_idle_c => next_ufc_idle_c,
      \s_axi_ufc_tx_tdata[0]\ => \s_axi_ufc_tx_tdata[0]\,
      \s_axi_ufc_tx_tdata[1]\ => \s_axi_ufc_tx_tdata[1]\,
      \s_axi_ufc_tx_tdata[2]\ => \s_axi_ufc_tx_tdata[2]\,
      tx_rem(0) => tx_rem(0),
      \tx_rem_pipeline_r_reg[0]\ => tx_ll_datapath_i_n_1,
      \tx_rem_pipeline_r_reg[0]_0\ => tx_ll_datapath_i_n_0,
      tx_sof => tx_sof,
      tx_sof_n_pipeline_r_reg => tx_sof_n_pipeline_r_reg,
      ufc_header_r_reg_0 => ufc_header_r_reg,
      \ufc_message_count_r_reg[2]_0\ => \ufc_message_count_r_reg[2]\,
      user_clk => user_clk
    );
tx_ll_datapath_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH
     port map (
      D(0) => tx_rem(0),
      \GEN_PAD_Buffer_reg[0]_0\(3 downto 0) => \GEN_PAD_Buffer_reg[0]\(3 downto 0),
      Q(3 downto 0) => Q(3 downto 0),
      S_AXI_TX_TDATA(63 downto 0) => S_AXI_TX_TDATA(63 downto 0),
      S_AXI_TX_TKEEP(7 downto 0) => S_AXI_TX_TKEEP(7 downto 0),
      S_AXI_TX_TLAST => S_AXI_TX_TLAST,
      S_AXI_TX_TVALID => S_AXI_TX_TVALID,
      \TX_PE_DATA_Buffer_reg[0]_0\(63 downto 0) => \TX_PE_DATA_Buffer_reg[0]\(63 downto 0),
      halt_c_pipeline_r_reg_inv_0 => halt_c_pipeline_r_reg_inv,
      halt_c_pipeline_r_reg_inv_1 => tx_ll_control_i_n_20,
      \s_axi_tx_tkeep[4]\ => tx_ll_datapath_i_n_0,
      \s_axi_tx_tkeep[5]\ => tx_ll_datapath_i_n_1,
      tx_dst_rdy => \^tx_dst_rdy\,
      tx_sof => tx_sof,
      \ufc_message_pipeline_r_reg[0]_0\(3) => tx_ll_control_i_n_16,
      \ufc_message_pipeline_r_reg[0]_0\(2) => ufc_message_i(1),
      \ufc_message_pipeline_r_reg[0]_0\(1) => ufc_message_i(2),
      \ufc_message_pipeline_r_reg[0]_0\(0) => UFC_MESSAGE_Buffer0,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_multi_gt is
  port (
    gt0_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    TXN : out STD_LOGIC_VECTOR ( 0 to 3 );
    TXP : out STD_LOGIC_VECTOR ( 0 to 3 );
    gt0_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_0 : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_1 : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_2 : out STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_tx_reset_i : in STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    gt0_txinhibit_in : in STD_LOGIC;
    gt0_txpcsreset_in : in STD_LOGIC;
    gt0_txpmareset_in : in STD_LOGIC;
    gt0_txpolarity_in : in STD_LOGIC;
    gt0_txprbsforceerr_in : in STD_LOGIC;
    gt_txuserrdy_i : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    TXCHARISK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    gt1_txinhibit_in : in STD_LOGIC;
    gt1_txpcsreset_in : in STD_LOGIC;
    gt1_txpmareset_in : in STD_LOGIC;
    gt1_txpolarity_in : in STD_LOGIC;
    gt1_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    gt2_txinhibit_in : in STD_LOGIC;
    gt2_txpcsreset_in : in STD_LOGIC;
    gt2_txpmareset_in : in STD_LOGIC;
    gt2_txpolarity_in : in STD_LOGIC;
    gt2_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    gt3_txinhibit_in : in STD_LOGIC;
    gt3_txpcsreset_in : in STD_LOGIC;
    gt3_txpmareset_in : in STD_LOGIC;
    gt3_txpolarity_in : in STD_LOGIC;
    gt3_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg : in STD_LOGIC;
    ENABLE_ERR_DETECT : in STD_LOGIC;
    ENABLE_ERR_DETECT_0 : in STD_LOGIC;
    ENABLE_ERR_DETECT_1 : in STD_LOGIC;
    ENABLE_ERR_DETECT_2 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_multi_gt : entity is "efex_aurora_hub2_multi_gt";
end efex_aurora_hub2_efex_aurora_hub2_multi_gt;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_multi_gt is
  signal chbondo_LANE1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal chbondo_LANE2 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^gt0_cplllock_out\ : STD_LOGIC;
  signal \^gt1_cplllock_out\ : STD_LOGIC;
  signal \^gt3_cplllock_out\ : STD_LOGIC;
  signal gt_rxdfeagchold_i : STD_LOGIC;
  signal gt_rxdfelfhold_i : STD_LOGIC;
  signal gt_rxuserrdy_i : STD_LOGIC;
begin
  gt0_cplllock_out <= \^gt0_cplllock_out\;
  gt1_cplllock_out <= \^gt1_cplllock_out\;
  gt3_cplllock_out <= \^gt3_cplllock_out\;
  gt_rxdfeagchold_i <= 'Z';
  gt_rxdfelfhold_i <= 'Z';
  gt_rxuserrdy_i <= 'Z';
gt0_efex_aurora_hub2_i: entity work.efex_aurora_hub2_efex_aurora_hub2_gt
     port map (
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPWE_IN => DRPWE_IN,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT,
      ENABLE_ERR_DETECT_Buffer_reg => ENABLE_ERR_DETECT_Buffer_reg,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE1(4 downto 0),
      TXCHARISK(1 downto 0) => TXCHARISK(1 downto 0),
      TXDATA(15 downto 0) => TXDATA(15 downto 0),
      TXN(0) => TXN(0),
      TXP(0) => TXP(0),
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      flag2_reg_0 => flag2_reg,
      gt0_cplllock_out => \^gt0_cplllock_out\,
      gt0_txbufstatus_out(1 downto 0) => gt0_txbufstatus_out(1 downto 0),
      gt0_txchardispmode_in(1 downto 0) => gt0_txchardispmode_in(1 downto 0),
      gt0_txchardispval_in(1 downto 0) => gt0_txchardispval_in(1 downto 0),
      gt0_txdiffctrl_in(3 downto 0) => gt0_txdiffctrl_in(3 downto 0),
      gt0_txinhibit_in => gt0_txinhibit_in,
      gt0_txmaincursor_in(6 downto 0) => gt0_txmaincursor_in(6 downto 0),
      gt0_txpcsreset_in => gt0_txpcsreset_in,
      gt0_txpmareset_in => gt0_txpmareset_in,
      gt0_txpolarity_in => gt0_txpolarity_in,
      gt0_txpostcursor_in(4 downto 0) => gt0_txpostcursor_in(4 downto 0),
      gt0_txprbsforceerr_in => gt0_txprbsforceerr_in,
      gt0_txprbssel_in(2 downto 0) => gt0_txprbssel_in(2 downto 0),
      gt0_txprecursor_in(4 downto 0) => gt0_txprecursor_in(4 downto 0),
      gt0_txresetdone_out => gt0_txresetdone_out,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      gt_rxdfeagchold_i => gt_rxdfeagchold_i,
      gt_rxdfelfhold_i => gt_rxdfelfhold_i,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gt_tx_reset_i => gt_tx_reset_i,
      gt_txuserrdy_i => gt_txuserrdy_i,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      user_clk => user_clk
    );
gt1_efex_aurora_hub2_i: entity work.efex_aurora_hub2_efex_aurora_hub2_gt_20
     port map (
      DRPADDR_IN_LANE1(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPEN_IN_LANE1 => DRPEN_IN_LANE1,
      DRPRDY_OUT_LANE1 => DRPRDY_OUT_LANE1,
      DRPWE_IN_LANE1 => DRPWE_IN_LANE1,
      ENABLE_ERR_DETECT_0 => ENABLE_ERR_DETECT_0,
      ENABLE_ERR_DETECT_Buffer_reg => ENABLE_ERR_DETECT_Buffer_reg_0,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE1(4 downto 0),
      TXN(0) => TXN(1),
      TXP(0) => TXP(1),
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      flag2_reg_0 => flag2_reg,
      gt1_cplllock_out => \^gt1_cplllock_out\,
      gt1_cplllock_out_0(15 downto 0) => gt1_cplllock_out_0(15 downto 0),
      gt1_cplllock_out_1(1 downto 0) => gt1_cplllock_out_1(1 downto 0),
      gt1_txbufstatus_out(1 downto 0) => gt1_txbufstatus_out(1 downto 0),
      gt1_txchardispmode_in(1 downto 0) => gt1_txchardispmode_in(1 downto 0),
      gt1_txchardispval_in(1 downto 0) => gt1_txchardispval_in(1 downto 0),
      gt1_txdiffctrl_in(3 downto 0) => gt1_txdiffctrl_in(3 downto 0),
      gt1_txinhibit_in => gt1_txinhibit_in,
      gt1_txmaincursor_in(6 downto 0) => gt1_txmaincursor_in(6 downto 0),
      gt1_txpcsreset_in => gt1_txpcsreset_in,
      gt1_txpmareset_in => gt1_txpmareset_in,
      gt1_txpolarity_in => gt1_txpolarity_in,
      gt1_txpostcursor_in(4 downto 0) => gt1_txpostcursor_in(4 downto 0),
      gt1_txprbsforceerr_in => gt1_txprbsforceerr_in,
      gt1_txprbssel_in(2 downto 0) => gt1_txprbssel_in(2 downto 0),
      gt1_txprecursor_in(4 downto 0) => gt1_txprecursor_in(4 downto 0),
      gt1_txresetdone_out => gt1_txresetdone_out,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      gt_rxdfeagchold_i => gt_rxdfeagchold_i,
      gt_rxdfelfhold_i => gt_rxdfelfhold_i,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gt_tx_reset_i => gt_tx_reset_i,
      gt_txuserrdy_i => gt_txuserrdy_i,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      user_clk => user_clk
    );
gt2_efex_aurora_hub2_i: entity work.efex_aurora_hub2_efex_aurora_hub2_gt_21
     port map (
      DRPADDR_IN_LANE2(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPEN_IN_LANE2 => DRPEN_IN_LANE2,
      DRPRDY_OUT_LANE2 => DRPRDY_OUT_LANE2,
      DRPWE_IN_LANE2 => DRPWE_IN_LANE2,
      ENABLE_ERR_DETECT_1 => ENABLE_ERR_DETECT_1,
      ENABLE_ERR_DETECT_Buffer_reg => ENABLE_ERR_DETECT_Buffer_reg_1,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE2(4 downto 0),
      TXN(0) => TXN(2),
      TXP(0) => TXP(2),
      TX_LOCK => TX_LOCK,
      TX_OUT_CLK => TX_OUT_CLK,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      flag2_reg_0 => flag2_reg,
      gt0_cplllock_out => \^gt0_cplllock_out\,
      gt1_cplllock_out => \^gt1_cplllock_out\,
      gt2_cplllock_out => gt2_cplllock_out,
      gt2_cplllock_out_0(4 downto 0) => chbondo_LANE1(4 downto 0),
      gt2_cplllock_out_1(15 downto 0) => gt2_cplllock_out_0(15 downto 0),
      gt2_cplllock_out_2(1 downto 0) => gt2_cplllock_out_1(1 downto 0),
      gt2_txbufstatus_out(1 downto 0) => gt2_txbufstatus_out(1 downto 0),
      gt2_txchardispmode_in(1 downto 0) => gt2_txchardispmode_in(1 downto 0),
      gt2_txchardispval_in(1 downto 0) => gt2_txchardispval_in(1 downto 0),
      gt2_txdiffctrl_in(3 downto 0) => gt2_txdiffctrl_in(3 downto 0),
      gt2_txinhibit_in => gt2_txinhibit_in,
      gt2_txmaincursor_in(6 downto 0) => gt2_txmaincursor_in(6 downto 0),
      gt2_txpcsreset_in => gt2_txpcsreset_in,
      gt2_txpmareset_in => gt2_txpmareset_in,
      gt2_txpolarity_in => gt2_txpolarity_in,
      gt2_txpostcursor_in(4 downto 0) => gt2_txpostcursor_in(4 downto 0),
      gt2_txprbsforceerr_in => gt2_txprbsforceerr_in,
      gt2_txprbssel_in(2 downto 0) => gt2_txprbssel_in(2 downto 0),
      gt2_txprecursor_in(4 downto 0) => gt2_txprecursor_in(4 downto 0),
      gt2_txresetdone_out => gt2_txresetdone_out,
      gt3_cplllock_out => \^gt3_cplllock_out\,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      gt_rxdfeagchold_i => gt_rxdfeagchold_i,
      gt_rxdfelfhold_i => gt_rxdfelfhold_i,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gt_tx_reset_i => gt_tx_reset_i,
      gt_txuserrdy_i => gt_txuserrdy_i,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      user_clk => user_clk
    );
gt3_efex_aurora_hub2_i: entity work.efex_aurora_hub2_efex_aurora_hub2_gt_22
     port map (
      DRPADDR_IN_LANE3(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN_IN_LANE3 => DRPEN_IN_LANE3,
      DRPRDY_OUT_LANE3 => DRPRDY_OUT_LANE3,
      DRPWE_IN_LANE3 => DRPWE_IN_LANE3,
      ENABLE_ERR_DETECT_2 => ENABLE_ERR_DETECT_2,
      ENABLE_ERR_DETECT_Buffer_reg => ENABLE_ERR_DETECT_Buffer_reg_2,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE2(4 downto 0),
      TXN(0) => TXN(3),
      TXP(0) => TXP(3),
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      flag2_reg_0 => flag2_reg,
      gt3_cplllock_out => \^gt3_cplllock_out\,
      gt3_cplllock_out_0(15 downto 0) => gt3_cplllock_out_0(15 downto 0),
      gt3_cplllock_out_1(1 downto 0) => gt3_cplllock_out_1(1 downto 0),
      gt3_txbufstatus_out(1 downto 0) => gt3_txbufstatus_out(1 downto 0),
      gt3_txchardispmode_in(1 downto 0) => gt3_txchardispmode_in(1 downto 0),
      gt3_txchardispval_in(1 downto 0) => gt3_txchardispval_in(1 downto 0),
      gt3_txdiffctrl_in(3 downto 0) => gt3_txdiffctrl_in(3 downto 0),
      gt3_txinhibit_in => gt3_txinhibit_in,
      gt3_txmaincursor_in(6 downto 0) => gt3_txmaincursor_in(6 downto 0),
      gt3_txpcsreset_in => gt3_txpcsreset_in,
      gt3_txpmareset_in => gt3_txpmareset_in,
      gt3_txpolarity_in => gt3_txpolarity_in,
      gt3_txpostcursor_in(4 downto 0) => gt3_txpostcursor_in(4 downto 0),
      gt3_txprbsforceerr_in => gt3_txprbsforceerr_in,
      gt3_txprbssel_in(2 downto 0) => gt3_txprbssel_in(2 downto 0),
      gt3_txprecursor_in(4 downto 0) => gt3_txprecursor_in(4 downto 0),
      gt3_txresetdone_out => gt3_txresetdone_out,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      gt_rxdfeagchold_i => gt_rxdfeagchold_i,
      gt_rxdfelfhold_i => gt_rxdfelfhold_i,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gt_tx_reset_i => gt_tx_reset_i,
      gt_txuserrdy_i => gt_txuserrdy_i,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm is
  port (
    \out\ : out STD_LOGIC;
    gt_tx_reset_i : out STD_LOGIC;
    cpll_reset_i : out STD_LOGIC;
    gt_txuserrdy_i : out STD_LOGIC;
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : out STD_LOGIC;
    CPLL_RESET_reg_0 : out STD_LOGIC;
    in0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    txfsm_txresetdone_r : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm : entity is "efex_aurora_hub2_tx_startup_fsm";
end efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm is
  signal CPLL_RESET_i_1_n_0 : STD_LOGIC;
  signal \FSM_sequential_tx_state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_9_n_0\ : STD_LOGIC;
  signal TXUSERRDY_i_1_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^cpll_reset_i\ : STD_LOGIC;
  signal \^gt_tx_reset_i\ : STD_LOGIC;
  signal \^gt_txuserrdy_i\ : STD_LOGIC;
  signal gttxreset_i_i_1_n_0 : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \init_wait_count[6]_i_3_n_0\ : STD_LOGIC;
  signal \init_wait_count[6]_i_4_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal init_wait_done_i_1_n_0 : STD_LOGIC;
  signal init_wait_done_i_2_n_0 : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_2_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_4_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal mmcm_lock_i : STD_LOGIC;
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal mmcm_lock_reclocked_i_1_n_0 : STD_LOGIC;
  signal \^out\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal p_0_in_0 : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal pll_reset_asserted_i_1_n_0 : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal reset_time_out : STD_LOGIC;
  signal run_phase_alignment_int : STD_LOGIC;
  signal run_phase_alignment_int_i_1_n_0 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal scndry_out : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_CPLLLOCK_cdc_sync_n_0 : STD_LOGIC;
  signal sync_CPLLLOCK_cdc_sync_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_cdc_sync_n_1 : STD_LOGIC;
  signal time_out_2ms_i_1_n_0 : STD_LOGIC;
  signal time_out_2ms_i_2_n_0 : STD_LOGIC;
  signal time_out_2ms_i_3_n_0 : STD_LOGIC;
  signal time_out_2ms_i_4_n_0 : STD_LOGIC;
  signal time_out_2ms_i_5_n_0 : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_500us_i_1_n_0 : STD_LOGIC;
  signal time_out_500us_i_2_n_0 : STD_LOGIC;
  signal time_out_500us_i_3_n_0 : STD_LOGIC;
  signal time_out_500us_i_4_n_0 : STD_LOGIC;
  signal time_out_500us_reg_n_0 : STD_LOGIC;
  signal \time_out_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \time_out_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal time_out_wait_bypass : STD_LOGIC;
  signal time_out_wait_bypass_i_1_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_2_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_3_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_4_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_5_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_6_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max_i_1_n_0 : STD_LOGIC;
  signal time_tlock_max_i_2_n_0 : STD_LOGIC;
  signal time_tlock_max_i_3_n_0 : STD_LOGIC;
  signal time_tlock_max_reg_n_0 : STD_LOGIC;
  signal tx_fsm_reset_done_int : STD_LOGIC;
  signal tx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC;
  signal tx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal tx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txresetdone_s2 : STD_LOGIC;
  signal txresetdone_s3 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[1]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[2]_i_2\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_10\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_6\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_7\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_8\ : label is "soft_lutpair0";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[2]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[3]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_2\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_3\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_4\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of init_wait_done_i_2 : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \mmcm_lock_count[8]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \mmcm_lock_count[9]_i_3\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of mmcm_lock_reclocked_i_1 : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of mmcm_lock_reclocked_i_2 : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of run_phase_alignment_int_i_1 : label is "soft_lutpair4";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of run_phase_alignment_int_s3_reg : label is "no";
  attribute SOFT_HLUTNM of time_out_2ms_i_3 : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of time_out_500us_i_4 : label is "soft_lutpair11";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[8]_i_1\ : label is 11;
  attribute equivalent_register_removal of time_out_wait_bypass_s3_reg : label is "no";
  attribute equivalent_register_removal of tx_fsm_reset_done_int_s3_reg : label is "no";
  attribute equivalent_register_removal of txresetdone_s3_reg : label is "no";
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[0]_i_3\ : label is 11;
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[8]_i_1\ : label is 11;
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1\ : label is "soft_lutpair5";
begin
  cpll_reset_i <= \^cpll_reset_i\;
  gt_tx_reset_i <= \^gt_tx_reset_i\;
  gt_txuserrdy_i <= \^gt_txuserrdy_i\;
  \out\ <= \^out\;
CPLL_RESET_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFF00000100"
    )
        port map (
      I0 => pll_reset_asserted_reg_n_0,
      I1 => tx_state(2),
      I2 => tx_state(1),
      I3 => tx_state(0),
      I4 => tx_state(3),
      I5 => \^cpll_reset_i\,
      O => CPLL_RESET_i_1_n_0
    );
CPLL_RESET_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => CPLL_RESET_i_1_n_0,
      Q => \^cpll_reset_i\,
      R => AR(0)
    );
\FSM_sequential_tx_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEFEFEFFFEFEF"
    )
        port map (
      I0 => \FSM_sequential_tx_state[3]_i_6_n_0\,
      I1 => tx_state(3),
      I2 => tx_state(0),
      I3 => \FSM_sequential_tx_state[2]_i_2_n_0\,
      I4 => tx_state(2),
      I5 => tx_state(1),
      O => \tx_state__0\(0)
    );
\FSM_sequential_tx_state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F00D0"
    )
        port map (
      I0 => tx_state(2),
      I1 => \FSM_sequential_tx_state[2]_i_2_n_0\,
      I2 => tx_state(0),
      I3 => tx_state(3),
      I4 => tx_state(1),
      O => \tx_state__0\(1)
    );
\FSM_sequential_tx_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000838CCCC"
    )
        port map (
      I0 => \FSM_sequential_tx_state[2]_i_2_n_0\,
      I1 => tx_state(2),
      I2 => tx_state(1),
      I3 => time_out_2ms_reg_n_0,
      I4 => tx_state(0),
      I5 => tx_state(3),
      O => \tx_state__0\(2)
    );
\FSM_sequential_tx_state[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => reset_time_out,
      I2 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[2]_i_2_n_0\
    );
\FSM_sequential_tx_state[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_10_n_0\
    );
\FSM_sequential_tx_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500F30000"
    )
        port map (
      I0 => time_out_wait_bypass_s3,
      I1 => time_out_500us_reg_n_0,
      I2 => reset_time_out,
      I3 => \FSM_sequential_tx_state[3]_i_7_n_0\,
      I4 => tx_state(0),
      I5 => tx_state(3),
      O => \tx_state__0\(3)
    );
\FSM_sequential_tx_state[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001100FF00F0"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4_n_0\,
      I2 => init_wait_done_reg_n_0,
      I3 => tx_state(0),
      I4 => tx_state(3),
      I5 => \FSM_sequential_tx_state[3]_i_8_n_0\,
      O => \FSM_sequential_tx_state[3]_i_3_n_0\
    );
\FSM_sequential_tx_state[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2020F000"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => reset_time_out,
      I2 => tx_state(1),
      I3 => time_out_2ms_reg_n_0,
      I4 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_6_n_0\
    );
\FSM_sequential_tx_state[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_7_n_0\
    );
\FSM_sequential_tx_state[3]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_8_n_0\
    );
\FSM_sequential_tx_state[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out,
      I1 => time_tlock_max_reg_n_0,
      O => \FSM_sequential_tx_state[3]_i_9_n_0\
    );
\FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_1,
      D => \tx_state__0\(0),
      Q => tx_state(0),
      R => AR(0)
    );
\FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_1,
      D => \tx_state__0\(1),
      Q => tx_state(1),
      R => AR(0)
    );
\FSM_sequential_tx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_1,
      D => \tx_state__0\(2),
      Q => tx_state(2),
      R => AR(0)
    );
\FSM_sequential_tx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_1,
      D => \tx_state__0\(3),
      Q => tx_state(3),
      R => AR(0)
    );
TXUSERRDY_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt_txuserrdy_i\,
      O => TXUSERRDY_i_1_n_0
    );
TXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => TXUSERRDY_i_1_n_0,
      Q => \^gt_txuserrdy_i\,
      R => AR(0)
    );
\flag2_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cpll_reset_i\,
      O => CPLL_RESET_reg_0
    );
gttxreset_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt_tx_reset_i\,
      O => gttxreset_i_i_1_n_0
    );
gttxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => gttxreset_i_i_1_n_0,
      Q => \^gt_tx_reset_i\,
      R => AR(0)
    );
\init_wait_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1_n_0\
    );
\init_wait_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(1),
      I4 => init_wait_count_reg(3),
      I5 => init_wait_count_reg(5),
      O => p_0_in(5)
    );
\init_wait_count[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFBFFFF"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => \init_wait_count[6]_i_3_n_0\,
      O => init_wait_count
    );
\init_wait_count[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C6"
    )
        port map (
      I0 => init_wait_count_reg(5),
      I1 => init_wait_count_reg(6),
      I2 => \init_wait_count[6]_i_4_n_0\,
      O => p_0_in(6)
    );
\init_wait_count[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(5),
      I1 => init_wait_count_reg(6),
      O => \init_wait_count[6]_i_3_n_0\
    );
\init_wait_count[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => \init_wait_count[6]_i_4_n_0\
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => \init_wait_count[0]_i_1_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_count_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(6),
      Q => init_wait_count_reg(6)
    );
init_wait_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000004"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(4),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_done_i_2_n_0,
      I4 => \init_wait_count[6]_i_3_n_0\,
      I5 => init_wait_done_reg_n_0,
      O => init_wait_done_i_1_n_0
    );
init_wait_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => init_wait_done_i_2_n_0
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => AR(0),
      D => init_wait_done_i_1_n_0,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[9]_i_4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => mmcm_lock_count_reg(7),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(6),
      I3 => mmcm_lock_count_reg(8),
      O => \p_0_in__0\(8)
    );
\mmcm_lock_count[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(7),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(6),
      I3 => mmcm_lock_count_reg(8),
      I4 => mmcm_lock_count_reg(9),
      O => \mmcm_lock_count[9]_i_2_n_0\
    );
\mmcm_lock_count[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FF0800"
    )
        port map (
      I0 => mmcm_lock_count_reg(8),
      I1 => mmcm_lock_count_reg(6),
      I2 => \mmcm_lock_count[9]_i_4_n_0\,
      I3 => mmcm_lock_count_reg(7),
      I4 => mmcm_lock_count_reg(9),
      O => \p_0_in__0\(9)
    );
\mmcm_lock_count[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[9]_i_4_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(8),
      Q => mmcm_lock_count_reg(8),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(9),
      Q => mmcm_lock_count_reg(9),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
mmcm_lock_reclocked_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => p_0_in_0,
      I2 => mmcm_lock_i,
      O => mmcm_lock_reclocked_i_1_n_0
    );
mmcm_lock_reclocked_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => mmcm_lock_count_reg(9),
      I1 => mmcm_lock_count_reg(8),
      I2 => mmcm_lock_count_reg(6),
      I3 => \mmcm_lock_count[9]_i_4_n_0\,
      I4 => mmcm_lock_count_reg(7),
      O => p_0_in_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => mmcm_lock_reclocked_i_1_n_0,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
pll_reset_asserted_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EF00FF10"
    )
        port map (
      I0 => tx_state(2),
      I1 => tx_state(3),
      I2 => tx_state(0),
      I3 => pll_reset_asserted_reg_n_0,
      I4 => tx_state(1),
      O => pll_reset_asserted_i_1_n_0
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => pll_reset_asserted_i_1_n_0,
      Q => pll_reset_asserted_reg_n_0,
      R => AR(0)
    );
reset_time_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => sync_CPLLLOCK_cdc_sync_n_0,
      Q => reset_time_out,
      R => AR(0)
    );
run_phase_alignment_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0002"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => run_phase_alignment_int,
      O => run_phase_alignment_int_i_1_n_0
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => run_phase_alignment_int_i_1_n_0,
      Q => run_phase_alignment_int,
      R => AR(0)
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => scndry_out,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
sync_CPLLLOCK_cdc_sync: entity work.efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13
     port map (
      E(0) => sync_CPLLLOCK_cdc_sync_n_1,
      \FSM_sequential_tx_state_reg[0]\ => \FSM_sequential_tx_state[3]_i_3_n_0\,
      \FSM_sequential_tx_state_reg[0]_0\ => \FSM_sequential_tx_state[3]_i_6_n_0\,
      \FSM_sequential_tx_state_reg[0]_1\ => \FSM_sequential_tx_state[3]_i_9_n_0\,
      \FSM_sequential_tx_state_reg[0]_2\ => \FSM_sequential_tx_state[3]_i_10_n_0\,
      \FSM_sequential_tx_state_reg[0]_3\ => pll_reset_asserted_reg_n_0,
      Q(3 downto 0) => tx_state(3 downto 0),
      in0 => in0,
      init_clk_in => init_clk_in,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      reset_time_out => reset_time_out,
      reset_time_out_reg => sync_CPLLLOCK_cdc_sync_n_0,
      reset_time_out_reg_0 => init_wait_done_reg_n_0,
      txresetdone_s3 => txresetdone_s3
    );
sync_QPLLLOCK_cdc_sync: entity work.efex_aurora_hub2_efex_aurora_hub2_cdc_sync_14
     port map (
      init_clk_in => init_clk_in
    );
sync_TXRESETDONE_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15\
     port map (
      init_clk_in => init_clk_in,
      \out\ => txresetdone_s2,
      txfsm_txresetdone_r => txfsm_txresetdone_r,
      user_clk => user_clk
    );
sync_mmcm_lock_reclocked_cdc_sync: entity work.efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16
     port map (
      SR(0) => sync_mmcm_lock_reclocked_cdc_sync_n_1,
      init_clk_in => init_clk_in,
      \out\ => mmcm_lock_i
    );
sync_run_phase_alignment_int_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17\
     port map (
      init_clk_in => init_clk_in,
      \out\ => scndry_out,
      run_phase_alignment_int => run_phase_alignment_int,
      user_clk => user_clk
    );
sync_time_out_wait_bypass_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18\
     port map (
      init_clk_in => init_clk_in,
      \out\ => time_out_wait_bypass_s2,
      time_out_wait_bypass => time_out_wait_bypass,
      user_clk => user_clk
    );
sync_tx_fsm_reset_done_int_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19\
     port map (
      \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\,
      init_clk_in => init_clk_in,
      \out\ => \^out\,
      tx_fsm_reset_done_int => tx_fsm_reset_done_int,
      user_clk => user_clk
    );
time_out_2ms_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAEA"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => time_out_2ms_i_2_n_0,
      I2 => time_out_2ms_i_3_n_0,
      I3 => time_out_2ms_i_4_n_0,
      I4 => time_out_2ms_i_5_n_0,
      I5 => reset_time_out,
      O => time_out_2ms_i_1_n_0
    );
time_out_2ms_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(9),
      I2 => time_out_counter_reg(4),
      I3 => time_out_counter_reg(8),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(14),
      O => time_out_2ms_i_2_n_0
    );
time_out_2ms_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(2),
      O => time_out_2ms_i_3_n_0
    );
time_out_2ms_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(7),
      I2 => time_out_counter_reg(13),
      I3 => time_out_counter_reg(6),
      I4 => time_out_counter_reg(3),
      O => time_out_2ms_i_4_n_0
    );
time_out_2ms_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(12),
      I2 => time_out_counter_reg(17),
      I3 => time_out_counter_reg(15),
      I4 => time_out_counter_reg(5),
      I5 => time_out_counter_reg(16),
      O => time_out_2ms_i_5_n_0
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_2ms_i_1_n_0,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
time_out_500us_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AABAAAAA"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => time_out_500us_i_2_n_0,
      I2 => time_out_500us_i_3_n_0,
      I3 => time_out_2ms_i_4_n_0,
      I4 => time_out_500us_i_4_n_0,
      I5 => reset_time_out,
      O => time_out_500us_i_1_n_0
    );
time_out_500us_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(15),
      I2 => time_out_counter_reg(17),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(10),
      O => time_out_500us_i_2_n_0
    );
time_out_500us_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(8),
      I3 => time_out_counter_reg(9),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(16),
      O => time_out_500us_i_3_n_0
    );
time_out_500us_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(2),
      I2 => time_out_counter_reg(1),
      O => time_out_500us_i_4_n_0
    );
time_out_500us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_500us_i_1_n_0,
      Q => time_out_500us_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \time_out_counter[0]_i_3_n_0\,
      I1 => time_out_2ms_i_4_n_0,
      I2 => time_out_counter_reg(4),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(1),
      O => \time_out_counter[0]_i_1_n_0\
    );
\time_out_counter[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFF7FFFF"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(18),
      I2 => time_out_counter_reg(8),
      I3 => time_out_counter_reg(9),
      I4 => time_out_counter_reg(11),
      I5 => time_out_2ms_i_5_n_0,
      O => \time_out_counter[0]_i_3_n_0\
    );
\time_out_counter[0]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_4_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[0]_i_2_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out
    );
\time_out_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_4_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[8]_i_1_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[8]_i_1_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[12]_i_1_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out
    );
\time_out_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[12]_i_1_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[12]_i_1_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[12]_i_1_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[16]_i_1_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out
    );
\time_out_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \time_out_counter_reg[16]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\(3),
      O(2) => \time_out_counter_reg[16]_i_1_n_5\,
      O(1) => \time_out_counter_reg[16]_i_1_n_6\,
      O(0) => \time_out_counter_reg[16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => time_out_counter_reg(18 downto 16)
    );
\time_out_counter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[16]_i_1_n_6\,
      Q => time_out_counter_reg(17),
      R => reset_time_out
    );
\time_out_counter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[16]_i_1_n_5\,
      Q => time_out_counter_reg(18),
      R => reset_time_out
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[0]_i_2_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[0]_i_2_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[0]_i_2_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[4]_i_1_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out
    );
\time_out_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[4]_i_1_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[4]_i_1_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[4]_i_1_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[8]_i_1_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out
    );
\time_out_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \time_out_counter[0]_i_1_n_0\,
      D => \time_out_counter_reg[8]_i_1_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out
    );
time_out_wait_bypass_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass,
      I1 => time_out_wait_bypass_i_2_n_0,
      I2 => tx_fsm_reset_done_int_s3,
      I3 => run_phase_alignment_int_s3,
      O => time_out_wait_bypass_i_1_n_0
    );
time_out_wait_bypass_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => time_out_wait_bypass_i_3_n_0,
      I1 => time_out_wait_bypass_i_4_n_0,
      I2 => time_out_wait_bypass_i_5_n_0,
      I3 => time_out_wait_bypass_i_6_n_0,
      O => time_out_wait_bypass_i_2_n_0
    );
time_out_wait_bypass_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(7),
      I3 => wait_bypass_count_reg(6),
      O => time_out_wait_bypass_i_3_n_0
    );
time_out_wait_bypass_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => wait_bypass_count_reg(1),
      I1 => wait_bypass_count_reg(0),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(2),
      O => time_out_wait_bypass_i_4_n_0
    );
time_out_wait_bypass_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(13),
      I1 => wait_bypass_count_reg(12),
      I2 => wait_bypass_count_reg(15),
      I3 => wait_bypass_count_reg(14),
      O => time_out_wait_bypass_i_5_n_0
    );
time_out_wait_bypass_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => wait_bypass_count_reg(8),
      I1 => wait_bypass_count_reg(9),
      I2 => wait_bypass_count_reg(10),
      I3 => wait_bypass_count_reg(11),
      O => time_out_wait_bypass_i_6_n_0
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => time_out_wait_bypass_i_1_n_0,
      Q => time_out_wait_bypass,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAEAAA"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => time_tlock_max_i_2_n_0,
      I2 => time_tlock_max_i_3_n_0,
      I3 => time_out_counter_reg(0),
      I4 => time_out_2ms_i_5_n_0,
      I5 => reset_time_out,
      O => time_tlock_max_i_1_n_0
    );
time_tlock_max_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(2),
      I3 => time_out_counter_reg(1),
      I4 => time_out_counter_reg(7),
      I5 => time_out_counter_reg(6),
      O => time_tlock_max_i_2_n_0
    );
time_tlock_max_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(11),
      I2 => time_out_counter_reg(8),
      I3 => time_out_counter_reg(9),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(14),
      O => time_tlock_max_i_3_n_0
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_tlock_max_i_1_n_0,
      Q => time_tlock_max_reg_n_0,
      R => '0'
    );
tx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(2),
      I3 => tx_state(1),
      I4 => tx_fsm_reset_done_int,
      O => tx_fsm_reset_done_int_i_1_n_0
    );
tx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => tx_fsm_reset_done_int_i_1_n_0,
      Q => tx_fsm_reset_done_int,
      R => AR(0)
    );
tx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \^out\,
      Q => tx_fsm_reset_done_int_s3,
      R => '0'
    );
txresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => txresetdone_s2,
      Q => txresetdone_s3,
      R => '0'
    );
\wait_bypass_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_wait_bypass_i_2_n_0,
      I1 => tx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2_n_0\
    );
\wait_bypass_count[0]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_4_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_4_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(3) => \NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \wait_bypass_count_reg[12]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[12]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[12]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[12]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[12]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[12]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(15 downto 12)
    );
\wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_6\,
      Q => wait_bypass_count_reg(13),
      R => clear
    );
\wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_5\,
      Q => wait_bypass_count_reg(14),
      R => clear
    );
\wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_4\,
      Q => wait_bypass_count_reg(15),
      R => clear
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0070"
    )
        port map (
      I0 => tx_state(2),
      I1 => tx_state(1),
      I2 => tx_state(0),
      I3 => tx_state(3),
      O => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER is
  port (
    TX_RESETDONE_OUT : out STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    TXN : out STD_LOGIC_VECTOR ( 0 to 3 );
    TXP : out STD_LOGIC_VECTOR ( 0 to 3 );
    gt0_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_0 : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_1 : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_2 : out STD_LOGIC;
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : out STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    gt0_txinhibit_in : in STD_LOGIC;
    gt0_txpcsreset_in : in STD_LOGIC;
    gt0_txpmareset_in : in STD_LOGIC;
    gt0_txpolarity_in : in STD_LOGIC;
    gt0_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    TXCHARISK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    gt1_txinhibit_in : in STD_LOGIC;
    gt1_txpcsreset_in : in STD_LOGIC;
    gt1_txpmareset_in : in STD_LOGIC;
    gt1_txpolarity_in : in STD_LOGIC;
    gt1_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    gt2_txinhibit_in : in STD_LOGIC;
    gt2_txpcsreset_in : in STD_LOGIC;
    gt2_txpmareset_in : in STD_LOGIC;
    gt2_txpolarity_in : in STD_LOGIC;
    gt2_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    gt3_txinhibit_in : in STD_LOGIC;
    gt3_txpcsreset_in : in STD_LOGIC;
    gt3_txpmareset_in : in STD_LOGIC;
    gt3_txpolarity_in : in STD_LOGIC;
    gt3_txprbsforceerr_in : in STD_LOGIC;
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_cplllock_out_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ENABLE_ERR_DETECT : in STD_LOGIC;
    ENABLE_ERR_DETECT_0 : in STD_LOGIC;
    ENABLE_ERR_DETECT_1 : in STD_LOGIC;
    ENABLE_ERR_DETECT_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER : entity is "efex_aurora_hub2_GT_WRAPPER";
end efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER is
  signal CPLLLOCK : STD_LOGIC;
  signal cpll_reset_i : STD_LOGIC;
  signal \^gt0_cplllock_out\ : STD_LOGIC;
  signal \^gt0_txresetdone_out\ : STD_LOGIC;
  signal gt0_txresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt0_txresetdone_r3 : STD_LOGIC;
  signal \^gt1_cplllock_out\ : STD_LOGIC;
  signal \^gt1_txresetdone_out\ : STD_LOGIC;
  signal gt1_txresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt1_txresetdone_r3 : STD_LOGIC;
  signal \^gt2_cplllock_out\ : STD_LOGIC;
  signal \^gt2_txresetdone_out\ : STD_LOGIC;
  signal gt2_txresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt2_txresetdone_r3 : STD_LOGIC;
  signal \^gt3_cplllock_out\ : STD_LOGIC;
  signal \^gt3_txresetdone_out\ : STD_LOGIC;
  signal gt3_txresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt3_txresetdone_r3 : STD_LOGIC;
  signal gt_tx_reset_i : STD_LOGIC;
  signal gt_txresetfsm_i_n_5 : STD_LOGIC;
  signal gt_txuserrdy_i : STD_LOGIC;
  signal \txfsm_txresetdone_i__0\ : STD_LOGIC;
  signal txfsm_txresetdone_r : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of gt0_txresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt0_txresetdone_r2_reg_srl2 ";
  attribute srl_name of gt1_txresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt1_txresetdone_r2_reg_srl2 ";
  attribute srl_name of gt2_txresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt2_txresetdone_r2_reg_srl2 ";
  attribute srl_name of gt3_txresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt3_txresetdone_r2_reg_srl2 ";
begin
  gt0_cplllock_out <= \^gt0_cplllock_out\;
  gt0_txresetdone_out <= \^gt0_txresetdone_out\;
  gt1_cplllock_out <= \^gt1_cplllock_out\;
  gt1_txresetdone_out <= \^gt1_txresetdone_out\;
  gt2_cplllock_out <= \^gt2_cplllock_out\;
  gt2_txresetdone_out <= \^gt2_txresetdone_out\;
  gt3_cplllock_out <= \^gt3_cplllock_out\;
  gt3_txresetdone_out <= \^gt3_txresetdone_out\;
efex_aurora_hub2_multi_gt_i: entity work.efex_aurora_hub2_efex_aurora_hub2_multi_gt
     port map (
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPADDR_IN_LANE1(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPADDR_IN_LANE2(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPADDR_IN_LANE3(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPEN_IN_LANE1 => DRPEN_IN_LANE1,
      DRPEN_IN_LANE2 => DRPEN_IN_LANE2,
      DRPEN_IN_LANE3 => DRPEN_IN_LANE3,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPRDY_OUT_LANE1 => DRPRDY_OUT_LANE1,
      DRPRDY_OUT_LANE2 => DRPRDY_OUT_LANE2,
      DRPRDY_OUT_LANE3 => DRPRDY_OUT_LANE3,
      DRPWE_IN => DRPWE_IN,
      DRPWE_IN_LANE1 => DRPWE_IN_LANE1,
      DRPWE_IN_LANE2 => DRPWE_IN_LANE2,
      DRPWE_IN_LANE3 => DRPWE_IN_LANE3,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT,
      ENABLE_ERR_DETECT_0 => ENABLE_ERR_DETECT_0,
      ENABLE_ERR_DETECT_1 => ENABLE_ERR_DETECT_1,
      ENABLE_ERR_DETECT_2 => ENABLE_ERR_DETECT_2,
      ENABLE_ERR_DETECT_Buffer_reg => ENABLE_ERR_DETECT_Buffer_reg,
      ENABLE_ERR_DETECT_Buffer_reg_0 => ENABLE_ERR_DETECT_Buffer_reg_0,
      ENABLE_ERR_DETECT_Buffer_reg_1 => ENABLE_ERR_DETECT_Buffer_reg_1,
      ENABLE_ERR_DETECT_Buffer_reg_2 => ENABLE_ERR_DETECT_Buffer_reg_2,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      TXCHARISK(1 downto 0) => TXCHARISK(1 downto 0),
      TXDATA(15 downto 0) => TXDATA(15 downto 0),
      TXN(0 to 3) => TXN(0 to 3),
      TXP(0 to 3) => TXP(0 to 3),
      TX_LOCK => TX_LOCK,
      TX_OUT_CLK => TX_OUT_CLK,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      flag2_reg => gt_txresetfsm_i_n_5,
      gt0_cplllock_out => \^gt0_cplllock_out\,
      gt0_txbufstatus_out(1 downto 0) => gt0_txbufstatus_out(1 downto 0),
      gt0_txchardispmode_in(1 downto 0) => gt0_txchardispmode_in(1 downto 0),
      gt0_txchardispval_in(1 downto 0) => gt0_txchardispval_in(1 downto 0),
      gt0_txdiffctrl_in(3 downto 0) => gt0_txdiffctrl_in(3 downto 0),
      gt0_txinhibit_in => gt0_txinhibit_in,
      gt0_txmaincursor_in(6 downto 0) => gt0_txmaincursor_in(6 downto 0),
      gt0_txpcsreset_in => gt0_txpcsreset_in,
      gt0_txpmareset_in => gt0_txpmareset_in,
      gt0_txpolarity_in => gt0_txpolarity_in,
      gt0_txpostcursor_in(4 downto 0) => gt0_txpostcursor_in(4 downto 0),
      gt0_txprbsforceerr_in => gt0_txprbsforceerr_in,
      gt0_txprbssel_in(2 downto 0) => gt0_txprbssel_in(2 downto 0),
      gt0_txprecursor_in(4 downto 0) => gt0_txprecursor_in(4 downto 0),
      gt0_txresetdone_out => \^gt0_txresetdone_out\,
      gt1_cplllock_out => \^gt1_cplllock_out\,
      gt1_cplllock_out_0(15 downto 0) => gt1_cplllock_out_0(15 downto 0),
      gt1_cplllock_out_1(1 downto 0) => gt1_cplllock_out_1(1 downto 0),
      gt1_txbufstatus_out(1 downto 0) => gt1_txbufstatus_out(1 downto 0),
      gt1_txchardispmode_in(1 downto 0) => gt1_txchardispmode_in(1 downto 0),
      gt1_txchardispval_in(1 downto 0) => gt1_txchardispval_in(1 downto 0),
      gt1_txdiffctrl_in(3 downto 0) => gt1_txdiffctrl_in(3 downto 0),
      gt1_txinhibit_in => gt1_txinhibit_in,
      gt1_txmaincursor_in(6 downto 0) => gt1_txmaincursor_in(6 downto 0),
      gt1_txpcsreset_in => gt1_txpcsreset_in,
      gt1_txpmareset_in => gt1_txpmareset_in,
      gt1_txpolarity_in => gt1_txpolarity_in,
      gt1_txpostcursor_in(4 downto 0) => gt1_txpostcursor_in(4 downto 0),
      gt1_txprbsforceerr_in => gt1_txprbsforceerr_in,
      gt1_txprbssel_in(2 downto 0) => gt1_txprbssel_in(2 downto 0),
      gt1_txprecursor_in(4 downto 0) => gt1_txprecursor_in(4 downto 0),
      gt1_txresetdone_out => \^gt1_txresetdone_out\,
      gt2_cplllock_out => \^gt2_cplllock_out\,
      gt2_cplllock_out_0(15 downto 0) => gt2_cplllock_out_0(15 downto 0),
      gt2_cplllock_out_1(1 downto 0) => gt2_cplllock_out_1(1 downto 0),
      gt2_txbufstatus_out(1 downto 0) => gt2_txbufstatus_out(1 downto 0),
      gt2_txchardispmode_in(1 downto 0) => gt2_txchardispmode_in(1 downto 0),
      gt2_txchardispval_in(1 downto 0) => gt2_txchardispval_in(1 downto 0),
      gt2_txdiffctrl_in(3 downto 0) => gt2_txdiffctrl_in(3 downto 0),
      gt2_txinhibit_in => gt2_txinhibit_in,
      gt2_txmaincursor_in(6 downto 0) => gt2_txmaincursor_in(6 downto 0),
      gt2_txpcsreset_in => gt2_txpcsreset_in,
      gt2_txpmareset_in => gt2_txpmareset_in,
      gt2_txpolarity_in => gt2_txpolarity_in,
      gt2_txpostcursor_in(4 downto 0) => gt2_txpostcursor_in(4 downto 0),
      gt2_txprbsforceerr_in => gt2_txprbsforceerr_in,
      gt2_txprbssel_in(2 downto 0) => gt2_txprbssel_in(2 downto 0),
      gt2_txprecursor_in(4 downto 0) => gt2_txprecursor_in(4 downto 0),
      gt2_txresetdone_out => \^gt2_txresetdone_out\,
      gt3_cplllock_out => \^gt3_cplllock_out\,
      gt3_cplllock_out_0(15 downto 0) => gt3_cplllock_out_0(15 downto 0),
      gt3_cplllock_out_1(1 downto 0) => gt3_cplllock_out_1(1 downto 0),
      gt3_txbufstatus_out(1 downto 0) => gt3_txbufstatus_out(1 downto 0),
      gt3_txchardispmode_in(1 downto 0) => gt3_txchardispmode_in(1 downto 0),
      gt3_txchardispval_in(1 downto 0) => gt3_txchardispval_in(1 downto 0),
      gt3_txdiffctrl_in(3 downto 0) => gt3_txdiffctrl_in(3 downto 0),
      gt3_txinhibit_in => gt3_txinhibit_in,
      gt3_txmaincursor_in(6 downto 0) => gt3_txmaincursor_in(6 downto 0),
      gt3_txpcsreset_in => gt3_txpcsreset_in,
      gt3_txpmareset_in => gt3_txpmareset_in,
      gt3_txpolarity_in => gt3_txpolarity_in,
      gt3_txpostcursor_in(4 downto 0) => gt3_txpostcursor_in(4 downto 0),
      gt3_txprbsforceerr_in => gt3_txprbsforceerr_in,
      gt3_txprbssel_in(2 downto 0) => gt3_txprbssel_in(2 downto 0),
      gt3_txprecursor_in(4 downto 0) => gt3_txprecursor_in(4 downto 0),
      gt3_txresetdone_out => \^gt3_txresetdone_out\,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      gt_tx_reset_i => gt_tx_reset_i,
      gt_txuserrdy_i => gt_txuserrdy_i,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      user_clk => user_clk
    );
gt0_txresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt0_txresetdone_out\,
      Q => gt0_txresetdone_r2_reg_srl2_n_0
    );
gt0_txresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt0_txresetdone_r2_reg_srl2_n_0,
      Q => gt0_txresetdone_r3,
      R => '0'
    );
gt1_txresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt1_txresetdone_out\,
      Q => gt1_txresetdone_r2_reg_srl2_n_0
    );
gt1_txresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt1_txresetdone_r2_reg_srl2_n_0,
      Q => gt1_txresetdone_r3,
      R => '0'
    );
gt2_txresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt2_txresetdone_out\,
      Q => gt2_txresetdone_r2_reg_srl2_n_0
    );
gt2_txresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt2_txresetdone_r2_reg_srl2_n_0,
      Q => gt2_txresetdone_r3,
      R => '0'
    );
gt3_txresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt3_txresetdone_out\,
      Q => gt3_txresetdone_r2_reg_srl2_n_0
    );
gt3_txresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt3_txresetdone_r2_reg_srl2_n_0,
      Q => gt3_txresetdone_r3,
      R => '0'
    );
gt_pll_lock_i: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^gt3_cplllock_out\,
      I1 => \^gt0_cplllock_out\,
      I2 => \^gt1_cplllock_out\,
      I3 => \^gt2_cplllock_out\,
      O => CPLLLOCK
    );
gt_txresetfsm_i: entity work.efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm
     port map (
      AR(0) => AR(0),
      CPLL_RESET_reg_0 => gt_txresetfsm_i_n_5,
      \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\,
      cpll_reset_i => cpll_reset_i,
      gt_tx_reset_i => gt_tx_reset_i,
      gt_txuserrdy_i => gt_txuserrdy_i,
      in0 => CPLLLOCK,
      init_clk_in => init_clk_in,
      \out\ => TX_RESETDONE_OUT,
      txfsm_txresetdone_r => txfsm_txresetdone_r,
      user_clk => user_clk
    );
gtrxreset_cdc_sync: entity work.\efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2\
     port map (
      init_clk_in => init_clk_in,
      user_clk => user_clk
    );
txfsm_txresetdone_i: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => gt3_txresetdone_r3,
      I1 => gt0_txresetdone_r3,
      I2 => gt1_txresetdone_r3,
      I3 => gt2_txresetdone_r3,
      O => \txfsm_txresetdone_i__0\
    );
txfsm_txresetdone_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \txfsm_txresetdone_i__0\,
      Q => txfsm_txresetdone_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2_efex_aurora_hub2_core is
  port (
    S_AXI_TX_TDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S_AXI_TX_TKEEP : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S_AXI_TX_TVALID : in STD_LOGIC;
    S_AXI_TX_TREADY : out STD_LOGIC;
    S_AXI_TX_TLAST : in STD_LOGIC;
    S_AXI_UFC_TX_REQ : in STD_LOGIC;
    S_AXI_UFC_TX_MS : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S_AXI_UFC_TX_ACK : out STD_LOGIC;
    TXP : out STD_LOGIC_VECTOR ( 0 to 3 );
    TXN : out STD_LOGIC_VECTOR ( 0 to 3 );
    gt_refclk1 : in STD_LOGIC;
    TX_HARD_ERR : out STD_LOGIC;
    TX_CHANNEL_UP : out STD_LOGIC;
    TX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 3 );
    user_clk : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    TX_SYSTEM_RESET : in STD_LOGIC;
    TX_RESETDONE_OUT : out STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    GT_RESET : in STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    PLL_NOT_LOCKED : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN : in STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt0_qplllock_in : in STD_LOGIC;
    gt0_qpllrefclklost_in : in STD_LOGIC;
    gt0_qpllreset_out : out STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    gt0_txresetdone_out : out STD_LOGIC;
    gt0_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_txpolarity_in : in STD_LOGIC;
    gt0_tx_buf_err_out : out STD_LOGIC;
    gt0_txprbsforceerr_in : in STD_LOGIC;
    gt0_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txpcsreset_in : in STD_LOGIC;
    gt0_txinhibit_in : in STD_LOGIC;
    gt0_txpmareset_in : in STD_LOGIC;
    gt1_cplllock_out : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    gt1_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_txpolarity_in : in STD_LOGIC;
    gt1_tx_buf_err_out : out STD_LOGIC;
    gt1_txprbsforceerr_in : in STD_LOGIC;
    gt1_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_txpcsreset_in : in STD_LOGIC;
    gt1_txinhibit_in : in STD_LOGIC;
    gt1_txpmareset_in : in STD_LOGIC;
    gt2_cplllock_out : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    gt2_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_txpolarity_in : in STD_LOGIC;
    gt2_tx_buf_err_out : out STD_LOGIC;
    gt2_txprbsforceerr_in : in STD_LOGIC;
    gt2_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_txpcsreset_in : in STD_LOGIC;
    gt2_txinhibit_in : in STD_LOGIC;
    gt2_txpmareset_in : in STD_LOGIC;
    gt3_cplllock_out : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    gt3_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_txpolarity_in : in STD_LOGIC;
    gt3_tx_buf_err_out : out STD_LOGIC;
    gt3_txprbsforceerr_in : in STD_LOGIC;
    gt3_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_txpcsreset_in : in STD_LOGIC;
    gt3_txinhibit_in : in STD_LOGIC;
    gt3_txpmareset_in : in STD_LOGIC;
    sys_reset_out : out STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute CC_FREQ_FACTOR : integer;
  attribute CC_FREQ_FACTOR of efex_aurora_hub2_efex_aurora_hub2_core : entity is 24;
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of efex_aurora_hub2_efex_aurora_hub2_core : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of efex_aurora_hub2_efex_aurora_hub2_core : entity is "efex_aurora_hub2_core";
  attribute SIM_GTRESET_SPEEDUP : string;
  attribute SIM_GTRESET_SPEEDUP of efex_aurora_hub2_efex_aurora_hub2_core : entity is "FALSE";
end efex_aurora_hub2_efex_aurora_hub2_core;

architecture STRUCTURE of efex_aurora_hub2_efex_aurora_hub2_core is
  signal \<const0>\ : STD_LOGIC;
  signal DO_CC_I : STD_LOGIC;
  signal ENABLE_ERR_DETECT : STD_LOGIC;
  signal ENABLE_ERR_DETECT_1 : STD_LOGIC;
  signal ENABLE_ERR_DETECT_3 : STD_LOGIC;
  signal ENABLE_ERR_DETECT_5 : STD_LOGIC;
  signal GEN_A : STD_LOGIC;
  signal GEN_CC : STD_LOGIC;
  signal GEN_K : STD_LOGIC_VECTOR ( 0 to 1 );
  signal GEN_PAD : STD_LOGIC;
  signal GEN_R : STD_LOGIC_VECTOR ( 0 to 1 );
  signal GEN_V : STD_LOGIC_VECTOR ( 0 to 1 );
  signal HARD_ERR : STD_LOGIC;
  signal RESET : STD_LOGIC;
  signal RESET_SYMGEN : STD_LOGIC;
  signal \^tx_channel_up\ : STD_LOGIC;
  signal \^tx_lane_up\ : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \^tx_lock\ : STD_LOGIC;
  signal TX_PE_DATA : STD_LOGIC_VECTOR ( 0 to 15 );
  signal TX_PE_DATA_V : STD_LOGIC;
  signal WARN_CC : STD_LOGIC;
  signal axi_to_ll_pdu_i_n_0 : STD_LOGIC;
  signal gen_ecp_i : STD_LOGIC;
  signal gen_scp_i : STD_LOGIC;
  signal gen_suf_i : STD_LOGIC;
  signal \^gt0_tx_buf_err_out\ : STD_LOGIC;
  signal \^gt0_txbufstatus_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^gt1_tx_buf_err_out\ : STD_LOGIC;
  signal \^gt1_txbufstatus_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^gt2_tx_buf_err_out\ : STD_LOGIC;
  signal \^gt2_txbufstatus_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^gt3_tx_buf_err_out\ : STD_LOGIC;
  signal \^gt3_txbufstatus_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal gt_reset_sync_init_clk : STD_LOGIC;
  signal gt_wrapper_i_n_94 : STD_LOGIC;
  signal gt_wrapper_i_n_95 : STD_LOGIC;
  signal gt_wrapper_i_n_96 : STD_LOGIC;
  signal gt_wrapper_i_n_97 : STD_LOGIC;
  signal gt_wrapper_i_n_98 : STD_LOGIC;
  signal hard_err_reset_i : STD_LOGIC;
  signal hard_err_reset_i_0 : STD_LOGIC;
  signal hard_err_reset_i_2 : STD_LOGIC;
  signal hard_err_reset_i_4 : STD_LOGIC;
  signal new_pkt_r : STD_LOGIC;
  signal reset_channel_i : STD_LOGIC;
  signal reset_sync_user_clk : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal simplex_timer_r0 : STD_LOGIC;
  signal \simplex_timer_r[0]_i_4_n_0\ : STD_LOGIC;
  signal simplex_timer_r_reg : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \simplex_timer_r_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \simplex_timer_r_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \simplex_timer_r_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \simplex_timer_r_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \simplex_timer_r_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \simplex_timer_r_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \simplex_timer_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \simplex_timer_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \^sys_reset_out\ : STD_LOGIC;
  signal tx_aligned_simplex_r : STD_LOGIC;
  signal tx_aligned_simplex_r_i_2_n_0 : STD_LOGIC;
  signal tx_aligned_simplex_r_i_3_n_0 : STD_LOGIC;
  signal tx_aligned_simplex_r_i_4_n_0 : STD_LOGIC;
  signal tx_aurora_lane_simplex_v5_1_i_n_5 : STD_LOGIC;
  signal tx_aurora_lane_simplex_v5_2_i_n_5 : STD_LOGIC;
  signal tx_aurora_lane_simplex_v5_3_i_n_5 : STD_LOGIC;
  signal tx_bonded1_simplex_r : STD_LOGIC;
  signal tx_bonded1_simplex_r_i_2_n_0 : STD_LOGIC;
  signal tx_bonded1_simplex_r_i_3_n_0 : STD_LOGIC;
  signal \tx_channel_init_sm_simplex_i/wait_for_lane_up_r0\ : STD_LOGIC;
  signal tx_char_is_k_i_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tx_char_is_k_i_2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tx_char_is_k_i_4 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tx_char_is_k_i_6 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tx_data_i_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal tx_data_i_16 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal tx_data_i_32 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal tx_data_i_48 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal tx_dst_rdy : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_10 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_11 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_12 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_14 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_15 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_16 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_19 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_2 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_20 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_21 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_22 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_23 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_24 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_27 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_28 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_29 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_3 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_30 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_31 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_32 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_35 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_36 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_37 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_38 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_4 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_44 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_7 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_8 : STD_LOGIC;
  signal tx_global_logic_simplex_i_n_9 : STD_LOGIC;
  signal \tx_lane_init_simplex_sm_i/rst_r0\ : STD_LOGIC;
  signal \tx_lane_init_simplex_sm_i/rst_r0_6\ : STD_LOGIC;
  signal \tx_lane_init_simplex_sm_i/rst_r0_7\ : STD_LOGIC;
  signal \tx_lane_init_simplex_sm_i/rst_r0_8\ : STD_LOGIC;
  signal \tx_lane_init_simplex_sm_i/tx_aligned_r\ : STD_LOGIC;
  signal \tx_ll_control_i/next_ufc_header_c\ : STD_LOGIC;
  signal \tx_ll_control_i/next_ufc_idle_c\ : STD_LOGIC;
  signal tx_ll_i_n_1 : STD_LOGIC;
  signal tx_ll_i_n_10 : STD_LOGIC;
  signal tx_ll_i_n_11 : STD_LOGIC;
  signal tx_ll_i_n_13 : STD_LOGIC;
  signal tx_ll_i_n_15 : STD_LOGIC;
  signal tx_ll_i_n_16 : STD_LOGIC;
  signal tx_ll_i_n_17 : STD_LOGIC;
  signal tx_ll_i_n_19 : STD_LOGIC;
  signal tx_ll_i_n_2 : STD_LOGIC;
  signal tx_ll_i_n_20 : STD_LOGIC;
  signal tx_ll_i_n_21 : STD_LOGIC;
  signal tx_ll_i_n_3 : STD_LOGIC;
  signal tx_ll_i_n_38 : STD_LOGIC;
  signal tx_ll_i_n_39 : STD_LOGIC;
  signal tx_ll_i_n_40 : STD_LOGIC;
  signal tx_ll_i_n_41 : STD_LOGIC;
  signal tx_ll_i_n_42 : STD_LOGIC;
  signal tx_ll_i_n_43 : STD_LOGIC;
  signal tx_ll_i_n_44 : STD_LOGIC;
  signal tx_ll_i_n_45 : STD_LOGIC;
  signal tx_ll_i_n_46 : STD_LOGIC;
  signal tx_ll_i_n_47 : STD_LOGIC;
  signal tx_ll_i_n_48 : STD_LOGIC;
  signal tx_ll_i_n_49 : STD_LOGIC;
  signal tx_ll_i_n_50 : STD_LOGIC;
  signal tx_ll_i_n_51 : STD_LOGIC;
  signal tx_ll_i_n_52 : STD_LOGIC;
  signal tx_ll_i_n_53 : STD_LOGIC;
  signal tx_ll_i_n_54 : STD_LOGIC;
  signal tx_ll_i_n_55 : STD_LOGIC;
  signal tx_ll_i_n_56 : STD_LOGIC;
  signal tx_ll_i_n_57 : STD_LOGIC;
  signal tx_ll_i_n_58 : STD_LOGIC;
  signal tx_ll_i_n_59 : STD_LOGIC;
  signal tx_ll_i_n_60 : STD_LOGIC;
  signal tx_ll_i_n_61 : STD_LOGIC;
  signal tx_ll_i_n_62 : STD_LOGIC;
  signal tx_ll_i_n_63 : STD_LOGIC;
  signal tx_ll_i_n_64 : STD_LOGIC;
  signal tx_ll_i_n_65 : STD_LOGIC;
  signal tx_ll_i_n_66 : STD_LOGIC;
  signal tx_ll_i_n_67 : STD_LOGIC;
  signal tx_ll_i_n_68 : STD_LOGIC;
  signal tx_ll_i_n_69 : STD_LOGIC;
  signal tx_ll_i_n_70 : STD_LOGIC;
  signal tx_ll_i_n_71 : STD_LOGIC;
  signal tx_ll_i_n_72 : STD_LOGIC;
  signal tx_ll_i_n_73 : STD_LOGIC;
  signal tx_ll_i_n_74 : STD_LOGIC;
  signal tx_ll_i_n_75 : STD_LOGIC;
  signal tx_ll_i_n_76 : STD_LOGIC;
  signal tx_ll_i_n_77 : STD_LOGIC;
  signal tx_ll_i_n_78 : STD_LOGIC;
  signal tx_ll_i_n_79 : STD_LOGIC;
  signal tx_ll_i_n_80 : STD_LOGIC;
  signal tx_ll_i_n_81 : STD_LOGIC;
  signal tx_ll_i_n_82 : STD_LOGIC;
  signal tx_ll_i_n_83 : STD_LOGIC;
  signal tx_ll_i_n_84 : STD_LOGIC;
  signal tx_ll_i_n_85 : STD_LOGIC;
  signal tx_ll_i_n_9 : STD_LOGIC;
  signal tx_reset_simplex_r : STD_LOGIC;
  signal tx_reset_simplex_r_i_2_n_0 : STD_LOGIC;
  signal tx_reset_simplex_r_i_3_n_0 : STD_LOGIC;
  signal tx_reset_simplex_r_i_4_n_0 : STD_LOGIC;
  signal tx_verify_simplex_r : STD_LOGIC;
  signal tx_verify_simplex_r_i_2_n_0 : STD_LOGIC;
  signal tx_verify_simplex_r_i_3_n_0 : STD_LOGIC;
  signal tx_verify_simplex_r_i_4_n_0 : STD_LOGIC;
  signal \NLW_simplex_timer_r_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_simplex_timer_r_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \simplex_timer_r_reg[0]_i_3\ : label is 11;
  attribute ADDER_THRESHOLD of \simplex_timer_r_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \simplex_timer_r_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \simplex_timer_r_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \simplex_timer_r_reg[8]_i_1\ : label is 11;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of tx_aligned_simplex_r_i_3 : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of tx_aligned_simplex_r_i_4 : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of tx_bonded1_simplex_r_i_3 : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of tx_reset_simplex_r_i_2 : label is "soft_lutpair59";
begin
  TX_CHANNEL_UP <= \^tx_channel_up\;
  TX_LANE_UP(0 to 3) <= \^tx_lane_up\(0 to 3);
  TX_LOCK <= \^tx_lock\;
  gt0_qpllreset_out <= \<const0>\;
  gt0_tx_buf_err_out <= \^gt0_tx_buf_err_out\;
  gt0_txbufstatus_out(1) <= \^gt0_tx_buf_err_out\;
  gt0_txbufstatus_out(0) <= \^gt0_txbufstatus_out\(0);
  gt1_tx_buf_err_out <= \^gt1_tx_buf_err_out\;
  gt1_txbufstatus_out(1) <= \^gt1_tx_buf_err_out\;
  gt1_txbufstatus_out(0) <= \^gt1_txbufstatus_out\(0);
  gt2_tx_buf_err_out <= \^gt2_tx_buf_err_out\;
  gt2_txbufstatus_out(1) <= \^gt2_tx_buf_err_out\;
  gt2_txbufstatus_out(0) <= \^gt2_txbufstatus_out\(0);
  gt3_tx_buf_err_out <= \^gt3_tx_buf_err_out\;
  gt3_txbufstatus_out(1) <= \^gt3_tx_buf_err_out\;
  gt3_txbufstatus_out(0) <= \^gt3_txbufstatus_out\(0);
  sys_reset_out <= \^sys_reset_out\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
axi_to_ll_pdu_i: entity work.efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL
     port map (
      new_pkt_r => new_pkt_r,
      new_pkt_r_reg_0 => axi_to_ll_pdu_i_n_0,
      user_clk => user_clk
    );
core_reset_logic_i: entity work.efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC
     port map (
      RESET_SYMGEN => RESET_SYMGEN,
      SYSTEM_RESET_reg_0 => \^sys_reset_out\,
      S_AXI_TX_TLAST => S_AXI_TX_TLAST,
      S_AXI_TX_TVALID => S_AXI_TX_TVALID,
      TX_CHANNEL_UP => \^tx_channel_up\,
      TX_LOCK => \^tx_lock\,
      gt_txresetdone_r2_reg_0 => gt_wrapper_i_n_98,
      init_clk_in => init_clk_in,
      new_pkt_r => new_pkt_r,
      new_pkt_r_reg => axi_to_ll_pdu_i_n_0,
      \out\ => reset_sync_user_clk,
      reset_channel_i => reset_channel_i,
      tx_dst_rdy => tx_dst_rdy,
      tx_reset_simplex_r => tx_reset_simplex_r,
      user_clk => user_clk,
      wait_for_lane_up_r0 => \tx_channel_init_sm_simplex_i/wait_for_lane_up_r0\
    );
gt_reset_cdc_sync: entity work.efex_aurora_hub2_efex_aurora_hub2_cdc_sync
     port map (
      AR(0) => gt_reset_sync_init_clk,
      GT_RESET => GT_RESET,
      init_clk_in => init_clk_in
    );
gt_wrapper_i: entity work.efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER
     port map (
      AR(0) => gt_reset_sync_init_clk,
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPADDR_IN_LANE1(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPADDR_IN_LANE2(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPADDR_IN_LANE3(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPEN_IN_LANE1 => DRPEN_IN_LANE1,
      DRPEN_IN_LANE2 => DRPEN_IN_LANE2,
      DRPEN_IN_LANE3 => DRPEN_IN_LANE3,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPRDY_OUT_LANE1 => DRPRDY_OUT_LANE1,
      DRPRDY_OUT_LANE2 => DRPRDY_OUT_LANE2,
      DRPRDY_OUT_LANE3 => DRPRDY_OUT_LANE3,
      DRPWE_IN => DRPWE_IN,
      DRPWE_IN_LANE1 => DRPWE_IN_LANE1,
      DRPWE_IN_LANE2 => DRPWE_IN_LANE2,
      DRPWE_IN_LANE3 => DRPWE_IN_LANE3,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT,
      ENABLE_ERR_DETECT_0 => ENABLE_ERR_DETECT_1,
      ENABLE_ERR_DETECT_1 => ENABLE_ERR_DETECT_3,
      ENABLE_ERR_DETECT_2 => ENABLE_ERR_DETECT_5,
      ENABLE_ERR_DETECT_Buffer_reg => gt_wrapper_i_n_94,
      ENABLE_ERR_DETECT_Buffer_reg_0 => gt_wrapper_i_n_95,
      ENABLE_ERR_DETECT_Buffer_reg_1 => gt_wrapper_i_n_96,
      ENABLE_ERR_DETECT_Buffer_reg_2 => gt_wrapper_i_n_97,
      \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ => gt_wrapper_i_n_98,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      TXCHARISK(1 downto 0) => tx_char_is_k_i_0(1 downto 0),
      TXDATA(15 downto 0) => tx_data_i_0(15 downto 0),
      TXN(0 to 3) => TXN(0 to 3),
      TXP(0 to 3) => TXP(0 to 3),
      TX_LOCK => \^tx_lock\,
      TX_OUT_CLK => TX_OUT_CLK,
      TX_RESETDONE_OUT => TX_RESETDONE_OUT,
      drpclk_in => drpclk_in,
      gt0_cplllock_out => gt0_cplllock_out,
      gt0_txbufstatus_out(1) => \^gt0_tx_buf_err_out\,
      gt0_txbufstatus_out(0) => \^gt0_txbufstatus_out\(0),
      gt0_txchardispmode_in(1 downto 0) => gt0_txchardispmode_in(1 downto 0),
      gt0_txchardispval_in(1 downto 0) => gt0_txchardispval_in(1 downto 0),
      gt0_txdiffctrl_in(3 downto 0) => gt0_txdiffctrl_in(3 downto 0),
      gt0_txinhibit_in => gt0_txinhibit_in,
      gt0_txmaincursor_in(6 downto 0) => gt0_txmaincursor_in(6 downto 0),
      gt0_txpcsreset_in => gt0_txpcsreset_in,
      gt0_txpmareset_in => gt0_txpmareset_in,
      gt0_txpolarity_in => gt0_txpolarity_in,
      gt0_txpostcursor_in(4 downto 0) => gt0_txpostcursor_in(4 downto 0),
      gt0_txprbsforceerr_in => gt0_txprbsforceerr_in,
      gt0_txprbssel_in(2 downto 0) => gt0_txprbssel_in(2 downto 0),
      gt0_txprecursor_in(4 downto 0) => gt0_txprecursor_in(4 downto 0),
      gt0_txresetdone_out => gt0_txresetdone_out,
      gt1_cplllock_out => gt1_cplllock_out,
      gt1_cplllock_out_0(15 downto 0) => tx_data_i_16(15 downto 0),
      gt1_cplllock_out_1(1 downto 0) => tx_char_is_k_i_2(1 downto 0),
      gt1_txbufstatus_out(1) => \^gt1_tx_buf_err_out\,
      gt1_txbufstatus_out(0) => \^gt1_txbufstatus_out\(0),
      gt1_txchardispmode_in(1 downto 0) => gt1_txchardispmode_in(1 downto 0),
      gt1_txchardispval_in(1 downto 0) => gt1_txchardispval_in(1 downto 0),
      gt1_txdiffctrl_in(3 downto 0) => gt1_txdiffctrl_in(3 downto 0),
      gt1_txinhibit_in => gt1_txinhibit_in,
      gt1_txmaincursor_in(6 downto 0) => gt1_txmaincursor_in(6 downto 0),
      gt1_txpcsreset_in => gt1_txpcsreset_in,
      gt1_txpmareset_in => gt1_txpmareset_in,
      gt1_txpolarity_in => gt1_txpolarity_in,
      gt1_txpostcursor_in(4 downto 0) => gt1_txpostcursor_in(4 downto 0),
      gt1_txprbsforceerr_in => gt1_txprbsforceerr_in,
      gt1_txprbssel_in(2 downto 0) => gt1_txprbssel_in(2 downto 0),
      gt1_txprecursor_in(4 downto 0) => gt1_txprecursor_in(4 downto 0),
      gt1_txresetdone_out => gt1_txresetdone_out,
      gt2_cplllock_out => gt2_cplllock_out,
      gt2_cplllock_out_0(15 downto 0) => tx_data_i_32(15 downto 0),
      gt2_cplllock_out_1(1 downto 0) => tx_char_is_k_i_4(1 downto 0),
      gt2_txbufstatus_out(1) => \^gt2_tx_buf_err_out\,
      gt2_txbufstatus_out(0) => \^gt2_txbufstatus_out\(0),
      gt2_txchardispmode_in(1 downto 0) => gt2_txchardispmode_in(1 downto 0),
      gt2_txchardispval_in(1 downto 0) => gt2_txchardispval_in(1 downto 0),
      gt2_txdiffctrl_in(3 downto 0) => gt2_txdiffctrl_in(3 downto 0),
      gt2_txinhibit_in => gt2_txinhibit_in,
      gt2_txmaincursor_in(6 downto 0) => gt2_txmaincursor_in(6 downto 0),
      gt2_txpcsreset_in => gt2_txpcsreset_in,
      gt2_txpmareset_in => gt2_txpmareset_in,
      gt2_txpolarity_in => gt2_txpolarity_in,
      gt2_txpostcursor_in(4 downto 0) => gt2_txpostcursor_in(4 downto 0),
      gt2_txprbsforceerr_in => gt2_txprbsforceerr_in,
      gt2_txprbssel_in(2 downto 0) => gt2_txprbssel_in(2 downto 0),
      gt2_txprecursor_in(4 downto 0) => gt2_txprecursor_in(4 downto 0),
      gt2_txresetdone_out => gt2_txresetdone_out,
      gt3_cplllock_out => gt3_cplllock_out,
      gt3_cplllock_out_0(15 downto 0) => tx_data_i_48(15 downto 0),
      gt3_cplllock_out_1(1 downto 0) => tx_char_is_k_i_6(1 downto 0),
      gt3_txbufstatus_out(1) => \^gt3_tx_buf_err_out\,
      gt3_txbufstatus_out(0) => \^gt3_txbufstatus_out\(0),
      gt3_txchardispmode_in(1 downto 0) => gt3_txchardispmode_in(1 downto 0),
      gt3_txchardispval_in(1 downto 0) => gt3_txchardispval_in(1 downto 0),
      gt3_txdiffctrl_in(3 downto 0) => gt3_txdiffctrl_in(3 downto 0),
      gt3_txinhibit_in => gt3_txinhibit_in,
      gt3_txmaincursor_in(6 downto 0) => gt3_txmaincursor_in(6 downto 0),
      gt3_txpcsreset_in => gt3_txpcsreset_in,
      gt3_txpmareset_in => gt3_txpmareset_in,
      gt3_txpolarity_in => gt3_txpolarity_in,
      gt3_txpostcursor_in(4 downto 0) => gt3_txpostcursor_in(4 downto 0),
      gt3_txprbsforceerr_in => gt3_txprbsforceerr_in,
      gt3_txprbssel_in(2 downto 0) => gt3_txprbssel_in(2 downto 0),
      gt3_txprecursor_in(4 downto 0) => gt3_txprecursor_in(4 downto 0),
      gt3_txresetdone_out => gt3_txresetdone_out,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      user_clk => user_clk
    );
reset_sync_user_clk_cdc_sync: entity work.efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0
     port map (
      TX_SYSTEM_RESET => TX_SYSTEM_RESET,
      \out\ => reset_sync_user_clk,
      user_clk => user_clk
    );
\simplex_timer_r[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => tx_verify_simplex_r,
      O => sel
    );
\simplex_timer_r[0]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => simplex_timer_r_reg(0),
      O => \simplex_timer_r[0]_i_4_n_0\
    );
\simplex_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[0]_i_3_n_7\,
      Q => simplex_timer_r_reg(0),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \simplex_timer_r_reg[0]_i_3_n_0\,
      CO(2) => \simplex_timer_r_reg[0]_i_3_n_1\,
      CO(1) => \simplex_timer_r_reg[0]_i_3_n_2\,
      CO(0) => \simplex_timer_r_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \simplex_timer_r_reg[0]_i_3_n_4\,
      O(2) => \simplex_timer_r_reg[0]_i_3_n_5\,
      O(1) => \simplex_timer_r_reg[0]_i_3_n_6\,
      O(0) => \simplex_timer_r_reg[0]_i_3_n_7\,
      S(3 downto 1) => simplex_timer_r_reg(3 downto 1),
      S(0) => \simplex_timer_r[0]_i_4_n_0\
    );
\simplex_timer_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[8]_i_1_n_5\,
      Q => simplex_timer_r_reg(10),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[8]_i_1_n_4\,
      Q => simplex_timer_r_reg(11),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[12]_i_1_n_7\,
      Q => simplex_timer_r_reg(12),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \simplex_timer_r_reg[8]_i_1_n_0\,
      CO(3) => \simplex_timer_r_reg[12]_i_1_n_0\,
      CO(2) => \simplex_timer_r_reg[12]_i_1_n_1\,
      CO(1) => \simplex_timer_r_reg[12]_i_1_n_2\,
      CO(0) => \simplex_timer_r_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \simplex_timer_r_reg[12]_i_1_n_4\,
      O(2) => \simplex_timer_r_reg[12]_i_1_n_5\,
      O(1) => \simplex_timer_r_reg[12]_i_1_n_6\,
      O(0) => \simplex_timer_r_reg[12]_i_1_n_7\,
      S(3 downto 0) => simplex_timer_r_reg(15 downto 12)
    );
\simplex_timer_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[12]_i_1_n_6\,
      Q => simplex_timer_r_reg(13),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[12]_i_1_n_5\,
      Q => simplex_timer_r_reg(14),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[12]_i_1_n_4\,
      Q => simplex_timer_r_reg(15),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[16]_i_1_n_7\,
      Q => simplex_timer_r_reg(16),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \simplex_timer_r_reg[12]_i_1_n_0\,
      CO(3 downto 1) => \NLW_simplex_timer_r_reg[16]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \simplex_timer_r_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_simplex_timer_r_reg[16]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1) => \simplex_timer_r_reg[16]_i_1_n_6\,
      O(0) => \simplex_timer_r_reg[16]_i_1_n_7\,
      S(3 downto 2) => B"00",
      S(1 downto 0) => simplex_timer_r_reg(17 downto 16)
    );
\simplex_timer_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[16]_i_1_n_6\,
      Q => simplex_timer_r_reg(17),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[0]_i_3_n_6\,
      Q => simplex_timer_r_reg(1),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[0]_i_3_n_5\,
      Q => simplex_timer_r_reg(2),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[0]_i_3_n_4\,
      Q => simplex_timer_r_reg(3),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[4]_i_1_n_7\,
      Q => simplex_timer_r_reg(4),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \simplex_timer_r_reg[0]_i_3_n_0\,
      CO(3) => \simplex_timer_r_reg[4]_i_1_n_0\,
      CO(2) => \simplex_timer_r_reg[4]_i_1_n_1\,
      CO(1) => \simplex_timer_r_reg[4]_i_1_n_2\,
      CO(0) => \simplex_timer_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \simplex_timer_r_reg[4]_i_1_n_4\,
      O(2) => \simplex_timer_r_reg[4]_i_1_n_5\,
      O(1) => \simplex_timer_r_reg[4]_i_1_n_6\,
      O(0) => \simplex_timer_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => simplex_timer_r_reg(7 downto 4)
    );
\simplex_timer_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[4]_i_1_n_6\,
      Q => simplex_timer_r_reg(5),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[4]_i_1_n_5\,
      Q => simplex_timer_r_reg(6),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[4]_i_1_n_4\,
      Q => simplex_timer_r_reg(7),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[8]_i_1_n_7\,
      Q => simplex_timer_r_reg(8),
      R => simplex_timer_r0
    );
\simplex_timer_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \simplex_timer_r_reg[4]_i_1_n_0\,
      CO(3) => \simplex_timer_r_reg[8]_i_1_n_0\,
      CO(2) => \simplex_timer_r_reg[8]_i_1_n_1\,
      CO(1) => \simplex_timer_r_reg[8]_i_1_n_2\,
      CO(0) => \simplex_timer_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \simplex_timer_r_reg[8]_i_1_n_4\,
      O(2) => \simplex_timer_r_reg[8]_i_1_n_5\,
      O(1) => \simplex_timer_r_reg[8]_i_1_n_6\,
      O(0) => \simplex_timer_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => simplex_timer_r_reg(11 downto 8)
    );
\simplex_timer_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => sel,
      D => \simplex_timer_r_reg[8]_i_1_n_6\,
      Q => simplex_timer_r_reg(9),
      R => simplex_timer_r0
    );
standard_cc_module_i: entity work.efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE
     port map (
      DO_CC_I => DO_CC_I,
      DO_CC_reg_0 => \^sys_reset_out\,
      S_AXI_UFC_TX_REQ => S_AXI_UFC_TX_REQ,
      WARN_CC => WARN_CC,
      next_ufc_header_c => \tx_ll_control_i/next_ufc_header_c\,
      next_ufc_idle_c => \tx_ll_control_i/next_ufc_idle_c\,
      ufc_idle_r_reg => tx_ll_i_n_13,
      user_clk => user_clk
    );
tx_aligned_simplex_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => simplex_timer_r_reg(11),
      I1 => simplex_timer_r_reg(13),
      I2 => simplex_timer_r_reg(8),
      I3 => simplex_timer_r_reg(10),
      I4 => simplex_timer_r_reg(17),
      I5 => simplex_timer_r_reg(14),
      O => tx_aligned_simplex_r_i_2_n_0
    );
tx_aligned_simplex_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => simplex_timer_r_reg(0),
      I1 => simplex_timer_r_reg(1),
      I2 => simplex_timer_r_reg(3),
      I3 => simplex_timer_r_reg(2),
      O => tx_aligned_simplex_r_i_3_n_0
    );
tx_aligned_simplex_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => simplex_timer_r_reg(9),
      I1 => tx_verify_simplex_r_i_2_n_0,
      I2 => simplex_timer_r_reg(12),
      O => tx_aligned_simplex_r_i_4_n_0
    );
tx_aligned_simplex_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_global_logic_simplex_i_n_37,
      Q => tx_aligned_simplex_r,
      R => '0'
    );
tx_aurora_lane_simplex_v5_0_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5
     port map (
      D(0) => HARD_ERR,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT,
      GEN_A => GEN_A,
      GEN_CC => GEN_CC,
      Q(0) => GEN_PAD,
      RESET => RESET,
      SS(0) => \tx_lane_init_simplex_sm_i/rst_r0_8\,
      TXCHARISK(1 downto 0) => tx_char_is_k_i_0(1 downto 0),
      TXDATA(15 downto 0) => tx_data_i_0(15 downto 0),
      TX_LANE_UP(0) => \^tx_lane_up\(0),
      \fc_nb_r_reg[0]\ => tx_ll_i_n_9,
      \fc_nb_r_reg[1]\ => tx_ll_i_n_10,
      \fc_nb_r_reg[2]\ => tx_ll_i_n_11,
      \gen_k_r_reg[0]\(1) => GEN_K(0),
      \gen_k_r_reg[0]\(0) => GEN_K(1),
      \gen_r_r_reg[0]\(1) => GEN_R(0),
      \gen_r_r_reg[0]\(0) => GEN_R(1),
      gen_scp_i => gen_scp_i,
      gen_suf_i => gen_suf_i,
      \gen_v_r_reg[0]\(1) => GEN_V(0),
      \gen_v_r_reg[0]\(0) => GEN_V(1),
      hard_err_flop_r_reg => gt_wrapper_i_n_94,
      hard_err_reset_i => hard_err_reset_i,
      tx_aligned_r => \tx_lane_init_simplex_sm_i/tx_aligned_r\,
      tx_aligned_simplex_r => tx_aligned_simplex_r,
      \tx_pe_data_r_reg[0]\(15) => TX_PE_DATA(0),
      \tx_pe_data_r_reg[0]\(14) => TX_PE_DATA(1),
      \tx_pe_data_r_reg[0]\(13) => TX_PE_DATA(2),
      \tx_pe_data_r_reg[0]\(12) => TX_PE_DATA(3),
      \tx_pe_data_r_reg[0]\(11) => TX_PE_DATA(4),
      \tx_pe_data_r_reg[0]\(10) => TX_PE_DATA(5),
      \tx_pe_data_r_reg[0]\(9) => TX_PE_DATA(6),
      \tx_pe_data_r_reg[0]\(8) => TX_PE_DATA(7),
      \tx_pe_data_r_reg[0]\(7) => TX_PE_DATA(8),
      \tx_pe_data_r_reg[0]\(6) => TX_PE_DATA(9),
      \tx_pe_data_r_reg[0]\(5) => TX_PE_DATA(10),
      \tx_pe_data_r_reg[0]\(4) => TX_PE_DATA(11),
      \tx_pe_data_r_reg[0]\(3) => TX_PE_DATA(12),
      \tx_pe_data_r_reg[0]\(2) => TX_PE_DATA(13),
      \tx_pe_data_r_reg[0]\(1) => TX_PE_DATA(14),
      \tx_pe_data_r_reg[0]\(0) => TX_PE_DATA(15),
      tx_pe_data_v_r_reg(0) => TX_PE_DATA_V,
      user_clk => user_clk
    );
tx_aurora_lane_simplex_v5_1_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1
     port map (
      D(0) => tx_aurora_lane_simplex_v5_1_i_n_5,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT_1,
      Q(0) => tx_ll_i_n_19,
      SS(0) => \tx_lane_init_simplex_sm_i/rst_r0_7\,
      \TX_CHAR_IS_K_Buffer_reg[0]\(1 downto 0) => tx_char_is_k_i_2(1 downto 0),
      \TX_DATA_Buffer_reg[7]\(15 downto 0) => tx_data_i_16(15 downto 0),
      TX_LANE_UP(0) => \^tx_lane_up\(1),
      gen_a_r_reg => tx_global_logic_simplex_i_n_14,
      gen_cc_r_reg => tx_ll_i_n_1,
      \gen_k_r_reg[0]\(1) => tx_global_logic_simplex_i_n_19,
      \gen_k_r_reg[0]\(0) => tx_global_logic_simplex_i_n_20,
      \gen_r_r_reg[0]\(1) => tx_global_logic_simplex_i_n_27,
      \gen_r_r_reg[0]\(0) => tx_global_logic_simplex_i_n_28,
      \gen_v_r_reg[0]\(1) => tx_global_logic_simplex_i_n_7,
      \gen_v_r_reg[0]\(0) => tx_global_logic_simplex_i_n_8,
      hard_err_flop_r_reg => gt_wrapper_i_n_95,
      hard_err_reset_i => hard_err_reset_i_0,
      lane_up_flop_i => tx_global_logic_simplex_i_n_2,
      tx_aligned_r => \tx_lane_init_simplex_sm_i/tx_aligned_r\,
      \tx_pe_data_r_reg[0]\(15) => tx_ll_i_n_38,
      \tx_pe_data_r_reg[0]\(14) => tx_ll_i_n_39,
      \tx_pe_data_r_reg[0]\(13) => tx_ll_i_n_40,
      \tx_pe_data_r_reg[0]\(12) => tx_ll_i_n_41,
      \tx_pe_data_r_reg[0]\(11) => tx_ll_i_n_42,
      \tx_pe_data_r_reg[0]\(10) => tx_ll_i_n_43,
      \tx_pe_data_r_reg[0]\(9) => tx_ll_i_n_44,
      \tx_pe_data_r_reg[0]\(8) => tx_ll_i_n_45,
      \tx_pe_data_r_reg[0]\(7) => tx_ll_i_n_46,
      \tx_pe_data_r_reg[0]\(6) => tx_ll_i_n_47,
      \tx_pe_data_r_reg[0]\(5) => tx_ll_i_n_48,
      \tx_pe_data_r_reg[0]\(4) => tx_ll_i_n_49,
      \tx_pe_data_r_reg[0]\(3) => tx_ll_i_n_50,
      \tx_pe_data_r_reg[0]\(2) => tx_ll_i_n_51,
      \tx_pe_data_r_reg[0]\(1) => tx_ll_i_n_52,
      \tx_pe_data_r_reg[0]\(0) => tx_ll_i_n_53,
      tx_pe_data_v_r_reg(0) => tx_ll_i_n_15,
      user_clk => user_clk
    );
tx_aurora_lane_simplex_v5_2_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2
     port map (
      D(0) => tx_aurora_lane_simplex_v5_2_i_n_5,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT_3,
      Q(0) => tx_ll_i_n_20,
      SS(0) => \tx_lane_init_simplex_sm_i/rst_r0_6\,
      \TX_CHAR_IS_K_Buffer_reg[0]\(1 downto 0) => tx_char_is_k_i_4(1 downto 0),
      \TX_DATA_Buffer_reg[7]\(15 downto 0) => tx_data_i_32(15 downto 0),
      TX_LANE_UP(0) => \^tx_lane_up\(2),
      gen_a_r_reg => tx_global_logic_simplex_i_n_15,
      gen_cc_r_reg => tx_ll_i_n_2,
      \gen_k_r_reg[0]\(1) => tx_global_logic_simplex_i_n_21,
      \gen_k_r_reg[0]\(0) => tx_global_logic_simplex_i_n_22,
      \gen_r_r_reg[0]\(1) => tx_global_logic_simplex_i_n_29,
      \gen_r_r_reg[0]\(0) => tx_global_logic_simplex_i_n_30,
      \gen_v_r_reg[0]\(1) => tx_global_logic_simplex_i_n_9,
      \gen_v_r_reg[0]\(0) => tx_global_logic_simplex_i_n_10,
      hard_err_flop_r_reg => gt_wrapper_i_n_96,
      hard_err_reset_i => hard_err_reset_i_2,
      lane_up_flop_i => tx_global_logic_simplex_i_n_3,
      tx_aligned_r => \tx_lane_init_simplex_sm_i/tx_aligned_r\,
      \tx_pe_data_r_reg[0]\(15) => tx_ll_i_n_54,
      \tx_pe_data_r_reg[0]\(14) => tx_ll_i_n_55,
      \tx_pe_data_r_reg[0]\(13) => tx_ll_i_n_56,
      \tx_pe_data_r_reg[0]\(12) => tx_ll_i_n_57,
      \tx_pe_data_r_reg[0]\(11) => tx_ll_i_n_58,
      \tx_pe_data_r_reg[0]\(10) => tx_ll_i_n_59,
      \tx_pe_data_r_reg[0]\(9) => tx_ll_i_n_60,
      \tx_pe_data_r_reg[0]\(8) => tx_ll_i_n_61,
      \tx_pe_data_r_reg[0]\(7) => tx_ll_i_n_62,
      \tx_pe_data_r_reg[0]\(6) => tx_ll_i_n_63,
      \tx_pe_data_r_reg[0]\(5) => tx_ll_i_n_64,
      \tx_pe_data_r_reg[0]\(4) => tx_ll_i_n_65,
      \tx_pe_data_r_reg[0]\(3) => tx_ll_i_n_66,
      \tx_pe_data_r_reg[0]\(2) => tx_ll_i_n_67,
      \tx_pe_data_r_reg[0]\(1) => tx_ll_i_n_68,
      \tx_pe_data_r_reg[0]\(0) => tx_ll_i_n_69,
      tx_pe_data_v_r_reg(0) => tx_ll_i_n_16,
      user_clk => user_clk
    );
tx_aurora_lane_simplex_v5_3_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3
     port map (
      D(0) => tx_aurora_lane_simplex_v5_3_i_n_5,
      ENABLE_ERR_DETECT => ENABLE_ERR_DETECT_5,
      Q(0) => tx_ll_i_n_21,
      SS(0) => \tx_lane_init_simplex_sm_i/rst_r0\,
      \TX_CHAR_IS_K_Buffer_reg[0]\(1 downto 0) => tx_char_is_k_i_6(1 downto 0),
      \TX_DATA_Buffer_reg[7]\(15 downto 0) => tx_data_i_48(15 downto 0),
      TX_LANE_UP(0) => \^tx_lane_up\(3),
      gen_a_r_reg => tx_global_logic_simplex_i_n_16,
      gen_cc_r_reg => tx_ll_i_n_3,
      gen_ecp_i => gen_ecp_i,
      \gen_k_r_reg[0]\(1) => tx_global_logic_simplex_i_n_23,
      \gen_k_r_reg[0]\(0) => tx_global_logic_simplex_i_n_24,
      \gen_r_r_reg[0]\(1) => tx_global_logic_simplex_i_n_31,
      \gen_r_r_reg[0]\(0) => tx_global_logic_simplex_i_n_32,
      \gen_v_r_reg[0]\(1) => tx_global_logic_simplex_i_n_11,
      \gen_v_r_reg[0]\(0) => tx_global_logic_simplex_i_n_12,
      hard_err_flop_r_reg => gt_wrapper_i_n_97,
      hard_err_reset_i => hard_err_reset_i_4,
      lane_up_flop_i => tx_global_logic_simplex_i_n_4,
      tx_aligned_r => \tx_lane_init_simplex_sm_i/tx_aligned_r\,
      \tx_pe_data_r_reg[0]\(15) => tx_ll_i_n_70,
      \tx_pe_data_r_reg[0]\(14) => tx_ll_i_n_71,
      \tx_pe_data_r_reg[0]\(13) => tx_ll_i_n_72,
      \tx_pe_data_r_reg[0]\(12) => tx_ll_i_n_73,
      \tx_pe_data_r_reg[0]\(11) => tx_ll_i_n_74,
      \tx_pe_data_r_reg[0]\(10) => tx_ll_i_n_75,
      \tx_pe_data_r_reg[0]\(9) => tx_ll_i_n_76,
      \tx_pe_data_r_reg[0]\(8) => tx_ll_i_n_77,
      \tx_pe_data_r_reg[0]\(7) => tx_ll_i_n_78,
      \tx_pe_data_r_reg[0]\(6) => tx_ll_i_n_79,
      \tx_pe_data_r_reg[0]\(5) => tx_ll_i_n_80,
      \tx_pe_data_r_reg[0]\(4) => tx_ll_i_n_81,
      \tx_pe_data_r_reg[0]\(3) => tx_ll_i_n_82,
      \tx_pe_data_r_reg[0]\(2) => tx_ll_i_n_83,
      \tx_pe_data_r_reg[0]\(1) => tx_ll_i_n_84,
      \tx_pe_data_r_reg[0]\(0) => tx_ll_i_n_85,
      tx_pe_data_v_r_reg(0) => tx_ll_i_n_17,
      user_clk => user_clk
    );
tx_bonded1_simplex_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_verify_simplex_r_i_2_n_0,
      I1 => simplex_timer_r_reg(9),
      O => tx_bonded1_simplex_r_i_2_n_0
    );
tx_bonded1_simplex_r_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => simplex_timer_r_reg(0),
      I1 => simplex_timer_r_reg(1),
      I2 => simplex_timer_r_reg(2),
      I3 => simplex_timer_r_reg(8),
      I4 => simplex_timer_r_reg(3),
      O => tx_bonded1_simplex_r_i_3_n_0
    );
tx_bonded1_simplex_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_global_logic_simplex_i_n_36,
      Q => tx_bonded1_simplex_r,
      R => '0'
    );
tx_global_logic_simplex_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX
     port map (
      CHANNEL_HARD_ERR_Buffer_reg => TX_HARD_ERR,
      D(3) => HARD_ERR,
      D(2) => tx_aurora_lane_simplex_v5_1_i_n_5,
      D(1) => tx_aurora_lane_simplex_v5_2_i_n_5,
      D(0) => tx_aurora_lane_simplex_v5_3_i_n_5,
      GEN_A => GEN_A,
      POWER_DOWN => POWER_DOWN,
      RESET => RESET,
      RESET_SYMGEN => RESET_SYMGEN,
      SS(0) => \tx_lane_init_simplex_sm_i/rst_r0_8\,
      TX_CHANNEL_UP => \^tx_channel_up\,
      TX_LANE_UP(0 to 3) => \^tx_lane_up\(0 to 3),
      gen_a_flop_1_i => tx_global_logic_simplex_i_n_14,
      gen_a_flop_2_i => tx_global_logic_simplex_i_n_15,
      gen_a_flop_3_i => tx_global_logic_simplex_i_n_16,
      gen_k_flop_0_i(1) => GEN_K(0),
      gen_k_flop_0_i(0) => GEN_K(1),
      gen_k_flop_2_i(1) => tx_global_logic_simplex_i_n_19,
      gen_k_flop_2_i(0) => tx_global_logic_simplex_i_n_20,
      gen_k_flop_4_i(1) => tx_global_logic_simplex_i_n_21,
      gen_k_flop_4_i(0) => tx_global_logic_simplex_i_n_22,
      gen_k_flop_6_i(1) => tx_global_logic_simplex_i_n_23,
      gen_k_flop_6_i(0) => tx_global_logic_simplex_i_n_24,
      gen_r_flop_0_i(1) => GEN_R(0),
      gen_r_flop_0_i(0) => GEN_R(1),
      gen_r_flop_2_i(1) => tx_global_logic_simplex_i_n_27,
      gen_r_flop_2_i(0) => tx_global_logic_simplex_i_n_28,
      gen_r_flop_4_i(1) => tx_global_logic_simplex_i_n_29,
      gen_r_flop_4_i(0) => tx_global_logic_simplex_i_n_30,
      gen_r_flop_6_i(1) => tx_global_logic_simplex_i_n_31,
      gen_r_flop_6_i(0) => tx_global_logic_simplex_i_n_32,
      gen_v_flop_0_i(1) => GEN_V(0),
      gen_v_flop_0_i(0) => GEN_V(1),
      gen_v_flop_2_i(1) => tx_global_logic_simplex_i_n_7,
      gen_v_flop_2_i(0) => tx_global_logic_simplex_i_n_8,
      gen_v_flop_4_i(1) => tx_global_logic_simplex_i_n_9,
      gen_v_flop_4_i(0) => tx_global_logic_simplex_i_n_10,
      gen_v_flop_6_i(1) => tx_global_logic_simplex_i_n_11,
      gen_v_flop_6_i(0) => tx_global_logic_simplex_i_n_12,
      hard_err_reset_i => hard_err_reset_i,
      hard_err_reset_i_0 => hard_err_reset_i_0,
      hard_err_reset_i_1 => hard_err_reset_i_2,
      hard_err_reset_i_2 => hard_err_reset_i_4,
      reset_channel_i => reset_channel_i,
      reset_lanes_flop_1_i => tx_global_logic_simplex_i_n_2,
      reset_lanes_flop_1_i_0(0) => \tx_lane_init_simplex_sm_i/rst_r0_7\,
      reset_lanes_flop_2_i => tx_global_logic_simplex_i_n_3,
      reset_lanes_flop_2_i_0(0) => \tx_lane_init_simplex_sm_i/rst_r0_6\,
      reset_lanes_flop_3_i => tx_global_logic_simplex_i_n_4,
      reset_lanes_flop_3_i_0(0) => \tx_lane_init_simplex_sm_i/rst_r0\,
      reset_lanes_flop_3_i_1 => \^sys_reset_out\,
      simplex_timer_r0 => simplex_timer_r0,
      simplex_timer_r_reg(2 downto 0) => simplex_timer_r_reg(2 downto 0),
      tx_aligned_simplex_r => tx_aligned_simplex_r,
      tx_aligned_simplex_r_reg => tx_global_logic_simplex_i_n_37,
      tx_aligned_simplex_r_reg_0 => tx_aligned_simplex_r_i_2_n_0,
      tx_aligned_simplex_r_reg_1 => tx_aligned_simplex_r_i_3_n_0,
      tx_aligned_simplex_r_reg_2 => tx_aligned_simplex_r_i_4_n_0,
      tx_bonded1_simplex_r => tx_bonded1_simplex_r,
      tx_bonded1_simplex_r_reg => tx_global_logic_simplex_i_n_36,
      tx_bonded1_simplex_r_reg_0 => tx_verify_simplex_r_i_3_n_0,
      tx_bonded1_simplex_r_reg_1 => tx_bonded1_simplex_r_i_2_n_0,
      tx_bonded1_simplex_r_reg_2 => tx_bonded1_simplex_r_i_3_n_0,
      tx_channel_up_i => tx_global_logic_simplex_i_n_44,
      tx_reset_simplex_r => tx_reset_simplex_r,
      tx_reset_simplex_r_reg => tx_global_logic_simplex_i_n_38,
      tx_reset_simplex_r_reg_0 => tx_reset_simplex_r_i_2_n_0,
      tx_verify_simplex_r => tx_verify_simplex_r,
      tx_verify_simplex_r_reg => tx_global_logic_simplex_i_n_35,
      tx_verify_simplex_r_reg_0 => tx_verify_simplex_r_i_2_n_0,
      tx_verify_simplex_r_reg_1 => tx_verify_simplex_r_i_4_n_0,
      user_clk => user_clk,
      wait_for_lane_up_r0 => \tx_channel_init_sm_simplex_i/wait_for_lane_up_r0\
    );
tx_ll_i: entity work.efex_aurora_hub2_efex_aurora_hub2_TX_LL
     port map (
      DO_CC_I => DO_CC_I,
      GEN_CC => GEN_CC,
      \GEN_PAD_Buffer_reg[0]\(3) => GEN_PAD,
      \GEN_PAD_Buffer_reg[0]\(2) => tx_ll_i_n_19,
      \GEN_PAD_Buffer_reg[0]\(1) => tx_ll_i_n_20,
      \GEN_PAD_Buffer_reg[0]\(0) => tx_ll_i_n_21,
      Q(3) => TX_PE_DATA_V,
      Q(2) => tx_ll_i_n_15,
      Q(1) => tx_ll_i_n_16,
      Q(0) => tx_ll_i_n_17,
      S_AXI_TX_TDATA(63 downto 0) => S_AXI_TX_TDATA(63 downto 0),
      S_AXI_TX_TKEEP(7 downto 0) => S_AXI_TX_TKEEP(7 downto 0),
      S_AXI_TX_TLAST => S_AXI_TX_TLAST,
      S_AXI_TX_TREADY => S_AXI_TX_TREADY,
      S_AXI_TX_TVALID => S_AXI_TX_TVALID,
      S_AXI_UFC_TX_MS(2 downto 0) => S_AXI_UFC_TX_MS(2 downto 0),
      S_AXI_UFC_TX_REQ => S_AXI_UFC_TX_REQ,
      \TX_PE_DATA_Buffer_reg[0]\(63) => TX_PE_DATA(0),
      \TX_PE_DATA_Buffer_reg[0]\(62) => TX_PE_DATA(1),
      \TX_PE_DATA_Buffer_reg[0]\(61) => TX_PE_DATA(2),
      \TX_PE_DATA_Buffer_reg[0]\(60) => TX_PE_DATA(3),
      \TX_PE_DATA_Buffer_reg[0]\(59) => TX_PE_DATA(4),
      \TX_PE_DATA_Buffer_reg[0]\(58) => TX_PE_DATA(5),
      \TX_PE_DATA_Buffer_reg[0]\(57) => TX_PE_DATA(6),
      \TX_PE_DATA_Buffer_reg[0]\(56) => TX_PE_DATA(7),
      \TX_PE_DATA_Buffer_reg[0]\(55) => TX_PE_DATA(8),
      \TX_PE_DATA_Buffer_reg[0]\(54) => TX_PE_DATA(9),
      \TX_PE_DATA_Buffer_reg[0]\(53) => TX_PE_DATA(10),
      \TX_PE_DATA_Buffer_reg[0]\(52) => TX_PE_DATA(11),
      \TX_PE_DATA_Buffer_reg[0]\(51) => TX_PE_DATA(12),
      \TX_PE_DATA_Buffer_reg[0]\(50) => TX_PE_DATA(13),
      \TX_PE_DATA_Buffer_reg[0]\(49) => TX_PE_DATA(14),
      \TX_PE_DATA_Buffer_reg[0]\(48) => TX_PE_DATA(15),
      \TX_PE_DATA_Buffer_reg[0]\(47) => tx_ll_i_n_38,
      \TX_PE_DATA_Buffer_reg[0]\(46) => tx_ll_i_n_39,
      \TX_PE_DATA_Buffer_reg[0]\(45) => tx_ll_i_n_40,
      \TX_PE_DATA_Buffer_reg[0]\(44) => tx_ll_i_n_41,
      \TX_PE_DATA_Buffer_reg[0]\(43) => tx_ll_i_n_42,
      \TX_PE_DATA_Buffer_reg[0]\(42) => tx_ll_i_n_43,
      \TX_PE_DATA_Buffer_reg[0]\(41) => tx_ll_i_n_44,
      \TX_PE_DATA_Buffer_reg[0]\(40) => tx_ll_i_n_45,
      \TX_PE_DATA_Buffer_reg[0]\(39) => tx_ll_i_n_46,
      \TX_PE_DATA_Buffer_reg[0]\(38) => tx_ll_i_n_47,
      \TX_PE_DATA_Buffer_reg[0]\(37) => tx_ll_i_n_48,
      \TX_PE_DATA_Buffer_reg[0]\(36) => tx_ll_i_n_49,
      \TX_PE_DATA_Buffer_reg[0]\(35) => tx_ll_i_n_50,
      \TX_PE_DATA_Buffer_reg[0]\(34) => tx_ll_i_n_51,
      \TX_PE_DATA_Buffer_reg[0]\(33) => tx_ll_i_n_52,
      \TX_PE_DATA_Buffer_reg[0]\(32) => tx_ll_i_n_53,
      \TX_PE_DATA_Buffer_reg[0]\(31) => tx_ll_i_n_54,
      \TX_PE_DATA_Buffer_reg[0]\(30) => tx_ll_i_n_55,
      \TX_PE_DATA_Buffer_reg[0]\(29) => tx_ll_i_n_56,
      \TX_PE_DATA_Buffer_reg[0]\(28) => tx_ll_i_n_57,
      \TX_PE_DATA_Buffer_reg[0]\(27) => tx_ll_i_n_58,
      \TX_PE_DATA_Buffer_reg[0]\(26) => tx_ll_i_n_59,
      \TX_PE_DATA_Buffer_reg[0]\(25) => tx_ll_i_n_60,
      \TX_PE_DATA_Buffer_reg[0]\(24) => tx_ll_i_n_61,
      \TX_PE_DATA_Buffer_reg[0]\(23) => tx_ll_i_n_62,
      \TX_PE_DATA_Buffer_reg[0]\(22) => tx_ll_i_n_63,
      \TX_PE_DATA_Buffer_reg[0]\(21) => tx_ll_i_n_64,
      \TX_PE_DATA_Buffer_reg[0]\(20) => tx_ll_i_n_65,
      \TX_PE_DATA_Buffer_reg[0]\(19) => tx_ll_i_n_66,
      \TX_PE_DATA_Buffer_reg[0]\(18) => tx_ll_i_n_67,
      \TX_PE_DATA_Buffer_reg[0]\(17) => tx_ll_i_n_68,
      \TX_PE_DATA_Buffer_reg[0]\(16) => tx_ll_i_n_69,
      \TX_PE_DATA_Buffer_reg[0]\(15) => tx_ll_i_n_70,
      \TX_PE_DATA_Buffer_reg[0]\(14) => tx_ll_i_n_71,
      \TX_PE_DATA_Buffer_reg[0]\(13) => tx_ll_i_n_72,
      \TX_PE_DATA_Buffer_reg[0]\(12) => tx_ll_i_n_73,
      \TX_PE_DATA_Buffer_reg[0]\(11) => tx_ll_i_n_74,
      \TX_PE_DATA_Buffer_reg[0]\(10) => tx_ll_i_n_75,
      \TX_PE_DATA_Buffer_reg[0]\(9) => tx_ll_i_n_76,
      \TX_PE_DATA_Buffer_reg[0]\(8) => tx_ll_i_n_77,
      \TX_PE_DATA_Buffer_reg[0]\(7) => tx_ll_i_n_78,
      \TX_PE_DATA_Buffer_reg[0]\(6) => tx_ll_i_n_79,
      \TX_PE_DATA_Buffer_reg[0]\(5) => tx_ll_i_n_80,
      \TX_PE_DATA_Buffer_reg[0]\(4) => tx_ll_i_n_81,
      \TX_PE_DATA_Buffer_reg[0]\(3) => tx_ll_i_n_82,
      \TX_PE_DATA_Buffer_reg[0]\(2) => tx_ll_i_n_83,
      \TX_PE_DATA_Buffer_reg[0]\(1) => tx_ll_i_n_84,
      \TX_PE_DATA_Buffer_reg[0]\(0) => tx_ll_i_n_85,
      WARN_CC => WARN_CC,
      gen_cc_flop_1_i => tx_ll_i_n_1,
      gen_cc_flop_2_i => tx_ll_i_n_2,
      gen_cc_flop_3_i => tx_ll_i_n_3,
      gen_ecp_i => gen_ecp_i,
      gen_scp_i => gen_scp_i,
      gen_suf_i => gen_suf_i,
      halt_c_pipeline_r_reg_inv => tx_global_logic_simplex_i_n_44,
      next_ufc_header_c => \tx_ll_control_i/next_ufc_header_c\,
      next_ufc_idle_c => \tx_ll_control_i/next_ufc_idle_c\,
      \s_axi_ufc_tx_tdata[0]\ => tx_ll_i_n_11,
      \s_axi_ufc_tx_tdata[1]\ => tx_ll_i_n_10,
      \s_axi_ufc_tx_tdata[2]\ => tx_ll_i_n_9,
      tx_dst_rdy => tx_dst_rdy,
      tx_sof_n_pipeline_r_reg => axi_to_ll_pdu_i_n_0,
      ufc_header_r_reg => S_AXI_UFC_TX_ACK,
      \ufc_message_count_r_reg[2]\ => tx_ll_i_n_13,
      user_clk => user_clk
    );
tx_reset_simplex_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => tx_reset_simplex_r_i_3_n_0,
      I1 => tx_reset_simplex_r_i_4_n_0,
      I2 => simplex_timer_r_reg(12),
      I3 => tx_verify_simplex_r_i_2_n_0,
      I4 => simplex_timer_r_reg(9),
      O => tx_reset_simplex_r_i_2_n_0
    );
tx_reset_simplex_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => simplex_timer_r_reg(17),
      I1 => simplex_timer_r_reg(14),
      I2 => simplex_timer_r_reg(3),
      O => tx_reset_simplex_r_i_3_n_0
    );
tx_reset_simplex_r_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => simplex_timer_r_reg(10),
      I1 => simplex_timer_r_reg(8),
      I2 => simplex_timer_r_reg(13),
      I3 => simplex_timer_r_reg(11),
      O => tx_reset_simplex_r_i_4_n_0
    );
tx_reset_simplex_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_global_logic_simplex_i_n_38,
      Q => tx_reset_simplex_r,
      R => '0'
    );
tx_verify_simplex_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => simplex_timer_r_reg(15),
      I1 => simplex_timer_r_reg(16),
      I2 => simplex_timer_r_reg(6),
      I3 => simplex_timer_r_reg(7),
      I4 => simplex_timer_r_reg(5),
      I5 => simplex_timer_r_reg(4),
      O => tx_verify_simplex_r_i_2_n_0
    );
tx_verify_simplex_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => simplex_timer_r_reg(12),
      I1 => simplex_timer_r_reg(13),
      I2 => simplex_timer_r_reg(10),
      I3 => simplex_timer_r_reg(11),
      I4 => simplex_timer_r_reg(17),
      I5 => simplex_timer_r_reg(14),
      O => tx_verify_simplex_r_i_3_n_0
    );
tx_verify_simplex_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => simplex_timer_r_reg(2),
      I1 => simplex_timer_r_reg(3),
      I2 => simplex_timer_r_reg(1),
      I3 => simplex_timer_r_reg(0),
      I4 => simplex_timer_r_reg(9),
      I5 => simplex_timer_r_reg(8),
      O => tx_verify_simplex_r_i_4_n_0
    );
tx_verify_simplex_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => tx_global_logic_simplex_i_n_35,
      Q => tx_verify_simplex_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity efex_aurora_hub2 is
  port (
    s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axi_tx_tvalid : in STD_LOGIC;
    s_axi_tx_tready : out STD_LOGIC;
    s_axi_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_tx_tlast : in STD_LOGIC;
    s_axi_ufc_tx_tvalid : in STD_LOGIC;
    s_axi_ufc_tx_tdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_ufc_tx_tready : out STD_LOGIC;
    txp : out STD_LOGIC_VECTOR ( 0 to 3 );
    txn : out STD_LOGIC_VECTOR ( 0 to 3 );
    gt_refclk1 : in STD_LOGIC;
    tx_hard_err : out STD_LOGIC;
    tx_lane_up : out STD_LOGIC_VECTOR ( 0 to 3 );
    tx_channel_up : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    tx_system_reset : in STD_LOGIC;
    power_down : in STD_LOGIC;
    loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_reset : in STD_LOGIC;
    tx_lock : out STD_LOGIC;
    sys_reset_out : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    tx_resetdone_out : out STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in : in STD_LOGIC;
    drprdy_out : out STD_LOGIC;
    drpwe_in : in STD_LOGIC;
    drpaddr_in_lane1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in_lane1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out_lane1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in_lane1 : in STD_LOGIC;
    drprdy_out_lane1 : out STD_LOGIC;
    drpwe_in_lane1 : in STD_LOGIC;
    drpaddr_in_lane2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in_lane2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out_lane2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in_lane2 : in STD_LOGIC;
    drprdy_out_lane2 : out STD_LOGIC;
    drpwe_in_lane2 : in STD_LOGIC;
    drpaddr_in_lane3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in_lane3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out_lane3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in_lane3 : in STD_LOGIC;
    drprdy_out_lane3 : out STD_LOGIC;
    drpwe_in_lane3 : in STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    gt0_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_txpolarity_in : in STD_LOGIC;
    gt0_tx_buf_err_out : out STD_LOGIC;
    gt0_txprbsforceerr_in : in STD_LOGIC;
    gt0_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_txpcsreset_in : in STD_LOGIC;
    gt0_txinhibit_in : in STD_LOGIC;
    gt0_txpmareset_in : in STD_LOGIC;
    gt0_txresetdone_out : out STD_LOGIC;
    gt0_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    gt1_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_txpolarity_in : in STD_LOGIC;
    gt1_tx_buf_err_out : out STD_LOGIC;
    gt1_txprbsforceerr_in : in STD_LOGIC;
    gt1_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_txpcsreset_in : in STD_LOGIC;
    gt1_txinhibit_in : in STD_LOGIC;
    gt1_txpmareset_in : in STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    gt1_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    gt2_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_txpolarity_in : in STD_LOGIC;
    gt2_tx_buf_err_out : out STD_LOGIC;
    gt2_txprbsforceerr_in : in STD_LOGIC;
    gt2_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_txpcsreset_in : in STD_LOGIC;
    gt2_txinhibit_in : in STD_LOGIC;
    gt2_txpmareset_in : in STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    gt2_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    gt3_txpostcursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txprecursor_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_txchardispmode_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txchardispval_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txdiffctrl_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_txmaincursor_in : in STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_txpolarity_in : in STD_LOGIC;
    gt3_tx_buf_err_out : out STD_LOGIC;
    gt3_txprbsforceerr_in : in STD_LOGIC;
    gt3_txprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_txpcsreset_in : in STD_LOGIC;
    gt3_txinhibit_in : in STD_LOGIC;
    gt3_txpmareset_in : in STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    gt3_txbufstatus_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_qplllock_in : in STD_LOGIC;
    gt0_qpllrefclklost_in : in STD_LOGIC;
    gt0_qpllreset_out : out STD_LOGIC;
    gt_qpllclk_quad5_in : in STD_LOGIC;
    gt_qpllrefclk_quad5_in : in STD_LOGIC;
    tx_out_clk : out STD_LOGIC;
    pll_not_locked : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of efex_aurora_hub2 : entity is true;
end efex_aurora_hub2;

architecture STRUCTURE of efex_aurora_hub2 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_gt0_qpllreset_out_UNCONNECTED : STD_LOGIC;
  attribute CC_FREQ_FACTOR : integer;
  attribute CC_FREQ_FACTOR of U0 : label is 24;
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of U0 : label is 0;
  attribute SIM_GTRESET_SPEEDUP : string;
  attribute SIM_GTRESET_SPEEDUP of U0 : label is "FALSE";
begin
  gt0_qpllreset_out <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.efex_aurora_hub2_efex_aurora_hub2_core
     port map (
      DRPADDR_IN(8 downto 0) => drpaddr_in(8 downto 0),
      DRPADDR_IN_LANE1(8 downto 0) => drpaddr_in_lane1(8 downto 0),
      DRPADDR_IN_LANE2(8 downto 0) => drpaddr_in_lane2(8 downto 0),
      DRPADDR_IN_LANE3(8 downto 0) => drpaddr_in_lane3(8 downto 0),
      DRPDI_IN(15 downto 0) => drpdi_in(15 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => drpdi_in_lane1(15 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => drpdi_in_lane2(15 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => drpdi_in_lane3(15 downto 0),
      DRPDO_OUT(15 downto 0) => drpdo_out(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => drpdo_out_lane1(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => drpdo_out_lane2(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => drpdo_out_lane3(15 downto 0),
      DRPEN_IN => drpen_in,
      DRPEN_IN_LANE1 => drpen_in_lane1,
      DRPEN_IN_LANE2 => drpen_in_lane2,
      DRPEN_IN_LANE3 => drpen_in_lane3,
      DRPRDY_OUT => drprdy_out,
      DRPRDY_OUT_LANE1 => drprdy_out_lane1,
      DRPRDY_OUT_LANE2 => drprdy_out_lane2,
      DRPRDY_OUT_LANE3 => drprdy_out_lane3,
      DRPWE_IN => drpwe_in,
      DRPWE_IN_LANE1 => drpwe_in_lane1,
      DRPWE_IN_LANE2 => drpwe_in_lane2,
      DRPWE_IN_LANE3 => drpwe_in_lane3,
      GT_RESET => gt_reset,
      LOOPBACK(2 downto 0) => loopback(2 downto 0),
      PLL_NOT_LOCKED => '0',
      POWER_DOWN => power_down,
      S_AXI_TX_TDATA(63 downto 0) => s_axi_tx_tdata(63 downto 0),
      S_AXI_TX_TKEEP(7 downto 0) => s_axi_tx_tkeep(7 downto 0),
      S_AXI_TX_TLAST => s_axi_tx_tlast,
      S_AXI_TX_TREADY => s_axi_tx_tready,
      S_AXI_TX_TVALID => s_axi_tx_tvalid,
      S_AXI_UFC_TX_ACK => s_axi_ufc_tx_tready,
      S_AXI_UFC_TX_MS(2 downto 0) => s_axi_ufc_tx_tdata(2 downto 0),
      S_AXI_UFC_TX_REQ => s_axi_ufc_tx_tvalid,
      TXN(0 to 3) => txn(0 to 3),
      TXP(0 to 3) => txp(0 to 3),
      TX_CHANNEL_UP => tx_channel_up,
      TX_HARD_ERR => tx_hard_err,
      TX_LANE_UP(0 to 3) => tx_lane_up(0 to 3),
      TX_LOCK => tx_lock,
      TX_OUT_CLK => tx_out_clk,
      TX_RESETDONE_OUT => tx_resetdone_out,
      TX_SYSTEM_RESET => tx_system_reset,
      drpclk_in => drpclk_in,
      gt0_cplllock_out => gt0_cplllock_out,
      gt0_qplllock_in => '0',
      gt0_qpllrefclklost_in => '0',
      gt0_qpllreset_out => NLW_U0_gt0_qpllreset_out_UNCONNECTED,
      gt0_tx_buf_err_out => gt0_tx_buf_err_out,
      gt0_txbufstatus_out(1 downto 0) => gt0_txbufstatus_out(1 downto 0),
      gt0_txchardispmode_in(1 downto 0) => gt0_txchardispmode_in(1 downto 0),
      gt0_txchardispval_in(1 downto 0) => gt0_txchardispval_in(1 downto 0),
      gt0_txdiffctrl_in(3 downto 0) => gt0_txdiffctrl_in(3 downto 0),
      gt0_txinhibit_in => gt0_txinhibit_in,
      gt0_txmaincursor_in(6 downto 0) => gt0_txmaincursor_in(6 downto 0),
      gt0_txpcsreset_in => gt0_txpcsreset_in,
      gt0_txpmareset_in => gt0_txpmareset_in,
      gt0_txpolarity_in => gt0_txpolarity_in,
      gt0_txpostcursor_in(4 downto 0) => gt0_txpostcursor_in(4 downto 0),
      gt0_txprbsforceerr_in => gt0_txprbsforceerr_in,
      gt0_txprbssel_in(2 downto 0) => gt0_txprbssel_in(2 downto 0),
      gt0_txprecursor_in(4 downto 0) => gt0_txprecursor_in(4 downto 0),
      gt0_txresetdone_out => gt0_txresetdone_out,
      gt1_cplllock_out => gt1_cplllock_out,
      gt1_tx_buf_err_out => gt1_tx_buf_err_out,
      gt1_txbufstatus_out(1 downto 0) => gt1_txbufstatus_out(1 downto 0),
      gt1_txchardispmode_in(1 downto 0) => gt1_txchardispmode_in(1 downto 0),
      gt1_txchardispval_in(1 downto 0) => gt1_txchardispval_in(1 downto 0),
      gt1_txdiffctrl_in(3 downto 0) => gt1_txdiffctrl_in(3 downto 0),
      gt1_txinhibit_in => gt1_txinhibit_in,
      gt1_txmaincursor_in(6 downto 0) => gt1_txmaincursor_in(6 downto 0),
      gt1_txpcsreset_in => gt1_txpcsreset_in,
      gt1_txpmareset_in => gt1_txpmareset_in,
      gt1_txpolarity_in => gt1_txpolarity_in,
      gt1_txpostcursor_in(4 downto 0) => gt1_txpostcursor_in(4 downto 0),
      gt1_txprbsforceerr_in => gt1_txprbsforceerr_in,
      gt1_txprbssel_in(2 downto 0) => gt1_txprbssel_in(2 downto 0),
      gt1_txprecursor_in(4 downto 0) => gt1_txprecursor_in(4 downto 0),
      gt1_txresetdone_out => gt1_txresetdone_out,
      gt2_cplllock_out => gt2_cplllock_out,
      gt2_tx_buf_err_out => gt2_tx_buf_err_out,
      gt2_txbufstatus_out(1 downto 0) => gt2_txbufstatus_out(1 downto 0),
      gt2_txchardispmode_in(1 downto 0) => gt2_txchardispmode_in(1 downto 0),
      gt2_txchardispval_in(1 downto 0) => gt2_txchardispval_in(1 downto 0),
      gt2_txdiffctrl_in(3 downto 0) => gt2_txdiffctrl_in(3 downto 0),
      gt2_txinhibit_in => gt2_txinhibit_in,
      gt2_txmaincursor_in(6 downto 0) => gt2_txmaincursor_in(6 downto 0),
      gt2_txpcsreset_in => gt2_txpcsreset_in,
      gt2_txpmareset_in => gt2_txpmareset_in,
      gt2_txpolarity_in => gt2_txpolarity_in,
      gt2_txpostcursor_in(4 downto 0) => gt2_txpostcursor_in(4 downto 0),
      gt2_txprbsforceerr_in => gt2_txprbsforceerr_in,
      gt2_txprbssel_in(2 downto 0) => gt2_txprbssel_in(2 downto 0),
      gt2_txprecursor_in(4 downto 0) => gt2_txprecursor_in(4 downto 0),
      gt2_txresetdone_out => gt2_txresetdone_out,
      gt3_cplllock_out => gt3_cplllock_out,
      gt3_tx_buf_err_out => gt3_tx_buf_err_out,
      gt3_txbufstatus_out(1 downto 0) => gt3_txbufstatus_out(1 downto 0),
      gt3_txchardispmode_in(1 downto 0) => gt3_txchardispmode_in(1 downto 0),
      gt3_txchardispval_in(1 downto 0) => gt3_txchardispval_in(1 downto 0),
      gt3_txdiffctrl_in(3 downto 0) => gt3_txdiffctrl_in(3 downto 0),
      gt3_txinhibit_in => gt3_txinhibit_in,
      gt3_txmaincursor_in(6 downto 0) => gt3_txmaincursor_in(6 downto 0),
      gt3_txpcsreset_in => gt3_txpcsreset_in,
      gt3_txpmareset_in => gt3_txpmareset_in,
      gt3_txpolarity_in => gt3_txpolarity_in,
      gt3_txpostcursor_in(4 downto 0) => gt3_txpostcursor_in(4 downto 0),
      gt3_txprbsforceerr_in => gt3_txprbsforceerr_in,
      gt3_txprbssel_in(2 downto 0) => gt3_txprbssel_in(2 downto 0),
      gt3_txprecursor_in(4 downto 0) => gt3_txprecursor_in(4 downto 0),
      gt3_txresetdone_out => gt3_txresetdone_out,
      gt_qpllclk_quad5_in => gt_qpllclk_quad5_in,
      gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_in,
      gt_refclk1 => gt_refclk1,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      sys_reset_out => sys_reset_out,
      user_clk => user_clk
    );
end STRUCTURE;
