// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
// Date        : Mon Jul  4 11:52:55 2022
// Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_stub.v
// Design      : fifo_40M_160M
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx330tffg1157-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_2_7,Vivado 2022.1" *)
module fifo_40M_160M(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, 
  empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[43:0],wr_en,rd_en,dout[43:0],full,empty" */;
  input rst;
  input wr_clk;
  input rd_clk;
  input [43:0]din;
  input wr_en;
  input rd_en;
  output [43:0]dout;
  output full;
  output empty;
endmodule
