-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
-- Date        : Fri Apr 25 10:10:24 2025
-- Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit AlmaLinux 9.5 (Teal Serval)
-- Command     : write_vhdl -force -mode funcsim
--               /home/fmorodei/builds/zqy4JUuos/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay_sim_netlist.vhdl
-- Design      : io_delay
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx550tffg1927-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity io_delay_io_delay_selectio_wiz is
  port (
    data_in_from_pins_p : in STD_LOGIC_VECTOR ( 15 downto 0 );
    data_in_from_pins_n : in STD_LOGIC_VECTOR ( 15 downto 0 );
    data_in_to_device : out STD_LOGIC_VECTOR ( 15 downto 0 );
    delay_clk : in STD_LOGIC;
    in_delay_reset : in STD_LOGIC;
    in_delay_data_ce : in STD_LOGIC_VECTOR ( 15 downto 0 );
    in_delay_data_inc : in STD_LOGIC_VECTOR ( 15 downto 0 );
    in_delay_tap_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
    in_delay_tap_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );
  attribute DEV_W : integer;
  attribute DEV_W of io_delay_io_delay_selectio_wiz : entity is 16;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of io_delay_io_delay_selectio_wiz : entity is "io_delay_selectio_wiz";
  attribute SYS_W : integer;
  attribute SYS_W of io_delay_io_delay_selectio_wiz : entity is 16;
end io_delay_io_delay_selectio_wiz;

architecture STRUCTURE of io_delay_io_delay_selectio_wiz is
  signal data_in_from_pins_delay : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of delayctrl : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of delayctrl : label is "io_delay_group";
  attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB : string;
  attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[0].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \pins[0].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE : string;
  attribute IBUF_DELAY_VALUE of \pins[0].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE : string;
  attribute IFD_DELAY_VALUE of \pins[0].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[0].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[0].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \pins[0].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[10].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[10].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[10].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[10].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[10].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[10].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[10].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[10].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[10].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[11].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[11].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[11].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[11].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[11].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[11].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[11].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[11].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[11].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[12].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[12].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[12].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[12].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[12].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[12].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[12].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[12].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[12].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[13].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[13].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[13].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[13].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[13].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[13].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[13].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[13].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[13].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[14].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[14].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[14].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[14].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[14].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[14].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[14].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[14].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[14].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[15].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[15].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[15].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[15].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[15].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[15].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[15].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[15].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[15].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[1].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[1].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[1].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[1].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[1].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[1].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[1].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[2].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[2].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[2].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[2].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[2].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[2].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[2].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[2].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[2].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[3].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[3].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[3].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[3].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[3].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[3].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[3].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[3].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[3].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[4].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[4].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[4].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[4].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[4].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[4].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[4].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[4].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[4].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[5].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[5].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[5].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[5].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[5].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[5].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[5].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[5].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[5].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[6].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[6].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[6].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[6].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[6].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[6].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[6].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[6].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[6].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[7].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[7].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[7].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[7].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[7].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[7].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[7].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[7].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[7].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[8].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[8].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[8].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[8].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[8].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[8].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[8].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[8].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[8].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[9].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[9].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[9].ibufds_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[9].ibufds_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[9].ibufds_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[9].ibufds_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[9].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[9].idelaye2_bus\ : label is "io_delay_group";
  attribute SIM_DELAY_D of \pins[9].idelaye2_bus\ : label is 0;
begin
delayctrl: unisim.vcomponents.IDELAYCTRL
    generic map(
      SIM_DEVICE => "7SERIES"
    )
        port map (
      RDY => delay_locked,
      REFCLK => ref_clock,
      RST => io_reset
    );
\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(0),
      Q => data_in_to_device(0),
      R => io_reset
    );
\pins[0].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(0),
      IB => data_in_from_pins_n(0),
      O => data_in_from_pins_int(0)
    );
\pins[0].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(0),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(4 downto 0),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(0),
      IDATAIN => data_in_from_pins_int(0),
      INC => in_delay_data_inc(0),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[10].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(10),
      Q => data_in_to_device(10),
      R => io_reset
    );
\pins[10].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(10),
      IB => data_in_from_pins_n(10),
      O => data_in_from_pins_int(10)
    );
\pins[10].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(10),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(54 downto 50),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(54 downto 50),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(10),
      IDATAIN => data_in_from_pins_int(10),
      INC => in_delay_data_inc(10),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[11].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(11),
      Q => data_in_to_device(11),
      R => io_reset
    );
\pins[11].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(11),
      IB => data_in_from_pins_n(11),
      O => data_in_from_pins_int(11)
    );
\pins[11].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(11),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(59 downto 55),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(59 downto 55),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(11),
      IDATAIN => data_in_from_pins_int(11),
      INC => in_delay_data_inc(11),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[12].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(12),
      Q => data_in_to_device(12),
      R => io_reset
    );
\pins[12].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(12),
      IB => data_in_from_pins_n(12),
      O => data_in_from_pins_int(12)
    );
\pins[12].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(12),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(64 downto 60),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(64 downto 60),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(12),
      IDATAIN => data_in_from_pins_int(12),
      INC => in_delay_data_inc(12),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[13].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(13),
      Q => data_in_to_device(13),
      R => io_reset
    );
\pins[13].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(13),
      IB => data_in_from_pins_n(13),
      O => data_in_from_pins_int(13)
    );
\pins[13].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(13),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(69 downto 65),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(69 downto 65),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(13),
      IDATAIN => data_in_from_pins_int(13),
      INC => in_delay_data_inc(13),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[14].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(14),
      Q => data_in_to_device(14),
      R => io_reset
    );
\pins[14].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(14),
      IB => data_in_from_pins_n(14),
      O => data_in_from_pins_int(14)
    );
\pins[14].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(14),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(74 downto 70),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(74 downto 70),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(14),
      IDATAIN => data_in_from_pins_int(14),
      INC => in_delay_data_inc(14),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[15].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(15),
      Q => data_in_to_device(15),
      R => io_reset
    );
\pins[15].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(15),
      IB => data_in_from_pins_n(15),
      O => data_in_from_pins_int(15)
    );
\pins[15].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(15),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(79 downto 75),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(79 downto 75),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(15),
      IDATAIN => data_in_from_pins_int(15),
      INC => in_delay_data_inc(15),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(1),
      Q => data_in_to_device(1),
      R => io_reset
    );
\pins[1].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(1),
      IB => data_in_from_pins_n(1),
      O => data_in_from_pins_int(1)
    );
\pins[1].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(1),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(9 downto 5),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(9 downto 5),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(1),
      IDATAIN => data_in_from_pins_int(1),
      INC => in_delay_data_inc(1),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[2].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(2),
      Q => data_in_to_device(2),
      R => io_reset
    );
\pins[2].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(2),
      IB => data_in_from_pins_n(2),
      O => data_in_from_pins_int(2)
    );
\pins[2].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(2),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(14 downto 10),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(14 downto 10),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(2),
      IDATAIN => data_in_from_pins_int(2),
      INC => in_delay_data_inc(2),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[3].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(3),
      Q => data_in_to_device(3),
      R => io_reset
    );
\pins[3].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(3),
      IB => data_in_from_pins_n(3),
      O => data_in_from_pins_int(3)
    );
\pins[3].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(3),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(19 downto 15),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(19 downto 15),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(3),
      IDATAIN => data_in_from_pins_int(3),
      INC => in_delay_data_inc(3),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[4].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(4),
      Q => data_in_to_device(4),
      R => io_reset
    );
\pins[4].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(4),
      IB => data_in_from_pins_n(4),
      O => data_in_from_pins_int(4)
    );
\pins[4].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(4),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(24 downto 20),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(24 downto 20),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(4),
      IDATAIN => data_in_from_pins_int(4),
      INC => in_delay_data_inc(4),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[5].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(5),
      Q => data_in_to_device(5),
      R => io_reset
    );
\pins[5].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(5),
      IB => data_in_from_pins_n(5),
      O => data_in_from_pins_int(5)
    );
\pins[5].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(5),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(29 downto 25),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(29 downto 25),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(5),
      IDATAIN => data_in_from_pins_int(5),
      INC => in_delay_data_inc(5),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[6].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(6),
      Q => data_in_to_device(6),
      R => io_reset
    );
\pins[6].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(6),
      IB => data_in_from_pins_n(6),
      O => data_in_from_pins_int(6)
    );
\pins[6].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(6),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(34 downto 30),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(34 downto 30),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(6),
      IDATAIN => data_in_from_pins_int(6),
      INC => in_delay_data_inc(6),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[7].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(7),
      Q => data_in_to_device(7),
      R => io_reset
    );
\pins[7].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(7),
      IB => data_in_from_pins_n(7),
      O => data_in_from_pins_int(7)
    );
\pins[7].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(7),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(39 downto 35),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(39 downto 35),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(7),
      IDATAIN => data_in_from_pins_int(7),
      INC => in_delay_data_inc(7),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[8].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(8),
      Q => data_in_to_device(8),
      R => io_reset
    );
\pins[8].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(8),
      IB => data_in_from_pins_n(8),
      O => data_in_from_pins_int(8)
    );
\pins[8].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(8),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(44 downto 40),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(44 downto 40),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(8),
      IDATAIN => data_in_from_pins_int(8),
      INC => in_delay_data_inc(8),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[9].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(9),
      Q => data_in_to_device(9),
      R => io_reset
    );
\pins[9].ibufds_inst\: unisim.vcomponents.IBUFDS
     port map (
      I => data_in_from_pins_p(9),
      IB => data_in_from_pins_n(9),
      O => data_in_from_pins_int(9)
    );
\pins[9].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(9),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(49 downto 45),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(49 downto 45),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(9),
      IDATAIN => data_in_from_pins_int(9),
      INC => in_delay_data_inc(9),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity io_delay is
  port (
    data_in_from_pins_p : in STD_LOGIC_VECTOR ( 15 downto 0 );
    data_in_from_pins_n : in STD_LOGIC_VECTOR ( 15 downto 0 );
    data_in_to_device : out STD_LOGIC_VECTOR ( 15 downto 0 );
    delay_clk : in STD_LOGIC;
    in_delay_reset : in STD_LOGIC;
    in_delay_data_ce : in STD_LOGIC_VECTOR ( 15 downto 0 );
    in_delay_data_inc : in STD_LOGIC_VECTOR ( 15 downto 0 );
    in_delay_tap_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
    in_delay_tap_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of io_delay : entity is true;
  attribute DEV_W : integer;
  attribute DEV_W of io_delay : entity is 16;
  attribute SYS_W : integer;
  attribute SYS_W of io_delay : entity is 16;
end io_delay;

architecture STRUCTURE of io_delay is
  attribute DEV_W of inst : label is 16;
  attribute SYS_W of inst : label is 16;
begin
inst: entity work.io_delay_io_delay_selectio_wiz
     port map (
      clk_in => clk_in,
      data_in_from_pins_n(15 downto 0) => data_in_from_pins_n(15 downto 0),
      data_in_from_pins_p(15 downto 0) => data_in_from_pins_p(15 downto 0),
      data_in_to_device(15 downto 0) => data_in_to_device(15 downto 0),
      delay_clk => delay_clk,
      delay_locked => delay_locked,
      in_delay_data_ce(15 downto 0) => in_delay_data_ce(15 downto 0),
      in_delay_data_inc(15 downto 0) => in_delay_data_inc(15 downto 0),
      in_delay_reset => in_delay_reset,
      in_delay_tap_in(79 downto 0) => in_delay_tap_in(79 downto 0),
      in_delay_tap_out(79 downto 0) => in_delay_tap_out(79 downto 0),
      io_reset => io_reset,
      ref_clock => ref_clock
    );
end STRUCTURE;
