
// file: io_delay2.v
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`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "io_delay2,selectio_wiz_v5_1_14,{component_name=io_delay2,bus_dir=INPUTS,bus_sig_type=DIFF,bus_io_std=LVDS,use_serialization=false,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=1,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=VAR_LOADABLE,selio_bus_out_delay=NONE,selio_clk_buf=MMCM,selio_active_edge=SDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVDS,selio_clk_sig_type=DIFF}" *)

module io_delay2
   // width of the data for the system
 #(parameter SYS_W = 1,
   // width of the data for the device
   parameter DEV_W = 1)
 (
  // From the system into the device
  input  [SYS_W-1:0] data_in_from_pins_p,
  input  [SYS_W-1:0] data_in_from_pins_n,
  output [DEV_W-1:0] data_in_to_device,
  input              delay_clk,
  input              in_delay_reset,                       // Active high synchronous reset for input delay
  input  [SYS_W -1 :0]           in_delay_data_ce,                     // Enable signal for delay
  input  [SYS_W -1 :0]           in_delay_data_inc,                    // Delay increment (high), decrement (low) signal
  input  [5*SYS_W -1:0]       in_delay_tap_in,  // Dynamically loadable delay tap value for input delay
  output [5*SYS_W -1:0]       in_delay_tap_out, // Delay tap value for monitoring input delay
  output             delay_locked,   // Locked signal from IDELAYCTRL
  input              ref_clock,      // Reference clock for IDELAYCTRL. Has to come from BUFG.
  input              clk_in,        // Fast clock input from PLL/MMCM
  input              io_reset);


  io_delay2_selectio_wiz 
  #(
   .SYS_W(SYS_W),
   .DEV_W(DEV_W)
  )
  inst
 (
   .data_in_from_pins_p(data_in_from_pins_p),
   .data_in_from_pins_n(data_in_from_pins_n),
   .data_in_to_device(data_in_to_device),
   .delay_clk(delay_clk),
   .in_delay_reset(in_delay_reset),                    
   .in_delay_data_ce(in_delay_data_ce),      
   .in_delay_data_inc(in_delay_data_inc),     
   .in_delay_tap_in(in_delay_tap_in),          
   .in_delay_tap_out(in_delay_tap_out),         
   .delay_locked(delay_locked),                      
   .ref_clock(ref_clock),                         
   .clk_in(clk_in),                            
   .io_reset(io_reset)
); 

endmodule

