-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Tue Apr  6 11:45:23 2021
-- Host        : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/io_delay_control_in/io_delay_control_in_sim_netlist.vhdl
-- Design      : io_delay_control_in
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx330tffg1157-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity io_delay_control_in_io_delay_control_in_selectio_wiz is
  port (
    data_in_from_pins : in STD_LOGIC_VECTOR ( 9 downto 0 );
    data_in_to_device : out STD_LOGIC_VECTOR ( 9 downto 0 );
    delay_clk : in STD_LOGIC;
    in_delay_reset : in STD_LOGIC;
    in_delay_data_ce : in STD_LOGIC_VECTOR ( 9 downto 0 );
    in_delay_data_inc : in STD_LOGIC_VECTOR ( 9 downto 0 );
    in_delay_tap_in : in STD_LOGIC_VECTOR ( 49 downto 0 );
    in_delay_tap_out : out STD_LOGIC_VECTOR ( 49 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );
  attribute DEV_W : integer;
  attribute DEV_W of io_delay_control_in_io_delay_control_in_selectio_wiz : entity is 10;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of io_delay_control_in_io_delay_control_in_selectio_wiz : entity is "io_delay_control_in_selectio_wiz";
  attribute SYS_W : integer;
  attribute SYS_W of io_delay_control_in_io_delay_control_in_selectio_wiz : entity is 10;
end io_delay_control_in_io_delay_control_in_selectio_wiz;

architecture STRUCTURE of io_delay_control_in_io_delay_control_in_selectio_wiz is
  signal data_in_from_pins_delay : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal ref_clock_bufg : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of delayctrl : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of delayctrl : label is "io_delay_control_in_group";
  attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB : string;
  attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE : string;
  attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE : string;
  attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[0].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[0].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \pins[0].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[1].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[1].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[1].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[2].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[2].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[2].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[2].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[2].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[2].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[2].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[2].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[2].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[3].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[3].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[3].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[3].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[3].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[3].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[3].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[3].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[3].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[4].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[4].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[4].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[4].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[4].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[4].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[4].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[4].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[4].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[5].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[5].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[5].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[5].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[5].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[5].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[5].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[5].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[5].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[6].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[6].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[6].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[6].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[6].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[6].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[6].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[6].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[6].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[7].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[7].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[7].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[7].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[7].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[7].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[7].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[7].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[7].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[8].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[8].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[8].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[8].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[8].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[8].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[8].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[8].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[8].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[9].fdre_in_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[9].fdre_in_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[9].ibuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[9].ibuf_inst\ : label is "DONT_CARE";
  attribute IBUF_DELAY_VALUE of \pins[9].ibuf_inst\ : label is "0";
  attribute IFD_DELAY_VALUE of \pins[9].ibuf_inst\ : label is "AUTO";
  attribute BOX_TYPE of \pins[9].idelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[9].idelaye2_bus\ : label is "io_delay_control_in_group";
  attribute SIM_DELAY_D of \pins[9].idelaye2_bus\ : label is 0;
  attribute BOX_TYPE of ref_clk_bufg : label is "PRIMITIVE";
begin
delayctrl: unisim.vcomponents.IDELAYCTRL
    generic map(
      SIM_DEVICE => "7SERIES"
    )
        port map (
      RDY => delay_locked,
      REFCLK => ref_clock_bufg,
      RST => io_reset
    );
\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(0),
      Q => data_in_to_device(0),
      R => io_reset
    );
\pins[0].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(0),
      O => data_in_from_pins_int(0)
    );
\pins[0].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(0),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(4 downto 0),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(0),
      IDATAIN => data_in_from_pins_int(0),
      INC => in_delay_data_inc(0),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(1),
      Q => data_in_to_device(1),
      R => io_reset
    );
\pins[1].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(1),
      O => data_in_from_pins_int(1)
    );
\pins[1].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(1),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(9 downto 5),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(9 downto 5),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(1),
      IDATAIN => data_in_from_pins_int(1),
      INC => in_delay_data_inc(1),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[2].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(2),
      Q => data_in_to_device(2),
      R => io_reset
    );
\pins[2].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(2),
      O => data_in_from_pins_int(2)
    );
\pins[2].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(2),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(14 downto 10),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(14 downto 10),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(2),
      IDATAIN => data_in_from_pins_int(2),
      INC => in_delay_data_inc(2),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[3].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(3),
      Q => data_in_to_device(3),
      R => io_reset
    );
\pins[3].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(3),
      O => data_in_from_pins_int(3)
    );
\pins[3].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(3),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(19 downto 15),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(19 downto 15),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(3),
      IDATAIN => data_in_from_pins_int(3),
      INC => in_delay_data_inc(3),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[4].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(4),
      Q => data_in_to_device(4),
      R => io_reset
    );
\pins[4].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(4),
      O => data_in_from_pins_int(4)
    );
\pins[4].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(4),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(24 downto 20),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(24 downto 20),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(4),
      IDATAIN => data_in_from_pins_int(4),
      INC => in_delay_data_inc(4),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[5].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(5),
      Q => data_in_to_device(5),
      R => io_reset
    );
\pins[5].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(5),
      O => data_in_from_pins_int(5)
    );
\pins[5].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(5),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(29 downto 25),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(29 downto 25),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(5),
      IDATAIN => data_in_from_pins_int(5),
      INC => in_delay_data_inc(5),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[6].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(6),
      Q => data_in_to_device(6),
      R => io_reset
    );
\pins[6].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(6),
      O => data_in_from_pins_int(6)
    );
\pins[6].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(6),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(34 downto 30),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(34 downto 30),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(6),
      IDATAIN => data_in_from_pins_int(6),
      INC => in_delay_data_inc(6),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[7].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(7),
      Q => data_in_to_device(7),
      R => io_reset
    );
\pins[7].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(7),
      O => data_in_from_pins_int(7)
    );
\pins[7].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(7),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(39 downto 35),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(39 downto 35),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(7),
      IDATAIN => data_in_from_pins_int(7),
      INC => in_delay_data_inc(7),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[8].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(8),
      Q => data_in_to_device(8),
      R => io_reset
    );
\pins[8].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(8),
      O => data_in_from_pins_int(8)
    );
\pins[8].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(8),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(44 downto 40),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(44 downto 40),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(8),
      IDATAIN => data_in_from_pins_int(8),
      INC => in_delay_data_inc(8),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
\pins[9].fdre_in_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_in_from_pins_delay(9),
      Q => data_in_to_device(9),
      R => io_reset
    );
\pins[9].ibuf_inst\: unisim.vcomponents.IBUF
     port map (
      I => data_in_from_pins(9),
      O => data_in_from_pins_int(9)
    );
\pins[9].idelaye2_bus\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IDELAY_TYPE => "VAR_LOAD",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => in_delay_data_ce(9),
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => in_delay_tap_in(49 downto 45),
      CNTVALUEOUT(4 downto 0) => in_delay_tap_out(49 downto 45),
      DATAIN => '0',
      DATAOUT => data_in_from_pins_delay(9),
      IDATAIN => data_in_from_pins_int(9),
      INC => in_delay_data_inc(9),
      LD => in_delay_reset,
      LDPIPEEN => '0',
      REGRST => io_reset
    );
ref_clk_bufg: unisim.vcomponents.BUFG
     port map (
      I => ref_clock,
      O => ref_clock_bufg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity io_delay_control_in is
  port (
    data_in_from_pins : in STD_LOGIC_VECTOR ( 9 downto 0 );
    data_in_to_device : out STD_LOGIC_VECTOR ( 9 downto 0 );
    delay_clk : in STD_LOGIC;
    in_delay_reset : in STD_LOGIC;
    in_delay_data_ce : in STD_LOGIC_VECTOR ( 9 downto 0 );
    in_delay_data_inc : in STD_LOGIC_VECTOR ( 9 downto 0 );
    in_delay_tap_in : in STD_LOGIC_VECTOR ( 49 downto 0 );
    in_delay_tap_out : out STD_LOGIC_VECTOR ( 49 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of io_delay_control_in : entity is true;
  attribute DEV_W : integer;
  attribute DEV_W of io_delay_control_in : entity is 10;
  attribute SYS_W : integer;
  attribute SYS_W of io_delay_control_in : entity is 10;
end io_delay_control_in;

architecture STRUCTURE of io_delay_control_in is
  attribute DEV_W of inst : label is 10;
  attribute SYS_W of inst : label is 10;
begin
inst: entity work.io_delay_control_in_io_delay_control_in_selectio_wiz
     port map (
      clk_in => clk_in,
      data_in_from_pins(9 downto 0) => data_in_from_pins(9 downto 0),
      data_in_to_device(9 downto 0) => data_in_to_device(9 downto 0),
      delay_clk => delay_clk,
      delay_locked => delay_locked,
      in_delay_data_ce(9 downto 0) => in_delay_data_ce(9 downto 0),
      in_delay_data_inc(9 downto 0) => in_delay_data_inc(9 downto 0),
      in_delay_reset => in_delay_reset,
      in_delay_tap_in(49 downto 0) => in_delay_tap_in(49 downto 0),
      in_delay_tap_out(49 downto 0) => in_delay_tap_out(49 downto 0),
      io_reset => io_reset,
      ref_clock => ref_clock
    );
end STRUCTURE;
