// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Tue Apr  6 11:47:17 2021
// Host        : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode funcsim
//               /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/io_delay_control_out/io_delay_control_out_sim_netlist.v
// Design      : io_delay_control_out
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7vx330tffg1157-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* DEV_W = "11" *) (* SYS_W = "11" *) 
(* NotValidForBitStream *)
module io_delay_control_out
   (data_out_from_device,
    data_out_to_pins,
    delay_clk,
    out_delay_reset,
    out_delay_data_ce,
    out_delay_data_inc,
    out_delay_tap_in,
    out_delay_tap_out,
    delay_locked,
    ref_clock,
    clk_in,
    io_reset);
  input [10:0]data_out_from_device;
  output [10:0]data_out_to_pins;
  input delay_clk;
  input out_delay_reset;
  input [10:0]out_delay_data_ce;
  input [10:0]out_delay_data_inc;
  input [54:0]out_delay_tap_in;
  output [54:0]out_delay_tap_out;
  output delay_locked;
  input ref_clock;
  input clk_in;
  input io_reset;

  wire clk_in;
  wire [10:0]data_out_from_device;
  (* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS18" *) (* SLEW = "SLOW" *) wire [10:0]data_out_to_pins;
  wire delay_clk;
  wire delay_locked;
  wire io_reset;
  wire [10:0]out_delay_data_ce;
  wire [10:0]out_delay_data_inc;
  wire out_delay_reset;
  wire [54:0]out_delay_tap_in;
  wire [54:0]out_delay_tap_out;
  wire ref_clock;

  (* DEV_W = "11" *) 
  (* SYS_W = "11" *) 
  io_delay_control_out_io_delay_control_out_selectio_wiz inst
       (.clk_in(clk_in),
        .data_out_from_device(data_out_from_device),
        .data_out_to_pins(data_out_to_pins),
        .delay_clk(delay_clk),
        .delay_locked(delay_locked),
        .io_reset(io_reset),
        .out_delay_data_ce(out_delay_data_ce),
        .out_delay_data_inc(out_delay_data_inc),
        .out_delay_reset(out_delay_reset),
        .out_delay_tap_in(out_delay_tap_in),
        .out_delay_tap_out(out_delay_tap_out),
        .ref_clock(ref_clock));
endmodule

(* DEV_W = "11" *) (* ORIG_REF_NAME = "io_delay_control_out_selectio_wiz" *) (* SYS_W = "11" *) 
module io_delay_control_out_io_delay_control_out_selectio_wiz
   (data_out_from_device,
    data_out_to_pins,
    delay_clk,
    out_delay_reset,
    out_delay_data_ce,
    out_delay_data_inc,
    out_delay_tap_in,
    out_delay_tap_out,
    delay_locked,
    ref_clock,
    clk_in,
    io_reset);
  input [10:0]data_out_from_device;
  output [10:0]data_out_to_pins;
  input delay_clk;
  input out_delay_reset;
  input [10:0]out_delay_data_ce;
  input [10:0]out_delay_data_inc;
  input [54:0]out_delay_tap_in;
  output [54:0]out_delay_tap_out;
  output delay_locked;
  input ref_clock;
  input clk_in;
  input io_reset;

  wire clk_in;
  wire [10:0]data_out_from_device;
  wire [10:0]data_out_to_pins;
  wire [10:0]data_out_to_pins_int;
  wire delay_clk;
  wire delay_locked;
  wire io_reset;
  wire [10:0]out_delay_data_ce;
  wire [10:0]out_delay_data_inc;
  wire out_delay_reset;
  wire [54:0]out_delay_tap_in;
  wire [54:0]out_delay_tap_out;
  wire \pins[0].data_out_from_device_q ;
  wire \pins[10].data_out_from_device_q ;
  wire \pins[1].data_out_from_device_q ;
  wire \pins[2].data_out_from_device_q ;
  wire \pins[3].data_out_from_device_q ;
  wire \pins[4].data_out_from_device_q ;
  wire \pins[5].data_out_from_device_q ;
  wire \pins[6].data_out_from_device_q ;
  wire \pins[7].data_out_from_device_q ;
  wire \pins[8].data_out_from_device_q ;
  wire \pins[9].data_out_from_device_q ;
  wire ref_clock;
  wire ref_clock_bufg;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  IDELAYCTRL #(
    .SIM_DEVICE("7SERIES")) 
    delayctrl
       (.RDY(delay_locked),
        .REFCLK(ref_clock_bufg),
        .RST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[0].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[0]),
        .Q(\pins[0].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[0].obuf_inst 
       (.I(data_out_to_pins_int[0]),
        .O(data_out_to_pins[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[0].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[0]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[4:0]),
        .CNTVALUEOUT(out_delay_tap_out[4:0]),
        .DATAOUT(data_out_to_pins_int[0]),
        .INC(out_delay_data_inc[0]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[0].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[10].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[10]),
        .Q(\pins[10].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[10].obuf_inst 
       (.I(data_out_to_pins_int[10]),
        .O(data_out_to_pins[10]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[10].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[10]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[54:50]),
        .CNTVALUEOUT(out_delay_tap_out[54:50]),
        .DATAOUT(data_out_to_pins_int[10]),
        .INC(out_delay_data_inc[10]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[10].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[1].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[1]),
        .Q(\pins[1].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[1].obuf_inst 
       (.I(data_out_to_pins_int[1]),
        .O(data_out_to_pins[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[1].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[1]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[9:5]),
        .CNTVALUEOUT(out_delay_tap_out[9:5]),
        .DATAOUT(data_out_to_pins_int[1]),
        .INC(out_delay_data_inc[1]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[1].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[2].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[2]),
        .Q(\pins[2].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[2].obuf_inst 
       (.I(data_out_to_pins_int[2]),
        .O(data_out_to_pins[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[2].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[2]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[14:10]),
        .CNTVALUEOUT(out_delay_tap_out[14:10]),
        .DATAOUT(data_out_to_pins_int[2]),
        .INC(out_delay_data_inc[2]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[2].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[3].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[3]),
        .Q(\pins[3].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[3].obuf_inst 
       (.I(data_out_to_pins_int[3]),
        .O(data_out_to_pins[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[3].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[3]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[19:15]),
        .CNTVALUEOUT(out_delay_tap_out[19:15]),
        .DATAOUT(data_out_to_pins_int[3]),
        .INC(out_delay_data_inc[3]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[3].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[4].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[4]),
        .Q(\pins[4].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[4].obuf_inst 
       (.I(data_out_to_pins_int[4]),
        .O(data_out_to_pins[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[4].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[4]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[24:20]),
        .CNTVALUEOUT(out_delay_tap_out[24:20]),
        .DATAOUT(data_out_to_pins_int[4]),
        .INC(out_delay_data_inc[4]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[4].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[5].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[5]),
        .Q(\pins[5].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[5].obuf_inst 
       (.I(data_out_to_pins_int[5]),
        .O(data_out_to_pins[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[5].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[5]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[29:25]),
        .CNTVALUEOUT(out_delay_tap_out[29:25]),
        .DATAOUT(data_out_to_pins_int[5]),
        .INC(out_delay_data_inc[5]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[5].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[6].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[6]),
        .Q(\pins[6].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[6].obuf_inst 
       (.I(data_out_to_pins_int[6]),
        .O(data_out_to_pins[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[6].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[6]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[34:30]),
        .CNTVALUEOUT(out_delay_tap_out[34:30]),
        .DATAOUT(data_out_to_pins_int[6]),
        .INC(out_delay_data_inc[6]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[6].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[7].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[7]),
        .Q(\pins[7].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[7].obuf_inst 
       (.I(data_out_to_pins_int[7]),
        .O(data_out_to_pins[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[7].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[7]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[39:35]),
        .CNTVALUEOUT(out_delay_tap_out[39:35]),
        .DATAOUT(data_out_to_pins_int[7]),
        .INC(out_delay_data_inc[7]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[7].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[8].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[8]),
        .Q(\pins[8].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[8].obuf_inst 
       (.I(data_out_to_pins_int[8]),
        .O(data_out_to_pins[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[8].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[8]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[44:40]),
        .CNTVALUEOUT(out_delay_tap_out[44:40]),
        .DATAOUT(data_out_to_pins_int[8]),
        .INC(out_delay_data_inc[8]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[8].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IOB = "TRUE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \pins[9].fdre_out_inst 
       (.C(clk_in),
        .CE(1'b1),
        .D(data_out_from_device[9]),
        .Q(\pins[9].data_out_from_device_q ),
        .R(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF \pins[9].obuf_inst 
       (.I(data_out_to_pins_int[9]),
        .O(data_out_to_pins[9]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "io_delay_control_out_group" *) 
  (* SIM_DELAY_D = "0" *) 
  ODELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("ODATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IS_C_INVERTED(1'b0),
    .IS_ODATAIN_INVERTED(1'b0),
    .ODELAY_TYPE("VAR_LOAD"),
    .ODELAY_VALUE(0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \pins[9].odelaye2_bus 
       (.C(delay_clk),
        .CE(out_delay_data_ce[9]),
        .CINVCTRL(1'b0),
        .CLKIN(1'b0),
        .CNTVALUEIN(out_delay_tap_in[49:45]),
        .CNTVALUEOUT(out_delay_tap_out[49:45]),
        .DATAOUT(data_out_to_pins_int[9]),
        .INC(out_delay_data_inc[9]),
        .LD(out_delay_reset),
        .LDPIPEEN(1'b0),
        .ODATAIN(\pins[9].data_out_from_device_q ),
        .REGRST(io_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG ref_clk_bufg
       (.I(ref_clock),
        .O(ref_clock_bufg));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
