// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Tue Apr  6 11:47:17 2021
// Host        : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/io_delay_control_out/io_delay_control_out_stub.v
// Design      : io_delay_control_out
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx330tffg1157-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module io_delay_control_out(data_out_from_device, data_out_to_pins, 
  delay_clk, out_delay_reset, out_delay_data_ce, out_delay_data_inc, out_delay_tap_in, 
  out_delay_tap_out, delay_locked, ref_clock, clk_in, io_reset)
/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[10:0],data_out_to_pins[10:0],delay_clk,out_delay_reset,out_delay_data_ce[10:0],out_delay_data_inc[10:0],out_delay_tap_in[54:0],out_delay_tap_out[54:0],delay_locked,ref_clock,clk_in,io_reset" */;
  input [10:0]data_out_from_device;
  output [10:0]data_out_to_pins;
  input delay_clk;
  input out_delay_reset;
  input [10:0]out_delay_data_ce;
  input [10:0]out_delay_data_inc;
  input [54:0]out_delay_tap_in;
  output [54:0]out_delay_tap_out;
  output delay_locked;
  input ref_clock;
  input clk_in;
  input io_reset;
endmodule
