-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Tue Apr  6 11:47:17 2021
-- Host        : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/io_delay_control_out/io_delay_control_out_sim_netlist.vhdl
-- Design      : io_delay_control_out
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx330tffg1157-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity io_delay_control_out_io_delay_control_out_selectio_wiz is
  port (
    data_out_from_device : in STD_LOGIC_VECTOR ( 10 downto 0 );
    data_out_to_pins : out STD_LOGIC_VECTOR ( 10 downto 0 );
    delay_clk : in STD_LOGIC;
    out_delay_reset : in STD_LOGIC;
    out_delay_data_ce : in STD_LOGIC_VECTOR ( 10 downto 0 );
    out_delay_data_inc : in STD_LOGIC_VECTOR ( 10 downto 0 );
    out_delay_tap_in : in STD_LOGIC_VECTOR ( 54 downto 0 );
    out_delay_tap_out : out STD_LOGIC_VECTOR ( 54 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );
  attribute DEV_W : integer;
  attribute DEV_W of io_delay_control_out_io_delay_control_out_selectio_wiz : entity is 11;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of io_delay_control_out_io_delay_control_out_selectio_wiz : entity is "io_delay_control_out_selectio_wiz";
  attribute SYS_W : integer;
  attribute SYS_W of io_delay_control_out_io_delay_control_out_selectio_wiz : entity is 11;
end io_delay_control_out_io_delay_control_out_selectio_wiz;

architecture STRUCTURE of io_delay_control_out_io_delay_control_out_selectio_wiz is
  signal data_out_to_pins_int : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \pins[0].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[10].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[1].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[2].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[3].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[4].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[5].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[6].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[7].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[8].data_out_from_device_q\ : STD_LOGIC;
  signal \pins[9].data_out_from_device_q\ : STD_LOGIC;
  signal ref_clock_bufg : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of delayctrl : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of delayctrl : label is "io_delay_control_out_group";
  attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB : string;
  attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[0].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[0].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \pins[0].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[10].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[10].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[10].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[10].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[10].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[10].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[10].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[1].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[1].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[1].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[2].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[2].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[2].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[3].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[3].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[3].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[4].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[4].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[4].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[4].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[4].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[4].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[4].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[5].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[5].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[5].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[5].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[5].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[5].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[5].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[6].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[6].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[6].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[6].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[6].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[6].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[6].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[7].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[7].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[7].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[7].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[7].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[7].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[7].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[8].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[8].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[8].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[8].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[8].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[8].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[8].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of \pins[9].fdre_out_inst\ : label is "PRIMITIVE";
  attribute IOB of \pins[9].fdre_out_inst\ : label is "TRUE";
  attribute BOX_TYPE of \pins[9].obuf_inst\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \pins[9].obuf_inst\ : label is "DONT_CARE";
  attribute BOX_TYPE of \pins[9].odelaye2_bus\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \pins[9].odelaye2_bus\ : label is "io_delay_control_out_group";
  attribute SIM_DELAY_D of \pins[9].odelaye2_bus\ : label is 0;
  attribute BOX_TYPE of ref_clk_bufg : label is "PRIMITIVE";
begin
delayctrl: unisim.vcomponents.IDELAYCTRL
    generic map(
      SIM_DEVICE => "7SERIES"
    )
        port map (
      RDY => delay_locked,
      REFCLK => ref_clock_bufg,
      RST => io_reset
    );
\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(0),
      Q => \pins[0].data_out_from_device_q\,
      R => io_reset
    );
\pins[0].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(0),
      O => data_out_to_pins(0)
    );
\pins[0].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(0),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(4 downto 0),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(4 downto 0),
      DATAOUT => data_out_to_pins_int(0),
      INC => out_delay_data_inc(0),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[0].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[10].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(10),
      Q => \pins[10].data_out_from_device_q\,
      R => io_reset
    );
\pins[10].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(10),
      O => data_out_to_pins(10)
    );
\pins[10].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(10),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(54 downto 50),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(54 downto 50),
      DATAOUT => data_out_to_pins_int(10),
      INC => out_delay_data_inc(10),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[10].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(1),
      Q => \pins[1].data_out_from_device_q\,
      R => io_reset
    );
\pins[1].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(1),
      O => data_out_to_pins(1)
    );
\pins[1].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(1),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(9 downto 5),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(9 downto 5),
      DATAOUT => data_out_to_pins_int(1),
      INC => out_delay_data_inc(1),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[1].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(2),
      Q => \pins[2].data_out_from_device_q\,
      R => io_reset
    );
\pins[2].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(2),
      O => data_out_to_pins(2)
    );
\pins[2].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(2),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(14 downto 10),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(14 downto 10),
      DATAOUT => data_out_to_pins_int(2),
      INC => out_delay_data_inc(2),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[2].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(3),
      Q => \pins[3].data_out_from_device_q\,
      R => io_reset
    );
\pins[3].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(3),
      O => data_out_to_pins(3)
    );
\pins[3].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(3),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(19 downto 15),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(19 downto 15),
      DATAOUT => data_out_to_pins_int(3),
      INC => out_delay_data_inc(3),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[3].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[4].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(4),
      Q => \pins[4].data_out_from_device_q\,
      R => io_reset
    );
\pins[4].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(4),
      O => data_out_to_pins(4)
    );
\pins[4].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(4),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(24 downto 20),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(24 downto 20),
      DATAOUT => data_out_to_pins_int(4),
      INC => out_delay_data_inc(4),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[4].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[5].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(5),
      Q => \pins[5].data_out_from_device_q\,
      R => io_reset
    );
\pins[5].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(5),
      O => data_out_to_pins(5)
    );
\pins[5].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(5),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(29 downto 25),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(29 downto 25),
      DATAOUT => data_out_to_pins_int(5),
      INC => out_delay_data_inc(5),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[5].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[6].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(6),
      Q => \pins[6].data_out_from_device_q\,
      R => io_reset
    );
\pins[6].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(6),
      O => data_out_to_pins(6)
    );
\pins[6].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(6),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(34 downto 30),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(34 downto 30),
      DATAOUT => data_out_to_pins_int(6),
      INC => out_delay_data_inc(6),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[6].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[7].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(7),
      Q => \pins[7].data_out_from_device_q\,
      R => io_reset
    );
\pins[7].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(7),
      O => data_out_to_pins(7)
    );
\pins[7].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(7),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(39 downto 35),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(39 downto 35),
      DATAOUT => data_out_to_pins_int(7),
      INC => out_delay_data_inc(7),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[7].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[8].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(8),
      Q => \pins[8].data_out_from_device_q\,
      R => io_reset
    );
\pins[8].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(8),
      O => data_out_to_pins(8)
    );
\pins[8].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(8),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(44 downto 40),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(44 downto 40),
      DATAOUT => data_out_to_pins_int(8),
      INC => out_delay_data_inc(8),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[8].data_out_from_device_q\,
      REGRST => io_reset
    );
\pins[9].fdre_out_inst\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => clk_in,
      CE => '1',
      D => data_out_from_device(9),
      Q => \pins[9].data_out_from_device_q\,
      R => io_reset
    );
\pins[9].obuf_inst\: unisim.vcomponents.OBUF
     port map (
      I => data_out_to_pins_int(9),
      O => data_out_to_pins(9)
    );
\pins[9].odelaye2_bus\: unisim.vcomponents.ODELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      IS_C_INVERTED => '0',
      IS_ODATAIN_INVERTED => '0',
      ODELAY_TYPE => "VAR_LOAD",
      ODELAY_VALUE => 0,
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => delay_clk,
      CE => out_delay_data_ce(9),
      CINVCTRL => '0',
      CLKIN => '0',
      CNTVALUEIN(4 downto 0) => out_delay_tap_in(49 downto 45),
      CNTVALUEOUT(4 downto 0) => out_delay_tap_out(49 downto 45),
      DATAOUT => data_out_to_pins_int(9),
      INC => out_delay_data_inc(9),
      LD => out_delay_reset,
      LDPIPEEN => '0',
      ODATAIN => \pins[9].data_out_from_device_q\,
      REGRST => io_reset
    );
ref_clk_bufg: unisim.vcomponents.BUFG
     port map (
      I => ref_clock,
      O => ref_clock_bufg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity io_delay_control_out is
  port (
    data_out_from_device : in STD_LOGIC_VECTOR ( 10 downto 0 );
    data_out_to_pins : out STD_LOGIC_VECTOR ( 10 downto 0 );
    delay_clk : in STD_LOGIC;
    out_delay_reset : in STD_LOGIC;
    out_delay_data_ce : in STD_LOGIC_VECTOR ( 10 downto 0 );
    out_delay_data_inc : in STD_LOGIC_VECTOR ( 10 downto 0 );
    out_delay_tap_in : in STD_LOGIC_VECTOR ( 54 downto 0 );
    out_delay_tap_out : out STD_LOGIC_VECTOR ( 54 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of io_delay_control_out : entity is true;
  attribute DEV_W : integer;
  attribute DEV_W of io_delay_control_out : entity is 11;
  attribute SYS_W : integer;
  attribute SYS_W of io_delay_control_out : entity is 11;
end io_delay_control_out;

architecture STRUCTURE of io_delay_control_out is
  attribute DEV_W of inst : label is 11;
  attribute SYS_W of inst : label is 11;
begin
inst: entity work.io_delay_control_out_io_delay_control_out_selectio_wiz
     port map (
      clk_in => clk_in,
      data_out_from_device(10 downto 0) => data_out_from_device(10 downto 0),
      data_out_to_pins(10 downto 0) => data_out_to_pins(10 downto 0),
      delay_clk => delay_clk,
      delay_locked => delay_locked,
      io_reset => io_reset,
      out_delay_data_ce(10 downto 0) => out_delay_data_ce(10 downto 0),
      out_delay_data_inc(10 downto 0) => out_delay_data_inc(10 downto 0),
      out_delay_reset => out_delay_reset,
      out_delay_tap_in(54 downto 0) => out_delay_tap_in(54 downto 0),
      out_delay_tap_out(54 downto 0) => out_delay_tap_out(54 downto 0),
      ref_clock => ref_clock
    );
end STRUCTURE;
