-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Tue Apr  6 11:47:17 2021
-- Host        : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode synth_stub
--               /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/io_delay_control_out/io_delay_control_out_stub.vhdl
-- Design      : io_delay_control_out
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xc7vx330tffg1157-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity io_delay_control_out is
  Port ( 
    data_out_from_device : in STD_LOGIC_VECTOR ( 10 downto 0 );
    data_out_to_pins : out STD_LOGIC_VECTOR ( 10 downto 0 );
    delay_clk : in STD_LOGIC;
    out_delay_reset : in STD_LOGIC;
    out_delay_data_ce : in STD_LOGIC_VECTOR ( 10 downto 0 );
    out_delay_data_inc : in STD_LOGIC_VECTOR ( 10 downto 0 );
    out_delay_tap_in : in STD_LOGIC_VECTOR ( 54 downto 0 );
    out_delay_tap_out : out STD_LOGIC_VECTOR ( 54 downto 0 );
    delay_locked : out STD_LOGIC;
    ref_clock : in STD_LOGIC;
    clk_in : in STD_LOGIC;
    io_reset : in STD_LOGIC
  );

end io_delay_control_out;

architecture stub of io_delay_control_out is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "data_out_from_device[10:0],data_out_to_pins[10:0],delay_clk,out_delay_reset,out_delay_data_ce[10:0],out_delay_data_inc[10:0],out_delay_tap_in[54:0],out_delay_tap_out[54:0],delay_locked,ref_clock,clk_in,io_reset";
begin
end;
