-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Fri Aug 14 17:37:40 2020
-- Host        : rod-vm.cern.ch running 64-bit CentOS Linux release 7.8.2003 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/gitlab-runner/builds/bb8b4gKx/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_sim_netlist.vhdl
-- Design      : mgt11g2_tx_rx_cfpga
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx330tffg1157-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT is
  port (
    gt0_drprdy_out : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_gthtxn_out : out STD_LOGIC;
    gt0_gthtxp_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxbyterealign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxdlysresetdone_out : out STD_LOGIC;
    gt0_rxoutclk_out : out STD_LOGIC;
    gt0_rxoutclkfabric_out : out STD_LOGIC;
    gt0_rxphaligndone_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_rxsyncdone_out : out STD_LOGIC;
    gt0_rxsyncout_i : out STD_LOGIC;
    gt0_txdlysresetdone_out : out STD_LOGIC;
    gt0_txoutclk_out : out STD_LOGIC;
    gt0_txoutclkfabric_out : out STD_LOGIC;
    gt0_txoutclkpcs_out : out STD_LOGIC;
    gt0_txphaligndone_out : out STD_LOGIC;
    gt0_txphinitdone_out : out STD_LOGIC;
    gt0_txresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_drpclk_in_0 : out STD_LOGIC;
    gt0_drpclk_in : in STD_LOGIC;
    gt0_drpen_in : in STD_LOGIC;
    gt0_drpwe_in : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_gthrxn_in : in STD_LOGIC;
    gt0_gthrxp_in : in STD_LOGIC;
    gt0_gtnorthrefclk0_in : in STD_LOGIC;
    gt0_gtnorthrefclk1_in : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_gtsouthrefclk0_in : in STD_LOGIC;
    gt0_gtsouthrefclk1_in : in STD_LOGIC;
    gt0_gttxreset_in : in STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC;
    gt0_rxdlysreset_in : in STD_LOGIC;
    gt0_rxsyncallin_in : in STD_LOGIC;
    gt0_rxuserrdy_in : in STD_LOGIC;
    gt0_rxusrclk_in : in STD_LOGIC;
    gt0_rxusrclk2_in : in STD_LOGIC;
    gt0_txdlyen_in : in STD_LOGIC;
    U0_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHALIGN : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHINIT : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_txuserrdy_in : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC;
    gt0_txusrclk2_in : in STD_LOGIC;
    gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT : entity is "mgt11g2_tx_rx_cfpga_GT";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT is
  signal gt0_rxpmaresetdone_i : STD_LOGIC;
  signal \^gt0_rxsyncout_i\ : STD_LOGIC;
  signal \^gt0_txphinitdone_out\ : STD_LOGIC;
  signal gthe2_i_n_50 : STD_LOGIC;
  signal NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCDRLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPRBSERR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of gthe2_i : label is "PRIMITIVE";
begin
  gt0_rxsyncout_i <= \^gt0_rxsyncout_i\;
  gt0_txphinitdone_out <= \^gt0_txphinitdone_out\;
\cdc[0].sync_TXPHINITDONE/stretch_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^gt0_txphinitdone_out\,
      O => gt0_drpclk_in_0
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 4,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 1,
      CHAN_BOND_SEQ_1_1 => B"0000000000",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "FALSE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 16,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100000000",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "TRUE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"3C",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FAST",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "FALSE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C208001A",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"11",
      RXPI_CFG2 => B"11",
      RXPI_CFG3 => B"11",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PCS",
      RXSYNC_MULTILANE => '1',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 12,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 40,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 1,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXUSR",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "TRUE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"001",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '1',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 12,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 40,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 1,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED,
      CPLLLOCK => NLW_gthe2_i_CPLLLOCK_UNCONNECTED,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => '1',
      CPLLREFCLKLOST => NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => '0',
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => gt0_drpaddr_in(8 downto 0),
      DRPCLK => gt0_drpclk_in,
      DRPDI(15 downto 0) => gt0_drpdi_in(15 downto 0),
      DRPDO(15 downto 0) => gt0_drpdo_out(15 downto 0),
      DRPEN => gt0_drpen_in,
      DRPRDY => gt0_drprdy_out,
      DRPWE => gt0_drpwe_in,
      EYESCANDATAERROR => gt0_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt0_eyescanreset_in,
      EYESCANTRIGGER => gt0_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => gt0_gthrxn_in,
      GTHRXP => gt0_gthrxp_in,
      GTHTXN => gt0_gthtxn_out,
      GTHTXP => gt0_gthtxp_out,
      GTNORTHREFCLK0 => gt0_gtnorthrefclk0_in,
      GTNORTHREFCLK1 => gt0_gtnorthrefclk1_in,
      GTREFCLK0 => '0',
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => SR(0),
      GTSOUTHREFCLK0 => gt0_gtsouthrefclk0_in,
      GTSOUTHREFCLK1 => gt0_gtsouthrefclk1_in,
      GTTXRESET => gt0_gttxreset_in,
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => GT0_QPLLOUTCLK_IN,
      QPLLREFCLK => GT0_QPLLOUTREFCLK_IN,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2 downto 0) => NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED(2 downto 0),
      RXBYTEISALIGNED => gt0_rxbyteisaligned_out,
      RXBYTEREALIGN => gt0_rxbyterealign_out,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => NLW_gthe2_i_RXCDRLOCK_UNCONNECTED,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED,
      RXCHANISALIGNED => NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED,
      RXCHANREALIGN => NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED,
      RXCHARISCOMMA(7 downto 4) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 4),
      RXCHARISCOMMA(3 downto 0) => gt0_rxchariscomma_out(3 downto 0),
      RXCHARISK(7 downto 4) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 4),
      RXCHARISK(3 downto 0) => gt0_rxcharisk_out(3 downto 0),
      RXCHBONDEN => '0',
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => NLW_gthe2_i_RXCHBONDO_UNCONNECTED(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED(1 downto 0),
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt0_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 32) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 32),
      RXDATA(31 downto 0) => gt0_rxdata_out(31 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '1',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 4) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 4),
      RXDISPERR(3 downto 0) => gt0_rxdisperr_out(3 downto 0),
      RXDLYBYPASS => '0',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => gt0_rxdlysreset_in,
      RXDLYSRESETDONE => gt0_rxdlysresetdone_out,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '1',
      RXMONITOROUT(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 4) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 4),
      RXNOTINTABLE(3 downto 0) => gt0_rxnotintable_out(3 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '1',
      RXOSINTHOLD => '0',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gt0_rxoutclk_out,
      RXOUTCLKFABRIC => gt0_rxoutclkfabric_out,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '1',
      RXPCSRESET => '0',
      RXPD(1 downto 0) => gt0_rxpd_in(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => gt0_rxphaligndone_out,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => gt0_rxphmonitor_out(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => gt0_rxphslipmonitor_out(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gt0_rxpmaresetdone_i,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => NLW_gthe2_i_RXPRBSERR_UNCONNECTED,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt0_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => gt0_rxsyncallin_in,
      RXSYNCDONE => gt0_rxsyncdone_out,
      RXSYNCIN => \^gt0_rxsyncout_i\,
      RXSYNCMODE => '1',
      RXSYNCOUT => \^gt0_rxsyncout_i\,
      RXSYSCLKSEL(1 downto 0) => B"11",
      RXUSERRDY => gt0_rxuserrdy_in,
      RXUSRCLK => gt0_rxusrclk_in,
      RXUSRCLK2 => gt0_rxusrclk2_in,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED(1 downto 0),
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 4) => B"0000",
      TXCHARISK(3 downto 0) => gt0_txcharisk_in(3 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 32) => B"00000000000000000000000000000000",
      TXDATA(31 downto 0) => gt0_txdata_in(31 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => gt0_txdlyen_in,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => U0_TXDLYSRESET(0),
      TXDLYSRESETDONE => gt0_txdlysresetdone_out,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gt0_txoutclk_out,
      TXOUTCLKFABRIC => gt0_txoutclkfabric_out,
      TXOUTCLKPCS => gt0_txoutclkpcs_out,
      TXOUTCLKSEL(2 downto 0) => B"011",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => gt0_txpd_in(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => U0_TXPHALIGN(0),
      TXPHALIGNDONE => gt0_txphaligndone_out,
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => U0_TXPHINIT(0),
      TXPHINITDONE => \^gt0_txphinitdone_out\,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '0',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => gthe2_i_n_50,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt0_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"11",
      TXUSERRDY => gt0_txuserrdy_in,
      TXUSRCLK => gt0_txusrclk_in,
      TXUSRCLK2 => gt0_txusrclk2_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10 is
  port (
    gt2_drprdy_out : out STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_gthtxn_out : out STD_LOGIC;
    gt2_gthtxp_out : out STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gt2_rxbyterealign_out : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxdlysresetdone_out : out STD_LOGIC;
    gt2_rxoutclk_out : out STD_LOGIC;
    gt2_rxoutclkfabric_out : out STD_LOGIC;
    gt2_rxphaligndone_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    gt2_txdlysresetdone_out : out STD_LOGIC;
    gt2_txoutclk_out : out STD_LOGIC;
    gt2_txoutclkfabric_out : out STD_LOGIC;
    gt2_txoutclkpcs_out : out STD_LOGIC;
    gt2_txphaligndone_out : out STD_LOGIC;
    gt2_txphinitdone_out : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_drpclk_in_0 : out STD_LOGIC;
    gt2_drpclk_in : in STD_LOGIC;
    gt2_drpen_in : in STD_LOGIC;
    gt2_drpwe_in : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt2_gthrxn_in : in STD_LOGIC;
    gt2_gthrxp_in : in STD_LOGIC;
    gt2_gtnorthrefclk0_in : in STD_LOGIC;
    gt2_gtnorthrefclk1_in : in STD_LOGIC;
    gt2_gtrxreset_in : in STD_LOGIC;
    gt2_gtsouthrefclk0_in : in STD_LOGIC;
    gt2_gtsouthrefclk1_in : in STD_LOGIC;
    gt2_gttxreset_in : in STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC;
    gt2_rxdlysreset_in : in STD_LOGIC;
    gt0_rxsyncallin_in : in STD_LOGIC;
    gt0_rxsyncout_i : in STD_LOGIC;
    gt2_rxuserrdy_in : in STD_LOGIC;
    gt2_rxusrclk_in : in STD_LOGIC;
    gt2_rxusrclk2_in : in STD_LOGIC;
    U0_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHALIGN : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHINIT : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt2_txuserrdy_in : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC;
    gt2_txusrclk2_in : in STD_LOGIC;
    gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10 : entity is "mgt11g2_tx_rx_cfpga_GT";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10 is
  signal \^gt2_txphinitdone_out\ : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_39 : STD_LOGIC;
  signal gthe2_i_n_40 : STD_LOGIC;
  signal gthe2_i_n_50 : STD_LOGIC;
  signal NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCDRLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPRBSERR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of gthe2_i : label is "PRIMITIVE";
begin
  gt2_txphinitdone_out <= \^gt2_txphinitdone_out\;
\cdc[2].sync_TXPHINITDONE/stretch_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^gt2_txphinitdone_out\,
      O => gt2_drpclk_in_0
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 4,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 1,
      CHAN_BOND_SEQ_1_1 => B"0000000000",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "FALSE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 16,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100000000",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "TRUE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"3C",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FAST",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "FALSE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C208001A",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"11",
      RXPI_CFG2 => B"11",
      RXPI_CFG3 => B"11",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PCS",
      RXSYNC_MULTILANE => '1',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 12,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 40,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 1,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXUSR",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "TRUE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"001",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '1',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 12,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 40,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 1,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED,
      CPLLLOCK => NLW_gthe2_i_CPLLLOCK_UNCONNECTED,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => '1',
      CPLLREFCLKLOST => NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => '0',
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => gt2_drpaddr_in(8 downto 0),
      DRPCLK => gt2_drpclk_in,
      DRPDI(15 downto 0) => gt2_drpdi_in(15 downto 0),
      DRPDO(15 downto 0) => gt2_drpdo_out(15 downto 0),
      DRPEN => gt2_drpen_in,
      DRPRDY => gt2_drprdy_out,
      DRPWE => gt2_drpwe_in,
      EYESCANDATAERROR => gt2_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt2_eyescanreset_in,
      EYESCANTRIGGER => gt2_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => gt2_gthrxn_in,
      GTHRXP => gt2_gthrxp_in,
      GTHTXN => gt2_gthtxn_out,
      GTHTXP => gt2_gthtxp_out,
      GTNORTHREFCLK0 => gt2_gtnorthrefclk0_in,
      GTNORTHREFCLK1 => gt2_gtnorthrefclk1_in,
      GTREFCLK0 => '0',
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => gt2_gtrxreset_in,
      GTSOUTHREFCLK0 => gt2_gtsouthrefclk0_in,
      GTSOUTHREFCLK1 => gt2_gtsouthrefclk1_in,
      GTTXRESET => gt2_gttxreset_in,
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => GT0_QPLLOUTCLK_IN,
      QPLLREFCLK => GT0_QPLLOUTREFCLK_IN,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2 downto 0) => NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED(2 downto 0),
      RXBYTEISALIGNED => gt2_rxbyteisaligned_out,
      RXBYTEREALIGN => gt2_rxbyterealign_out,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => NLW_gthe2_i_RXCDRLOCK_UNCONNECTED,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED,
      RXCHANISALIGNED => NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED,
      RXCHANREALIGN => NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED,
      RXCHARISCOMMA(7 downto 4) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 4),
      RXCHARISCOMMA(3 downto 0) => gt2_rxchariscomma_out(3 downto 0),
      RXCHARISK(7 downto 4) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 4),
      RXCHARISK(3 downto 0) => gt2_rxcharisk_out(3 downto 0),
      RXCHBONDEN => '0',
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => NLW_gthe2_i_RXCHBONDO_UNCONNECTED(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED(1 downto 0),
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt2_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 32) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 32),
      RXDATA(31 downto 0) => gt2_rxdata_out(31 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '1',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 4) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 4),
      RXDISPERR(3 downto 0) => gt2_rxdisperr_out(3 downto 0),
      RXDLYBYPASS => '0',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => gt2_rxdlysreset_in,
      RXDLYSRESETDONE => gt2_rxdlysresetdone_out,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '1',
      RXMONITOROUT(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 4) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 4),
      RXNOTINTABLE(3 downto 0) => gt2_rxnotintable_out(3 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '1',
      RXOSINTHOLD => '0',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gt2_rxoutclk_out,
      RXOUTCLKFABRIC => gt2_rxoutclkfabric_out,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '1',
      RXPCSRESET => '0',
      RXPD(1 downto 0) => gt2_rxpd_in(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => gt2_rxphaligndone_out,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => gt2_rxphmonitor_out(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => gt2_rxphslipmonitor_out(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => NLW_gthe2_i_RXPRBSERR_UNCONNECTED,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt2_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => gt0_rxsyncallin_in,
      RXSYNCDONE => gthe2_i_n_39,
      RXSYNCIN => gt0_rxsyncout_i,
      RXSYNCMODE => '0',
      RXSYNCOUT => gthe2_i_n_40,
      RXSYSCLKSEL(1 downto 0) => B"11",
      RXUSERRDY => gt2_rxuserrdy_in,
      RXUSRCLK => gt2_rxusrclk_in,
      RXUSRCLK2 => gt2_rxusrclk2_in,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED(1 downto 0),
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 4) => B"0000",
      TXCHARISK(3 downto 0) => gt2_txcharisk_in(3 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 32) => B"00000000000000000000000000000000",
      TXDATA(31 downto 0) => gt2_txdata_in(31 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => U0_TXDLYSRESET(0),
      TXDLYSRESETDONE => gt2_txdlysresetdone_out,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gt2_txoutclk_out,
      TXOUTCLKFABRIC => gt2_txoutclkfabric_out,
      TXOUTCLKPCS => gt2_txoutclkpcs_out,
      TXOUTCLKSEL(2 downto 0) => B"011",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => gt2_txpd_in(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => U0_TXPHALIGN(0),
      TXPHALIGNDONE => gt2_txphaligndone_out,
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => U0_TXPHINIT(0),
      TXPHINITDONE => \^gt2_txphinitdone_out\,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '0',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => gthe2_i_n_50,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt2_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"11",
      TXUSERRDY => gt2_txuserrdy_in,
      TXUSRCLK => gt2_txusrclk_in,
      TXUSRCLK2 => gt2_txusrclk2_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11 is
  port (
    gt3_drprdy_out : out STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_gthtxn_out : out STD_LOGIC;
    gt3_gthtxp_out : out STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gt3_rxbyterealign_out : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxdlysresetdone_out : out STD_LOGIC;
    gt3_rxoutclk_out : out STD_LOGIC;
    gt3_rxoutclkfabric_out : out STD_LOGIC;
    gt3_rxphaligndone_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_txdlysresetdone_out : out STD_LOGIC;
    gt3_txoutclk_out : out STD_LOGIC;
    gt3_txoutclkfabric_out : out STD_LOGIC;
    gt3_txoutclkpcs_out : out STD_LOGIC;
    gt3_txphaligndone_out : out STD_LOGIC;
    gt3_txphinitdone_out : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxsyncallin_in : out STD_LOGIC;
    gt3_drpclk_in_0 : out STD_LOGIC;
    gt3_drpclk_in : in STD_LOGIC;
    gt3_drpen_in : in STD_LOGIC;
    gt3_drpwe_in : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_gthrxn_in : in STD_LOGIC;
    gt3_gthrxp_in : in STD_LOGIC;
    gt3_gtnorthrefclk0_in : in STD_LOGIC;
    gt3_gtnorthrefclk1_in : in STD_LOGIC;
    gt3_gtrxreset_in : in STD_LOGIC;
    gt3_gtsouthrefclk0_in : in STD_LOGIC;
    gt3_gtsouthrefclk1_in : in STD_LOGIC;
    gt3_gttxreset_in : in STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC;
    gt3_rxdlysreset_in : in STD_LOGIC;
    gt0_rxsyncout_i : in STD_LOGIC;
    gt3_rxuserrdy_in : in STD_LOGIC;
    gt3_rxusrclk_in : in STD_LOGIC;
    gt3_rxusrclk2_in : in STD_LOGIC;
    U0_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHALIGN : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHINIT : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt3_txuserrdy_in : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC;
    gt3_txusrclk2_in : in STD_LOGIC;
    gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt0_rxphaligndone_out : in STD_LOGIC;
    gt1_rxphaligndone_out : in STD_LOGIC;
    gt2_rxphaligndone_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11 : entity is "mgt11g2_tx_rx_cfpga_GT";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11 is
  signal \^gt0_rxsyncallin_in\ : STD_LOGIC;
  signal \^gt3_rxphaligndone_out\ : STD_LOGIC;
  signal \^gt3_txphinitdone_out\ : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_39 : STD_LOGIC;
  signal gthe2_i_n_40 : STD_LOGIC;
  signal gthe2_i_n_50 : STD_LOGIC;
  signal NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCDRLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPRBSERR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of gthe2_i : label is "PRIMITIVE";
begin
  gt0_rxsyncallin_in <= \^gt0_rxsyncallin_in\;
  gt3_rxphaligndone_out <= \^gt3_rxphaligndone_out\;
  gt3_txphinitdone_out <= \^gt3_txphinitdone_out\;
\cdc[3].sync_TXPHINITDONE/stretch_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^gt3_txphinitdone_out\,
      O => gt3_drpclk_in_0
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 4,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 1,
      CHAN_BOND_SEQ_1_1 => B"0000000000",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "FALSE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 16,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100000000",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "TRUE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"3C",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FAST",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "FALSE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C208001A",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"11",
      RXPI_CFG2 => B"11",
      RXPI_CFG3 => B"11",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PCS",
      RXSYNC_MULTILANE => '1',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 12,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 40,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 1,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXUSR",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "TRUE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"001",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '1',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 12,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 40,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 1,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED,
      CPLLLOCK => NLW_gthe2_i_CPLLLOCK_UNCONNECTED,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => '1',
      CPLLREFCLKLOST => NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => '0',
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => gt3_drpaddr_in(8 downto 0),
      DRPCLK => gt3_drpclk_in,
      DRPDI(15 downto 0) => gt3_drpdi_in(15 downto 0),
      DRPDO(15 downto 0) => gt3_drpdo_out(15 downto 0),
      DRPEN => gt3_drpen_in,
      DRPRDY => gt3_drprdy_out,
      DRPWE => gt3_drpwe_in,
      EYESCANDATAERROR => gt3_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt3_eyescanreset_in,
      EYESCANTRIGGER => gt3_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => gt3_gthrxn_in,
      GTHRXP => gt3_gthrxp_in,
      GTHTXN => gt3_gthtxn_out,
      GTHTXP => gt3_gthtxp_out,
      GTNORTHREFCLK0 => gt3_gtnorthrefclk0_in,
      GTNORTHREFCLK1 => gt3_gtnorthrefclk1_in,
      GTREFCLK0 => '0',
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => gt3_gtrxreset_in,
      GTSOUTHREFCLK0 => gt3_gtsouthrefclk0_in,
      GTSOUTHREFCLK1 => gt3_gtsouthrefclk1_in,
      GTTXRESET => gt3_gttxreset_in,
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => GT0_QPLLOUTCLK_IN,
      QPLLREFCLK => GT0_QPLLOUTREFCLK_IN,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2 downto 0) => NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED(2 downto 0),
      RXBYTEISALIGNED => gt3_rxbyteisaligned_out,
      RXBYTEREALIGN => gt3_rxbyterealign_out,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => NLW_gthe2_i_RXCDRLOCK_UNCONNECTED,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED,
      RXCHANISALIGNED => NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED,
      RXCHANREALIGN => NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED,
      RXCHARISCOMMA(7 downto 4) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 4),
      RXCHARISCOMMA(3 downto 0) => gt3_rxchariscomma_out(3 downto 0),
      RXCHARISK(7 downto 4) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 4),
      RXCHARISK(3 downto 0) => gt3_rxcharisk_out(3 downto 0),
      RXCHBONDEN => '0',
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => NLW_gthe2_i_RXCHBONDO_UNCONNECTED(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED(1 downto 0),
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt3_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 32) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 32),
      RXDATA(31 downto 0) => gt3_rxdata_out(31 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '1',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 4) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 4),
      RXDISPERR(3 downto 0) => gt3_rxdisperr_out(3 downto 0),
      RXDLYBYPASS => '0',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => gt3_rxdlysreset_in,
      RXDLYSRESETDONE => gt3_rxdlysresetdone_out,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '1',
      RXMONITOROUT(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 4) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 4),
      RXNOTINTABLE(3 downto 0) => gt3_rxnotintable_out(3 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '1',
      RXOSINTHOLD => '0',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gt3_rxoutclk_out,
      RXOUTCLKFABRIC => gt3_rxoutclkfabric_out,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '1',
      RXPCSRESET => '0',
      RXPD(1 downto 0) => gt3_rxpd_in(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => \^gt3_rxphaligndone_out\,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => gt3_rxphmonitor_out(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => gt3_rxphslipmonitor_out(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => NLW_gthe2_i_RXPRBSERR_UNCONNECTED,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt3_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => \^gt0_rxsyncallin_in\,
      RXSYNCDONE => gthe2_i_n_39,
      RXSYNCIN => gt0_rxsyncout_i,
      RXSYNCMODE => '0',
      RXSYNCOUT => gthe2_i_n_40,
      RXSYSCLKSEL(1 downto 0) => B"11",
      RXUSERRDY => gt3_rxuserrdy_in,
      RXUSRCLK => gt3_rxusrclk_in,
      RXUSRCLK2 => gt3_rxusrclk2_in,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED(1 downto 0),
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 4) => B"0000",
      TXCHARISK(3 downto 0) => gt3_txcharisk_in(3 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 32) => B"00000000000000000000000000000000",
      TXDATA(31 downto 0) => gt3_txdata_in(31 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => U0_TXDLYSRESET(0),
      TXDLYSRESETDONE => gt3_txdlysresetdone_out,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gt3_txoutclk_out,
      TXOUTCLKFABRIC => gt3_txoutclkfabric_out,
      TXOUTCLKPCS => gt3_txoutclkpcs_out,
      TXOUTCLKSEL(2 downto 0) => B"011",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => gt3_txpd_in(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => U0_TXPHALIGN(0),
      TXPHALIGNDONE => gt3_txphaligndone_out,
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => U0_TXPHINIT(0),
      TXPHINITDONE => \^gt3_txphinitdone_out\,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '0',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => gthe2_i_n_50,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt3_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"11",
      TXUSERRDY => gt3_txuserrdy_in,
      TXUSRCLK => gt3_txusrclk_in,
      TXUSRCLK2 => gt3_txusrclk2_in
    );
gthe2_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^gt3_rxphaligndone_out\,
      I1 => gt0_rxphaligndone_out,
      I2 => gt1_rxphaligndone_out,
      I3 => gt2_rxphaligndone_out,
      O => \^gt0_rxsyncallin_in\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9 is
  port (
    gt1_drprdy_out : out STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_gthtxn_out : out STD_LOGIC;
    gt1_gthtxp_out : out STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gt1_rxbyterealign_out : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxdlysresetdone_out : out STD_LOGIC;
    gt1_rxoutclk_out : out STD_LOGIC;
    gt1_rxoutclkfabric_out : out STD_LOGIC;
    gt1_rxphaligndone_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_txdlysresetdone_out : out STD_LOGIC;
    gt1_txoutclk_out : out STD_LOGIC;
    gt1_txoutclkfabric_out : out STD_LOGIC;
    gt1_txoutclkpcs_out : out STD_LOGIC;
    gt1_txphaligndone_out : out STD_LOGIC;
    gt1_txphinitdone_out : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_drpclk_in_0 : out STD_LOGIC;
    gt1_drpclk_in : in STD_LOGIC;
    gt1_drpen_in : in STD_LOGIC;
    gt1_drpwe_in : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_gthrxn_in : in STD_LOGIC;
    gt1_gthrxp_in : in STD_LOGIC;
    gt1_gtnorthrefclk0_in : in STD_LOGIC;
    gt1_gtnorthrefclk1_in : in STD_LOGIC;
    gt1_gtrxreset_in : in STD_LOGIC;
    gt1_gtsouthrefclk0_in : in STD_LOGIC;
    gt1_gtsouthrefclk1_in : in STD_LOGIC;
    gt1_gttxreset_in : in STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC;
    gt1_rxdlysreset_in : in STD_LOGIC;
    gt0_rxsyncallin_in : in STD_LOGIC;
    gt0_rxsyncout_i : in STD_LOGIC;
    gt1_rxuserrdy_in : in STD_LOGIC;
    gt1_rxusrclk_in : in STD_LOGIC;
    gt1_rxusrclk2_in : in STD_LOGIC;
    U0_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHALIGN : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHINIT : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt1_txuserrdy_in : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC;
    gt1_txusrclk2_in : in STD_LOGIC;
    gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9 : entity is "mgt11g2_tx_rx_cfpga_GT";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9 is
  signal \^gt1_txphinitdone_out\ : STD_LOGIC;
  signal gthe2_i_n_33 : STD_LOGIC;
  signal gthe2_i_n_39 : STD_LOGIC;
  signal gthe2_i_n_40 : STD_LOGIC;
  signal gthe2_i_n_50 : STD_LOGIC;
  signal NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCDRLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPRBSERR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of gthe2_i : label is "PRIMITIVE";
begin
  gt1_txphinitdone_out <= \^gt1_txphinitdone_out\;
\cdc[1].sync_TXPHINITDONE/stretch_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^gt1_txphinitdone_out\,
      O => gt1_drpclk_in_0
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 4,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 1,
      CHAN_BOND_SEQ_1_1 => B"0000000000",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "FALSE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 16,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100000000",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "TRUE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"3C",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FAST",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "FALSE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C208001A",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"11",
      RXPI_CFG2 => B"11",
      RXPI_CFG3 => B"11",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PCS",
      RXSYNC_MULTILANE => '1',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 12,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 40,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 1,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXUSR",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "TRUE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"001",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '1',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 12,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 40,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 1,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED,
      CPLLLOCK => NLW_gthe2_i_CPLLLOCK_UNCONNECTED,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => '1',
      CPLLREFCLKLOST => NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => '0',
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => gt1_drpaddr_in(8 downto 0),
      DRPCLK => gt1_drpclk_in,
      DRPDI(15 downto 0) => gt1_drpdi_in(15 downto 0),
      DRPDO(15 downto 0) => gt1_drpdo_out(15 downto 0),
      DRPEN => gt1_drpen_in,
      DRPRDY => gt1_drprdy_out,
      DRPWE => gt1_drpwe_in,
      EYESCANDATAERROR => gt1_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt1_eyescanreset_in,
      EYESCANTRIGGER => gt1_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => gt1_gthrxn_in,
      GTHRXP => gt1_gthrxp_in,
      GTHTXN => gt1_gthtxn_out,
      GTHTXP => gt1_gthtxp_out,
      GTNORTHREFCLK0 => gt1_gtnorthrefclk0_in,
      GTNORTHREFCLK1 => gt1_gtnorthrefclk1_in,
      GTREFCLK0 => '0',
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => gt1_gtrxreset_in,
      GTSOUTHREFCLK0 => gt1_gtsouthrefclk0_in,
      GTSOUTHREFCLK1 => gt1_gtsouthrefclk1_in,
      GTTXRESET => gt1_gttxreset_in,
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => GT0_QPLLOUTCLK_IN,
      QPLLREFCLK => GT0_QPLLOUTREFCLK_IN,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => '0',
      RXBUFSTATUS(2 downto 0) => NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED(2 downto 0),
      RXBYTEISALIGNED => gt1_rxbyteisaligned_out,
      RXBYTEREALIGN => gt1_rxbyterealign_out,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => NLW_gthe2_i_RXCDRLOCK_UNCONNECTED,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED,
      RXCHANISALIGNED => NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED,
      RXCHANREALIGN => NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED,
      RXCHARISCOMMA(7 downto 4) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 4),
      RXCHARISCOMMA(3 downto 0) => gt1_rxchariscomma_out(3 downto 0),
      RXCHARISK(7 downto 4) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 4),
      RXCHARISK(3 downto 0) => gt1_rxcharisk_out(3 downto 0),
      RXCHBONDEN => '0',
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => NLW_gthe2_i_RXCHBONDO_UNCONNECTED(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED(1 downto 0),
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt1_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 32) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 32),
      RXDATA(31 downto 0) => gt1_rxdata_out(31 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '1',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => '0',
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 4) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 4),
      RXDISPERR(3 downto 0) => gt1_rxdisperr_out(3 downto 0),
      RXDLYBYPASS => '0',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => gt1_rxdlysreset_in,
      RXDLYSRESETDONE => gt1_rxdlysresetdone_out,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => '0',
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => '1',
      RXMONITOROUT(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 4) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 4),
      RXNOTINTABLE(3 downto 0) => gt1_rxnotintable_out(3 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '1',
      RXOSINTHOLD => '0',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gt1_rxoutclk_out,
      RXOUTCLKFABRIC => gt1_rxoutclkfabric_out,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => '1',
      RXPCSRESET => '0',
      RXPD(1 downto 0) => gt1_rxpd_in(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => gt1_rxphaligndone_out,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => gt1_rxphmonitor_out(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => gt1_rxphslipmonitor_out(4 downto 0),
      RXPMARESET => '0',
      RXPMARESETDONE => gthe2_i_n_33,
      RXPOLARITY => '0',
      RXPRBSCNTRESET => '0',
      RXPRBSERR => NLW_gthe2_i_RXPRBSERR_UNCONNECTED,
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt1_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => gt0_rxsyncallin_in,
      RXSYNCDONE => gthe2_i_n_39,
      RXSYNCIN => gt0_rxsyncout_i,
      RXSYNCMODE => '0',
      RXSYNCOUT => gthe2_i_n_40,
      RXSYSCLKSEL(1 downto 0) => B"11",
      RXUSERRDY => gt1_rxuserrdy_in,
      RXUSRCLK => gt1_rxusrclk_in,
      RXUSRCLK2 => gt1_rxusrclk2_in,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED(1 downto 0),
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 4) => B"0000",
      TXCHARISK(3 downto 0) => gt1_txcharisk_in(3 downto 0),
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 32) => B"00000000000000000000000000000000",
      TXDATA(31 downto 0) => gt1_txdata_in(31 downto 0),
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => U0_TXDLYSRESET(0),
      TXDLYSRESETDONE => gt1_txdlysresetdone_out,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gt1_txoutclk_out,
      TXOUTCLKFABRIC => gt1_txoutclkfabric_out,
      TXOUTCLKPCS => gt1_txoutclkpcs_out,
      TXOUTCLKSEL(2 downto 0) => B"011",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => gt1_txpd_in(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => U0_TXPHALIGN(0),
      TXPHALIGNDONE => gt1_txphaligndone_out,
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => U0_TXPHINIT(0),
      TXPHINITDONE => \^gt1_txphinitdone_out\,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '0',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => gthe2_i_n_50,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gt1_txresetdone_out,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"11",
      TXUSERRDY => gt1_txuserrdy_in,
      TXUSRCLK => gt1_txusrclk_in,
      TXUSRCLK2 => gt1_txusrclk2_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_time_out_reg : out STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_1\ : in STD_LOGIC;
    txresetdone_s3 : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_2\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    reset_time_out_reg_0 : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_3\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_5\ : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    \reset_time_out__0\ : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block is
  signal \FSM_sequential_tx_state[3]_i_6__2_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  signal \reset_time_out_i_3__6_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__6_n_0\ : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
\FSM_sequential_tx_state[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
        port map (
      I0 => \FSM_sequential_tx_state_reg[0]\,
      I1 => \FSM_sequential_tx_state_reg[0]_0\,
      I2 => \FSM_sequential_tx_state_reg[0]_1\,
      I3 => txresetdone_s3,
      I4 => \FSM_sequential_tx_state[3]_i_6__2_n_0\,
      I5 => \FSM_sequential_tx_state_reg[0]_2\,
      O => E(0)
    );
\FSM_sequential_tx_state[3]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF0400000A04"
    )
        port map (
      I0 => qplllock_sync,
      I1 => \FSM_sequential_tx_state_reg[0]_3\,
      I2 => Q(2),
      I3 => Q(1),
      I4 => \FSM_sequential_tx_state_reg[0]_4\,
      I5 => \FSM_sequential_tx_state_reg[0]_5\,
      O => \FSM_sequential_tx_state[3]_i_6__2_n_0\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => reset_time_out_reg_1,
      I1 => \reset_time_out_i_3__6_n_0\,
      I2 => \reset_time_out_i_4__6_n_0\,
      I3 => \reset_time_out__0\,
      O => reset_time_out_reg
    );
\reset_time_out_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020002000F000200"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(3),
      I3 => Q(0),
      I4 => qplllock_sync,
      I5 => Q(2),
      O => \reset_time_out_i_3__6_n_0\
    );
\reset_time_out_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF005555F544"
    )
        port map (
      I0 => Q(1),
      I1 => reset_time_out_reg_0,
      I2 => qplllock_sync,
      I3 => Q(0),
      I4 => Q(3),
      I5 => Q(2),
      O => \reset_time_out_i_4__6_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12 is
  port (
    data_out : out STD_LOGIC;
    gt3_txresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_txresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__2\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__2\ : label is "soft_lutpair110";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16 is
  port (
    data_out : out STD_LOGIC;
    GT3_TX_FSM_RESET_DONE_OUT : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => GT3_TX_FSM_RESET_DONE_OUT,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17 is
  port (
    \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]_0\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    rxresetdone_s3 : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17 is
  signal \^fsm_sequential_rx_state_reg[1]_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  \FSM_sequential_rx_state_reg[1]_0\ <= \^fsm_sequential_rx_state_reg[1]_0\;
\FSM_sequential_rx_state[3]_i_8__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF0000ABAB0000"
    )
        port map (
      I0 => \^fsm_sequential_rx_state_reg[1]_0\,
      I1 => Q(1),
      I2 => \FSM_sequential_rx_state_reg[0]\,
      I3 => \FSM_sequential_rx_state_reg[0]_0\,
      I4 => Q(0),
      I5 => Q(3),
      O => \FSM_sequential_rx_state_reg[1]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => Q(1),
      I1 => rxresetdone_s3,
      I2 => Q(2),
      I3 => qplllock_sync,
      O => \^fsm_sequential_rx_state_reg[1]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18 is
  port (
    data_out : out STD_LOGIC;
    gt3_rxresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_rxresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    time_out_100us_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_rx_state_reg[3]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]\ : in STD_LOGIC;
    reset_time_out_reg : in STD_LOGIC;
    time_out_wait_bypass_s3 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[3]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_5\ : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_6\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    reset_time_out_reg_2 : in STD_LOGIC;
    GT3_DATA_VALID_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19 is
  signal \FSM_sequential_rx_state[1]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_6__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_7__2_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_valid_sync : STD_LOGIC;
  signal \^time_out_100us_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[1]_i_3__2\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9__2\ : label is "soft_lutpair94";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  time_out_100us_reg <= \^time_out_100us_reg\;
\FSM_sequential_rx_state[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFAFAF"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]\,
      I1 => \^time_out_100us_reg\,
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(2),
      O => D(0)
    );
\FSM_sequential_rx_state[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABEBABEBAAEAAAE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[1]\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => \FSM_sequential_rx_state[1]_i_3__2_n_0\,
      I5 => reset_time_out_reg,
      O => D(1)
    );
\FSM_sequential_rx_state[1]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => data_valid_sync,
      I1 => DONT_RESET_ON_DATA_ERROR_IN,
      I2 => \FSM_sequential_rx_state_reg[0]_5\,
      O => \FSM_sequential_rx_state[1]_i_3__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_0\,
      I1 => \FSM_sequential_rx_state_reg[0]_1\,
      I2 => \FSM_sequential_rx_state_reg[0]_2\,
      I3 => \FSM_sequential_rx_state[3]_i_6__2_n_0\,
      I4 => \FSM_sequential_rx_state[3]_i_7__2_n_0\,
      I5 => \FSM_sequential_rx_state_reg[0]_3\,
      O => E(0)
    );
\FSM_sequential_rx_state[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFC8C0C8CC"
    )
        port map (
      I0 => \^time_out_100us_reg\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => time_out_wait_bypass_s3,
      I5 => \FSM_sequential_rx_state_reg[3]_0\,
      O => D(2)
    );
\FSM_sequential_rx_state[3]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4070FF0040700000"
    )
        port map (
      I0 => Q(1),
      I1 => data_valid_sync,
      I2 => time_out_wait_bypass_s3,
      I3 => Q(0),
      I4 => Q(2),
      I5 => \FSM_sequential_rx_state_reg[0]_6\,
      O => \FSM_sequential_rx_state[3]_i_6__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_7__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"32302220D2D0C2C0"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(2),
      I3 => mmcm_lock_reclocked,
      I4 => \FSM_sequential_rx_state_reg[0]_4\,
      I5 => data_valid_sync,
      O => \FSM_sequential_rx_state[3]_i_7__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_9__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_5\,
      I1 => DONT_RESET_ON_DATA_ERROR_IN,
      I2 => data_valid_sync,
      I3 => reset_time_out_reg,
      O => \^time_out_100us_reg\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT3_DATA_VALID_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_valid_sync,
      R => '0'
    );
\reset_time_out_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAEFFFFFFAE0000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_7__2_n_0\,
      I1 => reset_time_out_reg_0,
      I2 => Q(2),
      I3 => reset_time_out_reg_1,
      I4 => reset_time_out_reg_2,
      I5 => reset_time_out_reg,
      O => \FSM_sequential_rx_state_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__6\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__6\ : label is "soft_lutpair95";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt3_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt3_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24 is
  port (
    data_out : out STD_LOGIC;
    gt3_rxdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_rxdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25 is
  port (
    \FSM_onehot_phalign_state_reg[2]\ : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]\ : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_0\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_1\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_2\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_0\ : in STD_LOGIC;
    gt3_run_rx_phalignment_i : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_1\ : in STD_LOGIC;
    phaligndone_prev : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]_0\ : in STD_LOGIC;
    gt3_rxphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
\FSM_onehot_phalign_state[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEE2E2222"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[1]_1\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \^data_out\,
      I3 => phaligndone_prev,
      I4 => \FSM_onehot_phalign_state_reg[2]_0\,
      I5 => \FSM_onehot_phalign_state_reg[0]_0\,
      O => \FSM_onehot_phalign_state_reg[0]\
    );
\FSM_onehot_phalign_state[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[2]_2\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \FSM_onehot_phalign_state_reg[1]_1\,
      I3 => \FSM_onehot_phalign_state_reg[1]_0\,
      I4 => gt3_run_rx_phalignment_i,
      O => \FSM_onehot_phalign_state_reg[1]\
    );
\FSM_onehot_phalign_state[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[2]_0\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \FSM_onehot_phalign_state_reg[2]_2\,
      I3 => \FSM_onehot_phalign_state_reg[1]_0\,
      I4 => gt3_run_rx_phalignment_i,
      O => \FSM_onehot_phalign_state_reg[2]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_rxphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_time_out_reg : out STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_1\ : in STD_LOGIC;
    txresetdone_s3 : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_2\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    reset_time_out_reg_0 : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_3\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_5\ : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    \reset_time_out__0\ : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26 is
  signal \FSM_sequential_tx_state[3]_i_6__1_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  signal \reset_time_out_i_3__5_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__5_n_0\ : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
\FSM_sequential_tx_state[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
        port map (
      I0 => \FSM_sequential_tx_state_reg[0]\,
      I1 => \FSM_sequential_tx_state_reg[0]_0\,
      I2 => \FSM_sequential_tx_state_reg[0]_1\,
      I3 => txresetdone_s3,
      I4 => \FSM_sequential_tx_state[3]_i_6__1_n_0\,
      I5 => \FSM_sequential_tx_state_reg[0]_2\,
      O => E(0)
    );
\FSM_sequential_tx_state[3]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF0400000A04"
    )
        port map (
      I0 => qplllock_sync,
      I1 => \FSM_sequential_tx_state_reg[0]_3\,
      I2 => Q(2),
      I3 => Q(1),
      I4 => \FSM_sequential_tx_state_reg[0]_4\,
      I5 => \FSM_sequential_tx_state_reg[0]_5\,
      O => \FSM_sequential_tx_state[3]_i_6__1_n_0\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => reset_time_out_reg_1,
      I1 => \reset_time_out_i_3__5_n_0\,
      I2 => \reset_time_out_i_4__5_n_0\,
      I3 => \reset_time_out__0\,
      O => reset_time_out_reg
    );
\reset_time_out_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020002000F000200"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(3),
      I3 => Q(0),
      I4 => qplllock_sync,
      I5 => Q(2),
      O => \reset_time_out_i_3__5_n_0\
    );
\reset_time_out_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF005555F544"
    )
        port map (
      I0 => Q(1),
      I1 => reset_time_out_reg_0,
      I2 => qplllock_sync,
      I3 => Q(0),
      I4 => Q(3),
      I5 => Q(2),
      O => \reset_time_out_i_4__5_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27 is
  port (
    data_out : out STD_LOGIC;
    gt2_txresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_txresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__1\ : label is "soft_lutpair81";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29 is
  port (
    data_out : out STD_LOGIC;
    gt2_run_tx_phalignment_i : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => gt2_run_tx_phalignment_i,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31 is
  port (
    data_out : out STD_LOGIC;
    GT2_TX_FSM_RESET_DONE_OUT : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => GT2_TX_FSM_RESET_DONE_OUT,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32 is
  port (
    \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]_0\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    rxresetdone_s3 : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32 is
  signal \^fsm_sequential_rx_state_reg[1]_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  \FSM_sequential_rx_state_reg[1]_0\ <= \^fsm_sequential_rx_state_reg[1]_0\;
\FSM_sequential_rx_state[3]_i_8__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF0000ABAB0000"
    )
        port map (
      I0 => \^fsm_sequential_rx_state_reg[1]_0\,
      I1 => Q(1),
      I2 => \FSM_sequential_rx_state_reg[0]\,
      I3 => \FSM_sequential_rx_state_reg[0]_0\,
      I4 => Q(0),
      I5 => Q(3),
      O => \FSM_sequential_rx_state_reg[1]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => Q(1),
      I1 => rxresetdone_s3,
      I2 => Q(2),
      I3 => qplllock_sync,
      O => \^fsm_sequential_rx_state_reg[1]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33 is
  port (
    data_out : out STD_LOGIC;
    gt2_rxresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_rxresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    time_out_100us_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_rx_state_reg[3]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]\ : in STD_LOGIC;
    reset_time_out_reg : in STD_LOGIC;
    time_out_wait_bypass_s3 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[3]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_5\ : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_6\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    reset_time_out_reg_2 : in STD_LOGIC;
    GT2_DATA_VALID_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34 is
  signal \FSM_sequential_rx_state[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_6__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_7__1_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_valid_sync : STD_LOGIC;
  signal \^time_out_100us_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[1]_i_3__1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9__1\ : label is "soft_lutpair65";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  time_out_100us_reg <= \^time_out_100us_reg\;
\FSM_sequential_rx_state[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFAFAF"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]\,
      I1 => \^time_out_100us_reg\,
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(2),
      O => D(0)
    );
\FSM_sequential_rx_state[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABEBABEBAAEAAAE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[1]\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => \FSM_sequential_rx_state[1]_i_3__1_n_0\,
      I5 => reset_time_out_reg,
      O => D(1)
    );
\FSM_sequential_rx_state[1]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => data_valid_sync,
      I1 => DONT_RESET_ON_DATA_ERROR_IN,
      I2 => \FSM_sequential_rx_state_reg[0]_5\,
      O => \FSM_sequential_rx_state[1]_i_3__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_0\,
      I1 => \FSM_sequential_rx_state_reg[0]_1\,
      I2 => \FSM_sequential_rx_state_reg[0]_2\,
      I3 => \FSM_sequential_rx_state[3]_i_6__1_n_0\,
      I4 => \FSM_sequential_rx_state[3]_i_7__1_n_0\,
      I5 => \FSM_sequential_rx_state_reg[0]_3\,
      O => E(0)
    );
\FSM_sequential_rx_state[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFC8C0C8CC"
    )
        port map (
      I0 => \^time_out_100us_reg\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => time_out_wait_bypass_s3,
      I5 => \FSM_sequential_rx_state_reg[3]_0\,
      O => D(2)
    );
\FSM_sequential_rx_state[3]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4070FF0040700000"
    )
        port map (
      I0 => Q(1),
      I1 => data_valid_sync,
      I2 => time_out_wait_bypass_s3,
      I3 => Q(0),
      I4 => Q(2),
      I5 => \FSM_sequential_rx_state_reg[0]_6\,
      O => \FSM_sequential_rx_state[3]_i_6__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"32302220D2D0C2C0"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(2),
      I3 => mmcm_lock_reclocked,
      I4 => \FSM_sequential_rx_state_reg[0]_4\,
      I5 => data_valid_sync,
      O => \FSM_sequential_rx_state[3]_i_7__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_9__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_5\,
      I1 => DONT_RESET_ON_DATA_ERROR_IN,
      I2 => data_valid_sync,
      I3 => reset_time_out_reg,
      O => \^time_out_100us_reg\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT2_DATA_VALID_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_valid_sync,
      R => '0'
    );
\reset_time_out_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAEFFFFFFAE0000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_7__1_n_0\,
      I1 => reset_time_out_reg_0,
      I2 => Q(2),
      I3 => reset_time_out_reg_1,
      I4 => reset_time_out_reg_2,
      I5 => reset_time_out_reg,
      O => \FSM_sequential_rx_state_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__5\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__5\ : label is "soft_lutpair66";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt2_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt2_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39 is
  port (
    data_out : out STD_LOGIC;
    gt2_rxdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_rxdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40 is
  port (
    \FSM_onehot_phalign_state_reg[2]\ : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]\ : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_0\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_1\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_2\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_0\ : in STD_LOGIC;
    gt2_run_rx_phalignment_i : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_1\ : in STD_LOGIC;
    phaligndone_prev : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]_0\ : in STD_LOGIC;
    gt2_rxphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
\FSM_onehot_phalign_state[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEE2E2222"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[1]_1\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \^data_out\,
      I3 => phaligndone_prev,
      I4 => \FSM_onehot_phalign_state_reg[2]_0\,
      I5 => \FSM_onehot_phalign_state_reg[0]_0\,
      O => \FSM_onehot_phalign_state_reg[0]\
    );
\FSM_onehot_phalign_state[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[2]_2\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \FSM_onehot_phalign_state_reg[1]_1\,
      I3 => \FSM_onehot_phalign_state_reg[1]_0\,
      I4 => gt2_run_rx_phalignment_i,
      O => \FSM_onehot_phalign_state_reg[1]\
    );
\FSM_onehot_phalign_state[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[2]_0\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \FSM_onehot_phalign_state_reg[2]_2\,
      I3 => \FSM_onehot_phalign_state_reg[1]_0\,
      I4 => gt2_run_rx_phalignment_i,
      O => \FSM_onehot_phalign_state_reg[2]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_rxphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_time_out_reg : out STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_1\ : in STD_LOGIC;
    txresetdone_s3 : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_2\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    reset_time_out_reg_0 : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_3\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_5\ : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    \reset_time_out__0\ : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41 is
  signal \FSM_sequential_tx_state[3]_i_6__0_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  signal \reset_time_out_i_3__4_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__4_n_0\ : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
\FSM_sequential_tx_state[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
        port map (
      I0 => \FSM_sequential_tx_state_reg[0]\,
      I1 => \FSM_sequential_tx_state_reg[0]_0\,
      I2 => \FSM_sequential_tx_state_reg[0]_1\,
      I3 => txresetdone_s3,
      I4 => \FSM_sequential_tx_state[3]_i_6__0_n_0\,
      I5 => \FSM_sequential_tx_state_reg[0]_2\,
      O => E(0)
    );
\FSM_sequential_tx_state[3]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF0400000A04"
    )
        port map (
      I0 => qplllock_sync,
      I1 => \FSM_sequential_tx_state_reg[0]_3\,
      I2 => Q(2),
      I3 => Q(1),
      I4 => \FSM_sequential_tx_state_reg[0]_4\,
      I5 => \FSM_sequential_tx_state_reg[0]_5\,
      O => \FSM_sequential_tx_state[3]_i_6__0_n_0\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => reset_time_out_reg_1,
      I1 => \reset_time_out_i_3__4_n_0\,
      I2 => \reset_time_out_i_4__4_n_0\,
      I3 => \reset_time_out__0\,
      O => reset_time_out_reg
    );
\reset_time_out_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020002000F000200"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(3),
      I3 => Q(0),
      I4 => qplllock_sync,
      I5 => Q(2),
      O => \reset_time_out_i_3__4_n_0\
    );
\reset_time_out_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF005555F544"
    )
        port map (
      I0 => Q(1),
      I1 => reset_time_out_reg_0,
      I2 => qplllock_sync,
      I3 => Q(0),
      I4 => Q(3),
      I5 => Q(2),
      O => \reset_time_out_i_4__4_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42 is
  port (
    data_out : out STD_LOGIC;
    gt1_txresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_txresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__0\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__0\ : label is "soft_lutpair52";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46 is
  port (
    data_out : out STD_LOGIC;
    GT1_TX_FSM_RESET_DONE_OUT : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => GT1_TX_FSM_RESET_DONE_OUT,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47 is
  port (
    \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]_0\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    rxresetdone_s3 : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47 is
  signal \^fsm_sequential_rx_state_reg[1]_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  \FSM_sequential_rx_state_reg[1]_0\ <= \^fsm_sequential_rx_state_reg[1]_0\;
\FSM_sequential_rx_state[3]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF0000ABAB0000"
    )
        port map (
      I0 => \^fsm_sequential_rx_state_reg[1]_0\,
      I1 => Q(1),
      I2 => \FSM_sequential_rx_state_reg[0]\,
      I3 => \FSM_sequential_rx_state_reg[0]_0\,
      I4 => Q(0),
      I5 => Q(3),
      O => \FSM_sequential_rx_state_reg[1]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => Q(1),
      I1 => rxresetdone_s3,
      I2 => Q(2),
      I3 => qplllock_sync,
      O => \^fsm_sequential_rx_state_reg[1]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48 is
  port (
    data_out : out STD_LOGIC;
    gt1_rxresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_rxresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    time_out_100us_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_rx_state_reg[3]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]\ : in STD_LOGIC;
    reset_time_out_reg : in STD_LOGIC;
    time_out_wait_bypass_s3 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[3]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_5\ : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_6\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    reset_time_out_reg_2 : in STD_LOGIC;
    GT1_DATA_VALID_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49 is
  signal \FSM_sequential_rx_state[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_6__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_7__0_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_valid_sync : STD_LOGIC;
  signal \^time_out_100us_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[1]_i_3__0\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9__0\ : label is "soft_lutpair36";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  time_out_100us_reg <= \^time_out_100us_reg\;
\FSM_sequential_rx_state[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFAFAF"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]\,
      I1 => \^time_out_100us_reg\,
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(2),
      O => D(0)
    );
\FSM_sequential_rx_state[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABEBABEBAAEAAAE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[1]\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => \FSM_sequential_rx_state[1]_i_3__0_n_0\,
      I5 => reset_time_out_reg,
      O => D(1)
    );
\FSM_sequential_rx_state[1]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => data_valid_sync,
      I1 => DONT_RESET_ON_DATA_ERROR_IN,
      I2 => \FSM_sequential_rx_state_reg[0]_5\,
      O => \FSM_sequential_rx_state[1]_i_3__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_0\,
      I1 => \FSM_sequential_rx_state_reg[0]_1\,
      I2 => \FSM_sequential_rx_state_reg[0]_2\,
      I3 => \FSM_sequential_rx_state[3]_i_6__0_n_0\,
      I4 => \FSM_sequential_rx_state[3]_i_7__0_n_0\,
      I5 => \FSM_sequential_rx_state_reg[0]_3\,
      O => E(0)
    );
\FSM_sequential_rx_state[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFC8C0C8CC"
    )
        port map (
      I0 => \^time_out_100us_reg\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => time_out_wait_bypass_s3,
      I5 => \FSM_sequential_rx_state_reg[3]_0\,
      O => D(2)
    );
\FSM_sequential_rx_state[3]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4070FF0040700000"
    )
        port map (
      I0 => Q(1),
      I1 => data_valid_sync,
      I2 => time_out_wait_bypass_s3,
      I3 => Q(0),
      I4 => Q(2),
      I5 => \FSM_sequential_rx_state_reg[0]_6\,
      O => \FSM_sequential_rx_state[3]_i_6__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"32302220D2D0C2C0"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(2),
      I3 => mmcm_lock_reclocked,
      I4 => \FSM_sequential_rx_state_reg[0]_4\,
      I5 => data_valid_sync,
      O => \FSM_sequential_rx_state[3]_i_7__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_5\,
      I1 => DONT_RESET_ON_DATA_ERROR_IN,
      I2 => data_valid_sync,
      I3 => reset_time_out_reg,
      O => \^time_out_100us_reg\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT1_DATA_VALID_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_valid_sync,
      R => '0'
    );
\reset_time_out_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAEFFFFFFAE0000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_7__0_n_0\,
      I1 => reset_time_out_reg_0,
      I2 => Q(2),
      I3 => reset_time_out_reg_1,
      I4 => reset_time_out_reg_2,
      I5 => reset_time_out_reg,
      O => \FSM_sequential_rx_state_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__4\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__4\ : label is "soft_lutpair37";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt1_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt1_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54 is
  port (
    data_out : out STD_LOGIC;
    gt1_rxdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_rxdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55 is
  port (
    \FSM_onehot_phalign_state_reg[2]\ : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]\ : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_0\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_1\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[2]_2\ : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_0\ : in STD_LOGIC;
    gt1_run_rx_phalignment_i : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_1\ : in STD_LOGIC;
    phaligndone_prev : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]_0\ : in STD_LOGIC;
    gt1_rxphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
\FSM_onehot_phalign_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEE2E2222"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[1]_1\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \^data_out\,
      I3 => phaligndone_prev,
      I4 => \FSM_onehot_phalign_state_reg[2]_0\,
      I5 => \FSM_onehot_phalign_state_reg[0]_0\,
      O => \FSM_onehot_phalign_state_reg[0]\
    );
\FSM_onehot_phalign_state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[2]_2\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \FSM_onehot_phalign_state_reg[1]_1\,
      I3 => \FSM_onehot_phalign_state_reg[1]_0\,
      I4 => gt1_run_rx_phalignment_i,
      O => \FSM_onehot_phalign_state_reg[1]\
    );
\FSM_onehot_phalign_state[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[2]_0\,
      I1 => \FSM_onehot_phalign_state_reg[2]_1\,
      I2 => \FSM_onehot_phalign_state_reg[2]_2\,
      I3 => \FSM_onehot_phalign_state_reg[1]_0\,
      I4 => gt1_run_rx_phalignment_i,
      O => \FSM_onehot_phalign_state_reg[2]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_rxphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_time_out_reg : out STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_3\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_5\ : in STD_LOGIC;
    \FSM_sequential_tx_state_reg[0]_6\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    \reset_time_out__0\ : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56 is
  signal \FSM_sequential_tx_state[3]_i_4_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  signal \reset_time_out_i_3__3_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__3_n_0\ : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
\FSM_sequential_tx_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEEEEFEE"
    )
        port map (
      I0 => \FSM_sequential_tx_state_reg[0]\,
      I1 => \FSM_sequential_tx_state[3]_i_4_n_0\,
      I2 => \FSM_sequential_tx_state_reg[0]_0\,
      I3 => \FSM_sequential_tx_state_reg[0]_1\,
      I4 => \FSM_sequential_tx_state_reg[0]_2\,
      I5 => \FSM_sequential_tx_state_reg[0]_3\,
      O => E(0)
    );
\FSM_sequential_tx_state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF0400000A04"
    )
        port map (
      I0 => qplllock_sync,
      I1 => \FSM_sequential_tx_state_reg[0]_4\,
      I2 => Q(2),
      I3 => Q(1),
      I4 => \FSM_sequential_tx_state_reg[0]_5\,
      I5 => \FSM_sequential_tx_state_reg[0]_6\,
      O => \FSM_sequential_tx_state[3]_i_4_n_0\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
reset_time_out_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => reset_time_out_reg_0,
      I1 => \reset_time_out_i_3__3_n_0\,
      I2 => \reset_time_out_i_4__3_n_0\,
      I3 => \reset_time_out__0\,
      O => reset_time_out_reg
    );
\reset_time_out_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020002000F000200"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(3),
      I3 => Q(0),
      I4 => qplllock_sync,
      I5 => Q(2),
      O => \reset_time_out_i_3__3_n_0\
    );
\reset_time_out_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF005555F544"
    )
        port map (
      I0 => Q(1),
      I1 => \FSM_sequential_tx_state_reg[0]_1\,
      I2 => qplllock_sync,
      I3 => Q(0),
      I4 => Q(3),
      I5 => Q(2),
      O => \reset_time_out_i_4__3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57 is
  port (
    data_out : out STD_LOGIC;
    gt0_txresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_txresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of mmcm_lock_reclocked_i_1 : label is "soft_lutpair23";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
mmcm_lock_reclocked_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59 is
  port (
    data_out : out STD_LOGIC;
    gt0_run_tx_phalignment_i : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => gt0_run_tx_phalignment_i,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61 is
  port (
    data_out : out STD_LOGIC;
    GT0_TX_FSM_RESET_DONE_OUT : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => GT0_TX_FSM_RESET_DONE_OUT,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62 is
  port (
    data_sync_reg6_0 : out STD_LOGIC;
    \txdlysresetdone_store_reg[0]\ : in STD_LOGIC;
    gt0_txdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal txdlysresetdone_sync_0 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_txdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => txdlysresetdone_sync_0,
      R => '0'
    );
\txdlysresetdone_store[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txdlysresetdone_sync_0,
      I1 => \txdlysresetdone_store_reg[0]\,
      O => data_sync_reg6_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_tx_phalign_manual_state_reg[3]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    \txphaligndone_prev_reg[0]\ : out STD_LOGIC;
    \FSM_sequential_tx_phalign_manual_state_reg[1]\ : out STD_LOGIC;
    \FSM_sequential_tx_phalign_manual_state_reg[0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_tx_phalign_manual_state_reg[0]_0\ : in STD_LOGIC;
    txphinitdone_sync_0 : in STD_LOGIC;
    \FSM_sequential_tx_phalign_manual_state_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphinitdone_store_edge : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_txdlyen_in : in STD_LOGIC;
    \txphaligndone_store_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphaligndone_store : in STD_LOGIC_VECTOR ( 0 to 0 );
    U0_TXPHALIGN : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_txphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63 is
  signal \FSM_sequential_tx_phalign_manual_state[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_phalign_manual_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \TXPHALIGN[0]_i_2_n_0\ : STD_LOGIC;
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TXPHALIGN[0]_i_2\ : label is "soft_lutpair18";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \txphaligndone_store[0]_i_1\ : label is "soft_lutpair18";
begin
  data_out <= \^data_out\;
\FSM_sequential_tx_phalign_manual_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => \FSM_sequential_tx_phalign_manual_state_reg[0]\,
      I1 => Q(2),
      I2 => \FSM_sequential_tx_phalign_manual_state[3]_i_5_n_0\,
      I3 => Q(1),
      I4 => \FSM_sequential_tx_phalign_manual_state[3]_i_6_n_0\,
      I5 => Q(3),
      O => E(0)
    );
\FSM_sequential_tx_phalign_manual_state[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"800000008000FFFF"
    )
        port map (
      I0 => txphinitdone_store_edge(3),
      I1 => txphinitdone_store_edge(2),
      I2 => txphinitdone_store_edge(1),
      I3 => txphinitdone_store_edge(0),
      I4 => Q(0),
      I5 => \TXPHALIGN[0]_i_2_n_0\,
      O => \FSM_sequential_tx_phalign_manual_state[3]_i_5_n_0\
    );
\FSM_sequential_tx_phalign_manual_state[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F880F880FBB0F88"
    )
        port map (
      I0 => \FSM_sequential_tx_phalign_manual_state_reg[0]_0\,
      I1 => Q(2),
      I2 => \TXPHALIGN[0]_i_2_n_0\,
      I3 => Q(0),
      I4 => txphinitdone_sync_0,
      I5 => \FSM_sequential_tx_phalign_manual_state_reg[0]_1\(0),
      O => \FSM_sequential_tx_phalign_manual_state[3]_i_6_n_0\
    );
\TXDLYEN[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFF3000020C"
    )
        port map (
      I0 => \TXPHALIGN[0]_i_2_n_0\,
      I1 => Q(3),
      I2 => Q(1),
      I3 => Q(2),
      I4 => Q(0),
      I5 => gt0_txdlyen_in,
      O => \FSM_sequential_tx_phalign_manual_state_reg[3]\
    );
\TXPHALIGN[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFB3F00000800"
    )
        port map (
      I0 => \TXPHALIGN[0]_i_2_n_0\,
      I1 => Q(1),
      I2 => Q(2),
      I3 => Q(0),
      I4 => Q(3),
      I5 => U0_TXPHALIGN(0),
      O => \FSM_sequential_tx_phalign_manual_state_reg[1]\
    );
\TXPHALIGN[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \txphaligndone_store_reg[0]\(0),
      I1 => \^data_out\,
      O => \TXPHALIGN[0]_i_2_n_0\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_txphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
\txphaligndone_store[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \txphaligndone_store_reg[0]\(0),
      I1 => \^data_out\,
      I2 => txphaligndone_store(0),
      O => \txphaligndone_prev_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64 is
  port (
    data_sync_reg6_0 : out STD_LOGIC;
    p_1_in : in STD_LOGIC;
    gt1_txdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal txdlysresetdone_sync_1 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_txdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => txdlysresetdone_sync_1,
      R => '0'
    );
\txdlysresetdone_store[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txdlysresetdone_sync_1,
      I1 => p_1_in,
      O => data_sync_reg6_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65 is
  port (
    \txphaligndone_prev_reg[1]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphaligndone_store : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt1_txphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_txphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
\txphaligndone_store[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => Q(0),
      I1 => \^data_out\,
      I2 => txphaligndone_store(0),
      O => \txphaligndone_prev_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67 is
  port (
    data_sync_reg6_0 : out STD_LOGIC;
    p_2_in : in STD_LOGIC;
    gt2_txdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal txdlysresetdone_sync_2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_txdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => txdlysresetdone_sync_2,
      R => '0'
    );
\txdlysresetdone_store[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txdlysresetdone_sync_2,
      I1 => p_2_in,
      O => data_sync_reg6_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68 is
  port (
    \txphaligndone_prev_reg[2]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphaligndone_store : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt2_txphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_txphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
\txphaligndone_store[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => Q(0),
      I1 => \^data_out\,
      I2 => txphaligndone_store(0),
      O => \txphaligndone_prev_reg[2]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70 is
  port (
    data_sync_reg6_0 : out STD_LOGIC;
    \txdlysresetdone_store_reg[3]\ : in STD_LOGIC;
    gt3_txdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal txdlysresetdone_sync_3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_txdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => txdlysresetdone_sync_3,
      R => '0'
    );
\txdlysresetdone_store[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txdlysresetdone_sync_3,
      I1 => \txdlysresetdone_store_reg[3]\,
      O => data_sync_reg6_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71 is
  port (
    \txphaligndone_prev_reg[3]\ : out STD_LOGIC;
    data_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphaligndone_store : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt3_txphaligndone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_txphaligndone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
\txphaligndone_store[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => Q(0),
      I1 => \^data_out\,
      I2 => txphaligndone_store(0),
      O => \txphaligndone_prev_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73 is
  port (
    \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]_0\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    rxresetdone_s3 : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73 is
  signal \^fsm_sequential_rx_state_reg[1]_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal qplllock_sync : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  \FSM_sequential_rx_state_reg[1]_0\ <= \^fsm_sequential_rx_state_reg[1]_0\;
\FSM_sequential_rx_state[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF0000ABAB0000"
    )
        port map (
      I0 => \^fsm_sequential_rx_state_reg[1]_0\,
      I1 => Q(1),
      I2 => \FSM_sequential_rx_state_reg[0]\,
      I3 => \FSM_sequential_rx_state_reg[0]_0\,
      I4 => Q(0),
      I5 => Q(3),
      O => \FSM_sequential_rx_state_reg[1]\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_QPLLLOCK_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => qplllock_sync,
      R => '0'
    );
\reset_time_out_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => Q(1),
      I1 => rxresetdone_s3,
      I2 => Q(2),
      I3 => qplllock_sync,
      O => \^fsm_sequential_rx_state_reg[1]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74 is
  port (
    data_out : out STD_LOGIC;
    gt0_rxresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_rxresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DONT_RESET_ON_DATA_ERROR_IN_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_rx_state_reg[3]\ : out STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_4\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[1]\ : in STD_LOGIC;
    reset_time_out_reg : in STD_LOGIC;
    time_out_wait_bypass_s3 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[3]_0\ : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_5\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_6\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    reset_time_out_reg_2 : in STD_LOGIC;
    GT0_DATA_VALID_IN : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75 is
  signal \^dont_reset_on_data_error_in_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_7_n_0\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_valid_sync : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[1]_i_3\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9\ : label is "soft_lutpair2";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  DONT_RESET_ON_DATA_ERROR_IN_0 <= \^dont_reset_on_data_error_in_0\;
\FSM_sequential_rx_state[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFAFAF"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]\,
      I1 => \^dont_reset_on_data_error_in_0\,
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(2),
      O => D(0)
    );
\FSM_sequential_rx_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABEBABEBAAEAAAE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[1]\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => \FSM_sequential_rx_state[1]_i_3_n_0\,
      I5 => reset_time_out_reg,
      O => D(1)
    );
\FSM_sequential_rx_state[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_5\,
      I1 => data_valid_sync,
      I2 => DONT_RESET_ON_DATA_ERROR_IN,
      O => \FSM_sequential_rx_state[1]_i_3_n_0\
    );
\FSM_sequential_rx_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_0\,
      I1 => \FSM_sequential_rx_state_reg[0]_1\,
      I2 => \FSM_sequential_rx_state_reg[0]_2\,
      I3 => \FSM_sequential_rx_state[3]_i_6_n_0\,
      I4 => \FSM_sequential_rx_state[3]_i_7_n_0\,
      I5 => \FSM_sequential_rx_state_reg[0]_3\,
      O => E(0)
    );
\FSM_sequential_rx_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFC8C0C8CC"
    )
        port map (
      I0 => \^dont_reset_on_data_error_in_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => time_out_wait_bypass_s3,
      I5 => \FSM_sequential_rx_state_reg[3]_0\,
      O => D(2)
    );
\FSM_sequential_rx_state[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4070FF0040700000"
    )
        port map (
      I0 => Q(1),
      I1 => data_valid_sync,
      I2 => time_out_wait_bypass_s3,
      I3 => Q(0),
      I4 => Q(2),
      I5 => \FSM_sequential_rx_state_reg[0]_6\,
      O => \FSM_sequential_rx_state[3]_i_6_n_0\
    );
\FSM_sequential_rx_state[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"32302220D2D0C2C0"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(2),
      I3 => mmcm_lock_reclocked,
      I4 => \FSM_sequential_rx_state_reg[0]_4\,
      I5 => data_valid_sync,
      O => \FSM_sequential_rx_state[3]_i_7_n_0\
    );
\FSM_sequential_rx_state[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => DONT_RESET_ON_DATA_ERROR_IN,
      I1 => data_valid_sync,
      I2 => \FSM_sequential_rx_state_reg[0]_5\,
      I3 => reset_time_out_reg,
      O => \^dont_reset_on_data_error_in_0\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => GT0_DATA_VALID_IN,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_valid_sync,
      R => '0'
    );
\reset_time_out_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAEFFFFFFAE0000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_7_n_0\,
      I1 => reset_time_out_reg_0,
      I2 => Q(2),
      I3 => reset_time_out_reg_1,
      I4 => reset_time_out_reg_2,
      I5 => reset_time_out_reg,
      O => \FSM_sequential_rx_state_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal mmcm_lock_i : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__3\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__3\ : label is "soft_lutpair3";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => '1',
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => mmcm_lock_i,
      R => '0'
    );
\mmcm_lock_count[7]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_i,
      O => SR(0)
    );
\mmcm_lock_reclocked_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEA0000"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => Q(1),
      I2 => Q(0),
      I3 => mmcm_lock_reclocked_reg_0,
      I4 => mmcm_lock_i,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt0_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    gt0_rxusrclk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79 is
  port (
    data_out : out STD_LOGIC;
    data_in : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_in,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80 is
  port (
    data_out : out STD_LOGIC;
    gt0_rxdlysresetdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80 is
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_rxdlysresetdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => data_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81 is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    data_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    phaligndone_prev : in STD_LOGIC;
    gt0_rxsyncdone_out : in STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81 : entity is "mgt11g2_tx_rx_cfpga_sync_block";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81 is
  signal \^data_out\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_phalign_state[0]_i_1__2\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_onehot_phalign_state[3]_i_2\ : label is "soft_lutpair0";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute box_type : string;
  attribute box_type of data_sync_reg1 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute box_type of data_sync_reg2 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute box_type of data_sync_reg3 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute box_type of data_sync_reg4 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute box_type of data_sync_reg5 : label is "PRIMITIVE";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute box_type of data_sync_reg6 : label is "PRIMITIVE";
begin
  data_out <= \^data_out\;
\FSM_onehot_phalign_state[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => Q(0),
      I1 => phaligndone_prev,
      I2 => \^data_out\,
      O => D(0)
    );
\FSM_onehot_phalign_state[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => Q(0),
      I1 => phaligndone_prev,
      I2 => \^data_out\,
      O => D(1)
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_rxsyncdone_out,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_sync5,
      Q => \^data_out\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse is
  port (
    txphinitdone_sync_0 : out STD_LOGIC;
    txdone_clear_reg : out STD_LOGIC;
    \FSM_sequential_tx_phalign_manual_state_reg[2]\ : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \stretch_r_reg[2]_0\ : in STD_LOGIC;
    \txphinitdone_store_edge_reg[0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphinitdone_store_edge : in STD_LOGIC_VECTOR ( 0 to 0 );
    \TXPHINIT_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    U0_TXPHINIT : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_txphinitdone_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse : entity is "mgt11g2_tx_rx_cfpga_sync_pulse";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse is
  signal \TXPHINIT[0]_i_2_n_0\ : STD_LOGIC;
  signal USER_DONE_i_1_n_0 : STD_LOGIC;
  signal stretch_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal sync1_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg : string;
  attribute async_reg of sync1_r : signal is "true";
  attribute shreg_extract : string;
  attribute shreg_extract of sync1_r : signal is "no";
  signal sync2_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of sync2_r : signal is "true";
  attribute shreg_extract of sync2_r : signal is "no";
  signal \^txphinitdone_sync_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TXPHINIT[0]_i_2\ : label is "soft_lutpair19";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync1_r_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync1_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[2]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[2]\ : label is "no";
  attribute SOFT_HLUTNM of \txphinitdone_store_edge[0]_i_1\ : label is "soft_lutpair19";
begin
  txphinitdone_sync_0 <= \^txphinitdone_sync_0\;
\TXPHINIT[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFE3F00000200"
    )
        port map (
      I0 => \TXPHINIT[0]_i_2_n_0\,
      I1 => \TXPHINIT_reg[0]\(2),
      I2 => \TXPHINIT_reg[0]\(0),
      I3 => \TXPHINIT_reg[0]\(1),
      I4 => \TXPHINIT_reg[0]\(3),
      I5 => U0_TXPHINIT(0),
      O => \FSM_sequential_tx_phalign_manual_state_reg[2]\
    );
\TXPHINIT[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => Q(0),
      I1 => \^txphinitdone_sync_0\,
      O => \TXPHINIT[0]_i_2_n_0\
    );
USER_DONE_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sync1_r(0),
      I1 => sync2_r(0),
      O => USER_DONE_i_1_n_0
    );
USER_DONE_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => USER_DONE_i_1_n_0,
      Q => \^txphinitdone_sync_0\,
      R => '0'
    );
\stretch_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => stretch_r(1),
      Q => stretch_r(0)
    );
\stretch_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => stretch_r(2),
      Q => stretch_r(1)
    );
\stretch_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => '1',
      Q => stretch_r(2)
    );
\sync1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(1),
      Q => sync1_r(0),
      R => '0'
    );
\sync1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(2),
      Q => sync1_r(1),
      R => '0'
    );
\sync1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => stretch_r(0),
      Q => sync1_r(2),
      R => '0'
    );
\sync2_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(1),
      Q => sync2_r(0),
      R => '0'
    );
\sync2_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(2),
      Q => sync2_r(1),
      R => '0'
    );
\sync2_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_txphinitdone_out,
      Q => sync2_r(2),
      R => '0'
    );
\txphinitdone_store_edge[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => \txphinitdone_store_edge_reg[0]\,
      I1 => \^txphinitdone_sync_0\,
      I2 => Q(0),
      I3 => txphinitdone_store_edge(0),
      O => txdone_clear_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \txphinitdone_prev_reg[1]\ : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \stretch_r_reg[2]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphinitdone_store_edge : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt1_txphinitdone_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66 : entity is "mgt11g2_tx_rx_cfpga_sync_pulse";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \USER_DONE_i_1__0_n_0\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[2]\ : STD_LOGIC;
  signal sync1_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg : string;
  attribute async_reg of sync1_r : signal is "true";
  attribute shreg_extract : string;
  attribute shreg_extract of sync1_r : signal is "no";
  signal sync2_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of sync2_r : signal is "true";
  attribute shreg_extract of sync2_r : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync1_r_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync1_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[2]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[2]\ : label is "no";
begin
  D(0) <= \^d\(0);
\USER_DONE_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sync1_r(0),
      I1 => sync2_r(0),
      O => \USER_DONE_i_1__0_n_0\
    );
USER_DONE_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \USER_DONE_i_1__0_n_0\,
      Q => \^d\(0),
      R => '0'
    );
\stretch_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => \stretch_r_reg_n_0_[1]\,
      Q => \stretch_r_reg_n_0_[0]\
    );
\stretch_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => \stretch_r_reg_n_0_[2]\,
      Q => \stretch_r_reg_n_0_[1]\
    );
\stretch_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => '1',
      Q => \stretch_r_reg_n_0_[2]\
    );
\sync1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(1),
      Q => sync1_r(0),
      R => '0'
    );
\sync1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(2),
      Q => sync1_r(1),
      R => '0'
    );
\sync1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \stretch_r_reg_n_0_[0]\,
      Q => sync1_r(2),
      R => '0'
    );
\sync2_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(1),
      Q => sync2_r(0),
      R => '0'
    );
\sync2_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(2),
      Q => sync2_r(1),
      R => '0'
    );
\sync2_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt1_txphinitdone_out,
      Q => sync2_r(2),
      R => '0'
    );
\txphinitdone_store_edge[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => Q(0),
      I1 => \^d\(0),
      I2 => txphinitdone_store_edge(0),
      O => \txphinitdone_prev_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \txphinitdone_prev_reg[2]\ : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \stretch_r_reg[2]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphinitdone_store_edge : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt2_txphinitdone_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69 : entity is "mgt11g2_tx_rx_cfpga_sync_pulse";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \USER_DONE_i_1__1_n_0\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[2]\ : STD_LOGIC;
  signal sync1_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg : string;
  attribute async_reg of sync1_r : signal is "true";
  attribute shreg_extract : string;
  attribute shreg_extract of sync1_r : signal is "no";
  signal sync2_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of sync2_r : signal is "true";
  attribute shreg_extract of sync2_r : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync1_r_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync1_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[2]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[2]\ : label is "no";
begin
  D(0) <= \^d\(0);
\USER_DONE_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sync1_r(0),
      I1 => sync2_r(0),
      O => \USER_DONE_i_1__1_n_0\
    );
USER_DONE_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \USER_DONE_i_1__1_n_0\,
      Q => \^d\(0),
      R => '0'
    );
\stretch_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => \stretch_r_reg_n_0_[1]\,
      Q => \stretch_r_reg_n_0_[0]\
    );
\stretch_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => \stretch_r_reg_n_0_[2]\,
      Q => \stretch_r_reg_n_0_[1]\
    );
\stretch_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => '1',
      Q => \stretch_r_reg_n_0_[2]\
    );
\sync1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(1),
      Q => sync1_r(0),
      R => '0'
    );
\sync1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(2),
      Q => sync1_r(1),
      R => '0'
    );
\sync1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \stretch_r_reg_n_0_[0]\,
      Q => sync1_r(2),
      R => '0'
    );
\sync2_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(1),
      Q => sync2_r(0),
      R => '0'
    );
\sync2_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(2),
      Q => sync2_r(1),
      R => '0'
    );
\sync2_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt2_txphinitdone_out,
      Q => sync2_r(2),
      R => '0'
    );
\txphinitdone_store_edge[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => Q(0),
      I1 => \^d\(0),
      I2 => txphinitdone_store_edge(0),
      O => \txphinitdone_prev_reg[2]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \txphinitdone_prev_reg[3]\ : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \stretch_r_reg[2]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphinitdone_store_edge : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt3_txphinitdone_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72 : entity is "mgt11g2_tx_rx_cfpga_sync_pulse";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \USER_DONE_i_1__2_n_0\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \stretch_r_reg_n_0_[2]\ : STD_LOGIC;
  signal sync1_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg : string;
  attribute async_reg of sync1_r : signal is "true";
  attribute shreg_extract : string;
  attribute shreg_extract of sync1_r : signal is "no";
  signal sync2_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute async_reg of sync2_r : signal is "true";
  attribute shreg_extract of sync2_r : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync1_r_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync1_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync1_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync1_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync1_r_reg[2]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[0]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[0]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[1]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[1]\ : label is "no";
  attribute ASYNC_REG_boolean of \sync2_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \sync2_r_reg[2]\ : label is "yes";
  attribute SHREG_EXTRACT of \sync2_r_reg[2]\ : label is "no";
begin
  D(0) <= \^d\(0);
\USER_DONE_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sync1_r(0),
      I1 => sync2_r(0),
      O => \USER_DONE_i_1__2_n_0\
    );
USER_DONE_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \USER_DONE_i_1__2_n_0\,
      Q => \^d\(0),
      R => '0'
    );
\stretch_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => \stretch_r_reg_n_0_[1]\,
      Q => \stretch_r_reg_n_0_[0]\
    );
\stretch_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => \stretch_r_reg_n_0_[2]\,
      Q => \stretch_r_reg_n_0_[1]\
    );
\stretch_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => \stretch_r_reg[2]_0\,
      D => '1',
      Q => \stretch_r_reg_n_0_[2]\
    );
\sync1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(1),
      Q => sync1_r(0),
      R => '0'
    );
\sync1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync1_r(2),
      Q => sync1_r(1),
      R => '0'
    );
\sync1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \stretch_r_reg_n_0_[0]\,
      Q => sync1_r(2),
      R => '0'
    );
\sync2_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(1),
      Q => sync2_r(0),
      R => '0'
    );
\sync2_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync2_r(2),
      Q => sync2_r(1),
      R => '0'
    );
\sync2_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt3_txphinitdone_out,
      Q => sync2_r(2),
      R => '0'
    );
\txphinitdone_store_edge[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => Q(0),
      I1 => \^d\(0),
      I2 => txphinitdone_store_edge(0),
      O => \txphinitdone_prev_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN is
  port (
    PHASE_ALIGNMENT_DONE_reg_0 : out STD_LOGIC;
    gt0_rxdlysreset_in : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    PHASE_ALIGNMENT_DONE_reg_1 : in STD_LOGIC;
    gt0_run_rx_phalignment_i : in STD_LOGIC;
    gt0_rxsyncdone_out : in STD_LOGIC;
    gt0_rxdlysresetdone_out : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN : entity is "mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN is
  signal DLYSRESET_i_1_n_0 : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[3]\ : STD_LOGIC;
  signal \PHASE_ALIGNMENT_DONE_i_1__0_n_0\ : STD_LOGIC;
  signal \^phase_alignment_done_reg_0\ : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal dlysresetdone_sync : STD_LOGIC;
  signal phalign_state_n_0 : STD_LOGIC;
  signal phaligndone_prev : STD_LOGIC;
  signal sync_PHALIGNDONE_n_0 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_1 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of DLYSRESET_i_1 : label is "soft_lutpair1";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[0]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[1]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[2]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[3]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute SOFT_HLUTNM of \PHASE_ALIGNMENT_DONE_i_1__0\ : label is "soft_lutpair1";
begin
  PHASE_ALIGNMENT_DONE_reg_0 <= \^phase_alignment_done_reg_0\;
DLYSRESET_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => PHASE_ALIGNMENT_DONE_reg_1,
      I2 => gt0_run_rx_phalignment_i,
      O => DLYSRESET_i_1_n_0
    );
DLYSRESET_reg: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => '1',
      D => DLYSRESET_i_1_n_0,
      Q => gt0_rxdlysreset_in,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => SYSCLK_IN,
      CE => phalign_state_n_0,
      D => sync_PHALIGNDONE_n_1,
      Q => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      S => SS(0)
    );
\FSM_onehot_phalign_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => phalign_state_n_0,
      D => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      Q => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      R => SS(0)
    );
\FSM_onehot_phalign_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => phalign_state_n_0,
      D => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      Q => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      R => SS(0)
    );
\FSM_onehot_phalign_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => phalign_state_n_0,
      D => sync_PHALIGNDONE_n_0,
      Q => \FSM_onehot_phalign_state_reg_n_0_[3]\,
      R => SS(0)
    );
\PHASE_ALIGNMENT_DONE_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CE000000"
    )
        port map (
      I0 => \^phase_alignment_done_reg_0\,
      I1 => \FSM_onehot_phalign_state_reg_n_0_[3]\,
      I2 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I3 => PHASE_ALIGNMENT_DONE_reg_1,
      I4 => gt0_run_rx_phalignment_i,
      O => \PHASE_ALIGNMENT_DONE_i_1__0_n_0\
    );
PHASE_ALIGNMENT_DONE_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \PHASE_ALIGNMENT_DONE_i_1__0_n_0\,
      Q => \^phase_alignment_done_reg_0\,
      R => '0'
    );
phalign_state: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAEAAAEAAAEAA"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      I2 => phaligndone_prev,
      I3 => data_out,
      I4 => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      I5 => dlysresetdone_sync,
      O => phalign_state_n_0
    );
phaligndone_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_out,
      Q => phaligndone_prev,
      R => '0'
    );
sync_DLYSRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => dlysresetdone_sync,
      gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_out
    );
sync_PHALIGNDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81
     port map (
      D(1) => sync_PHALIGNDONE_n_0,
      D(0) => sync_PHALIGNDONE_n_1,
      Q(0) => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      SYSCLK_IN => SYSCLK_IN,
      data_out => data_out,
      gt0_rxsyncdone_out => gt0_rxsyncdone_out,
      phaligndone_prev => phaligndone_prev
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 is
  port (
    gt1_rxdlysreset_in : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_0\ : in STD_LOGIC;
    gt1_run_rx_phalignment_i : in STD_LOGIC;
    gt1_rxphaligndone_out : in STD_LOGIC;
    gt1_rxdlysresetdone_out : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 : entity is "mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 is
  signal \DLYSRESET_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[2]\ : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal dlysresetdone_sync : STD_LOGIC;
  signal phalign_state_n_0 : STD_LOGIC;
  signal phaligndone_prev : STD_LOGIC;
  signal sync_PHALIGNDONE_n_0 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_1 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_2 : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[0]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[1]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[2]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
begin
\DLYSRESET_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg[1]_0\,
      I2 => gt1_run_rx_phalignment_i,
      O => \DLYSRESET_i_1__0_n_0\
    );
DLYSRESET_reg: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \DLYSRESET_i_1__0_n_0\,
      Q => gt1_rxdlysreset_in,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_2,
      Q => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_1,
      Q => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_0,
      Q => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      R => '0'
    );
phalign_state: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAEAAAEAAAEAA"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      I2 => phaligndone_prev,
      I3 => data_out,
      I4 => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      I5 => dlysresetdone_sync,
      O => phalign_state_n_0
    );
phaligndone_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_out,
      Q => phaligndone_prev,
      R => '0'
    );
sync_DLYSRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => dlysresetdone_sync,
      gt1_rxdlysresetdone_out => gt1_rxdlysresetdone_out
    );
sync_PHALIGNDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55
     port map (
      \FSM_onehot_phalign_state_reg[0]\ => sync_PHALIGNDONE_n_2,
      \FSM_onehot_phalign_state_reg[0]_0\ => \FSM_onehot_phalign_state_reg[0]_0\,
      \FSM_onehot_phalign_state_reg[1]\ => sync_PHALIGNDONE_n_1,
      \FSM_onehot_phalign_state_reg[1]_0\ => \FSM_onehot_phalign_state_reg[1]_0\,
      \FSM_onehot_phalign_state_reg[1]_1\ => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      \FSM_onehot_phalign_state_reg[2]\ => sync_PHALIGNDONE_n_0,
      \FSM_onehot_phalign_state_reg[2]_0\ => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      \FSM_onehot_phalign_state_reg[2]_1\ => phalign_state_n_0,
      \FSM_onehot_phalign_state_reg[2]_2\ => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      SYSCLK_IN => SYSCLK_IN,
      data_out => data_out,
      gt1_run_rx_phalignment_i => gt1_run_rx_phalignment_i,
      gt1_rxphaligndone_out => gt1_rxphaligndone_out,
      phaligndone_prev => phaligndone_prev
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 is
  port (
    gt2_rxdlysreset_in : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_0\ : in STD_LOGIC;
    gt2_run_rx_phalignment_i : in STD_LOGIC;
    gt2_rxphaligndone_out : in STD_LOGIC;
    gt2_rxdlysresetdone_out : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 : entity is "mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 is
  signal \DLYSRESET_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[2]\ : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal dlysresetdone_sync : STD_LOGIC;
  signal phalign_state_n_0 : STD_LOGIC;
  signal phaligndone_prev : STD_LOGIC;
  signal sync_PHALIGNDONE_n_0 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_1 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_2 : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[0]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[1]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[2]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
begin
\DLYSRESET_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg[1]_0\,
      I2 => gt2_run_rx_phalignment_i,
      O => \DLYSRESET_i_1__1_n_0\
    );
DLYSRESET_reg: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \DLYSRESET_i_1__1_n_0\,
      Q => gt2_rxdlysreset_in,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_2,
      Q => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_1,
      Q => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_0,
      Q => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      R => '0'
    );
phalign_state: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAEAAAEAAAEAA"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      I2 => phaligndone_prev,
      I3 => data_out,
      I4 => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      I5 => dlysresetdone_sync,
      O => phalign_state_n_0
    );
phaligndone_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_out,
      Q => phaligndone_prev,
      R => '0'
    );
sync_DLYSRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => dlysresetdone_sync,
      gt2_rxdlysresetdone_out => gt2_rxdlysresetdone_out
    );
sync_PHALIGNDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40
     port map (
      \FSM_onehot_phalign_state_reg[0]\ => sync_PHALIGNDONE_n_2,
      \FSM_onehot_phalign_state_reg[0]_0\ => \FSM_onehot_phalign_state_reg[0]_0\,
      \FSM_onehot_phalign_state_reg[1]\ => sync_PHALIGNDONE_n_1,
      \FSM_onehot_phalign_state_reg[1]_0\ => \FSM_onehot_phalign_state_reg[1]_0\,
      \FSM_onehot_phalign_state_reg[1]_1\ => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      \FSM_onehot_phalign_state_reg[2]\ => sync_PHALIGNDONE_n_0,
      \FSM_onehot_phalign_state_reg[2]_0\ => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      \FSM_onehot_phalign_state_reg[2]_1\ => phalign_state_n_0,
      \FSM_onehot_phalign_state_reg[2]_2\ => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      SYSCLK_IN => SYSCLK_IN,
      data_out => data_out,
      gt2_run_rx_phalignment_i => gt2_run_rx_phalignment_i,
      gt2_rxphaligndone_out => gt2_rxphaligndone_out,
      phaligndone_prev => phaligndone_prev
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 is
  port (
    gt3_rxdlysreset_in : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]_0\ : in STD_LOGIC;
    gt3_run_rx_phalignment_i : in STD_LOGIC;
    gt3_rxphaligndone_out : in STD_LOGIC;
    gt3_rxdlysresetdone_out : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 : entity is "mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 is
  signal \DLYSRESET_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_phalign_state_reg_n_0_[2]\ : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal dlysresetdone_sync : STD_LOGIC;
  signal phalign_state_n_0 : STD_LOGIC;
  signal phaligndone_prev : STD_LOGIC;
  signal sync_PHALIGNDONE_n_0 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_1 : STD_LOGIC;
  signal sync_PHALIGNDONE_n_2 : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[0]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[1]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_phalign_state_reg[2]\ : label is "wait_phrst_done:0010,count_phalign_done:0100,init:0001,phalign_done:1000";
begin
\DLYSRESET_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg[1]_0\,
      I2 => gt3_run_rx_phalignment_i,
      O => \DLYSRESET_i_1__2_n_0\
    );
DLYSRESET_reg: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \DLYSRESET_i_1__2_n_0\,
      Q => gt3_rxdlysreset_in,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_2,
      Q => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_1,
      Q => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_phalign_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_PHALIGNDONE_n_0,
      Q => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      R => '0'
    );
phalign_state: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAEAAAEAAAEAA"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      I2 => phaligndone_prev,
      I3 => data_out,
      I4 => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      I5 => dlysresetdone_sync,
      O => phalign_state_n_0
    );
phaligndone_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => data_out,
      Q => phaligndone_prev,
      R => '0'
    );
sync_DLYSRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => dlysresetdone_sync,
      gt3_rxdlysresetdone_out => gt3_rxdlysresetdone_out
    );
sync_PHALIGNDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25
     port map (
      \FSM_onehot_phalign_state_reg[0]\ => sync_PHALIGNDONE_n_2,
      \FSM_onehot_phalign_state_reg[0]_0\ => \FSM_onehot_phalign_state_reg[0]_0\,
      \FSM_onehot_phalign_state_reg[1]\ => sync_PHALIGNDONE_n_1,
      \FSM_onehot_phalign_state_reg[1]_0\ => \FSM_onehot_phalign_state_reg[1]_0\,
      \FSM_onehot_phalign_state_reg[1]_1\ => \FSM_onehot_phalign_state_reg_n_0_[0]\,
      \FSM_onehot_phalign_state_reg[2]\ => sync_PHALIGNDONE_n_0,
      \FSM_onehot_phalign_state_reg[2]_0\ => \FSM_onehot_phalign_state_reg_n_0_[2]\,
      \FSM_onehot_phalign_state_reg[2]_1\ => phalign_state_n_0,
      \FSM_onehot_phalign_state_reg[2]_2\ => \FSM_onehot_phalign_state_reg_n_0_[1]\,
      SYSCLK_IN => SYSCLK_IN,
      data_out => data_out,
      gt3_run_rx_phalignment_i => gt3_run_rx_phalignment_i,
      gt3_rxphaligndone_out => gt3_rxphaligndone_out,
      phaligndone_prev => phaligndone_prev
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_rxuserrdy_in : out STD_LOGIC;
    gt0_run_rx_phalignment_i : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_rx_cdrlocked_reg : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt0_rxusrclk_in : in STD_LOGIC;
    PHALIGNMENT_DONE_i_reg_0 : in STD_LOGIC;
    SOFT_RESET_RX_IN : in STD_LOGIC;
    \FSM_onehot_phalign_state_reg[1]\ : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    gt0_rx_cdrlocked_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_cdrlocked_reg_1 : in STD_LOGIC;
    gt0_rxresetdone_out : in STD_LOGIC;
    GT0_DATA_VALID_IN : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM : entity is "mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM is
  signal \FSM_sequential_rx_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_5_n_0\ : STD_LOGIC;
  signal PHALIGNMENT_DONE_i : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of PHALIGNMENT_DONE_i : signal is "true";
  signal RXUSERRDY_i_1_n_0 : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal check_tlock_max_i_1_n_0 : STD_LOGIC;
  signal check_tlock_max_reg_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^gt0_run_rx_phalignment_i\ : STD_LOGIC;
  signal \^gt0_rxuserrdy_in\ : STD_LOGIC;
  signal gtrxreset_i_i_1_n_0 : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__3_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__3_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__3_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__3_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__3_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal reset_time_out_i_3_n_0 : STD_LOGIC;
  signal reset_time_out_i_4_n_0 : STD_LOGIC;
  signal reset_time_out_reg_n_0 : STD_LOGIC;
  signal run_phase_alignment_int_i_1_n_0 : STD_LOGIC;
  signal run_phase_alignment_int_s2 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxresetdone_s2 : STD_LOGIC;
  signal rxresetdone_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_data_valid_n_3 : STD_LOGIC;
  signal sync_data_valid_n_4 : STD_LOGIC;
  signal sync_data_valid_n_5 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal time_out_100us_i_1_n_0 : STD_LOGIC;
  signal time_out_100us_i_2_n_0 : STD_LOGIC;
  signal time_out_100us_i_3_n_0 : STD_LOGIC;
  signal time_out_100us_reg_n_0 : STD_LOGIC;
  signal time_out_2ms_i_1_n_0 : STD_LOGIC;
  signal \time_out_2ms_i_2__3_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_6_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__3_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__3_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__3_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__3_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__3_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__3_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max : STD_LOGIC;
  signal time_tlock_max1 : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_1_n_0\ : STD_LOGIC;
  signal time_tlock_max1_carry_i_1_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_2_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_3_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_4_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_5_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_6_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_7_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_1 : STD_LOGIC;
  signal time_tlock_max1_carry_n_2 : STD_LOGIC;
  signal time_tlock_max1_carry_n_3 : STD_LOGIC;
  signal time_tlock_max_i_1_n_0 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__3_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__3_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__3_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_11\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_12\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_5\ : label is "soft_lutpair4";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute KEEP : string;
  attribute KEEP of PHALIGNMENT_DONE_i_reg : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of PHALIGNMENT_DONE_i_reg : label is "no";
  attribute SOFT_HLUTNM of gtrxreset_i_i_1 : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__3\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__3\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__3\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__3\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__3\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__3\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__3\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__3\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__3\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__3\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__3\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__3\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of reset_time_out_i_3 : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of reset_time_out_i_4 : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of time_out_100us_i_1 : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of time_out_100us_i_3 : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of time_out_2ms_i_1 : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \time_out_counter[0]_i_3__3\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__3\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__3\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__3\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__3\ : label is "soft_lutpair7";
begin
  SR(0) <= \^sr\(0);
  gt0_run_rx_phalignment_i <= \^gt0_run_rx_phalignment_i\;
  gt0_rxuserrdy_in <= \^gt0_rxuserrdy_in\;
\FSM_onehot_phalign_state[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^gt0_run_rx_phalignment_i\,
      I1 => \FSM_onehot_phalign_state_reg[1]\,
      O => SS(0)
    );
\FSM_sequential_rx_state[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22220030AAAA0000"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => reset_time_out_reg_n_0,
      I2 => time_tlock_max,
      I3 => rx_state(3),
      I4 => rx_state(1),
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[0]_i_2_n_0\
    );
\FSM_sequential_rx_state[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00070000"
    )
        port map (
      I0 => time_tlock_max,
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(1),
      I4 => rx_state(0),
      O => \FSM_sequential_rx_state[1]_i_2_n_0\
    );
\FSM_sequential_rx_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000008380000CCCC"
    )
        port map (
      I0 => \FSM_sequential_rx_state[2]_i_2_n_0\,
      I1 => rx_state(2),
      I2 => rx_state(1),
      I3 => time_out_2ms_reg_n_0,
      I4 => rx_state(3),
      I5 => rx_state(0),
      O => \rx_state__0\(2)
    );
\FSM_sequential_rx_state[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      O => \FSM_sequential_rx_state[2]_i_2_n_0\
    );
\FSM_sequential_rx_state[3]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80800080"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => time_out_2ms_reg_n_0,
      I4 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_10_n_0\
    );
\FSM_sequential_rx_state[3]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_11_n_0\
    );
\FSM_sequential_rx_state[3]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_12_n_0\
    );
\FSM_sequential_rx_state[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0000"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[1]\,
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => init_wait_done_reg_n_0,
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_3_n_0\
    );
\FSM_sequential_rx_state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055000300000000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_11_n_0\,
      I1 => \wait_time_cnt[6]_i_4__3_n_0\,
      I2 => wait_time_cnt_reg(6),
      I3 => rx_state(3),
      I4 => rx_state(0),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_4_n_0\
    );
\FSM_sequential_rx_state[3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_5_n_0\
    );
\FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(0),
      Q => rx_state(0),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(1),
      Q => rx_state(1),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(2),
      Q => rx_state(2),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(3),
      Q => rx_state(3),
      R => SOFT_RESET_RX_IN
    );
PHALIGNMENT_DONE_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => PHALIGNMENT_DONE_i_reg_0,
      Q => PHALIGNMENT_DONE_i,
      R => '0'
    );
RXUSERRDY_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF2000"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt0_rxuserrdy_in\,
      O => RXUSERRDY_i_1_n_0
    );
RXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => RXUSERRDY_i_1_n_0,
      Q => \^gt0_rxuserrdy_in\,
      R => SOFT_RESET_RX_IN
    );
check_tlock_max_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0200"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => check_tlock_max_reg_n_0,
      O => check_tlock_max_i_1_n_0
    );
check_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => check_tlock_max_i_1_n_0,
      Q => check_tlock_max_reg_n_0,
      R => SOFT_RESET_RX_IN
    );
gt0_rx_cdrlocked_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAABAAAA"
    )
        port map (
      I0 => \FSM_onehot_phalign_state_reg[1]\,
      I1 => gt0_rx_cdrlocked_reg_0,
      I2 => Q(0),
      I3 => Q(1),
      I4 => gt0_rx_cdrlocked_reg_1,
      I5 => \^sr\(0),
      O => gt0_rx_cdrlocked_reg
    );
gtrxreset_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0100"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^sr\(0),
      O => gtrxreset_i_i_1_n_0
    );
gtrxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gtrxreset_i_i_1_n_0,
      Q => \^sr\(0),
      R => SOFT_RESET_RX_IN
    );
\init_wait_count[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__3_n_0\
    );
\init_wait_count[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_count[0]_i_1__3_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__3_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__3_n_0\
    );
\init_wait_done_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__3_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_done_i_1__3_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__3_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__3_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__3_n_0\
    );
\mmcm_lock_count[7]_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__3_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__3_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__3_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
reset_time_out_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010301"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => \FSM_onehot_phalign_state_reg[1]\,
      I4 => rx_state(0),
      O => reset_time_out_i_3_n_0
    );
reset_time_out_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11FF5520"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => \FSM_onehot_phalign_state_reg[1]\,
      I3 => rx_state(3),
      I4 => rx_state(0),
      O => reset_time_out_i_4_n_0
    );
reset_time_out_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_data_valid_n_5,
      Q => reset_time_out_reg_n_0,
      S => SOFT_RESET_RX_IN
    );
run_phase_alignment_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt0_run_rx_phalignment_i\,
      O => run_phase_alignment_int_i_1_n_0
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => run_phase_alignment_int_i_1_n_0,
      Q => \^gt0_run_rx_phalignment_i\,
      R => SOFT_RESET_RX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => run_phase_alignment_int_s2,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => rx_fsm_reset_done_int_s2,
      Q => rx_fsm_reset_done_int_s3,
      R => '0'
    );
rxresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => rxresetdone_s2,
      Q => rxresetdone_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73
     port map (
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[2]_i_2_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => sync_data_valid_n_3,
      \FSM_sequential_rx_state_reg[1]\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[1]_0\ => sync_QPLLLOCK_n_1,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => rx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      rxresetdone_s3 => rxresetdone_s3
    );
sync_RXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => rxresetdone_s2,
      gt0_rxresetdone_out => gt0_rxresetdone_out
    );
sync_data_valid: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75
     port map (
      D(2) => \rx_state__0\(3),
      D(1 downto 0) => \rx_state__0\(1 downto 0),
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      DONT_RESET_ON_DATA_ERROR_IN_0 => sync_data_valid_n_3,
      E(0) => sync_data_valid_n_4,
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[0]_i_2_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_3_n_0\,
      \FSM_sequential_rx_state_reg[0]_1\ => \FSM_sequential_rx_state[3]_i_4_n_0\,
      \FSM_sequential_rx_state_reg[0]_2\ => \FSM_sequential_rx_state[3]_i_5_n_0\,
      \FSM_sequential_rx_state_reg[0]_3\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[0]_4\ => PHALIGNMENT_DONE_i_reg_0,
      \FSM_sequential_rx_state_reg[0]_5\ => time_out_100us_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_6\ => \FSM_sequential_rx_state[3]_i_12_n_0\,
      \FSM_sequential_rx_state_reg[1]\ => \FSM_sequential_rx_state[1]_i_2_n_0\,
      \FSM_sequential_rx_state_reg[3]\ => sync_data_valid_n_5,
      \FSM_sequential_rx_state_reg[3]_0\ => \FSM_sequential_rx_state[3]_i_10_n_0\,
      GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
      Q(2) => rx_state(3),
      Q(1 downto 0) => rx_state(1 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      reset_time_out_reg => reset_time_out_reg_n_0,
      reset_time_out_reg_0 => sync_QPLLLOCK_n_1,
      reset_time_out_reg_1 => reset_time_out_i_3_n_0,
      reset_time_out_reg_2 => reset_time_out_i_4_n_0,
      time_out_wait_bypass_s3 => time_out_wait_bypass_s3
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__3_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77
     port map (
      data_in => \^gt0_run_rx_phalignment_i\,
      data_out => run_phase_alignment_int_s2,
      gt0_rxusrclk_in => gt0_rxusrclk_in
    );
sync_rx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78
     port map (
      data_in => PHALIGNMENT_DONE_i,
      data_out => rx_fsm_reset_done_int_s2,
      gt0_rxusrclk_in => gt0_rxusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
time_out_100us_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_100us_reg_n_0,
      I1 => time_out_100us_i_2_n_0,
      I2 => \time_out_counter[0]_i_4_n_0\,
      I3 => reset_time_out_reg_n_0,
      O => time_out_100us_i_1_n_0
    );
time_out_100us_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => time_out_100us_i_3_n_0,
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(16),
      I3 => time_out_counter_reg(1),
      I4 => time_out_counter_reg(5),
      I5 => time_out_counter_reg(12),
      O => time_out_100us_i_2_n_0
    );
time_out_100us_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => time_out_100us_i_3_n_0
    );
time_out_100us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_100us_i_1_n_0,
      Q => time_out_100us_reg_n_0,
      R => '0'
    );
time_out_2ms_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AABA"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => time_out_counter_reg(1),
      I2 => \time_out_2ms_i_2__3_n_0\,
      I3 => \time_out_counter[0]_i_4_n_0\,
      I4 => reset_time_out_reg_n_0,
      O => time_out_2ms_i_1_n_0
    );
\time_out_2ms_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_2ms_i_2__3_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_2ms_i_1_n_0,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(1),
      I2 => \time_out_counter[0]_i_3__3_n_0\,
      I3 => \time_out_counter[0]_i_4_n_0\,
      I4 => time_out_counter_reg(14),
      I5 => time_out_counter_reg(13),
      O => time_out_counter
    );
\time_out_counter[0]_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(15),
      O => \time_out_counter[0]_i_3__3_n_0\
    );
\time_out_counter[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \time_out_counter[0]_i_6_n_0\,
      I1 => time_out_counter_reg(7),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(3),
      O => \time_out_counter[0]_i_4_n_0\
    );
\time_out_counter[0]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__3_n_0\
    );
\time_out_counter[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      I2 => time_out_counter_reg(10),
      I3 => time_out_counter_reg(11),
      I4 => time_out_counter_reg(4),
      I5 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_6_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__3_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[0]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__3_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__3_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__3_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__3_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__3_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__3_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__3_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__3_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__3_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__3_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__3_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__3_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__3_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__3_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__3_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__3_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__3_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__3_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__3_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__3_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__3_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__3_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__3_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__3_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__3_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__3_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__3_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__3_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__3_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__3_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__3_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__3_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__3_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__3_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__3_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__3_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__3_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__3_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__3_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__3_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__3_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__3_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__3_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__3_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__3_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__3_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__3_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__3_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__3_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__3_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__3_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__3_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out_reg_n_0
    );
\time_out_wait_bypass_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => rx_fsm_reset_done_int_s3,
      I2 => \wait_bypass_count[0]_i_4__3_n_0\,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__3_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_rxusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__3_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => time_tlock_max1_carry_n_0,
      CO(2) => time_tlock_max1_carry_n_1,
      CO(1) => time_tlock_max1_carry_n_2,
      CO(0) => time_tlock_max1_carry_n_3,
      CYINIT => '0',
      DI(3) => time_out_counter_reg(7),
      DI(2) => time_tlock_max1_carry_i_1_n_0,
      DI(1) => time_tlock_max1_carry_i_2_n_0,
      DI(0) => time_tlock_max1_carry_i_3_n_0,
      O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => time_tlock_max1_carry_i_4_n_0,
      S(2) => time_tlock_max1_carry_i_5_n_0,
      S(1) => time_tlock_max1_carry_i_6_n_0,
      S(0) => time_tlock_max1_carry_i_7_n_0
    );
\time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => time_tlock_max1_carry_n_0,
      CO(3) => \time_tlock_max1_carry__0_n_0\,
      CO(2) => \time_tlock_max1_carry__0_n_1\,
      CO(1) => \time_tlock_max1_carry__0_n_2\,
      CO(0) => \time_tlock_max1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \time_tlock_max1_carry__0_i_1_n_0\,
      DI(2) => time_out_counter_reg(13),
      DI(1) => \time_tlock_max1_carry__0_i_2_n_0\,
      DI(0) => \time_tlock_max1_carry__0_i_3_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \time_tlock_max1_carry__0_i_4_n_0\,
      S(2) => \time_tlock_max1_carry__0_i_5_n_0\,
      S(1) => \time_tlock_max1_carry__0_i_6_n_0\,
      S(0) => \time_tlock_max1_carry__0_i_7_n_0\
    );
\time_tlock_max1_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_tlock_max1_carry__0_i_1_n_0\
    );
\time_tlock_max1_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => \time_tlock_max1_carry__0_i_2_n_0\
    );
\time_tlock_max1_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_tlock_max1_carry__0_i_3_n_0\
    );
\time_tlock_max1_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(14),
      O => \time_tlock_max1_carry__0_i_4_n_0\
    );
\time_tlock_max1_carry__0_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      O => \time_tlock_max1_carry__0_i_5_n_0\
    );
\time_tlock_max1_carry__0_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(10),
      O => \time_tlock_max1_carry__0_i_6_n_0\
    );
\time_tlock_max1_carry__0_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(8),
      O => \time_tlock_max1_carry__0_i_7_n_0\
    );
\time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_tlock_max1_carry__0_n_0\,
      CO(3 downto 1) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => time_tlock_max1,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => time_out_counter_reg(16),
      O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \time_tlock_max1_carry__1_i_1_n_0\
    );
\time_tlock_max1_carry__1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(16),
      O => \time_tlock_max1_carry__1_i_1_n_0\
    );
time_tlock_max1_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => time_tlock_max1_carry_i_1_n_0
    );
time_tlock_max1_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(3),
      O => time_tlock_max1_carry_i_2_n_0
    );
time_tlock_max1_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => time_tlock_max1_carry_i_3_n_0
    );
time_tlock_max1_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(6),
      I1 => time_out_counter_reg(7),
      O => time_tlock_max1_carry_i_4_n_0
    );
time_tlock_max1_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(4),
      O => time_tlock_max1_carry_i_5_n_0
    );
time_tlock_max1_carry_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(2),
      O => time_tlock_max1_carry_i_6_n_0
    );
time_tlock_max1_carry_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(0),
      O => time_tlock_max1_carry_i_7_n_0
    );
time_tlock_max_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => time_tlock_max,
      I1 => time_tlock_max1,
      I2 => check_tlock_max_reg_n_0,
      I3 => reset_time_out_reg_n_0,
      O => time_tlock_max_i_1_n_0
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_tlock_max_i_1_n_0,
      Q => time_tlock_max,
      R => '0'
    );
\wait_bypass_count[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__3_n_0\,
      I1 => rx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__3_n_0\
    );
\wait_bypass_count[0]_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__3_n_0\,
      I1 => wait_bypass_count_reg(1),
      I2 => wait_bypass_count_reg(11),
      I3 => wait_bypass_count_reg(0),
      I4 => \wait_bypass_count[0]_i_7__3_n_0\,
      O => \wait_bypass_count[0]_i_4__3_n_0\
    );
\wait_bypass_count[0]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__3_n_0\
    );
\wait_bypass_count[0]_i_6__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(9),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(12),
      I3 => wait_bypass_count_reg(2),
      O => \wait_bypass_count[0]_i_6__3_n_0\
    );
\wait_bypass_count[0]_i_7__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(6),
      I4 => wait_bypass_count_reg(10),
      I5 => wait_bypass_count_reg(8),
      O => \wait_bypass_count[0]_i_7__3_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__3_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__3_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__3_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__3_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__3_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__3_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__3_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__3_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__3_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__3_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__3_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__3_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__3_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1__3_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1__3_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[12]_i_1__3_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(12)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__3_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__3_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__3_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__3_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__3_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__3_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__3_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__3_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__3_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__3_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__3_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__3_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__3_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__3_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__3_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__3_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__3_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__3_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__3_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__3_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__3_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__3_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__3_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__3_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__3_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__3_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(1),
      I2 => rx_state(0),
      O => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt[6]_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__3_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__3_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__3_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 is
  port (
    gt1_gtrxreset_in : out STD_LOGIC;
    gt1_rxuserrdy_in : out STD_LOGIC;
    gt1_run_rx_phalignment_i : out STD_LOGIC;
    run_phase_alignment_int_reg_0 : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt1_rxusrclk_in : in STD_LOGIC;
    PHALIGNMENT_DONE_i_reg_0 : in STD_LOGIC;
    SOFT_RESET_RX_IN : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    gt1_rxresetdone_out : in STD_LOGIC;
    GT1_DATA_VALID_IN : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 : entity is "mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 is
  signal \FSM_sequential_rx_state[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_10__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_11__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_12__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_5__0_n_0\ : STD_LOGIC;
  signal PHALIGNMENT_DONE_i : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of PHALIGNMENT_DONE_i : signal is "true";
  signal \RXUSERRDY_i_1__0_n_0\ : STD_LOGIC;
  signal \check_tlock_max_i_1__0_n_0\ : STD_LOGIC;
  signal check_tlock_max_reg_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^gt1_gtrxreset_in\ : STD_LOGIC;
  signal \^gt1_run_rx_phalignment_i\ : STD_LOGIC;
  signal \^gt1_rxuserrdy_in\ : STD_LOGIC;
  signal \gtrxreset_i_i_1__0_n_0\ : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__4_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__4_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__4_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__4_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__4_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \reset_time_out_i_3__0_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__0_n_0\ : STD_LOGIC;
  signal reset_time_out_reg_n_0 : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__0_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s2 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxresetdone_s2 : STD_LOGIC;
  signal rxresetdone_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_data_valid_n_3 : STD_LOGIC;
  signal sync_data_valid_n_4 : STD_LOGIC;
  signal sync_data_valid_n_5 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_100us_i_1__0_n_0\ : STD_LOGIC;
  signal \time_out_100us_i_2__0_n_0\ : STD_LOGIC;
  signal \time_out_100us_i_3__0_n_0\ : STD_LOGIC;
  signal time_out_100us_reg_n_0 : STD_LOGIC;
  signal \time_out_2ms_i_1__0_n_0\ : STD_LOGIC;
  signal \time_out_2ms_i_2__4_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__4_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__4_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_6__0_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__4_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__4_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__4_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__4_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__4_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__4_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max : STD_LOGIC;
  signal time_tlock_max1 : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_1__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_2__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_3__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_4__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_5__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_6__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_7__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_1__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_1__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_2__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_3__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_4__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_5__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_6__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_7__0_n_0\ : STD_LOGIC;
  signal time_tlock_max1_carry_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_1 : STD_LOGIC;
  signal time_tlock_max1_carry_n_2 : STD_LOGIC;
  signal time_tlock_max1_carry_n_3 : STD_LOGIC;
  signal \time_tlock_max_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__4_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__4_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__4_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__4_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__4_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__4_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2__0\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10__0\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_11__0\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_12__0\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_5__0\ : label is "soft_lutpair38";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute KEEP : string;
  attribute KEEP of PHALIGNMENT_DONE_i_reg : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of PHALIGNMENT_DONE_i_reg : label is "no";
  attribute SOFT_HLUTNM of \RXUSERRDY_i_1__0\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__4\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__4\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__4\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__4\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__4\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__4\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__4\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__4\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__4\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__4\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__4\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__4\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \reset_time_out_i_3__0\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \reset_time_out_i_4__0\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \time_out_100us_i_1__0\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \time_out_100us_i_3__0\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \time_out_2ms_i_1__0\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \time_out_counter[0]_i_3__4\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__4\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__4\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__4\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__4\ : label is "soft_lutpair42";
begin
  gt1_gtrxreset_in <= \^gt1_gtrxreset_in\;
  gt1_run_rx_phalignment_i <= \^gt1_run_rx_phalignment_i\;
  gt1_rxuserrdy_in <= \^gt1_rxuserrdy_in\;
\FSM_onehot_phalign_state[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^gt1_run_rx_phalignment_i\,
      I1 => reset_time_out_reg_0,
      O => run_phase_alignment_int_reg_0
    );
\FSM_sequential_rx_state[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22220030AAAA0000"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => reset_time_out_reg_n_0,
      I2 => time_tlock_max,
      I3 => rx_state(3),
      I4 => rx_state(1),
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[0]_i_2__0_n_0\
    );
\FSM_sequential_rx_state[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00070000"
    )
        port map (
      I0 => time_tlock_max,
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(1),
      I4 => rx_state(0),
      O => \FSM_sequential_rx_state[1]_i_2__0_n_0\
    );
\FSM_sequential_rx_state[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000008380000CCCC"
    )
        port map (
      I0 => \FSM_sequential_rx_state[2]_i_2__0_n_0\,
      I1 => rx_state(2),
      I2 => rx_state(1),
      I3 => time_out_2ms_reg_n_0,
      I4 => rx_state(3),
      I5 => rx_state(0),
      O => \rx_state__0\(2)
    );
\FSM_sequential_rx_state[2]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      O => \FSM_sequential_rx_state[2]_i_2__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80800080"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => time_out_2ms_reg_n_0,
      I4 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_10__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_11__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_11__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_12__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_12__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0000"
    )
        port map (
      I0 => reset_time_out_reg_0,
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => init_wait_done_reg_n_0,
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_3__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055000300000000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_11__0_n_0\,
      I1 => \wait_time_cnt[6]_i_4__4_n_0\,
      I2 => wait_time_cnt_reg(6),
      I3 => rx_state(3),
      I4 => rx_state(0),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_4__0_n_0\
    );
\FSM_sequential_rx_state[3]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_5__0_n_0\
    );
\FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(0),
      Q => rx_state(0),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(1),
      Q => rx_state(1),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(2),
      Q => rx_state(2),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(3),
      Q => rx_state(3),
      R => SOFT_RESET_RX_IN
    );
PHALIGNMENT_DONE_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => PHALIGNMENT_DONE_i_reg_0,
      Q => PHALIGNMENT_DONE_i,
      R => '0'
    );
\RXUSERRDY_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF2000"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt1_rxuserrdy_in\,
      O => \RXUSERRDY_i_1__0_n_0\
    );
RXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \RXUSERRDY_i_1__0_n_0\,
      Q => \^gt1_rxuserrdy_in\,
      R => SOFT_RESET_RX_IN
    );
\check_tlock_max_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0200"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => check_tlock_max_reg_n_0,
      O => \check_tlock_max_i_1__0_n_0\
    );
check_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \check_tlock_max_i_1__0_n_0\,
      Q => check_tlock_max_reg_n_0,
      R => SOFT_RESET_RX_IN
    );
\gtrxreset_i_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0100"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt1_gtrxreset_in\,
      O => \gtrxreset_i_i_1__0_n_0\
    );
gtrxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \gtrxreset_i_i_1__0_n_0\,
      Q => \^gt1_gtrxreset_in\,
      R => SOFT_RESET_RX_IN
    );
\init_wait_count[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__4_n_0\
    );
\init_wait_count[1]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_count[0]_i_1__4_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__4_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__4_n_0\
    );
\init_wait_done_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__4_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_done_i_1__4_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__4_n_0\
    );
\mmcm_lock_count[7]_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__4_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__4_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__4_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
\reset_time_out_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010301"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => reset_time_out_reg_0,
      I4 => rx_state(0),
      O => \reset_time_out_i_3__0_n_0\
    );
\reset_time_out_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11FF5520"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => reset_time_out_reg_0,
      I3 => rx_state(3),
      I4 => rx_state(0),
      O => \reset_time_out_i_4__0_n_0\
    );
reset_time_out_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_data_valid_n_5,
      Q => reset_time_out_reg_n_0,
      S => SOFT_RESET_RX_IN
    );
\run_phase_alignment_int_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt1_run_rx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__0_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__0_n_0\,
      Q => \^gt1_run_rx_phalignment_i\,
      R => SOFT_RESET_RX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => run_phase_alignment_int_s2,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => rx_fsm_reset_done_int_s2,
      Q => rx_fsm_reset_done_int_s3,
      R => '0'
    );
rxresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => rxresetdone_s2,
      Q => rxresetdone_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47
     port map (
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[2]_i_2__0_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => sync_data_valid_n_3,
      \FSM_sequential_rx_state_reg[1]\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[1]_0\ => sync_QPLLLOCK_n_1,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => rx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      rxresetdone_s3 => rxresetdone_s3
    );
sync_RXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => rxresetdone_s2,
      gt1_rxresetdone_out => gt1_rxresetdone_out
    );
sync_data_valid: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49
     port map (
      D(2) => \rx_state__0\(3),
      D(1 downto 0) => \rx_state__0\(1 downto 0),
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      E(0) => sync_data_valid_n_4,
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[0]_i_2__0_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_3__0_n_0\,
      \FSM_sequential_rx_state_reg[0]_1\ => \FSM_sequential_rx_state[3]_i_4__0_n_0\,
      \FSM_sequential_rx_state_reg[0]_2\ => \FSM_sequential_rx_state[3]_i_5__0_n_0\,
      \FSM_sequential_rx_state_reg[0]_3\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[0]_4\ => PHALIGNMENT_DONE_i_reg_0,
      \FSM_sequential_rx_state_reg[0]_5\ => time_out_100us_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_6\ => \FSM_sequential_rx_state[3]_i_12__0_n_0\,
      \FSM_sequential_rx_state_reg[1]\ => \FSM_sequential_rx_state[1]_i_2__0_n_0\,
      \FSM_sequential_rx_state_reg[3]\ => sync_data_valid_n_5,
      \FSM_sequential_rx_state_reg[3]_0\ => \FSM_sequential_rx_state[3]_i_10__0_n_0\,
      GT1_DATA_VALID_IN => GT1_DATA_VALID_IN,
      Q(2) => rx_state(3),
      Q(1 downto 0) => rx_state(1 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      reset_time_out_reg => reset_time_out_reg_n_0,
      reset_time_out_reg_0 => sync_QPLLLOCK_n_1,
      reset_time_out_reg_1 => \reset_time_out_i_3__0_n_0\,
      reset_time_out_reg_2 => \reset_time_out_i_4__0_n_0\,
      time_out_100us_reg => sync_data_valid_n_3,
      time_out_wait_bypass_s3 => time_out_wait_bypass_s3
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__4_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51
     port map (
      data_in => \^gt1_run_rx_phalignment_i\,
      data_out => run_phase_alignment_int_s2,
      gt1_rxusrclk_in => gt1_rxusrclk_in
    );
sync_rx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52
     port map (
      data_in => PHALIGNMENT_DONE_i,
      data_out => rx_fsm_reset_done_int_s2,
      gt1_rxusrclk_in => gt1_rxusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
\time_out_100us_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_100us_reg_n_0,
      I1 => \time_out_100us_i_2__0_n_0\,
      I2 => \time_out_counter[0]_i_4__0_n_0\,
      I3 => reset_time_out_reg_n_0,
      O => \time_out_100us_i_1__0_n_0\
    );
\time_out_100us_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \time_out_100us_i_3__0_n_0\,
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(16),
      I3 => time_out_counter_reg(1),
      I4 => time_out_counter_reg(5),
      I5 => time_out_counter_reg(12),
      O => \time_out_100us_i_2__0_n_0\
    );
\time_out_100us_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_out_100us_i_3__0_n_0\
    );
time_out_100us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_100us_i_1__0_n_0\,
      Q => time_out_100us_reg_n_0,
      R => '0'
    );
\time_out_2ms_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AABA"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => time_out_counter_reg(1),
      I2 => \time_out_2ms_i_2__4_n_0\,
      I3 => \time_out_counter[0]_i_4__0_n_0\,
      I4 => reset_time_out_reg_n_0,
      O => \time_out_2ms_i_1__0_n_0\
    );
\time_out_2ms_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_2ms_i_2__4_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__0_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(1),
      I2 => \time_out_counter[0]_i_3__4_n_0\,
      I3 => \time_out_counter[0]_i_4__0_n_0\,
      I4 => time_out_counter_reg(14),
      I5 => time_out_counter_reg(13),
      O => time_out_counter
    );
\time_out_counter[0]_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(15),
      O => \time_out_counter[0]_i_3__4_n_0\
    );
\time_out_counter[0]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \time_out_counter[0]_i_6__0_n_0\,
      I1 => time_out_counter_reg(7),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(3),
      O => \time_out_counter[0]_i_4__0_n_0\
    );
\time_out_counter[0]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__4_n_0\
    );
\time_out_counter[0]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      I2 => time_out_counter_reg(10),
      I3 => time_out_counter_reg(11),
      I4 => time_out_counter_reg(4),
      I5 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_6__0_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__4_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[0]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__4_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__4_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__4_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__4_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__4_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__4_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__4_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__4_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__4_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__4_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__4_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__4_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__4_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__4_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__4_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__4_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__4_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__4_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__4_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__4_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__4_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__4_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__4_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__4_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__4_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__4_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__4_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__4_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__4_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__4_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__4_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__4_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__4_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__4_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__4_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__4_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__4_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__4_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__4_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__4_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__4_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__4_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__4_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__4_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__4_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__4_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__4_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__4_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__4_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__4_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__4_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out_reg_n_0
    );
\time_out_wait_bypass_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => rx_fsm_reset_done_int_s3,
      I2 => \wait_bypass_count[0]_i_4__4_n_0\,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__4_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_rxusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__4_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => time_tlock_max1_carry_n_0,
      CO(2) => time_tlock_max1_carry_n_1,
      CO(1) => time_tlock_max1_carry_n_2,
      CO(0) => time_tlock_max1_carry_n_3,
      CYINIT => '0',
      DI(3) => time_out_counter_reg(7),
      DI(2) => \time_tlock_max1_carry_i_1__0_n_0\,
      DI(1) => \time_tlock_max1_carry_i_2__0_n_0\,
      DI(0) => \time_tlock_max1_carry_i_3__0_n_0\,
      O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \time_tlock_max1_carry_i_4__0_n_0\,
      S(2) => \time_tlock_max1_carry_i_5__0_n_0\,
      S(1) => \time_tlock_max1_carry_i_6__0_n_0\,
      S(0) => \time_tlock_max1_carry_i_7__0_n_0\
    );
\time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => time_tlock_max1_carry_n_0,
      CO(3) => \time_tlock_max1_carry__0_n_0\,
      CO(2) => \time_tlock_max1_carry__0_n_1\,
      CO(1) => \time_tlock_max1_carry__0_n_2\,
      CO(0) => \time_tlock_max1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \time_tlock_max1_carry__0_i_1__0_n_0\,
      DI(2) => time_out_counter_reg(13),
      DI(1) => \time_tlock_max1_carry__0_i_2__0_n_0\,
      DI(0) => \time_tlock_max1_carry__0_i_3__0_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \time_tlock_max1_carry__0_i_4__0_n_0\,
      S(2) => \time_tlock_max1_carry__0_i_5__0_n_0\,
      S(1) => \time_tlock_max1_carry__0_i_6__0_n_0\,
      S(0) => \time_tlock_max1_carry__0_i_7__0_n_0\
    );
\time_tlock_max1_carry__0_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_tlock_max1_carry__0_i_1__0_n_0\
    );
\time_tlock_max1_carry__0_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => \time_tlock_max1_carry__0_i_2__0_n_0\
    );
\time_tlock_max1_carry__0_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_tlock_max1_carry__0_i_3__0_n_0\
    );
\time_tlock_max1_carry__0_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(14),
      O => \time_tlock_max1_carry__0_i_4__0_n_0\
    );
\time_tlock_max1_carry__0_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      O => \time_tlock_max1_carry__0_i_5__0_n_0\
    );
\time_tlock_max1_carry__0_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(10),
      O => \time_tlock_max1_carry__0_i_6__0_n_0\
    );
\time_tlock_max1_carry__0_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(8),
      O => \time_tlock_max1_carry__0_i_7__0_n_0\
    );
\time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_tlock_max1_carry__0_n_0\,
      CO(3 downto 1) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => time_tlock_max1,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => time_out_counter_reg(16),
      O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \time_tlock_max1_carry__1_i_1__0_n_0\
    );
\time_tlock_max1_carry__1_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(16),
      O => \time_tlock_max1_carry__1_i_1__0_n_0\
    );
\time_tlock_max1_carry_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => \time_tlock_max1_carry_i_1__0_n_0\
    );
\time_tlock_max1_carry_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(3),
      O => \time_tlock_max1_carry_i_2__0_n_0\
    );
\time_tlock_max1_carry_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => \time_tlock_max1_carry_i_3__0_n_0\
    );
\time_tlock_max1_carry_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(6),
      I1 => time_out_counter_reg(7),
      O => \time_tlock_max1_carry_i_4__0_n_0\
    );
\time_tlock_max1_carry_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(4),
      O => \time_tlock_max1_carry_i_5__0_n_0\
    );
\time_tlock_max1_carry_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(2),
      O => \time_tlock_max1_carry_i_6__0_n_0\
    );
\time_tlock_max1_carry_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(0),
      O => \time_tlock_max1_carry_i_7__0_n_0\
    );
\time_tlock_max_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => time_tlock_max,
      I1 => time_tlock_max1,
      I2 => check_tlock_max_reg_n_0,
      I3 => reset_time_out_reg_n_0,
      O => \time_tlock_max_i_1__0_n_0\
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__0_n_0\,
      Q => time_tlock_max,
      R => '0'
    );
\wait_bypass_count[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__4_n_0\,
      I1 => rx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__4_n_0\
    );
\wait_bypass_count[0]_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__4_n_0\,
      I1 => wait_bypass_count_reg(1),
      I2 => wait_bypass_count_reg(11),
      I3 => wait_bypass_count_reg(0),
      I4 => \wait_bypass_count[0]_i_7__4_n_0\,
      O => \wait_bypass_count[0]_i_4__4_n_0\
    );
\wait_bypass_count[0]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__4_n_0\
    );
\wait_bypass_count[0]_i_6__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(9),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(12),
      I3 => wait_bypass_count_reg(2),
      O => \wait_bypass_count[0]_i_6__4_n_0\
    );
\wait_bypass_count[0]_i_7__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(6),
      I4 => wait_bypass_count_reg(10),
      I5 => wait_bypass_count_reg(8),
      O => \wait_bypass_count[0]_i_7__4_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__4_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__4_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__4_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__4_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__4_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__4_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__4_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__4_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__4_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__4_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__4_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__4_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__4_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1__4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1__4_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[12]_i_1__4_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(12)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__4_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__4_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__4_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__4_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__4_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__4_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__4_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__4_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__4_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__4_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__4_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__4_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__4_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__4_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__4_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__4_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__4_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__4_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__4_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__4_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__4_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__4_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__4_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__4_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__4_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__4_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(1),
      I2 => rx_state(0),
      O => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt[6]_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__4_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__4_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__4_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__0_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__0_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 is
  port (
    gt2_gtrxreset_in : out STD_LOGIC;
    gt2_rxuserrdy_in : out STD_LOGIC;
    gt2_run_rx_phalignment_i : out STD_LOGIC;
    run_phase_alignment_int_reg_0 : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt2_rxusrclk_in : in STD_LOGIC;
    PHALIGNMENT_DONE_i_reg_0 : in STD_LOGIC;
    SOFT_RESET_RX_IN : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    gt2_rxresetdone_out : in STD_LOGIC;
    GT2_DATA_VALID_IN : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 : entity is "mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 is
  signal \FSM_sequential_rx_state[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_10__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_11__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_12__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_5__1_n_0\ : STD_LOGIC;
  signal PHALIGNMENT_DONE_i : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of PHALIGNMENT_DONE_i : signal is "true";
  signal \RXUSERRDY_i_1__1_n_0\ : STD_LOGIC;
  signal \check_tlock_max_i_1__1_n_0\ : STD_LOGIC;
  signal check_tlock_max_reg_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^gt2_gtrxreset_in\ : STD_LOGIC;
  signal \^gt2_run_rx_phalignment_i\ : STD_LOGIC;
  signal \^gt2_rxuserrdy_in\ : STD_LOGIC;
  signal \gtrxreset_i_i_1__1_n_0\ : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__5_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__5_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__5_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__5_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__5_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \reset_time_out_i_3__1_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__1_n_0\ : STD_LOGIC;
  signal reset_time_out_reg_n_0 : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__1_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s2 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxresetdone_s2 : STD_LOGIC;
  signal rxresetdone_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_data_valid_n_3 : STD_LOGIC;
  signal sync_data_valid_n_4 : STD_LOGIC;
  signal sync_data_valid_n_5 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_100us_i_1__1_n_0\ : STD_LOGIC;
  signal \time_out_100us_i_2__1_n_0\ : STD_LOGIC;
  signal \time_out_100us_i_3__1_n_0\ : STD_LOGIC;
  signal time_out_100us_reg_n_0 : STD_LOGIC;
  signal \time_out_2ms_i_1__1_n_0\ : STD_LOGIC;
  signal \time_out_2ms_i_2__5_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__5_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_6__1_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__5_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__5_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__5_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__5_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__5_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__5_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max : STD_LOGIC;
  signal time_tlock_max1 : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_1__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_2__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_3__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_4__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_5__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_6__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_7__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_1__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_1__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_2__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_3__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_4__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_5__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_6__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_7__1_n_0\ : STD_LOGIC;
  signal time_tlock_max1_carry_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_1 : STD_LOGIC;
  signal time_tlock_max1_carry_n_2 : STD_LOGIC;
  signal time_tlock_max1_carry_n_3 : STD_LOGIC;
  signal \time_tlock_max_i_1__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__5_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__5_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__5_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__5_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__5_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__5_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2__1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10__1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_11__1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_12__1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_5__1\ : label is "soft_lutpair67";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute KEEP : string;
  attribute KEEP of PHALIGNMENT_DONE_i_reg : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of PHALIGNMENT_DONE_i_reg : label is "no";
  attribute SOFT_HLUTNM of \RXUSERRDY_i_1__1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__5\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__5\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__5\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__5\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__5\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__5\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__5\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__5\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__5\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__5\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__5\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__5\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \reset_time_out_i_3__1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \reset_time_out_i_4__1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \time_out_100us_i_1__1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \time_out_100us_i_3__1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \time_out_2ms_i_1__1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \time_out_counter[0]_i_3__5\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__5\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__5\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__5\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__5\ : label is "soft_lutpair71";
begin
  gt2_gtrxreset_in <= \^gt2_gtrxreset_in\;
  gt2_run_rx_phalignment_i <= \^gt2_run_rx_phalignment_i\;
  gt2_rxuserrdy_in <= \^gt2_rxuserrdy_in\;
\FSM_onehot_phalign_state[0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^gt2_run_rx_phalignment_i\,
      I1 => reset_time_out_reg_0,
      O => run_phase_alignment_int_reg_0
    );
\FSM_sequential_rx_state[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22220030AAAA0000"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => reset_time_out_reg_n_0,
      I2 => time_tlock_max,
      I3 => rx_state(3),
      I4 => rx_state(1),
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[0]_i_2__1_n_0\
    );
\FSM_sequential_rx_state[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00070000"
    )
        port map (
      I0 => time_tlock_max,
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(1),
      I4 => rx_state(0),
      O => \FSM_sequential_rx_state[1]_i_2__1_n_0\
    );
\FSM_sequential_rx_state[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000008380000CCCC"
    )
        port map (
      I0 => \FSM_sequential_rx_state[2]_i_2__1_n_0\,
      I1 => rx_state(2),
      I2 => rx_state(1),
      I3 => time_out_2ms_reg_n_0,
      I4 => rx_state(3),
      I5 => rx_state(0),
      O => \rx_state__0\(2)
    );
\FSM_sequential_rx_state[2]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      O => \FSM_sequential_rx_state[2]_i_2__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_10__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80800080"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => time_out_2ms_reg_n_0,
      I4 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_10__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_11__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_11__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_12__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_12__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0000"
    )
        port map (
      I0 => reset_time_out_reg_0,
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => init_wait_done_reg_n_0,
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_3__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055000300000000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_11__1_n_0\,
      I1 => \wait_time_cnt[6]_i_4__5_n_0\,
      I2 => wait_time_cnt_reg(6),
      I3 => rx_state(3),
      I4 => rx_state(0),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_4__1_n_0\
    );
\FSM_sequential_rx_state[3]_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_5__1_n_0\
    );
\FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(0),
      Q => rx_state(0),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(1),
      Q => rx_state(1),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(2),
      Q => rx_state(2),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(3),
      Q => rx_state(3),
      R => SOFT_RESET_RX_IN
    );
PHALIGNMENT_DONE_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => PHALIGNMENT_DONE_i_reg_0,
      Q => PHALIGNMENT_DONE_i,
      R => '0'
    );
\RXUSERRDY_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF2000"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt2_rxuserrdy_in\,
      O => \RXUSERRDY_i_1__1_n_0\
    );
RXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \RXUSERRDY_i_1__1_n_0\,
      Q => \^gt2_rxuserrdy_in\,
      R => SOFT_RESET_RX_IN
    );
\check_tlock_max_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0200"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => check_tlock_max_reg_n_0,
      O => \check_tlock_max_i_1__1_n_0\
    );
check_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \check_tlock_max_i_1__1_n_0\,
      Q => check_tlock_max_reg_n_0,
      R => SOFT_RESET_RX_IN
    );
\gtrxreset_i_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0100"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt2_gtrxreset_in\,
      O => \gtrxreset_i_i_1__1_n_0\
    );
gtrxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \gtrxreset_i_i_1__1_n_0\,
      Q => \^gt2_gtrxreset_in\,
      R => SOFT_RESET_RX_IN
    );
\init_wait_count[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__5_n_0\
    );
\init_wait_count[1]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_count[0]_i_1__5_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__5_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__5_n_0\
    );
\init_wait_done_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__5_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_done_i_1__5_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__5_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__5_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__5_n_0\
    );
\mmcm_lock_count[7]_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__5_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__5_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__5_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
\reset_time_out_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010301"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => reset_time_out_reg_0,
      I4 => rx_state(0),
      O => \reset_time_out_i_3__1_n_0\
    );
\reset_time_out_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11FF5520"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => reset_time_out_reg_0,
      I3 => rx_state(3),
      I4 => rx_state(0),
      O => \reset_time_out_i_4__1_n_0\
    );
reset_time_out_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_data_valid_n_5,
      Q => reset_time_out_reg_n_0,
      S => SOFT_RESET_RX_IN
    );
\run_phase_alignment_int_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt2_run_rx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__1_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__1_n_0\,
      Q => \^gt2_run_rx_phalignment_i\,
      R => SOFT_RESET_RX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => run_phase_alignment_int_s2,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => rx_fsm_reset_done_int_s2,
      Q => rx_fsm_reset_done_int_s3,
      R => '0'
    );
rxresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => rxresetdone_s2,
      Q => rxresetdone_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32
     port map (
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[2]_i_2__1_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => sync_data_valid_n_3,
      \FSM_sequential_rx_state_reg[1]\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[1]_0\ => sync_QPLLLOCK_n_1,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => rx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      rxresetdone_s3 => rxresetdone_s3
    );
sync_RXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => rxresetdone_s2,
      gt2_rxresetdone_out => gt2_rxresetdone_out
    );
sync_data_valid: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34
     port map (
      D(2) => \rx_state__0\(3),
      D(1 downto 0) => \rx_state__0\(1 downto 0),
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      E(0) => sync_data_valid_n_4,
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[0]_i_2__1_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_3__1_n_0\,
      \FSM_sequential_rx_state_reg[0]_1\ => \FSM_sequential_rx_state[3]_i_4__1_n_0\,
      \FSM_sequential_rx_state_reg[0]_2\ => \FSM_sequential_rx_state[3]_i_5__1_n_0\,
      \FSM_sequential_rx_state_reg[0]_3\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[0]_4\ => PHALIGNMENT_DONE_i_reg_0,
      \FSM_sequential_rx_state_reg[0]_5\ => time_out_100us_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_6\ => \FSM_sequential_rx_state[3]_i_12__1_n_0\,
      \FSM_sequential_rx_state_reg[1]\ => \FSM_sequential_rx_state[1]_i_2__1_n_0\,
      \FSM_sequential_rx_state_reg[3]\ => sync_data_valid_n_5,
      \FSM_sequential_rx_state_reg[3]_0\ => \FSM_sequential_rx_state[3]_i_10__1_n_0\,
      GT2_DATA_VALID_IN => GT2_DATA_VALID_IN,
      Q(2) => rx_state(3),
      Q(1 downto 0) => rx_state(1 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      reset_time_out_reg => reset_time_out_reg_n_0,
      reset_time_out_reg_0 => sync_QPLLLOCK_n_1,
      reset_time_out_reg_1 => \reset_time_out_i_3__1_n_0\,
      reset_time_out_reg_2 => \reset_time_out_i_4__1_n_0\,
      time_out_100us_reg => sync_data_valid_n_3,
      time_out_wait_bypass_s3 => time_out_wait_bypass_s3
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__5_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36
     port map (
      data_in => \^gt2_run_rx_phalignment_i\,
      data_out => run_phase_alignment_int_s2,
      gt2_rxusrclk_in => gt2_rxusrclk_in
    );
sync_rx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37
     port map (
      data_in => PHALIGNMENT_DONE_i,
      data_out => rx_fsm_reset_done_int_s2,
      gt2_rxusrclk_in => gt2_rxusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
\time_out_100us_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_100us_reg_n_0,
      I1 => \time_out_100us_i_2__1_n_0\,
      I2 => \time_out_counter[0]_i_4__1_n_0\,
      I3 => reset_time_out_reg_n_0,
      O => \time_out_100us_i_1__1_n_0\
    );
\time_out_100us_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \time_out_100us_i_3__1_n_0\,
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(16),
      I3 => time_out_counter_reg(1),
      I4 => time_out_counter_reg(5),
      I5 => time_out_counter_reg(12),
      O => \time_out_100us_i_2__1_n_0\
    );
\time_out_100us_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_out_100us_i_3__1_n_0\
    );
time_out_100us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_100us_i_1__1_n_0\,
      Q => time_out_100us_reg_n_0,
      R => '0'
    );
\time_out_2ms_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AABA"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => time_out_counter_reg(1),
      I2 => \time_out_2ms_i_2__5_n_0\,
      I3 => \time_out_counter[0]_i_4__1_n_0\,
      I4 => reset_time_out_reg_n_0,
      O => \time_out_2ms_i_1__1_n_0\
    );
\time_out_2ms_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_2ms_i_2__5_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__1_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(1),
      I2 => \time_out_counter[0]_i_3__5_n_0\,
      I3 => \time_out_counter[0]_i_4__1_n_0\,
      I4 => time_out_counter_reg(14),
      I5 => time_out_counter_reg(13),
      O => time_out_counter
    );
\time_out_counter[0]_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(15),
      O => \time_out_counter[0]_i_3__5_n_0\
    );
\time_out_counter[0]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \time_out_counter[0]_i_6__1_n_0\,
      I1 => time_out_counter_reg(7),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(3),
      O => \time_out_counter[0]_i_4__1_n_0\
    );
\time_out_counter[0]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__5_n_0\
    );
\time_out_counter[0]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      I2 => time_out_counter_reg(10),
      I3 => time_out_counter_reg(11),
      I4 => time_out_counter_reg(4),
      I5 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_6__1_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__5_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[0]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__5_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__5_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__5_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__5_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__5_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__5_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__5_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__5_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__5_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__5_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__5_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__5_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__5_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__5_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__5_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__5_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__5_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__5_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__5_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__5_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__5_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__5_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__5_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__5_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__5_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__5_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__5_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__5_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__5_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__5_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__5_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__5_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__5_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__5_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__5_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__5_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__5_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__5_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__5_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__5_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__5_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__5_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__5_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__5_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__5_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__5_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__5_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__5_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__5_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__5_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__5_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__5_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out_reg_n_0
    );
\time_out_wait_bypass_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => rx_fsm_reset_done_int_s3,
      I2 => \wait_bypass_count[0]_i_4__5_n_0\,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__5_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_rxusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__5_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => time_tlock_max1_carry_n_0,
      CO(2) => time_tlock_max1_carry_n_1,
      CO(1) => time_tlock_max1_carry_n_2,
      CO(0) => time_tlock_max1_carry_n_3,
      CYINIT => '0',
      DI(3) => time_out_counter_reg(7),
      DI(2) => \time_tlock_max1_carry_i_1__1_n_0\,
      DI(1) => \time_tlock_max1_carry_i_2__1_n_0\,
      DI(0) => \time_tlock_max1_carry_i_3__1_n_0\,
      O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \time_tlock_max1_carry_i_4__1_n_0\,
      S(2) => \time_tlock_max1_carry_i_5__1_n_0\,
      S(1) => \time_tlock_max1_carry_i_6__1_n_0\,
      S(0) => \time_tlock_max1_carry_i_7__1_n_0\
    );
\time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => time_tlock_max1_carry_n_0,
      CO(3) => \time_tlock_max1_carry__0_n_0\,
      CO(2) => \time_tlock_max1_carry__0_n_1\,
      CO(1) => \time_tlock_max1_carry__0_n_2\,
      CO(0) => \time_tlock_max1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \time_tlock_max1_carry__0_i_1__1_n_0\,
      DI(2) => time_out_counter_reg(13),
      DI(1) => \time_tlock_max1_carry__0_i_2__1_n_0\,
      DI(0) => \time_tlock_max1_carry__0_i_3__1_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \time_tlock_max1_carry__0_i_4__1_n_0\,
      S(2) => \time_tlock_max1_carry__0_i_5__1_n_0\,
      S(1) => \time_tlock_max1_carry__0_i_6__1_n_0\,
      S(0) => \time_tlock_max1_carry__0_i_7__1_n_0\
    );
\time_tlock_max1_carry__0_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_tlock_max1_carry__0_i_1__1_n_0\
    );
\time_tlock_max1_carry__0_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => \time_tlock_max1_carry__0_i_2__1_n_0\
    );
\time_tlock_max1_carry__0_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_tlock_max1_carry__0_i_3__1_n_0\
    );
\time_tlock_max1_carry__0_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(14),
      O => \time_tlock_max1_carry__0_i_4__1_n_0\
    );
\time_tlock_max1_carry__0_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      O => \time_tlock_max1_carry__0_i_5__1_n_0\
    );
\time_tlock_max1_carry__0_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(10),
      O => \time_tlock_max1_carry__0_i_6__1_n_0\
    );
\time_tlock_max1_carry__0_i_7__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(8),
      O => \time_tlock_max1_carry__0_i_7__1_n_0\
    );
\time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_tlock_max1_carry__0_n_0\,
      CO(3 downto 1) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => time_tlock_max1,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => time_out_counter_reg(16),
      O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \time_tlock_max1_carry__1_i_1__1_n_0\
    );
\time_tlock_max1_carry__1_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(16),
      O => \time_tlock_max1_carry__1_i_1__1_n_0\
    );
\time_tlock_max1_carry_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => \time_tlock_max1_carry_i_1__1_n_0\
    );
\time_tlock_max1_carry_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(3),
      O => \time_tlock_max1_carry_i_2__1_n_0\
    );
\time_tlock_max1_carry_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => \time_tlock_max1_carry_i_3__1_n_0\
    );
\time_tlock_max1_carry_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(6),
      I1 => time_out_counter_reg(7),
      O => \time_tlock_max1_carry_i_4__1_n_0\
    );
\time_tlock_max1_carry_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(4),
      O => \time_tlock_max1_carry_i_5__1_n_0\
    );
\time_tlock_max1_carry_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(2),
      O => \time_tlock_max1_carry_i_6__1_n_0\
    );
\time_tlock_max1_carry_i_7__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(0),
      O => \time_tlock_max1_carry_i_7__1_n_0\
    );
\time_tlock_max_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => time_tlock_max,
      I1 => time_tlock_max1,
      I2 => check_tlock_max_reg_n_0,
      I3 => reset_time_out_reg_n_0,
      O => \time_tlock_max_i_1__1_n_0\
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__1_n_0\,
      Q => time_tlock_max,
      R => '0'
    );
\wait_bypass_count[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__5_n_0\,
      I1 => rx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__5_n_0\
    );
\wait_bypass_count[0]_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__5_n_0\,
      I1 => wait_bypass_count_reg(1),
      I2 => wait_bypass_count_reg(11),
      I3 => wait_bypass_count_reg(0),
      I4 => \wait_bypass_count[0]_i_7__5_n_0\,
      O => \wait_bypass_count[0]_i_4__5_n_0\
    );
\wait_bypass_count[0]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__5_n_0\
    );
\wait_bypass_count[0]_i_6__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(9),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(12),
      I3 => wait_bypass_count_reg(2),
      O => \wait_bypass_count[0]_i_6__5_n_0\
    );
\wait_bypass_count[0]_i_7__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(6),
      I4 => wait_bypass_count_reg(10),
      I5 => wait_bypass_count_reg(8),
      O => \wait_bypass_count[0]_i_7__5_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__5_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__5_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__5_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__5_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__5_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__5_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__5_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__5_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__5_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__5_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__5_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__5_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__5_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1__5_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1__5_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[12]_i_1__5_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(12)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__5_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__5_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__5_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__5_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__5_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__5_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__5_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__5_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__5_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__5_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__5_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__5_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__5_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__5_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__5_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__5_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__5_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__5_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__5_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__5_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__5_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__5_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__5_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__5_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__5_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__5_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(1),
      I2 => rx_state(0),
      O => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt[6]_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__5_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__5_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__5_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__1_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 is
  port (
    gt3_gtrxreset_in : out STD_LOGIC;
    gt3_rxuserrdy_in : out STD_LOGIC;
    gt3_run_rx_phalignment_i : out STD_LOGIC;
    run_phase_alignment_int_reg_0 : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt3_rxusrclk_in : in STD_LOGIC;
    PHALIGNMENT_DONE_i_reg_0 : in STD_LOGIC;
    SOFT_RESET_RX_IN : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    gt3_rxresetdone_out : in STD_LOGIC;
    GT3_DATA_VALID_IN : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 : entity is "mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 is
  signal \FSM_sequential_rx_state[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_10__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_11__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_12__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_5__2_n_0\ : STD_LOGIC;
  signal PHALIGNMENT_DONE_i : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of PHALIGNMENT_DONE_i : signal is "true";
  signal \RXUSERRDY_i_1__2_n_0\ : STD_LOGIC;
  signal \check_tlock_max_i_1__2_n_0\ : STD_LOGIC;
  signal check_tlock_max_reg_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^gt3_gtrxreset_in\ : STD_LOGIC;
  signal \^gt3_run_rx_phalignment_i\ : STD_LOGIC;
  signal \^gt3_rxuserrdy_in\ : STD_LOGIC;
  signal \gtrxreset_i_i_1__2_n_0\ : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__6_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__6_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__6_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__6_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__6_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \reset_time_out_i_3__2_n_0\ : STD_LOGIC;
  signal \reset_time_out_i_4__2_n_0\ : STD_LOGIC;
  signal reset_time_out_reg_n_0 : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__2_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s2 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxresetdone_s2 : STD_LOGIC;
  signal rxresetdone_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_data_valid_n_3 : STD_LOGIC;
  signal sync_data_valid_n_4 : STD_LOGIC;
  signal sync_data_valid_n_5 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_100us_i_1__2_n_0\ : STD_LOGIC;
  signal \time_out_100us_i_2__2_n_0\ : STD_LOGIC;
  signal \time_out_100us_i_3__2_n_0\ : STD_LOGIC;
  signal time_out_100us_reg_n_0 : STD_LOGIC;
  signal \time_out_2ms_i_1__2_n_0\ : STD_LOGIC;
  signal \time_out_2ms_i_2__6_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__6_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__6_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_6__2_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__6_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__6_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__6_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__6_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__6_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__6_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max : STD_LOGIC;
  signal time_tlock_max1 : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_1__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_2__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_3__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_4__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_5__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_6__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_7__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_1__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_1__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_2__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_3__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_4__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_5__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_6__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry_i_7__2_n_0\ : STD_LOGIC;
  signal time_tlock_max1_carry_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_1 : STD_LOGIC;
  signal time_tlock_max1_carry_n_2 : STD_LOGIC;
  signal time_tlock_max1_carry_n_3 : STD_LOGIC;
  signal \time_tlock_max_i_1__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__6_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__6_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__6_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__6_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__6_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__6_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2__2\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10__2\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_11__2\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_12__2\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_5__2\ : label is "soft_lutpair96";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute KEEP : string;
  attribute KEEP of PHALIGNMENT_DONE_i_reg : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of PHALIGNMENT_DONE_i_reg : label is "no";
  attribute SOFT_HLUTNM of \RXUSERRDY_i_1__2\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__6\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__6\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__6\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__6\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__6\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__6\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__6\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__6\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__6\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__6\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__6\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__6\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \reset_time_out_i_3__2\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \reset_time_out_i_4__2\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \time_out_100us_i_1__2\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \time_out_100us_i_3__2\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \time_out_2ms_i_1__2\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \time_out_counter[0]_i_3__6\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__6\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__6\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__6\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__6\ : label is "soft_lutpair100";
begin
  gt3_gtrxreset_in <= \^gt3_gtrxreset_in\;
  gt3_run_rx_phalignment_i <= \^gt3_run_rx_phalignment_i\;
  gt3_rxuserrdy_in <= \^gt3_rxuserrdy_in\;
\FSM_onehot_phalign_state[0]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^gt3_run_rx_phalignment_i\,
      I1 => reset_time_out_reg_0,
      O => run_phase_alignment_int_reg_0
    );
\FSM_sequential_rx_state[0]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22220030AAAA0000"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => reset_time_out_reg_n_0,
      I2 => time_tlock_max,
      I3 => rx_state(3),
      I4 => rx_state(1),
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[0]_i_2__2_n_0\
    );
\FSM_sequential_rx_state[1]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00070000"
    )
        port map (
      I0 => time_tlock_max,
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(1),
      I4 => rx_state(0),
      O => \FSM_sequential_rx_state[1]_i_2__2_n_0\
    );
\FSM_sequential_rx_state[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000008380000CCCC"
    )
        port map (
      I0 => \FSM_sequential_rx_state[2]_i_2__2_n_0\,
      I1 => rx_state(2),
      I2 => rx_state(1),
      I3 => time_out_2ms_reg_n_0,
      I4 => rx_state(3),
      I5 => rx_state(0),
      O => \rx_state__0\(2)
    );
\FSM_sequential_rx_state[2]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      O => \FSM_sequential_rx_state[2]_i_2__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_10__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80800080"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => time_out_2ms_reg_n_0,
      I4 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_10__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_11__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_11__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_12__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_12__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0000"
    )
        port map (
      I0 => reset_time_out_reg_0,
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => init_wait_done_reg_n_0,
      I5 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_3__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055000300000000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_11__2_n_0\,
      I1 => \wait_time_cnt[6]_i_4__6_n_0\,
      I2 => wait_time_cnt_reg(6),
      I3 => rx_state(3),
      I4 => rx_state(0),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_4__2_n_0\
    );
\FSM_sequential_rx_state[3]_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => rx_state(2),
      O => \FSM_sequential_rx_state[3]_i_5__2_n_0\
    );
\FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(0),
      Q => rx_state(0),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(1),
      Q => rx_state(1),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(2),
      Q => rx_state(2),
      R => SOFT_RESET_RX_IN
    );
\FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_data_valid_n_4,
      D => \rx_state__0\(3),
      Q => rx_state(3),
      R => SOFT_RESET_RX_IN
    );
PHALIGNMENT_DONE_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => PHALIGNMENT_DONE_i_reg_0,
      Q => PHALIGNMENT_DONE_i,
      R => '0'
    );
\RXUSERRDY_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF2000"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt3_rxuserrdy_in\,
      O => \RXUSERRDY_i_1__2_n_0\
    );
RXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \RXUSERRDY_i_1__2_n_0\,
      Q => \^gt3_rxuserrdy_in\,
      R => SOFT_RESET_RX_IN
    );
\check_tlock_max_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0200"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => check_tlock_max_reg_n_0,
      O => \check_tlock_max_i_1__2_n_0\
    );
check_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \check_tlock_max_i_1__2_n_0\,
      Q => check_tlock_max_reg_n_0,
      R => SOFT_RESET_RX_IN
    );
\gtrxreset_i_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0100"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt3_gtrxreset_in\,
      O => \gtrxreset_i_i_1__2_n_0\
    );
gtrxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \gtrxreset_i_i_1__2_n_0\,
      Q => \^gt3_gtrxreset_in\,
      R => SOFT_RESET_RX_IN
    );
\init_wait_count[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__6_n_0\
    );
\init_wait_count[1]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_count[0]_i_1__6_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_RX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__6_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__6_n_0\
    );
\init_wait_done_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__6_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_RX_IN,
      D => \init_wait_done_i_1__6_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__6_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__6_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__6_n_0\
    );
\mmcm_lock_count[7]_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__6_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__6_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__6_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
\reset_time_out_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010301"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => reset_time_out_reg_0,
      I4 => rx_state(0),
      O => \reset_time_out_i_3__2_n_0\
    );
\reset_time_out_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11FF5520"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => reset_time_out_reg_0,
      I3 => rx_state(3),
      I4 => rx_state(0),
      O => \reset_time_out_i_4__2_n_0\
    );
reset_time_out_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_data_valid_n_5,
      Q => reset_time_out_reg_n_0,
      S => SOFT_RESET_RX_IN
    );
\run_phase_alignment_int_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      I2 => rx_state(1),
      I3 => rx_state(0),
      I4 => \^gt3_run_rx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__2_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__2_n_0\,
      Q => \^gt3_run_rx_phalignment_i\,
      R => SOFT_RESET_RX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => run_phase_alignment_int_s2,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => rx_fsm_reset_done_int_s2,
      Q => rx_fsm_reset_done_int_s3,
      R => '0'
    );
rxresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => rxresetdone_s2,
      Q => rxresetdone_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17
     port map (
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[2]_i_2__2_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => sync_data_valid_n_3,
      \FSM_sequential_rx_state_reg[1]\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[1]_0\ => sync_QPLLLOCK_n_1,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => rx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      rxresetdone_s3 => rxresetdone_s3
    );
sync_RXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => rxresetdone_s2,
      gt3_rxresetdone_out => gt3_rxresetdone_out
    );
sync_data_valid: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19
     port map (
      D(2) => \rx_state__0\(3),
      D(1 downto 0) => \rx_state__0\(1 downto 0),
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      E(0) => sync_data_valid_n_4,
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[0]_i_2__2_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_3__2_n_0\,
      \FSM_sequential_rx_state_reg[0]_1\ => \FSM_sequential_rx_state[3]_i_4__2_n_0\,
      \FSM_sequential_rx_state_reg[0]_2\ => \FSM_sequential_rx_state[3]_i_5__2_n_0\,
      \FSM_sequential_rx_state_reg[0]_3\ => sync_QPLLLOCK_n_0,
      \FSM_sequential_rx_state_reg[0]_4\ => PHALIGNMENT_DONE_i_reg_0,
      \FSM_sequential_rx_state_reg[0]_5\ => time_out_100us_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_6\ => \FSM_sequential_rx_state[3]_i_12__2_n_0\,
      \FSM_sequential_rx_state_reg[1]\ => \FSM_sequential_rx_state[1]_i_2__2_n_0\,
      \FSM_sequential_rx_state_reg[3]\ => sync_data_valid_n_5,
      \FSM_sequential_rx_state_reg[3]_0\ => \FSM_sequential_rx_state[3]_i_10__2_n_0\,
      GT3_DATA_VALID_IN => GT3_DATA_VALID_IN,
      Q(2) => rx_state(3),
      Q(1 downto 0) => rx_state(1 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      reset_time_out_reg => reset_time_out_reg_n_0,
      reset_time_out_reg_0 => sync_QPLLLOCK_n_1,
      reset_time_out_reg_1 => \reset_time_out_i_3__2_n_0\,
      reset_time_out_reg_2 => \reset_time_out_i_4__2_n_0\,
      time_out_100us_reg => sync_data_valid_n_3,
      time_out_wait_bypass_s3 => time_out_wait_bypass_s3
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__6_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21
     port map (
      data_in => \^gt3_run_rx_phalignment_i\,
      data_out => run_phase_alignment_int_s2,
      gt3_rxusrclk_in => gt3_rxusrclk_in
    );
sync_rx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22
     port map (
      data_in => PHALIGNMENT_DONE_i,
      data_out => rx_fsm_reset_done_int_s2,
      gt3_rxusrclk_in => gt3_rxusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
\time_out_100us_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_100us_reg_n_0,
      I1 => \time_out_100us_i_2__2_n_0\,
      I2 => \time_out_counter[0]_i_4__2_n_0\,
      I3 => reset_time_out_reg_n_0,
      O => \time_out_100us_i_1__2_n_0\
    );
\time_out_100us_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \time_out_100us_i_3__2_n_0\,
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(16),
      I3 => time_out_counter_reg(1),
      I4 => time_out_counter_reg(5),
      I5 => time_out_counter_reg(12),
      O => \time_out_100us_i_2__2_n_0\
    );
\time_out_100us_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_out_100us_i_3__2_n_0\
    );
time_out_100us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_100us_i_1__2_n_0\,
      Q => time_out_100us_reg_n_0,
      R => '0'
    );
\time_out_2ms_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AABA"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => time_out_counter_reg(1),
      I2 => \time_out_2ms_i_2__6_n_0\,
      I3 => \time_out_counter[0]_i_4__2_n_0\,
      I4 => reset_time_out_reg_n_0,
      O => \time_out_2ms_i_1__2_n_0\
    );
\time_out_2ms_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_2ms_i_2__6_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__2_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(1),
      I2 => \time_out_counter[0]_i_3__6_n_0\,
      I3 => \time_out_counter[0]_i_4__2_n_0\,
      I4 => time_out_counter_reg(14),
      I5 => time_out_counter_reg(13),
      O => time_out_counter
    );
\time_out_counter[0]_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(15),
      O => \time_out_counter[0]_i_3__6_n_0\
    );
\time_out_counter[0]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \time_out_counter[0]_i_6__2_n_0\,
      I1 => time_out_counter_reg(7),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(3),
      O => \time_out_counter[0]_i_4__2_n_0\
    );
\time_out_counter[0]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__6_n_0\
    );
\time_out_counter[0]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      I2 => time_out_counter_reg(10),
      I3 => time_out_counter_reg(11),
      I4 => time_out_counter_reg(4),
      I5 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_6__2_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__6_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[0]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__6_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__6_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__6_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__6_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__6_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__6_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__6_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__6_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__6_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__6_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__6_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__6_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__6_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__6_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__6_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__6_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__6_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__6_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__6_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__6_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__6_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__6_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__6_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__6_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__6_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__6_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__6_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__6_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__6_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__6_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__6_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__6_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__6_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__6_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__6_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__6_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__6_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__6_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__6_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__6_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__6_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__6_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__6_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__6_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__6_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__6_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__6_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__6_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__6_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__6_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__6_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__6_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out_reg_n_0
    );
\time_out_wait_bypass_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => rx_fsm_reset_done_int_s3,
      I2 => \wait_bypass_count[0]_i_4__6_n_0\,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__6_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_rxusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__6_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => time_tlock_max1_carry_n_0,
      CO(2) => time_tlock_max1_carry_n_1,
      CO(1) => time_tlock_max1_carry_n_2,
      CO(0) => time_tlock_max1_carry_n_3,
      CYINIT => '0',
      DI(3) => time_out_counter_reg(7),
      DI(2) => \time_tlock_max1_carry_i_1__2_n_0\,
      DI(1) => \time_tlock_max1_carry_i_2__2_n_0\,
      DI(0) => \time_tlock_max1_carry_i_3__2_n_0\,
      O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \time_tlock_max1_carry_i_4__2_n_0\,
      S(2) => \time_tlock_max1_carry_i_5__2_n_0\,
      S(1) => \time_tlock_max1_carry_i_6__2_n_0\,
      S(0) => \time_tlock_max1_carry_i_7__2_n_0\
    );
\time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => time_tlock_max1_carry_n_0,
      CO(3) => \time_tlock_max1_carry__0_n_0\,
      CO(2) => \time_tlock_max1_carry__0_n_1\,
      CO(1) => \time_tlock_max1_carry__0_n_2\,
      CO(0) => \time_tlock_max1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \time_tlock_max1_carry__0_i_1__2_n_0\,
      DI(2) => time_out_counter_reg(13),
      DI(1) => \time_tlock_max1_carry__0_i_2__2_n_0\,
      DI(0) => \time_tlock_max1_carry__0_i_3__2_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \time_tlock_max1_carry__0_i_4__2_n_0\,
      S(2) => \time_tlock_max1_carry__0_i_5__2_n_0\,
      S(1) => \time_tlock_max1_carry__0_i_6__2_n_0\,
      S(0) => \time_tlock_max1_carry__0_i_7__2_n_0\
    );
\time_tlock_max1_carry__0_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_tlock_max1_carry__0_i_1__2_n_0\
    );
\time_tlock_max1_carry__0_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => \time_tlock_max1_carry__0_i_2__2_n_0\
    );
\time_tlock_max1_carry__0_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_tlock_max1_carry__0_i_3__2_n_0\
    );
\time_tlock_max1_carry__0_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(14),
      O => \time_tlock_max1_carry__0_i_4__2_n_0\
    );
\time_tlock_max1_carry__0_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      O => \time_tlock_max1_carry__0_i_5__2_n_0\
    );
\time_tlock_max1_carry__0_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(10),
      O => \time_tlock_max1_carry__0_i_6__2_n_0\
    );
\time_tlock_max1_carry__0_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(8),
      O => \time_tlock_max1_carry__0_i_7__2_n_0\
    );
\time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_tlock_max1_carry__0_n_0\,
      CO(3 downto 1) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => time_tlock_max1,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => time_out_counter_reg(16),
      O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \time_tlock_max1_carry__1_i_1__2_n_0\
    );
\time_tlock_max1_carry__1_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(16),
      O => \time_tlock_max1_carry__1_i_1__2_n_0\
    );
\time_tlock_max1_carry_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => \time_tlock_max1_carry_i_1__2_n_0\
    );
\time_tlock_max1_carry_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(3),
      O => \time_tlock_max1_carry_i_2__2_n_0\
    );
\time_tlock_max1_carry_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => \time_tlock_max1_carry_i_3__2_n_0\
    );
\time_tlock_max1_carry_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(6),
      I1 => time_out_counter_reg(7),
      O => \time_tlock_max1_carry_i_4__2_n_0\
    );
\time_tlock_max1_carry_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(4),
      O => \time_tlock_max1_carry_i_5__2_n_0\
    );
\time_tlock_max1_carry_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(2),
      O => \time_tlock_max1_carry_i_6__2_n_0\
    );
\time_tlock_max1_carry_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(0),
      O => \time_tlock_max1_carry_i_7__2_n_0\
    );
\time_tlock_max_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => time_tlock_max,
      I1 => time_tlock_max1,
      I2 => check_tlock_max_reg_n_0,
      I3 => reset_time_out_reg_n_0,
      O => \time_tlock_max_i_1__2_n_0\
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__2_n_0\,
      Q => time_tlock_max,
      R => '0'
    );
\wait_bypass_count[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__6_n_0\,
      I1 => rx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__6_n_0\
    );
\wait_bypass_count[0]_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__6_n_0\,
      I1 => wait_bypass_count_reg(1),
      I2 => wait_bypass_count_reg(11),
      I3 => wait_bypass_count_reg(0),
      I4 => \wait_bypass_count[0]_i_7__6_n_0\,
      O => \wait_bypass_count[0]_i_4__6_n_0\
    );
\wait_bypass_count[0]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__6_n_0\
    );
\wait_bypass_count[0]_i_6__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(9),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(12),
      I3 => wait_bypass_count_reg(2),
      O => \wait_bypass_count[0]_i_6__6_n_0\
    );
\wait_bypass_count[0]_i_7__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(6),
      I4 => wait_bypass_count_reg(10),
      I5 => wait_bypass_count_reg(8),
      O => \wait_bypass_count[0]_i_7__6_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__6_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__6\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__6_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__6_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__6_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__6_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__6_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__6_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__6_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__6_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__6_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__6_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__6_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__6_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1__6_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1__6_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[12]_i_1__6_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(12)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__6_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__6_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__6_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__6_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__6_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__6_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__6_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__6_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__6_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__6_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__6_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__6_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__6_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__6_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__6_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__6_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__6_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__6_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__6_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__6_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__6_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__6_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__6_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__6_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_rxusrclk_in,
      CE => \wait_bypass_count[0]_i_2__6_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__6_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(1),
      I2 => rx_state(0),
      O => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt[6]_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__6_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__6_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__6_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__2_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__2_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN is
  port (
    gt0_tx_phalignment_done_i : out STD_LOGIC;
    gt0_txdlyen_in : out STD_LOGIC;
    U0_TXDLYSRESET : out STD_LOGIC_VECTOR ( 3 downto 0 );
    U0_TXPHINIT : out STD_LOGIC_VECTOR ( 3 downto 0 );
    U0_TXPHALIGN : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SYSCLK_IN : in STD_LOGIC;
    \stretch_r_reg[2]\ : in STD_LOGIC;
    \stretch_r_reg[2]_0\ : in STD_LOGIC;
    \stretch_r_reg[2]_1\ : in STD_LOGIC;
    \stretch_r_reg[2]_2\ : in STD_LOGIC;
    RESET_PHALIGNMENT : in STD_LOGIC;
    \FSM_sequential_tx_phalign_manual_state_reg[0]_0\ : in STD_LOGIC;
    gt1_run_tx_phalignment_i : in STD_LOGIC;
    gt3_run_tx_phalignment_i : in STD_LOGIC;
    gt0_run_tx_phalignment_i : in STD_LOGIC;
    gt2_run_tx_phalignment_i : in STD_LOGIC;
    txdone_clear_reg_0 : in STD_LOGIC;
    gt0_txphaligndone_out : in STD_LOGIC;
    gt0_txdlysresetdone_out : in STD_LOGIC;
    gt1_txphaligndone_out : in STD_LOGIC;
    gt1_txdlysresetdone_out : in STD_LOGIC;
    gt2_txphaligndone_out : in STD_LOGIC;
    gt2_txdlysresetdone_out : in STD_LOGIC;
    gt3_txphaligndone_out : in STD_LOGIC;
    gt3_txdlysresetdone_out : in STD_LOGIC;
    gt0_txphinitdone_out : in STD_LOGIC;
    gt1_txphinitdone_out : in STD_LOGIC;
    gt2_txphinitdone_out : in STD_LOGIC;
    gt3_txphinitdone_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN : entity is "mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN is
  signal \FSM_sequential_tx_phalign_manual_state[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_phalign_manual_state[3]_i_8_n_0\ : STD_LOGIC;
  signal PHASE_ALIGNMENT_DONE_i_1_n_0 : STD_LOGIC;
  signal \TXDLYSRESET[0]_i_1_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[0]_i_2_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[1]_i_1_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[1]_i_2_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[2]_i_1_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[2]_i_2_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[3]_i_1_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[3]_i_2_n_0\ : STD_LOGIC;
  signal \TXDLYSRESET[3]_i_3_n_0\ : STD_LOGIC;
  signal \TXPHALIGN[1]_i_1_n_0\ : STD_LOGIC;
  signal \TXPHALIGN[2]_i_1_n_0\ : STD_LOGIC;
  signal \TXPHALIGN[3]_i_1_n_0\ : STD_LOGIC;
  signal \TXPHINIT[1]_i_1_n_0\ : STD_LOGIC;
  signal \TXPHINIT[2]_i_1_n_0\ : STD_LOGIC;
  signal \TXPHINIT[3]_i_1_n_0\ : STD_LOGIC;
  signal \^u0_txdlysreset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^u0_txphalign\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^u0_txphinit\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cdc[0].sync_TXDLYSRESETDONE_n_0\ : STD_LOGIC;
  signal \cdc[0].sync_TXPHALIGNDONE_n_0\ : STD_LOGIC;
  signal \cdc[0].sync_TXPHALIGNDONE_n_1\ : STD_LOGIC;
  signal \cdc[0].sync_TXPHALIGNDONE_n_3\ : STD_LOGIC;
  signal \cdc[0].sync_TXPHALIGNDONE_n_4\ : STD_LOGIC;
  signal \cdc[0].sync_TXPHINITDONE_n_1\ : STD_LOGIC;
  signal \cdc[0].sync_TXPHINITDONE_n_2\ : STD_LOGIC;
  signal \cdc[1].sync_TXDLYSRESETDONE_n_0\ : STD_LOGIC;
  signal \cdc[1].sync_TXPHALIGNDONE_n_0\ : STD_LOGIC;
  signal \cdc[1].sync_TXPHINITDONE_n_1\ : STD_LOGIC;
  signal \cdc[2].sync_TXDLYSRESETDONE_n_0\ : STD_LOGIC;
  signal \cdc[2].sync_TXPHALIGNDONE_n_0\ : STD_LOGIC;
  signal \cdc[2].sync_TXPHINITDONE_n_1\ : STD_LOGIC;
  signal \cdc[3].sync_TXDLYSRESETDONE_n_0\ : STD_LOGIC;
  signal \cdc[3].sync_TXPHALIGNDONE_n_0\ : STD_LOGIC;
  signal \cdc[3].sync_TXPHINITDONE_n_1\ : STD_LOGIC;
  signal \^gt0_tx_phalignment_done_i\ : STD_LOGIC;
  signal \^gt0_txdlyen_in\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal tx_phalign_manual_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tx_phalign_manual_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txdlysresetdone_store_reg_n_0_[0]\ : STD_LOGIC;
  signal \txdlysresetdone_store_reg_n_0_[3]\ : STD_LOGIC;
  signal txdone_clear_i_1_n_0 : STD_LOGIC;
  signal txdone_clear_i_3_n_0 : STD_LOGIC;
  signal txdone_clear_reg_n_0 : STD_LOGIC;
  signal txphaligndone_prev : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txphaligndone_store : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txphaligndone_sync_0 : STD_LOGIC;
  signal txphaligndone_sync_1 : STD_LOGIC;
  signal txphaligndone_sync_2 : STD_LOGIC;
  signal txphaligndone_sync_3 : STD_LOGIC;
  signal txphinitdone_prev : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txphinitdone_store_edge : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txphinitdone_sync_0 : STD_LOGIC;
  signal txphinitdone_sync_1 : STD_LOGIC;
  signal txphinitdone_sync_2 : STD_LOGIC;
  signal txphinitdone_sync_3 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_phalign_manual_state[0]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_phalign_manual_state[1]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_phalign_manual_state[2]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_phalign_manual_state[3]_i_3\ : label is "soft_lutpair21";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_phalign_manual_state_reg[0]\ : label is "m_phalign:0011,m_dlyen:0100,m_phinit:0010,wait_phrst_done:0001,init:0000,m_dlyen2:0111,s_phalign:0110,phalign_done:1000,s_phinit:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_phalign_manual_state_reg[1]\ : label is "m_phalign:0011,m_dlyen:0100,m_phinit:0010,wait_phrst_done:0001,init:0000,m_dlyen2:0111,s_phalign:0110,phalign_done:1000,s_phinit:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_phalign_manual_state_reg[2]\ : label is "m_phalign:0011,m_dlyen:0100,m_phinit:0010,wait_phrst_done:0001,init:0000,m_dlyen2:0111,s_phalign:0110,phalign_done:1000,s_phinit:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_phalign_manual_state_reg[3]\ : label is "m_phalign:0011,m_dlyen:0100,m_phinit:0010,wait_phrst_done:0001,init:0000,m_dlyen2:0111,s_phalign:0110,phalign_done:1000,s_phinit:0101";
  attribute SOFT_HLUTNM of PHASE_ALIGNMENT_DONE_i_1 : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of txdone_clear_i_3 : label is "soft_lutpair20";
begin
  U0_TXDLYSRESET(3 downto 0) <= \^u0_txdlysreset\(3 downto 0);
  U0_TXPHALIGN(3 downto 0) <= \^u0_txphalign\(3 downto 0);
  U0_TXPHINIT(3 downto 0) <= \^u0_txphinit\(3 downto 0);
  gt0_tx_phalignment_done_i <= \^gt0_tx_phalignment_done_i\;
  gt0_txdlyen_in <= \^gt0_txdlyen_in\;
\FSM_sequential_tx_phalign_manual_state[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => tx_phalign_manual_state(0),
      O => \tx_phalign_manual_state__0\(0)
    );
\FSM_sequential_tx_phalign_manual_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => tx_phalign_manual_state(1),
      I1 => tx_phalign_manual_state(0),
      O => \tx_phalign_manual_state__0\(1)
    );
\FSM_sequential_tx_phalign_manual_state[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => tx_phalign_manual_state(0),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(2),
      O => \tx_phalign_manual_state__0\(2)
    );
\FSM_sequential_tx_phalign_manual_state[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => tx_phalign_manual_state(2),
      I1 => tx_phalign_manual_state(0),
      I2 => tx_phalign_manual_state(1),
      O => \tx_phalign_manual_state__0\(3)
    );
\FSM_sequential_tx_phalign_manual_state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => \txdlysresetdone_store_reg_n_0_[3]\,
      I1 => p_1_in,
      I2 => \txdlysresetdone_store_reg_n_0_[0]\,
      I3 => p_2_in,
      I4 => tx_phalign_manual_state(0),
      I5 => \FSM_sequential_tx_phalign_manual_state_reg[0]_0\,
      O => \FSM_sequential_tx_phalign_manual_state[3]_i_4_n_0\
    );
\FSM_sequential_tx_phalign_manual_state[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => txphaligndone_store(2),
      I1 => txphaligndone_store(1),
      I2 => txphaligndone_store(0),
      I3 => txphaligndone_store(3),
      O => \FSM_sequential_tx_phalign_manual_state[3]_i_8_n_0\
    );
\FSM_sequential_tx_phalign_manual_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \cdc[0].sync_TXPHALIGNDONE_n_0\,
      D => \tx_phalign_manual_state__0\(0),
      Q => tx_phalign_manual_state(0),
      R => RESET_PHALIGNMENT
    );
\FSM_sequential_tx_phalign_manual_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \cdc[0].sync_TXPHALIGNDONE_n_0\,
      D => \tx_phalign_manual_state__0\(1),
      Q => tx_phalign_manual_state(1),
      R => RESET_PHALIGNMENT
    );
\FSM_sequential_tx_phalign_manual_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \cdc[0].sync_TXPHALIGNDONE_n_0\,
      D => \tx_phalign_manual_state__0\(2),
      Q => tx_phalign_manual_state(2),
      R => RESET_PHALIGNMENT
    );
\FSM_sequential_tx_phalign_manual_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \cdc[0].sync_TXPHALIGNDONE_n_0\,
      D => \tx_phalign_manual_state__0\(3),
      Q => tx_phalign_manual_state(3),
      R => RESET_PHALIGNMENT
    );
PHASE_ALIGNMENT_DONE_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => tx_phalign_manual_state(3),
      I1 => tx_phalign_manual_state(2),
      I2 => tx_phalign_manual_state(0),
      I3 => tx_phalign_manual_state(1),
      I4 => \^gt0_tx_phalignment_done_i\,
      O => PHASE_ALIGNMENT_DONE_i_1_n_0
    );
PHASE_ALIGNMENT_DONE_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => PHASE_ALIGNMENT_DONE_i_1_n_0,
      Q => \^gt0_tx_phalignment_done_i\,
      R => RESET_PHALIGNMENT
    );
\TXDLYEN_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[0].sync_TXPHALIGNDONE_n_1\,
      Q => \^gt0_txdlyen_in\,
      R => RESET_PHALIGNMENT
    );
\TXDLYSRESET[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEF00000020"
    )
        port map (
      I0 => \TXDLYSRESET[3]_i_2_n_0\,
      I1 => tx_phalign_manual_state(1),
      I2 => \TXDLYSRESET[0]_i_2_n_0\,
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txdlysreset\(0),
      O => \TXDLYSRESET[0]_i_1_n_0\
    );
\TXDLYSRESET[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888888888888888"
    )
        port map (
      I0 => \txdlysresetdone_store_reg_n_0_[0]\,
      I1 => tx_phalign_manual_state(0),
      I2 => gt1_run_tx_phalignment_i,
      I3 => gt3_run_tx_phalignment_i,
      I4 => gt0_run_tx_phalignment_i,
      I5 => gt2_run_tx_phalignment_i,
      O => \TXDLYSRESET[0]_i_2_n_0\
    );
\TXDLYSRESET[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEF00000020"
    )
        port map (
      I0 => \TXDLYSRESET[3]_i_2_n_0\,
      I1 => tx_phalign_manual_state(1),
      I2 => \TXDLYSRESET[1]_i_2_n_0\,
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txdlysreset\(1),
      O => \TXDLYSRESET[1]_i_1_n_0\
    );
\TXDLYSRESET[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888888888888888"
    )
        port map (
      I0 => p_1_in,
      I1 => tx_phalign_manual_state(0),
      I2 => gt1_run_tx_phalignment_i,
      I3 => gt3_run_tx_phalignment_i,
      I4 => gt0_run_tx_phalignment_i,
      I5 => gt2_run_tx_phalignment_i,
      O => \TXDLYSRESET[1]_i_2_n_0\
    );
\TXDLYSRESET[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEF00000020"
    )
        port map (
      I0 => \TXDLYSRESET[3]_i_2_n_0\,
      I1 => tx_phalign_manual_state(1),
      I2 => \TXDLYSRESET[2]_i_2_n_0\,
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txdlysreset\(2),
      O => \TXDLYSRESET[2]_i_1_n_0\
    );
\TXDLYSRESET[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888888888888888"
    )
        port map (
      I0 => p_2_in,
      I1 => tx_phalign_manual_state(0),
      I2 => gt1_run_tx_phalignment_i,
      I3 => gt3_run_tx_phalignment_i,
      I4 => gt0_run_tx_phalignment_i,
      I5 => gt2_run_tx_phalignment_i,
      O => \TXDLYSRESET[2]_i_2_n_0\
    );
\TXDLYSRESET[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEF00000020"
    )
        port map (
      I0 => \TXDLYSRESET[3]_i_2_n_0\,
      I1 => tx_phalign_manual_state(1),
      I2 => \TXDLYSRESET[3]_i_3_n_0\,
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txdlysreset\(3),
      O => \TXDLYSRESET[3]_i_1_n_0\
    );
\TXDLYSRESET[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => tx_phalign_manual_state(0),
      I1 => gt1_run_tx_phalignment_i,
      I2 => gt3_run_tx_phalignment_i,
      I3 => gt0_run_tx_phalignment_i,
      I4 => gt2_run_tx_phalignment_i,
      I5 => tx_phalign_manual_state(3),
      O => \TXDLYSRESET[3]_i_2_n_0\
    );
\TXDLYSRESET[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888888888888888"
    )
        port map (
      I0 => \txdlysresetdone_store_reg_n_0_[3]\,
      I1 => tx_phalign_manual_state(0),
      I2 => gt1_run_tx_phalignment_i,
      I3 => gt3_run_tx_phalignment_i,
      I4 => gt0_run_tx_phalignment_i,
      I5 => gt2_run_tx_phalignment_i,
      O => \TXDLYSRESET[3]_i_3_n_0\
    );
\TXDLYSRESET_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXDLYSRESET[0]_i_1_n_0\,
      Q => \^u0_txdlysreset\(0),
      R => RESET_PHALIGNMENT
    );
\TXDLYSRESET_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXDLYSRESET[1]_i_1_n_0\,
      Q => \^u0_txdlysreset\(1),
      R => RESET_PHALIGNMENT
    );
\TXDLYSRESET_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXDLYSRESET[2]_i_1_n_0\,
      Q => \^u0_txdlysreset\(2),
      R => RESET_PHALIGNMENT
    );
\TXDLYSRESET_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXDLYSRESET[3]_i_1_n_0\,
      Q => \^u0_txdlysreset\(3),
      R => RESET_PHALIGNMENT
    );
\TXPHALIGN[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7F00000040"
    )
        port map (
      I0 => txphaligndone_store(1),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(2),
      I3 => tx_phalign_manual_state(0),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txphalign\(1),
      O => \TXPHALIGN[1]_i_1_n_0\
    );
\TXPHALIGN[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7F00000040"
    )
        port map (
      I0 => txphaligndone_store(2),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(2),
      I3 => tx_phalign_manual_state(0),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txphalign\(2),
      O => \TXPHALIGN[2]_i_1_n_0\
    );
\TXPHALIGN[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7F00000040"
    )
        port map (
      I0 => txphaligndone_store(3),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(2),
      I3 => tx_phalign_manual_state(0),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txphalign\(3),
      O => \TXPHALIGN[3]_i_1_n_0\
    );
\TXPHALIGN_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[0].sync_TXPHALIGNDONE_n_4\,
      Q => \^u0_txphalign\(0),
      R => RESET_PHALIGNMENT
    );
\TXPHALIGN_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXPHALIGN[1]_i_1_n_0\,
      Q => \^u0_txphalign\(1),
      R => RESET_PHALIGNMENT
    );
\TXPHALIGN_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXPHALIGN[2]_i_1_n_0\,
      Q => \^u0_txphalign\(2),
      R => RESET_PHALIGNMENT
    );
\TXPHALIGN_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXPHALIGN[3]_i_1_n_0\,
      Q => \^u0_txphalign\(3),
      R => RESET_PHALIGNMENT
    );
\TXPHINIT[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDFFF00001000"
    )
        port map (
      I0 => txphinitdone_store_edge(1),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(0),
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txphinit\(1),
      O => \TXPHINIT[1]_i_1_n_0\
    );
\TXPHINIT[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDFFF00001000"
    )
        port map (
      I0 => txphinitdone_store_edge(2),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(0),
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txphinit\(2),
      O => \TXPHINIT[2]_i_1_n_0\
    );
\TXPHINIT[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDFFF00001000"
    )
        port map (
      I0 => txphinitdone_store_edge(3),
      I1 => tx_phalign_manual_state(1),
      I2 => tx_phalign_manual_state(0),
      I3 => tx_phalign_manual_state(2),
      I4 => tx_phalign_manual_state(3),
      I5 => \^u0_txphinit\(3),
      O => \TXPHINIT[3]_i_1_n_0\
    );
\TXPHINIT_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[0].sync_TXPHINITDONE_n_2\,
      Q => \^u0_txphinit\(0),
      R => RESET_PHALIGNMENT
    );
\TXPHINIT_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXPHINIT[1]_i_1_n_0\,
      Q => \^u0_txphinit\(1),
      R => RESET_PHALIGNMENT
    );
\TXPHINIT_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXPHINIT[2]_i_1_n_0\,
      Q => \^u0_txphinit\(2),
      R => RESET_PHALIGNMENT
    );
\TXPHINIT_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXPHINIT[3]_i_1_n_0\,
      Q => \^u0_txphinit\(3),
      R => RESET_PHALIGNMENT
    );
\cdc[0].sync_TXDLYSRESETDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_sync_reg6_0 => \cdc[0].sync_TXDLYSRESETDONE_n_0\,
      gt0_txdlysresetdone_out => gt0_txdlysresetdone_out,
      \txdlysresetdone_store_reg[0]\ => \txdlysresetdone_store_reg_n_0_[0]\
    );
\cdc[0].sync_TXPHALIGNDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63
     port map (
      E(0) => \cdc[0].sync_TXPHALIGNDONE_n_0\,
      \FSM_sequential_tx_phalign_manual_state_reg[0]\ => \FSM_sequential_tx_phalign_manual_state[3]_i_4_n_0\,
      \FSM_sequential_tx_phalign_manual_state_reg[0]_0\ => \FSM_sequential_tx_phalign_manual_state[3]_i_8_n_0\,
      \FSM_sequential_tx_phalign_manual_state_reg[0]_1\(0) => txphinitdone_prev(0),
      \FSM_sequential_tx_phalign_manual_state_reg[1]\ => \cdc[0].sync_TXPHALIGNDONE_n_4\,
      \FSM_sequential_tx_phalign_manual_state_reg[3]\ => \cdc[0].sync_TXPHALIGNDONE_n_1\,
      Q(3 downto 0) => tx_phalign_manual_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      U0_TXPHALIGN(0) => \^u0_txphalign\(0),
      data_out => txphaligndone_sync_0,
      gt0_txdlyen_in => \^gt0_txdlyen_in\,
      gt0_txphaligndone_out => gt0_txphaligndone_out,
      \txphaligndone_prev_reg[0]\ => \cdc[0].sync_TXPHALIGNDONE_n_3\,
      txphaligndone_store(0) => txphaligndone_store(0),
      \txphaligndone_store_reg[0]\(0) => txphaligndone_prev(0),
      txphinitdone_store_edge(3 downto 0) => txphinitdone_store_edge(3 downto 0),
      txphinitdone_sync_0 => txphinitdone_sync_0
    );
\cdc[0].sync_TXPHINITDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse
     port map (
      \FSM_sequential_tx_phalign_manual_state_reg[2]\ => \cdc[0].sync_TXPHINITDONE_n_2\,
      Q(0) => txphinitdone_prev(0),
      SYSCLK_IN => SYSCLK_IN,
      \TXPHINIT_reg[0]\(3 downto 0) => tx_phalign_manual_state(3 downto 0),
      U0_TXPHINIT(0) => \^u0_txphinit\(0),
      gt0_txphinitdone_out => gt0_txphinitdone_out,
      \stretch_r_reg[2]_0\ => \stretch_r_reg[2]\,
      txdone_clear_reg => \cdc[0].sync_TXPHINITDONE_n_1\,
      txphinitdone_store_edge(0) => txphinitdone_store_edge(0),
      \txphinitdone_store_edge_reg[0]\ => txdone_clear_reg_n_0,
      txphinitdone_sync_0 => txphinitdone_sync_0
    );
\cdc[1].sync_TXDLYSRESETDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_sync_reg6_0 => \cdc[1].sync_TXDLYSRESETDONE_n_0\,
      gt1_txdlysresetdone_out => gt1_txdlysresetdone_out,
      p_1_in => p_1_in
    );
\cdc[1].sync_TXPHALIGNDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65
     port map (
      Q(0) => txphaligndone_prev(1),
      SYSCLK_IN => SYSCLK_IN,
      data_out => txphaligndone_sync_1,
      gt1_txphaligndone_out => gt1_txphaligndone_out,
      \txphaligndone_prev_reg[1]\ => \cdc[1].sync_TXPHALIGNDONE_n_0\,
      txphaligndone_store(0) => txphaligndone_store(1)
    );
\cdc[1].sync_TXPHINITDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66
     port map (
      D(0) => txphinitdone_sync_1,
      Q(0) => txphinitdone_prev(1),
      SYSCLK_IN => SYSCLK_IN,
      gt1_txphinitdone_out => gt1_txphinitdone_out,
      \stretch_r_reg[2]_0\ => \stretch_r_reg[2]_0\,
      \txphinitdone_prev_reg[1]\ => \cdc[1].sync_TXPHINITDONE_n_1\,
      txphinitdone_store_edge(0) => txphinitdone_store_edge(1)
    );
\cdc[2].sync_TXDLYSRESETDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_sync_reg6_0 => \cdc[2].sync_TXDLYSRESETDONE_n_0\,
      gt2_txdlysresetdone_out => gt2_txdlysresetdone_out,
      p_2_in => p_2_in
    );
\cdc[2].sync_TXPHALIGNDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68
     port map (
      Q(0) => txphaligndone_prev(2),
      SYSCLK_IN => SYSCLK_IN,
      data_out => txphaligndone_sync_2,
      gt2_txphaligndone_out => gt2_txphaligndone_out,
      \txphaligndone_prev_reg[2]\ => \cdc[2].sync_TXPHALIGNDONE_n_0\,
      txphaligndone_store(0) => txphaligndone_store(2)
    );
\cdc[2].sync_TXPHINITDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69
     port map (
      D(0) => txphinitdone_sync_2,
      Q(0) => txphinitdone_prev(2),
      SYSCLK_IN => SYSCLK_IN,
      gt2_txphinitdone_out => gt2_txphinitdone_out,
      \stretch_r_reg[2]_0\ => \stretch_r_reg[2]_1\,
      \txphinitdone_prev_reg[2]\ => \cdc[2].sync_TXPHINITDONE_n_1\,
      txphinitdone_store_edge(0) => txphinitdone_store_edge(2)
    );
\cdc[3].sync_TXDLYSRESETDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_sync_reg6_0 => \cdc[3].sync_TXDLYSRESETDONE_n_0\,
      gt3_txdlysresetdone_out => gt3_txdlysresetdone_out,
      \txdlysresetdone_store_reg[3]\ => \txdlysresetdone_store_reg_n_0_[3]\
    );
\cdc[3].sync_TXPHALIGNDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71
     port map (
      Q(0) => txphaligndone_prev(3),
      SYSCLK_IN => SYSCLK_IN,
      data_out => txphaligndone_sync_3,
      gt3_txphaligndone_out => gt3_txphaligndone_out,
      \txphaligndone_prev_reg[3]\ => \cdc[3].sync_TXPHALIGNDONE_n_0\,
      txphaligndone_store(0) => txphaligndone_store(3)
    );
\cdc[3].sync_TXPHINITDONE\: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72
     port map (
      D(0) => txphinitdone_sync_3,
      Q(0) => txphinitdone_prev(3),
      SYSCLK_IN => SYSCLK_IN,
      gt3_txphinitdone_out => gt3_txphinitdone_out,
      \stretch_r_reg[2]_0\ => \stretch_r_reg[2]_2\,
      \txphinitdone_prev_reg[3]\ => \cdc[3].sync_TXPHINITDONE_n_1\,
      txphinitdone_store_edge(0) => txphinitdone_store_edge(3)
    );
\txdlysresetdone_store_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[0].sync_TXDLYSRESETDONE_n_0\,
      Q => \txdlysresetdone_store_reg_n_0_[0]\,
      R => txdone_clear_reg_n_0
    );
\txdlysresetdone_store_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[1].sync_TXDLYSRESETDONE_n_0\,
      Q => p_1_in,
      R => txdone_clear_reg_n_0
    );
\txdlysresetdone_store_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[2].sync_TXDLYSRESETDONE_n_0\,
      Q => p_2_in,
      R => txdone_clear_reg_n_0
    );
\txdlysresetdone_store_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[3].sync_TXDLYSRESETDONE_n_0\,
      Q => \txdlysresetdone_store_reg_n_0_[3]\,
      R => txdone_clear_reg_n_0
    );
txdone_clear_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFF00007F00"
    )
        port map (
      I0 => gt1_run_tx_phalignment_i,
      I1 => txdone_clear_reg_0,
      I2 => gt2_run_tx_phalignment_i,
      I3 => txdone_clear_i_3_n_0,
      I4 => tx_phalign_manual_state(3),
      I5 => txdone_clear_reg_n_0,
      O => txdone_clear_i_1_n_0
    );
txdone_clear_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => tx_phalign_manual_state(2),
      I1 => tx_phalign_manual_state(0),
      I2 => tx_phalign_manual_state(1),
      O => txdone_clear_i_3_n_0
    );
txdone_clear_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txdone_clear_i_1_n_0,
      Q => txdone_clear_reg_n_0,
      S => RESET_PHALIGNMENT
    );
\txphaligndone_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphaligndone_sync_0,
      Q => txphaligndone_prev(0),
      R => '0'
    );
\txphaligndone_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphaligndone_sync_1,
      Q => txphaligndone_prev(1),
      R => '0'
    );
\txphaligndone_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphaligndone_sync_2,
      Q => txphaligndone_prev(2),
      R => '0'
    );
\txphaligndone_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphaligndone_sync_3,
      Q => txphaligndone_prev(3),
      R => '0'
    );
\txphaligndone_store_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[0].sync_TXPHALIGNDONE_n_3\,
      Q => txphaligndone_store(0),
      R => txdone_clear_reg_n_0
    );
\txphaligndone_store_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[1].sync_TXPHALIGNDONE_n_0\,
      Q => txphaligndone_store(1),
      R => txdone_clear_reg_n_0
    );
\txphaligndone_store_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[2].sync_TXPHALIGNDONE_n_0\,
      Q => txphaligndone_store(2),
      R => txdone_clear_reg_n_0
    );
\txphaligndone_store_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[3].sync_TXPHALIGNDONE_n_0\,
      Q => txphaligndone_store(3),
      R => txdone_clear_reg_n_0
    );
\txphinitdone_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphinitdone_sync_0,
      Q => txphinitdone_prev(0),
      R => '0'
    );
\txphinitdone_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphinitdone_sync_1,
      Q => txphinitdone_prev(1),
      R => '0'
    );
\txphinitdone_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphinitdone_sync_2,
      Q => txphinitdone_prev(2),
      R => '0'
    );
\txphinitdone_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txphinitdone_sync_3,
      Q => txphinitdone_prev(3),
      R => '0'
    );
\txphinitdone_store_edge_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[0].sync_TXPHINITDONE_n_1\,
      Q => txphinitdone_store_edge(0),
      R => '0'
    );
\txphinitdone_store_edge_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[1].sync_TXPHINITDONE_n_1\,
      Q => txphinitdone_store_edge(1),
      R => txdone_clear_reg_n_0
    );
\txphinitdone_store_edge_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[2].sync_TXPHINITDONE_n_1\,
      Q => txphinitdone_store_edge(2),
      R => txdone_clear_reg_n_0
    );
\txphinitdone_store_edge_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \cdc[3].sync_TXPHINITDONE_n_1\,
      Q => txphinitdone_store_edge(3),
      R => txdone_clear_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM is
  port (
    gt0_gttxreset_in : out STD_LOGIC;
    GT0_QPLLRESET_OUT : out STD_LOGIC;
    GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    gt0_txuserrdy_in : out STD_LOGIC;
    gt0_run_tx_phalignment_i : out STD_LOGIC;
    gt0_rst_tx_phalignment_i : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC;
    SOFT_RESET_TX_IN : in STD_LOGIC;
    gt0_tx_phalignment_done_i : in STD_LOGIC;
    GT0_QPLLREFCLKLOST_IN : in STD_LOGIC;
    gt0_txresetdone_out : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM : entity is "mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM is
  signal \FSM_sequential_tx_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_9_n_0\ : STD_LOGIC;
  signal \^gt0_qpllreset_out\ : STD_LOGIC;
  signal \^gt0_tx_fsm_reset_done_out\ : STD_LOGIC;
  signal QPLL_RESET_i_1_n_0 : STD_LOGIC;
  signal QPLL_RESET_i_2_n_0 : STD_LOGIC;
  signal RESET_PHALIGNMENT_i_1_n_0 : STD_LOGIC;
  signal TXUSERRDY_i_1_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal \^gt0_gttxreset_in\ : STD_LOGIC;
  signal \^gt0_rst_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt0_run_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt0_txuserrdy_in\ : STD_LOGIC;
  signal gttxreset_i_i_1_n_0 : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal init_wait_done_i_1_n_0 : STD_LOGIC;
  signal init_wait_done_i_2_n_0 : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pll_reset_asserted_i_1_n_0 : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal \reset_time_out__0\ : STD_LOGIC;
  signal reset_time_out_i_2_n_0 : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__3_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_2ms_i_1__3_n_0\ : STD_LOGIC;
  signal time_out_2ms_i_2_n_0 : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_500us_i_1_n_0 : STD_LOGIC;
  signal time_out_500us_i_2_n_0 : STD_LOGIC;
  signal time_out_500us_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal time_out_wait_bypass_i_1_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal \time_tlock_max_i_1__3_n_0\ : STD_LOGIC;
  signal time_tlock_max_i_2_n_0 : STD_LOGIC;
  signal time_tlock_max_i_3_n_0 : STD_LOGIC;
  signal time_tlock_max_reg_n_0 : STD_LOGIC;
  signal tx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC;
  signal tx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal tx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal tx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txresetdone_s2 : STD_LOGIC;
  signal txresetdone_s3 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_8_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_9_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_5\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_6\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_8\ : label is "soft_lutpair24";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[2]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[3]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of QPLL_RESET_i_2 : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of RESET_PHALIGNMENT_i_1 : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of TXUSERRDY_i_1 : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of gttxreset_i_i_1 : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of init_wait_done_i_2 : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \run_phase_alignment_int_i_1__3\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1\ : label is "soft_lutpair30";
begin
  GT0_QPLLRESET_OUT <= \^gt0_qpllreset_out\;
  GT0_TX_FSM_RESET_DONE_OUT <= \^gt0_tx_fsm_reset_done_out\;
  gt0_gttxreset_in <= \^gt0_gttxreset_in\;
  gt0_rst_tx_phalignment_i <= \^gt0_rst_tx_phalignment_i\;
  gt0_run_tx_phalignment_i <= \^gt0_run_tx_phalignment_i\;
  gt0_txuserrdy_in <= \^gt0_txuserrdy_in\;
\FSM_sequential_tx_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBBFBBBBBBBFB"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(2),
      I3 => \FSM_sequential_tx_state[2]_i_2_n_0\,
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[0]_i_2_n_0\,
      O => \tx_state__0\(0)
    );
\FSM_sequential_tx_state[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => tx_state(2),
      I3 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_tx_state[0]_i_2_n_0\
    );
\FSM_sequential_tx_state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F00D0"
    )
        port map (
      I0 => tx_state(2),
      I1 => \FSM_sequential_tx_state[2]_i_2_n_0\,
      I2 => tx_state(0),
      I3 => tx_state(3),
      I4 => tx_state(1),
      O => \tx_state__0\(1)
    );
\FSM_sequential_tx_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010C0C0C010C000C"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[2]_i_2_n_0\,
      O => \tx_state__0\(2)
    );
\FSM_sequential_tx_state[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[2]_i_2_n_0\
    );
\FSM_sequential_tx_state[3]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000005400000000"
    )
        port map (
      I0 => tx_state(0),
      I1 => time_out_wait_bypass_s3,
      I2 => gt0_tx_phalignment_done_i,
      I3 => tx_state(1),
      I4 => tx_state(2),
      I5 => tx_state(3),
      O => \FSM_sequential_tx_state[3]_i_10_n_0\
    );
\FSM_sequential_tx_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF5D0C0C0C0C0C0C"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => tx_state(3),
      I2 => time_out_wait_bypass_s3,
      I3 => \reset_time_out__0\,
      I4 => \FSM_sequential_tx_state[3]_i_8_n_0\,
      I5 => tx_state(2),
      O => \tx_state__0\(3)
    );
\FSM_sequential_tx_state[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEFEE"
    )
        port map (
      I0 => \FSM_sequential_tx_state[3]_i_9_n_0\,
      I1 => \FSM_sequential_tx_state[3]_i_10_n_0\,
      I2 => \FSM_sequential_tx_state[3]_i_5_n_0\,
      I3 => \FSM_sequential_tx_state[3]_i_6_n_0\,
      I4 => wait_time_cnt_reg(6),
      I5 => \wait_time_cnt[6]_i_4_n_0\,
      O => \FSM_sequential_tx_state[3]_i_3_n_0\
    );
\FSM_sequential_tx_state[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      O => \FSM_sequential_tx_state[3]_i_5_n_0\
    );
\FSM_sequential_tx_state[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_6_n_0\
    );
\FSM_sequential_tx_state[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040400040000"
    )
        port map (
      I0 => QPLL_RESET_i_2_n_0,
      I1 => tx_state(2),
      I2 => tx_state(1),
      I3 => \reset_time_out__0\,
      I4 => time_tlock_max_reg_n_0,
      I5 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[3]_i_7_n_0\
    );
\FSM_sequential_tx_state[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(0),
      I2 => tx_state(3),
      O => \FSM_sequential_tx_state[3]_i_8_n_0\
    );
\FSM_sequential_tx_state[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => tx_state(2),
      I1 => tx_state(1),
      I2 => tx_state(0),
      I3 => tx_state(3),
      I4 => txresetdone_s3,
      O => \FSM_sequential_tx_state[3]_i_9_n_0\
    );
\FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(0),
      Q => tx_state(0),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(1),
      Q => tx_state(1),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(2),
      Q => tx_state(2),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(3),
      Q => tx_state(3),
      R => SOFT_RESET_TX_IN
    );
QPLL_RESET_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF100000001"
    )
        port map (
      I0 => GT0_QPLLREFCLKLOST_IN,
      I1 => pll_reset_asserted_reg_n_0,
      I2 => tx_state(2),
      I3 => tx_state(1),
      I4 => QPLL_RESET_i_2_n_0,
      I5 => \^gt0_qpllreset_out\,
      O => QPLL_RESET_i_1_n_0
    );
QPLL_RESET_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      O => QPLL_RESET_i_2_n_0
    );
QPLL_RESET_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => QPLL_RESET_i_1_n_0,
      Q => \^gt0_qpllreset_out\,
      R => SOFT_RESET_TX_IN
    );
RESET_PHALIGNMENT_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt0_rst_tx_phalignment_i\,
      O => RESET_PHALIGNMENT_i_1_n_0
    );
RESET_PHALIGNMENT_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => RESET_PHALIGNMENT_i_1_n_0,
      Q => \^gt0_rst_tx_phalignment_i\,
      S => SOFT_RESET_TX_IN
    );
TXUSERRDY_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt0_txuserrdy_in\,
      O => TXUSERRDY_i_1_n_0
    );
TXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => TXUSERRDY_i_1_n_0,
      Q => \^gt0_txuserrdy_in\,
      R => SOFT_RESET_TX_IN
    );
gttxreset_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt0_gttxreset_in\,
      O => gttxreset_i_i_1_n_0
    );
gttxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gttxreset_i_i_1_n_0,
      Q => \^gt0_gttxreset_in\,
      R => SOFT_RESET_TX_IN
    );
\init_wait_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1_n_0\
    );
\init_wait_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_count[0]_i_1_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
init_wait_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => init_wait_done_i_2_n_0,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => init_wait_done_i_1_n_0
    );
init_wait_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => init_wait_done_i_2_n_0
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_TX_IN,
      D => init_wait_done_i_1_n_0,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2_n_0\
    );
\mmcm_lock_count[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
pll_reset_asserted_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF00DF00DF10"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(3),
      I2 => tx_state(0),
      I3 => pll_reset_asserted_reg_n_0,
      I4 => GT0_QPLLREFCLKLOST_IN,
      I5 => tx_state(2),
      O => pll_reset_asserted_i_1_n_0
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => pll_reset_asserted_i_1_n_0,
      Q => pll_reset_asserted_reg_n_0,
      R => SOFT_RESET_TX_IN
    );
reset_time_out_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"440000FF50505050"
    )
        port map (
      I0 => tx_state(3),
      I1 => txresetdone_s3,
      I2 => init_wait_done_reg_n_0,
      I3 => tx_state(1),
      I4 => tx_state(2),
      I5 => tx_state(0),
      O => reset_time_out_i_2_n_0
    );
reset_time_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_QPLLLOCK_n_1,
      Q => \reset_time_out__0\,
      R => SOFT_RESET_TX_IN
    );
\run_phase_alignment_int_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0002"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt0_run_tx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__3_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__3_n_0\,
      Q => \^gt0_run_tx_phalignment_i\,
      R => SOFT_RESET_TX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => data_out,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56
     port map (
      E(0) => sync_QPLLLOCK_n_0,
      \FSM_sequential_tx_state_reg[0]\ => \FSM_sequential_tx_state[3]_i_3_n_0\,
      \FSM_sequential_tx_state_reg[0]_0\ => \FSM_sequential_tx_state[3]_i_5_n_0\,
      \FSM_sequential_tx_state_reg[0]_1\ => init_wait_done_reg_n_0,
      \FSM_sequential_tx_state_reg[0]_2\ => \FSM_sequential_tx_state[3]_i_6_n_0\,
      \FSM_sequential_tx_state_reg[0]_3\ => \FSM_sequential_tx_state[3]_i_7_n_0\,
      \FSM_sequential_tx_state_reg[0]_4\ => pll_reset_asserted_reg_n_0,
      \FSM_sequential_tx_state_reg[0]_5\ => QPLL_RESET_i_2_n_0,
      \FSM_sequential_tx_state_reg[0]_6\ => \FSM_sequential_tx_state[0]_i_2_n_0\,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => tx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      \reset_time_out__0\ => \reset_time_out__0\,
      reset_time_out_reg => sync_QPLLLOCK_n_1,
      reset_time_out_reg_0 => reset_time_out_i_2_n_0
    );
sync_TXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => txresetdone_s2,
      gt0_txresetdone_out => gt0_txresetdone_out
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59
     port map (
      data_out => data_out,
      gt0_run_tx_phalignment_i => \^gt0_run_tx_phalignment_i\,
      gt0_txusrclk_in => gt0_txusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
sync_tx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61
     port map (
      GT0_TX_FSM_RESET_DONE_OUT => \^gt0_tx_fsm_reset_done_out\,
      data_out => tx_fsm_reset_done_int_s2,
      gt0_txusrclk_in => gt0_txusrclk_in
    );
\time_out_2ms_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => time_out_2ms_i_2_n_0,
      I2 => \time_out_counter[0]_i_3_n_0\,
      I3 => \reset_time_out__0\,
      O => \time_out_2ms_i_1__3_n_0\
    );
time_out_2ms_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(12),
      I4 => \time_out_counter[0]_i_4__3_n_0\,
      O => time_out_2ms_i_2_n_0
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__3_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
time_out_500us_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAEA"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => time_out_500us_i_2_n_0,
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(3),
      I4 => \time_out_counter[0]_i_3_n_0\,
      I5 => \reset_time_out__0\,
      O => time_out_500us_i_1_n_0
    );
time_out_500us_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(12),
      I2 => time_out_counter_reg(4),
      I3 => time_out_counter_reg(6),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => time_out_500us_i_2_n_0
    );
time_out_500us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_500us_i_1_n_0,
      Q => time_out_500us_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(12),
      I2 => \time_out_counter[0]_i_3_n_0\,
      I3 => time_out_counter_reg(15),
      I4 => time_out_counter_reg(16),
      I5 => \time_out_counter[0]_i_4__3_n_0\,
      O => time_out_counter
    );
\time_out_counter[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(14),
      I3 => time_tlock_max_i_2_n_0,
      O => \time_out_counter[0]_i_3_n_0\
    );
\time_out_counter[0]_i_4__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(9),
      O => \time_out_counter[0]_i_4__3_n_0\
    );
\time_out_counter[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_7\,
      Q => time_out_counter_reg(0),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_5\,
      Q => time_out_counter_reg(10),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_4\,
      Q => time_out_counter_reg(11),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_7\,
      Q => time_out_counter_reg(12),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_6\,
      Q => time_out_counter_reg(13),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_5\,
      Q => time_out_counter_reg(14),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_4\,
      Q => time_out_counter_reg(15),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_7\,
      Q => time_out_counter_reg(16),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_6\,
      Q => time_out_counter_reg(1),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_5\,
      Q => time_out_counter_reg(2),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_4\,
      Q => time_out_counter_reg(3),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_7\,
      Q => time_out_counter_reg(4),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_6\,
      Q => time_out_counter_reg(5),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_5\,
      Q => time_out_counter_reg(6),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_4\,
      Q => time_out_counter_reg(7),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_7\,
      Q => time_out_counter_reg(8),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_6\,
      Q => time_out_counter_reg(9),
      R => \reset_time_out__0\
    );
time_out_wait_bypass_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => \wait_bypass_count[0]_i_4_n_0\,
      I2 => tx_fsm_reset_done_int_s3,
      I3 => run_phase_alignment_int_s3,
      O => time_out_wait_bypass_i_1_n_0
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => time_out_wait_bypass_i_1_n_0,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
\time_tlock_max_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AABAAAAA"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => time_tlock_max_i_2_n_0,
      I2 => time_out_counter_reg(1),
      I3 => \time_out_counter[0]_i_4__3_n_0\,
      I4 => time_tlock_max_i_3_n_0,
      I5 => \reset_time_out__0\,
      O => \time_tlock_max_i_1__3_n_0\
    );
time_tlock_max_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      I2 => time_out_counter_reg(7),
      I3 => time_out_counter_reg(8),
      I4 => time_out_counter_reg(2),
      I5 => time_out_counter_reg(0),
      O => time_tlock_max_i_2_n_0
    );
time_tlock_max_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => time_tlock_max_i_3_n_0
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__3_n_0\,
      Q => time_tlock_max_reg_n_0,
      R => '0'
    );
tx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(2),
      I3 => tx_state(1),
      I4 => \^gt0_tx_fsm_reset_done_out\,
      O => tx_fsm_reset_done_int_i_1_n_0
    );
tx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => tx_fsm_reset_done_int_i_1_n_0,
      Q => \^gt0_tx_fsm_reset_done_out\,
      R => SOFT_RESET_TX_IN
    );
tx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt0_txusrclk_in,
      CE => '1',
      D => tx_fsm_reset_done_int_s2,
      Q => tx_fsm_reset_done_int_s3,
      R => '0'
    );
txresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txresetdone_s2,
      Q => txresetdone_s3,
      R => '0'
    );
\wait_bypass_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4_n_0\,
      I1 => tx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2_n_0\
    );
\wait_bypass_count[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6_n_0\,
      I1 => \wait_bypass_count[0]_i_7_n_0\,
      I2 => \wait_bypass_count[0]_i_8_n_0\,
      I3 => \wait_bypass_count[0]_i_9_n_0\,
      O => \wait_bypass_count[0]_i_4_n_0\
    );
\wait_bypass_count[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5_n_0\
    );
\wait_bypass_count[0]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => wait_bypass_count_reg(4),
      I1 => wait_bypass_count_reg(3),
      I2 => wait_bypass_count_reg(6),
      I3 => wait_bypass_count_reg(5),
      O => \wait_bypass_count[0]_i_6_n_0\
    );
\wait_bypass_count[0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      I1 => wait_bypass_count_reg(15),
      I2 => wait_bypass_count_reg(16),
      I3 => wait_bypass_count_reg(2),
      I4 => wait_bypass_count_reg(1),
      O => \wait_bypass_count[0]_i_7_n_0\
    );
\wait_bypass_count[0]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(12),
      I1 => wait_bypass_count_reg(11),
      I2 => wait_bypass_count_reg(14),
      I3 => wait_bypass_count_reg(13),
      O => \wait_bypass_count[0]_i_8_n_0\
    );
\wait_bypass_count[0]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => wait_bypass_count_reg(8),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(10),
      I3 => wait_bypass_count_reg(9),
      O => \wait_bypass_count[0]_i_9_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(3) => \wait_bypass_count_reg[12]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[12]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[12]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[12]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[12]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[12]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[12]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(15 downto 12)
    );
\wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_6\,
      Q => wait_bypass_count_reg(13),
      R => clear
    );
\wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_5\,
      Q => wait_bypass_count_reg(14),
      R => clear
    );
\wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_4\,
      Q => wait_bypass_count_reg(15),
      R => clear
    );
\wait_bypass_count_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[16]_i_1_n_7\,
      Q => wait_bypass_count_reg(16),
      R => clear
    );
\wait_bypass_count_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[12]_i_1_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[16]_i_1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(16)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt0_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      O => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__3_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 is
  port (
    gt1_gttxreset_in : out STD_LOGIC;
    GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    gt1_txuserrdy_in : out STD_LOGIC;
    gt1_run_tx_phalignment_i : out STD_LOGIC;
    gt1_rst_tx_phalignment_i : out STD_LOGIC;
    run_phase_alignment_int_reg_0 : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC;
    SOFT_RESET_TX_IN : in STD_LOGIC;
    gt0_tx_phalignment_done_i : in STD_LOGIC;
    gt3_run_tx_phalignment_i : in STD_LOGIC;
    gt0_run_tx_phalignment_i : in STD_LOGIC;
    gt2_run_tx_phalignment_i : in STD_LOGIC;
    GT0_QPLLREFCLKLOST_IN : in STD_LOGIC;
    gt1_txresetdone_out : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 : entity is "mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 is
  signal \FSM_sequential_tx_state[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_10__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_7__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_8__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_9__0_n_0\ : STD_LOGIC;
  signal \^gt1_tx_fsm_reset_done_out\ : STD_LOGIC;
  signal \RESET_PHALIGNMENT_i_1__0_n_0\ : STD_LOGIC;
  signal \TXUSERRDY_i_1__0_n_0\ : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal \^gt1_gttxreset_in\ : STD_LOGIC;
  signal \^gt1_rst_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt1_run_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt1_txuserrdy_in\ : STD_LOGIC;
  signal \gttxreset_i_i_1__0_n_0\ : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__0_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__0_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__0_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__0_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pll_reset_asserted_i_1__0_n_0\ : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal \reset_time_out__0\ : STD_LOGIC;
  signal \reset_time_out_i_2__0_n_0\ : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__4_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_2ms_i_1__4_n_0\ : STD_LOGIC;
  signal \time_out_2ms_i_2__0_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal \time_out_500us_i_1__0_n_0\ : STD_LOGIC;
  signal \time_out_500us_i_2__0_n_0\ : STD_LOGIC;
  signal time_out_500us_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__4_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__0_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__0_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__0_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__0_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__0_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__0_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__0_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal \time_tlock_max_i_1__4_n_0\ : STD_LOGIC;
  signal \time_tlock_max_i_2__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max_i_3__0_n_0\ : STD_LOGIC;
  signal time_tlock_max_reg_n_0 : STD_LOGIC;
  signal \tx_fsm_reset_done_int_i_1__0_n_0\ : STD_LOGIC;
  signal tx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal tx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal tx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txresetdone_s2 : STD_LOGIC;
  signal txresetdone_s3 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_8__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_9__0_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__0_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__0_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[16]_i_1__0_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__0_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__0_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__4_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__0_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_wait_bypass_count_reg[16]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[16]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_10__0\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_5__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_8__0\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_9__0\ : label is "soft_lutpair55";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[2]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[3]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of \RESET_PHALIGNMENT_i_1__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \TXUSERRDY_i_1__0\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__0\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__0\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__0\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__0\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__0\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__0\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__0\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__0\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__0\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__0\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__0\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__0\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \run_phase_alignment_int_i_1__4\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \tx_fsm_reset_done_int_i_1__0\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__0\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__0\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__0\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__0\ : label is "soft_lutpair57";
begin
  GT1_TX_FSM_RESET_DONE_OUT <= \^gt1_tx_fsm_reset_done_out\;
  gt1_gttxreset_in <= \^gt1_gttxreset_in\;
  gt1_rst_tx_phalignment_i <= \^gt1_rst_tx_phalignment_i\;
  gt1_run_tx_phalignment_i <= \^gt1_run_tx_phalignment_i\;
  gt1_txuserrdy_in <= \^gt1_txuserrdy_in\;
\FSM_sequential_tx_phalign_manual_state[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^gt1_run_tx_phalignment_i\,
      I1 => gt3_run_tx_phalignment_i,
      I2 => gt0_run_tx_phalignment_i,
      I3 => gt2_run_tx_phalignment_i,
      O => run_phase_alignment_int_reg_0
    );
\FSM_sequential_tx_state[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBBFBBBBBBBFB"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(2),
      I3 => \FSM_sequential_tx_state[2]_i_2__0_n_0\,
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[0]_i_2__0_n_0\,
      O => \tx_state__0\(0)
    );
\FSM_sequential_tx_state[0]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => tx_state(2),
      I3 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_tx_state[0]_i_2__0_n_0\
    );
\FSM_sequential_tx_state[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F00D0"
    )
        port map (
      I0 => tx_state(2),
      I1 => \FSM_sequential_tx_state[2]_i_2__0_n_0\,
      I2 => tx_state(0),
      I3 => tx_state(3),
      I4 => tx_state(1),
      O => \tx_state__0\(1)
    );
\FSM_sequential_tx_state[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010C0C0C010C000C"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[2]_i_2__0_n_0\,
      O => \tx_state__0\(2)
    );
\FSM_sequential_tx_state[2]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[2]_i_2__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_10__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF5D0C0C0C0C0C0C"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => tx_state(3),
      I2 => time_out_wait_bypass_s3,
      I3 => \reset_time_out__0\,
      I4 => \FSM_sequential_tx_state[3]_i_8__0_n_0\,
      I5 => tx_state(2),
      O => \tx_state__0\(3)
    );
\FSM_sequential_tx_state[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001110"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => wait_time_cnt_reg(6),
      I5 => \wait_time_cnt[6]_i_4__0_n_0\,
      O => \FSM_sequential_tx_state[3]_i_3__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040400040000"
    )
        port map (
      I0 => \FSM_sequential_tx_state[3]_i_9__0_n_0\,
      I1 => tx_state(2),
      I2 => tx_state(1),
      I3 => \reset_time_out__0\,
      I4 => time_tlock_max_reg_n_0,
      I5 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[3]_i_4__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_5__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E0E0E02"
    )
        port map (
      I0 => init_wait_done_reg_n_0,
      I1 => tx_state(3),
      I2 => \FSM_sequential_tx_state[3]_i_10__0_n_0\,
      I3 => gt0_tx_phalignment_done_i,
      I4 => time_out_wait_bypass_s3,
      I5 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_7__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(0),
      I2 => tx_state(3),
      O => \FSM_sequential_tx_state[3]_i_8__0_n_0\
    );
\FSM_sequential_tx_state[3]_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_9__0_n_0\
    );
\FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(0),
      Q => tx_state(0),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(1),
      Q => tx_state(1),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(2),
      Q => tx_state(2),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(3),
      Q => tx_state(3),
      R => SOFT_RESET_TX_IN
    );
\RESET_PHALIGNMENT_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt1_rst_tx_phalignment_i\,
      O => \RESET_PHALIGNMENT_i_1__0_n_0\
    );
RESET_PHALIGNMENT_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \RESET_PHALIGNMENT_i_1__0_n_0\,
      Q => \^gt1_rst_tx_phalignment_i\,
      S => SOFT_RESET_TX_IN
    );
\TXUSERRDY_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt1_txuserrdy_in\,
      O => \TXUSERRDY_i_1__0_n_0\
    );
TXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXUSERRDY_i_1__0_n_0\,
      Q => \^gt1_txuserrdy_in\,
      R => SOFT_RESET_TX_IN
    );
\gttxreset_i_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt1_gttxreset_in\,
      O => \gttxreset_i_i_1__0_n_0\
    );
gttxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \gttxreset_i_i_1__0_n_0\,
      Q => \^gt1_gttxreset_in\,
      R => SOFT_RESET_TX_IN
    );
\init_wait_count[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__0_n_0\
    );
\init_wait_count[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_count[0]_i_1__0_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__0_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__0_n_0\
    );
\init_wait_done_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__0_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_done_i_1__0_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__0_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__0_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__0_n_0\
    );
\mmcm_lock_count[7]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__0_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__0_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__0_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
\pll_reset_asserted_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000DFDF0010"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(3),
      I2 => tx_state(0),
      I3 => GT0_QPLLREFCLKLOST_IN,
      I4 => pll_reset_asserted_reg_n_0,
      I5 => tx_state(2),
      O => \pll_reset_asserted_i_1__0_n_0\
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \pll_reset_asserted_i_1__0_n_0\,
      Q => pll_reset_asserted_reg_n_0,
      R => SOFT_RESET_TX_IN
    );
\reset_time_out_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"440000FF50505050"
    )
        port map (
      I0 => tx_state(3),
      I1 => txresetdone_s3,
      I2 => init_wait_done_reg_n_0,
      I3 => tx_state(1),
      I4 => tx_state(2),
      I5 => tx_state(0),
      O => \reset_time_out_i_2__0_n_0\
    );
reset_time_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_QPLLLOCK_n_1,
      Q => \reset_time_out__0\,
      R => SOFT_RESET_TX_IN
    );
\run_phase_alignment_int_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0002"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt1_run_tx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__4_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__4_n_0\,
      Q => \^gt1_run_tx_phalignment_i\,
      R => SOFT_RESET_TX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => data_out,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41
     port map (
      E(0) => sync_QPLLLOCK_n_0,
      \FSM_sequential_tx_state_reg[0]\ => \FSM_sequential_tx_state[3]_i_3__0_n_0\,
      \FSM_sequential_tx_state_reg[0]_0\ => \FSM_sequential_tx_state[3]_i_4__0_n_0\,
      \FSM_sequential_tx_state_reg[0]_1\ => \FSM_sequential_tx_state[3]_i_5__0_n_0\,
      \FSM_sequential_tx_state_reg[0]_2\ => \FSM_sequential_tx_state[3]_i_7__0_n_0\,
      \FSM_sequential_tx_state_reg[0]_3\ => pll_reset_asserted_reg_n_0,
      \FSM_sequential_tx_state_reg[0]_4\ => \FSM_sequential_tx_state[3]_i_9__0_n_0\,
      \FSM_sequential_tx_state_reg[0]_5\ => \FSM_sequential_tx_state[0]_i_2__0_n_0\,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => tx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      \reset_time_out__0\ => \reset_time_out__0\,
      reset_time_out_reg => sync_QPLLLOCK_n_1,
      reset_time_out_reg_0 => init_wait_done_reg_n_0,
      reset_time_out_reg_1 => \reset_time_out_i_2__0_n_0\,
      txresetdone_s3 => txresetdone_s3
    );
sync_TXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => txresetdone_s2,
      gt1_txresetdone_out => gt1_txresetdone_out
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__0_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44
     port map (
      data_in => \^gt1_run_tx_phalignment_i\,
      data_out => data_out,
      gt1_txusrclk_in => gt1_txusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
sync_tx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46
     port map (
      GT1_TX_FSM_RESET_DONE_OUT => \^gt1_tx_fsm_reset_done_out\,
      data_out => tx_fsm_reset_done_int_s2,
      gt1_txusrclk_in => gt1_txusrclk_in
    );
\time_out_2ms_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => \time_out_2ms_i_2__0_n_0\,
      I2 => \time_out_counter[0]_i_3__0_n_0\,
      I3 => \reset_time_out__0\,
      O => \time_out_2ms_i_1__4_n_0\
    );
\time_out_2ms_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(12),
      I4 => \time_out_counter[0]_i_4__4_n_0\,
      O => \time_out_2ms_i_2__0_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__4_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_500us_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAEA"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \time_out_500us_i_2__0_n_0\,
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(3),
      I4 => \time_out_counter[0]_i_3__0_n_0\,
      I5 => \reset_time_out__0\,
      O => \time_out_500us_i_1__0_n_0\
    );
\time_out_500us_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(12),
      I2 => time_out_counter_reg(4),
      I3 => time_out_counter_reg(6),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_500us_i_2__0_n_0\
    );
time_out_500us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_500us_i_1__0_n_0\,
      Q => time_out_500us_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(12),
      I2 => \time_out_counter[0]_i_3__0_n_0\,
      I3 => time_out_counter_reg(15),
      I4 => time_out_counter_reg(16),
      I5 => \time_out_counter[0]_i_4__4_n_0\,
      O => time_out_counter
    );
\time_out_counter[0]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(14),
      I3 => \time_tlock_max_i_2__0_n_0\,
      O => \time_out_counter[0]_i_3__0_n_0\
    );
\time_out_counter[0]_i_4__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(9),
      O => \time_out_counter[0]_i_4__4_n_0\
    );
\time_out_counter[0]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__0_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__0_n_7\,
      Q => time_out_counter_reg(0),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__0_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__0_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__0_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__0_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__0_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__0_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__0_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__0_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__0_n_5\,
      Q => time_out_counter_reg(10),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__0_n_4\,
      Q => time_out_counter_reg(11),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__0_n_7\,
      Q => time_out_counter_reg(12),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__0_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__0_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__0_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__0_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__0_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__0_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__0_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__0_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__0_n_6\,
      Q => time_out_counter_reg(13),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__0_n_5\,
      Q => time_out_counter_reg(14),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__0_n_4\,
      Q => time_out_counter_reg(15),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__0_n_7\,
      Q => time_out_counter_reg(16),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__0_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__0_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__0_n_6\,
      Q => time_out_counter_reg(1),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__0_n_5\,
      Q => time_out_counter_reg(2),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__0_n_4\,
      Q => time_out_counter_reg(3),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__0_n_7\,
      Q => time_out_counter_reg(4),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__0_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__0_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__0_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__0_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__0_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__0_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__0_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__0_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__0_n_6\,
      Q => time_out_counter_reg(5),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__0_n_5\,
      Q => time_out_counter_reg(6),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__0_n_4\,
      Q => time_out_counter_reg(7),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__0_n_7\,
      Q => time_out_counter_reg(8),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__0_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__0_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__0_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__0_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__0_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__0_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__0_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__0_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__0_n_6\,
      Q => time_out_counter_reg(9),
      R => \reset_time_out__0\
    );
\time_out_wait_bypass_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => \wait_bypass_count[0]_i_4__0_n_0\,
      I2 => tx_fsm_reset_done_int_s3,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__0_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__0_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
\time_tlock_max_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AABAAAAA"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \time_tlock_max_i_2__0_n_0\,
      I2 => time_out_counter_reg(1),
      I3 => \time_out_counter[0]_i_4__4_n_0\,
      I4 => \time_tlock_max_i_3__0_n_0\,
      I5 => \reset_time_out__0\,
      O => \time_tlock_max_i_1__4_n_0\
    );
\time_tlock_max_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      I2 => time_out_counter_reg(7),
      I3 => time_out_counter_reg(8),
      I4 => time_out_counter_reg(2),
      I5 => time_out_counter_reg(0),
      O => \time_tlock_max_i_2__0_n_0\
    );
\time_tlock_max_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_tlock_max_i_3__0_n_0\
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__4_n_0\,
      Q => time_tlock_max_reg_n_0,
      R => '0'
    );
\tx_fsm_reset_done_int_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(2),
      I3 => tx_state(1),
      I4 => \^gt1_tx_fsm_reset_done_out\,
      O => \tx_fsm_reset_done_int_i_1__0_n_0\
    );
tx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \tx_fsm_reset_done_int_i_1__0_n_0\,
      Q => \^gt1_tx_fsm_reset_done_out\,
      R => SOFT_RESET_TX_IN
    );
tx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt1_txusrclk_in,
      CE => '1',
      D => tx_fsm_reset_done_int_s2,
      Q => tx_fsm_reset_done_int_s3,
      R => '0'
    );
txresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txresetdone_s2,
      Q => txresetdone_s3,
      R => '0'
    );
\wait_bypass_count[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__0_n_0\,
      I1 => tx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__0_n_0\
    );
\wait_bypass_count[0]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__0_n_0\,
      I1 => \wait_bypass_count[0]_i_7__0_n_0\,
      I2 => \wait_bypass_count[0]_i_8__0_n_0\,
      I3 => \wait_bypass_count[0]_i_9__0_n_0\,
      O => \wait_bypass_count[0]_i_4__0_n_0\
    );
\wait_bypass_count[0]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__0_n_0\
    );
\wait_bypass_count[0]_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => wait_bypass_count_reg(4),
      I1 => wait_bypass_count_reg(3),
      I2 => wait_bypass_count_reg(6),
      I3 => wait_bypass_count_reg(5),
      O => \wait_bypass_count[0]_i_6__0_n_0\
    );
\wait_bypass_count[0]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      I1 => wait_bypass_count_reg(15),
      I2 => wait_bypass_count_reg(16),
      I3 => wait_bypass_count_reg(2),
      I4 => wait_bypass_count_reg(1),
      O => \wait_bypass_count[0]_i_7__0_n_0\
    );
\wait_bypass_count[0]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(12),
      I1 => wait_bypass_count_reg(11),
      I2 => wait_bypass_count_reg(14),
      I3 => wait_bypass_count_reg(13),
      O => \wait_bypass_count[0]_i_8__0_n_0\
    );
\wait_bypass_count[0]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => wait_bypass_count_reg(8),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(10),
      I3 => wait_bypass_count_reg(9),
      O => \wait_bypass_count[0]_i_9__0_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__0_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__0_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__0_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__0_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__0_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__0_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__0_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__0_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__0_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__0_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__0_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__0_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__0_n_0\,
      CO(3) => \wait_bypass_count_reg[12]_i_1__0_n_0\,
      CO(2) => \wait_bypass_count_reg[12]_i_1__0_n_1\,
      CO(1) => \wait_bypass_count_reg[12]_i_1__0_n_2\,
      CO(0) => \wait_bypass_count_reg[12]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[12]_i_1__0_n_4\,
      O(2) => \wait_bypass_count_reg[12]_i_1__0_n_5\,
      O(1) => \wait_bypass_count_reg[12]_i_1__0_n_6\,
      O(0) => \wait_bypass_count_reg[12]_i_1__0_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(15 downto 12)
    );
\wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__0_n_6\,
      Q => wait_bypass_count_reg(13),
      R => clear
    );
\wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__0_n_5\,
      Q => wait_bypass_count_reg(14),
      R => clear
    );
\wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__0_n_4\,
      Q => wait_bypass_count_reg(15),
      R => clear
    );
\wait_bypass_count_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[16]_i_1__0_n_7\,
      Q => wait_bypass_count_reg(16),
      R => clear
    );
\wait_bypass_count_reg[16]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[12]_i_1__0_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[16]_i_1__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[16]_i_1__0_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[16]_i_1__0_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(16)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__0_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__0_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__0_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__0_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__0_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__0_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__0_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__0_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__0_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__0_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__0_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__0_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__0_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__0_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__0_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__0_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__0_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__0_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__0_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__0_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__0_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__0_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__0_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__0_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt1_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__0_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__0_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      O => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt[6]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__0_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__0_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__0_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__4_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__4_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 is
  port (
    gt2_gttxreset_in : out STD_LOGIC;
    GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    gt2_txuserrdy_in : out STD_LOGIC;
    gt2_run_tx_phalignment_i : out STD_LOGIC;
    gt2_rst_tx_phalignment_i : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC;
    SOFT_RESET_TX_IN : in STD_LOGIC;
    gt0_tx_phalignment_done_i : in STD_LOGIC;
    GT0_QPLLREFCLKLOST_IN : in STD_LOGIC;
    gt2_txresetdone_out : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 : entity is "mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 is
  signal \FSM_sequential_tx_state[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_10__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_5__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_7__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_8__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_9__1_n_0\ : STD_LOGIC;
  signal \^gt2_tx_fsm_reset_done_out\ : STD_LOGIC;
  signal \RESET_PHALIGNMENT_i_1__1_n_0\ : STD_LOGIC;
  signal \TXUSERRDY_i_1__1_n_0\ : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal \^gt2_gttxreset_in\ : STD_LOGIC;
  signal \^gt2_rst_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt2_run_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt2_txuserrdy_in\ : STD_LOGIC;
  signal \gttxreset_i_i_1__1_n_0\ : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__1_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__1_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__1_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__1_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pll_reset_asserted_i_1__1_n_0\ : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal \reset_time_out__0\ : STD_LOGIC;
  signal \reset_time_out_i_2__1_n_0\ : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__5_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_2ms_i_1__5_n_0\ : STD_LOGIC;
  signal \time_out_2ms_i_2__1_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal \time_out_500us_i_1__1_n_0\ : STD_LOGIC;
  signal \time_out_500us_i_2__1_n_0\ : STD_LOGIC;
  signal time_out_500us_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__5_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__1_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__1_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__1_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal \time_tlock_max_i_1__5_n_0\ : STD_LOGIC;
  signal \time_tlock_max_i_2__1_n_0\ : STD_LOGIC;
  signal \time_tlock_max_i_3__1_n_0\ : STD_LOGIC;
  signal time_tlock_max_reg_n_0 : STD_LOGIC;
  signal \tx_fsm_reset_done_int_i_1__1_n_0\ : STD_LOGIC;
  signal tx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal tx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal tx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txresetdone_s2 : STD_LOGIC;
  signal txresetdone_s3 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_8__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_9__1_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[16]_i_1__1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__1_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__1_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_wait_bypass_count_reg[16]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[16]_i_1__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[1]_i_1__1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_10__1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_5__1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_8__1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_9__1\ : label is "soft_lutpair84";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[2]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[3]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of \gttxreset_i_i_1__1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \run_phase_alignment_int_i_1__5\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \tx_fsm_reset_done_int_i_1__1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__1\ : label is "soft_lutpair87";
begin
  GT2_TX_FSM_RESET_DONE_OUT <= \^gt2_tx_fsm_reset_done_out\;
  gt2_gttxreset_in <= \^gt2_gttxreset_in\;
  gt2_rst_tx_phalignment_i <= \^gt2_rst_tx_phalignment_i\;
  gt2_run_tx_phalignment_i <= \^gt2_run_tx_phalignment_i\;
  gt2_txuserrdy_in <= \^gt2_txuserrdy_in\;
\FSM_sequential_tx_state[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBBFBBBBBBBFB"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(2),
      I3 => \FSM_sequential_tx_state[2]_i_2__1_n_0\,
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[0]_i_2__1_n_0\,
      O => \tx_state__0\(0)
    );
\FSM_sequential_tx_state[0]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => tx_state(2),
      I3 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_tx_state[0]_i_2__1_n_0\
    );
\FSM_sequential_tx_state[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F00D0"
    )
        port map (
      I0 => tx_state(2),
      I1 => \FSM_sequential_tx_state[2]_i_2__1_n_0\,
      I2 => tx_state(0),
      I3 => tx_state(3),
      I4 => tx_state(1),
      O => \tx_state__0\(1)
    );
\FSM_sequential_tx_state[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010C0C0C010C000C"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[2]_i_2__1_n_0\,
      O => \tx_state__0\(2)
    );
\FSM_sequential_tx_state[2]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[2]_i_2__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_10__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_10__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF5D0C0C0C0C0C0C"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => tx_state(3),
      I2 => time_out_wait_bypass_s3,
      I3 => \reset_time_out__0\,
      I4 => \FSM_sequential_tx_state[3]_i_8__1_n_0\,
      I5 => tx_state(2),
      O => \tx_state__0\(3)
    );
\FSM_sequential_tx_state[3]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001110"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => wait_time_cnt_reg(6),
      I5 => \wait_time_cnt[6]_i_4__1_n_0\,
      O => \FSM_sequential_tx_state[3]_i_3__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040400040000"
    )
        port map (
      I0 => \FSM_sequential_tx_state[3]_i_9__1_n_0\,
      I1 => tx_state(2),
      I2 => tx_state(1),
      I3 => \reset_time_out__0\,
      I4 => time_tlock_max_reg_n_0,
      I5 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[3]_i_4__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_5__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E0E0E02"
    )
        port map (
      I0 => init_wait_done_reg_n_0,
      I1 => tx_state(3),
      I2 => \FSM_sequential_tx_state[3]_i_10__1_n_0\,
      I3 => gt0_tx_phalignment_done_i,
      I4 => time_out_wait_bypass_s3,
      I5 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_7__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_8__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(0),
      I2 => tx_state(3),
      O => \FSM_sequential_tx_state[3]_i_8__1_n_0\
    );
\FSM_sequential_tx_state[3]_i_9__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_9__1_n_0\
    );
\FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(0),
      Q => tx_state(0),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(1),
      Q => tx_state(1),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(2),
      Q => tx_state(2),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(3),
      Q => tx_state(3),
      R => SOFT_RESET_TX_IN
    );
\RESET_PHALIGNMENT_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt2_rst_tx_phalignment_i\,
      O => \RESET_PHALIGNMENT_i_1__1_n_0\
    );
RESET_PHALIGNMENT_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \RESET_PHALIGNMENT_i_1__1_n_0\,
      Q => \^gt2_rst_tx_phalignment_i\,
      S => SOFT_RESET_TX_IN
    );
\TXUSERRDY_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt2_txuserrdy_in\,
      O => \TXUSERRDY_i_1__1_n_0\
    );
TXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXUSERRDY_i_1__1_n_0\,
      Q => \^gt2_txuserrdy_in\,
      R => SOFT_RESET_TX_IN
    );
\gttxreset_i_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt2_gttxreset_in\,
      O => \gttxreset_i_i_1__1_n_0\
    );
gttxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \gttxreset_i_i_1__1_n_0\,
      Q => \^gt2_gttxreset_in\,
      R => SOFT_RESET_TX_IN
    );
\init_wait_count[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__1_n_0\
    );
\init_wait_count[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_count[0]_i_1__1_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__1_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__1_n_0\
    );
\init_wait_done_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__1_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_done_i_1__1_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__1_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__1_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__1_n_0\
    );
\mmcm_lock_count[7]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__1_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__1_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__1_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
\pll_reset_asserted_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000DFDF0010"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(3),
      I2 => tx_state(0),
      I3 => GT0_QPLLREFCLKLOST_IN,
      I4 => pll_reset_asserted_reg_n_0,
      I5 => tx_state(2),
      O => \pll_reset_asserted_i_1__1_n_0\
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \pll_reset_asserted_i_1__1_n_0\,
      Q => pll_reset_asserted_reg_n_0,
      R => SOFT_RESET_TX_IN
    );
\reset_time_out_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"440000FF50505050"
    )
        port map (
      I0 => tx_state(3),
      I1 => txresetdone_s3,
      I2 => init_wait_done_reg_n_0,
      I3 => tx_state(1),
      I4 => tx_state(2),
      I5 => tx_state(0),
      O => \reset_time_out_i_2__1_n_0\
    );
reset_time_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_QPLLLOCK_n_1,
      Q => \reset_time_out__0\,
      R => SOFT_RESET_TX_IN
    );
\run_phase_alignment_int_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0002"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt2_run_tx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__5_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__5_n_0\,
      Q => \^gt2_run_tx_phalignment_i\,
      R => SOFT_RESET_TX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => data_out,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26
     port map (
      E(0) => sync_QPLLLOCK_n_0,
      \FSM_sequential_tx_state_reg[0]\ => \FSM_sequential_tx_state[3]_i_3__1_n_0\,
      \FSM_sequential_tx_state_reg[0]_0\ => \FSM_sequential_tx_state[3]_i_4__1_n_0\,
      \FSM_sequential_tx_state_reg[0]_1\ => \FSM_sequential_tx_state[3]_i_5__1_n_0\,
      \FSM_sequential_tx_state_reg[0]_2\ => \FSM_sequential_tx_state[3]_i_7__1_n_0\,
      \FSM_sequential_tx_state_reg[0]_3\ => pll_reset_asserted_reg_n_0,
      \FSM_sequential_tx_state_reg[0]_4\ => \FSM_sequential_tx_state[3]_i_9__1_n_0\,
      \FSM_sequential_tx_state_reg[0]_5\ => \FSM_sequential_tx_state[0]_i_2__1_n_0\,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => tx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      \reset_time_out__0\ => \reset_time_out__0\,
      reset_time_out_reg => sync_QPLLLOCK_n_1,
      reset_time_out_reg_0 => init_wait_done_reg_n_0,
      reset_time_out_reg_1 => \reset_time_out_i_2__1_n_0\,
      txresetdone_s3 => txresetdone_s3
    );
sync_TXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => txresetdone_s2,
      gt2_txresetdone_out => gt2_txresetdone_out
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__1_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29
     port map (
      data_out => data_out,
      gt2_run_tx_phalignment_i => \^gt2_run_tx_phalignment_i\,
      gt2_txusrclk_in => gt2_txusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
sync_tx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31
     port map (
      GT2_TX_FSM_RESET_DONE_OUT => \^gt2_tx_fsm_reset_done_out\,
      data_out => tx_fsm_reset_done_int_s2,
      gt2_txusrclk_in => gt2_txusrclk_in
    );
\time_out_2ms_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => \time_out_2ms_i_2__1_n_0\,
      I2 => \time_out_counter[0]_i_3__1_n_0\,
      I3 => \reset_time_out__0\,
      O => \time_out_2ms_i_1__5_n_0\
    );
\time_out_2ms_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(12),
      I4 => \time_out_counter[0]_i_4__5_n_0\,
      O => \time_out_2ms_i_2__1_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__5_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_500us_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAEA"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \time_out_500us_i_2__1_n_0\,
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(3),
      I4 => \time_out_counter[0]_i_3__1_n_0\,
      I5 => \reset_time_out__0\,
      O => \time_out_500us_i_1__1_n_0\
    );
\time_out_500us_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(12),
      I2 => time_out_counter_reg(4),
      I3 => time_out_counter_reg(6),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_500us_i_2__1_n_0\
    );
time_out_500us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_500us_i_1__1_n_0\,
      Q => time_out_500us_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(12),
      I2 => \time_out_counter[0]_i_3__1_n_0\,
      I3 => time_out_counter_reg(15),
      I4 => time_out_counter_reg(16),
      I5 => \time_out_counter[0]_i_4__5_n_0\,
      O => time_out_counter
    );
\time_out_counter[0]_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(14),
      I3 => \time_tlock_max_i_2__1_n_0\,
      O => \time_out_counter[0]_i_3__1_n_0\
    );
\time_out_counter[0]_i_4__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(9),
      O => \time_out_counter[0]_i_4__5_n_0\
    );
\time_out_counter[0]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__1_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__1_n_7\,
      Q => time_out_counter_reg(0),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[0]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__1_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__1_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__1_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__1_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__1_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__1_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__1_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__1_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__1_n_5\,
      Q => time_out_counter_reg(10),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__1_n_4\,
      Q => time_out_counter_reg(11),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__1_n_7\,
      Q => time_out_counter_reg(12),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__1_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__1_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__1_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__1_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__1_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__1_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__1_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__1_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__1_n_6\,
      Q => time_out_counter_reg(13),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__1_n_5\,
      Q => time_out_counter_reg(14),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__1_n_4\,
      Q => time_out_counter_reg(15),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__1_n_7\,
      Q => time_out_counter_reg(16),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__1_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__1_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__1_n_6\,
      Q => time_out_counter_reg(1),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__1_n_5\,
      Q => time_out_counter_reg(2),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__1_n_4\,
      Q => time_out_counter_reg(3),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__1_n_7\,
      Q => time_out_counter_reg(4),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__1_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__1_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__1_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__1_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__1_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__1_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__1_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__1_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__1_n_6\,
      Q => time_out_counter_reg(5),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__1_n_5\,
      Q => time_out_counter_reg(6),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__1_n_4\,
      Q => time_out_counter_reg(7),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__1_n_7\,
      Q => time_out_counter_reg(8),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__1_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__1_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__1_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__1_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__1_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__1_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__1_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__1_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__1_n_6\,
      Q => time_out_counter_reg(9),
      R => \reset_time_out__0\
    );
\time_out_wait_bypass_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => \wait_bypass_count[0]_i_4__1_n_0\,
      I2 => tx_fsm_reset_done_int_s3,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__1_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__1_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
\time_tlock_max_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AABAAAAA"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \time_tlock_max_i_2__1_n_0\,
      I2 => time_out_counter_reg(1),
      I3 => \time_out_counter[0]_i_4__5_n_0\,
      I4 => \time_tlock_max_i_3__1_n_0\,
      I5 => \reset_time_out__0\,
      O => \time_tlock_max_i_1__5_n_0\
    );
\time_tlock_max_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      I2 => time_out_counter_reg(7),
      I3 => time_out_counter_reg(8),
      I4 => time_out_counter_reg(2),
      I5 => time_out_counter_reg(0),
      O => \time_tlock_max_i_2__1_n_0\
    );
\time_tlock_max_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_tlock_max_i_3__1_n_0\
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__5_n_0\,
      Q => time_tlock_max_reg_n_0,
      R => '0'
    );
\tx_fsm_reset_done_int_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(2),
      I3 => tx_state(1),
      I4 => \^gt2_tx_fsm_reset_done_out\,
      O => \tx_fsm_reset_done_int_i_1__1_n_0\
    );
tx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \tx_fsm_reset_done_int_i_1__1_n_0\,
      Q => \^gt2_tx_fsm_reset_done_out\,
      R => SOFT_RESET_TX_IN
    );
tx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt2_txusrclk_in,
      CE => '1',
      D => tx_fsm_reset_done_int_s2,
      Q => tx_fsm_reset_done_int_s3,
      R => '0'
    );
txresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txresetdone_s2,
      Q => txresetdone_s3,
      R => '0'
    );
\wait_bypass_count[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__1_n_0\,
      I1 => tx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__1_n_0\
    );
\wait_bypass_count[0]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__1_n_0\,
      I1 => \wait_bypass_count[0]_i_7__1_n_0\,
      I2 => \wait_bypass_count[0]_i_8__1_n_0\,
      I3 => \wait_bypass_count[0]_i_9__1_n_0\,
      O => \wait_bypass_count[0]_i_4__1_n_0\
    );
\wait_bypass_count[0]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__1_n_0\
    );
\wait_bypass_count[0]_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => wait_bypass_count_reg(4),
      I1 => wait_bypass_count_reg(3),
      I2 => wait_bypass_count_reg(6),
      I3 => wait_bypass_count_reg(5),
      O => \wait_bypass_count[0]_i_6__1_n_0\
    );
\wait_bypass_count[0]_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      I1 => wait_bypass_count_reg(15),
      I2 => wait_bypass_count_reg(16),
      I3 => wait_bypass_count_reg(2),
      I4 => wait_bypass_count_reg(1),
      O => \wait_bypass_count[0]_i_7__1_n_0\
    );
\wait_bypass_count[0]_i_8__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(12),
      I1 => wait_bypass_count_reg(11),
      I2 => wait_bypass_count_reg(14),
      I3 => wait_bypass_count_reg(13),
      O => \wait_bypass_count[0]_i_8__1_n_0\
    );
\wait_bypass_count[0]_i_9__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => wait_bypass_count_reg(8),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(10),
      I3 => wait_bypass_count_reg(9),
      O => \wait_bypass_count[0]_i_9__1_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__1_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__1_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__1_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__1_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__1_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__1_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__1_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__1_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__1_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__1_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__1_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__1_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__1_n_0\,
      CO(3) => \wait_bypass_count_reg[12]_i_1__1_n_0\,
      CO(2) => \wait_bypass_count_reg[12]_i_1__1_n_1\,
      CO(1) => \wait_bypass_count_reg[12]_i_1__1_n_2\,
      CO(0) => \wait_bypass_count_reg[12]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[12]_i_1__1_n_4\,
      O(2) => \wait_bypass_count_reg[12]_i_1__1_n_5\,
      O(1) => \wait_bypass_count_reg[12]_i_1__1_n_6\,
      O(0) => \wait_bypass_count_reg[12]_i_1__1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(15 downto 12)
    );
\wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__1_n_6\,
      Q => wait_bypass_count_reg(13),
      R => clear
    );
\wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__1_n_5\,
      Q => wait_bypass_count_reg(14),
      R => clear
    );
\wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__1_n_4\,
      Q => wait_bypass_count_reg(15),
      R => clear
    );
\wait_bypass_count_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[16]_i_1__1_n_7\,
      Q => wait_bypass_count_reg(16),
      R => clear
    );
\wait_bypass_count_reg[16]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[12]_i_1__1_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[16]_i_1__1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[16]_i_1__1_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[16]_i_1__1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(16)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__1_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__1_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__1_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__1_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__1_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__1_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__1_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__1_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__1_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__1_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__1_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__1_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__1_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__1_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__1_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__1_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__1_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__1_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__1_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__1_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__1_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__1_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt2_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__1_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__1_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      O => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt[6]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__1_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__1_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__1_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__5_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__5_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 is
  port (
    gt3_gttxreset_in : out STD_LOGIC;
    GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    gt3_txuserrdy_in : out STD_LOGIC;
    gt3_run_tx_phalignment_i : out STD_LOGIC;
    RESET_PHALIGNMENT : out STD_LOGIC;
    run_phase_alignment_int_reg_0 : out STD_LOGIC;
    SYSCLK_IN : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC;
    SOFT_RESET_TX_IN : in STD_LOGIC;
    gt0_rst_tx_phalignment_i : in STD_LOGIC;
    gt1_rst_tx_phalignment_i : in STD_LOGIC;
    gt2_rst_tx_phalignment_i : in STD_LOGIC;
    gt0_tx_phalignment_done_i : in STD_LOGIC;
    gt0_run_tx_phalignment_i : in STD_LOGIC;
    GT0_QPLLREFCLKLOST_IN : in STD_LOGIC;
    gt3_txresetdone_out : in STD_LOGIC;
    GT0_QPLLLOCK_IN : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 : entity is "mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 is
  signal \FSM_sequential_tx_state[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_10__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_5__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_7__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_8__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[3]_i_9__2_n_0\ : STD_LOGIC;
  signal \^gt3_tx_fsm_reset_done_out\ : STD_LOGIC;
  signal \RESET_PHALIGNMENT_i_1__2_n_0\ : STD_LOGIC;
  signal \TXUSERRDY_i_1__2_n_0\ : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal data_out : STD_LOGIC;
  signal \^gt3_gttxreset_in\ : STD_LOGIC;
  signal gt3_rst_tx_phalignment_i : STD_LOGIC;
  signal \^gt3_run_tx_phalignment_i\ : STD_LOGIC;
  signal \^gt3_txuserrdy_in\ : STD_LOGIC;
  signal \gttxreset_i_i_1__2_n_0\ : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1__2_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_wait_done_i_1__2_n_0\ : STD_LOGIC;
  signal \init_wait_done_i_2__2_n_0\ : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_4__2_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pll_reset_asserted_i_1__2_n_0\ : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal \reset_time_out__0\ : STD_LOGIC;
  signal \reset_time_out_i_2__2_n_0\ : STD_LOGIC;
  signal \run_phase_alignment_int_i_1__6_n_0\ : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_QPLLLOCK_n_0 : STD_LOGIC;
  signal sync_QPLLLOCK_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC;
  signal \time_out_2ms_i_1__6_n_0\ : STD_LOGIC;
  signal \time_out_2ms_i_2__2_n_0\ : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal \time_out_500us_i_1__2_n_0\ : STD_LOGIC;
  signal \time_out_500us_i_2__2_n_0\ : STD_LOGIC;
  signal time_out_500us_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4__6_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5__2_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \time_out_counter_reg[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2__2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1__2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1__2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1__2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1__2_n_7\ : STD_LOGIC;
  signal \time_out_wait_bypass_i_1__2_n_0\ : STD_LOGIC;
  signal time_out_wait_bypass_reg_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal \time_tlock_max_i_1__6_n_0\ : STD_LOGIC;
  signal \time_tlock_max_i_2__2_n_0\ : STD_LOGIC;
  signal \time_tlock_max_i_3__2_n_0\ : STD_LOGIC;
  signal time_tlock_max_reg_n_0 : STD_LOGIC;
  signal \tx_fsm_reset_done_int_i_1__2_n_0\ : STD_LOGIC;
  signal tx_fsm_reset_done_int_s2 : STD_LOGIC;
  signal tx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal tx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txresetdone_s2 : STD_LOGIC;
  signal txresetdone_s3 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_8__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_9__2_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3__2_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1__2_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[16]_i_1__2_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1__2_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1__2_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1__6_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4__2_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_wait_bypass_count_reg[16]_i_1__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[16]_i_1__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[1]_i_1__2\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_10__2\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_5__2\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_8__2\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_9__2\ : label is "soft_lutpair113";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[2]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[3]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of \RESET_PHALIGNMENT_i_1__2\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \TXUSERRDY_i_1__2\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1__2\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__2\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__2\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__2\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__2\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \init_wait_done_i_2__2\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__2\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__2\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__2\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__2\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__2\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__2\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \run_phase_alignment_int_i_1__6\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__2\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__2\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__2\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__2\ : label is "soft_lutpair117";
begin
  GT3_TX_FSM_RESET_DONE_OUT <= \^gt3_tx_fsm_reset_done_out\;
  gt3_gttxreset_in <= \^gt3_gttxreset_in\;
  gt3_run_tx_phalignment_i <= \^gt3_run_tx_phalignment_i\;
  gt3_txuserrdy_in <= \^gt3_txuserrdy_in\;
\FSM_sequential_tx_phalign_manual_state[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => gt3_rst_tx_phalignment_i,
      I1 => gt0_rst_tx_phalignment_i,
      I2 => gt1_rst_tx_phalignment_i,
      I3 => gt2_rst_tx_phalignment_i,
      O => RESET_PHALIGNMENT
    );
\FSM_sequential_tx_state[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBBFBBBBBBBFB"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(2),
      I3 => \FSM_sequential_tx_state[2]_i_2__2_n_0\,
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[0]_i_2__2_n_0\,
      O => \tx_state__0\(0)
    );
\FSM_sequential_tx_state[0]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => tx_state(2),
      I3 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_tx_state[0]_i_2__2_n_0\
    );
\FSM_sequential_tx_state[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F00D0"
    )
        port map (
      I0 => tx_state(2),
      I1 => \FSM_sequential_tx_state[2]_i_2__2_n_0\,
      I2 => tx_state(0),
      I3 => tx_state(3),
      I4 => tx_state(1),
      O => \tx_state__0\(1)
    );
\FSM_sequential_tx_state[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010C0C0C010C000C"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      I4 => tx_state(1),
      I5 => \FSM_sequential_tx_state[2]_i_2__2_n_0\,
      O => \tx_state__0\(2)
    );
\FSM_sequential_tx_state[2]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \reset_time_out__0\,
      I2 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[2]_i_2__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_10__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_10__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF5D0C0C0C0C0C0C"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => tx_state(3),
      I2 => time_out_wait_bypass_s3,
      I3 => \reset_time_out__0\,
      I4 => \FSM_sequential_tx_state[3]_i_8__2_n_0\,
      I5 => tx_state(2),
      O => \tx_state__0\(3)
    );
\FSM_sequential_tx_state[3]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001110"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => wait_time_cnt_reg(6),
      I5 => \wait_time_cnt[6]_i_4__2_n_0\,
      O => \FSM_sequential_tx_state[3]_i_3__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040400040000"
    )
        port map (
      I0 => \FSM_sequential_tx_state[3]_i_9__2_n_0\,
      I1 => tx_state(2),
      I2 => tx_state(1),
      I3 => \reset_time_out__0\,
      I4 => time_tlock_max_reg_n_0,
      I5 => mmcm_lock_reclocked,
      O => \FSM_sequential_tx_state[3]_i_4__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      O => \FSM_sequential_tx_state[3]_i_5__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_7__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E0E0E02"
    )
        port map (
      I0 => init_wait_done_reg_n_0,
      I1 => tx_state(3),
      I2 => \FSM_sequential_tx_state[3]_i_10__2_n_0\,
      I3 => gt0_tx_phalignment_done_i,
      I4 => time_out_wait_bypass_s3,
      I5 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_7__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_8__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(0),
      I2 => tx_state(3),
      O => \FSM_sequential_tx_state[3]_i_8__2_n_0\
    );
\FSM_sequential_tx_state[3]_i_9__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      O => \FSM_sequential_tx_state[3]_i_9__2_n_0\
    );
\FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(0),
      Q => tx_state(0),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(1),
      Q => tx_state(1),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(2),
      Q => tx_state(2),
      R => SOFT_RESET_TX_IN
    );
\FSM_sequential_tx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => sync_QPLLLOCK_n_0,
      D => \tx_state__0\(3),
      Q => tx_state(3),
      R => SOFT_RESET_TX_IN
    );
\RESET_PHALIGNMENT_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => gt3_rst_tx_phalignment_i,
      O => \RESET_PHALIGNMENT_i_1__2_n_0\
    );
RESET_PHALIGNMENT_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \RESET_PHALIGNMENT_i_1__2_n_0\,
      Q => gt3_rst_tx_phalignment_i,
      S => SOFT_RESET_TX_IN
    );
\TXUSERRDY_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB4000"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt3_txuserrdy_in\,
      O => \TXUSERRDY_i_1__2_n_0\
    );
TXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \TXUSERRDY_i_1__2_n_0\,
      Q => \^gt3_txuserrdy_in\,
      R => SOFT_RESET_TX_IN
    );
\gttxreset_i_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0004"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt3_gttxreset_in\,
      O => \gttxreset_i_i_1__2_n_0\
    );
gttxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \gttxreset_i_i_1__2_n_0\,
      Q => \^gt3_gttxreset_in\,
      R => SOFT_RESET_TX_IN
    );
\init_wait_count[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1__2_n_0\
    );
\init_wait_count[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => init_wait_count
    );
\init_wait_count[5]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(0),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(3),
      O => p_0_in(5)
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_count[0]_i_1__2_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => init_wait_count,
      CLR => SOFT_RESET_TX_IN,
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_done_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => \init_wait_done_i_2__2_n_0\,
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(3),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_done_reg_n_0,
      O => \init_wait_done_i_1__2_n_0\
    );
\init_wait_done_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      O => \init_wait_done_i_2__2_n_0\
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      CLR => SOFT_RESET_TX_IN,
      D => \init_wait_done_i_1__2_n_0\,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__0\(2)
    );
\mmcm_lock_count[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__0\(3)
    );
\mmcm_lock_count[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__0\(4)
    );
\mmcm_lock_count[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__0\(5)
    );
\mmcm_lock_count[6]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__2_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__0\(6)
    );
\mmcm_lock_count[7]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \mmcm_lock_count[7]_i_4__2_n_0\,
      I1 => mmcm_lock_count_reg(6),
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_2__2_n_0\
    );
\mmcm_lock_count[7]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[7]_i_4__2_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__0\(7)
    );
\mmcm_lock_count[7]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[7]_i_4__2_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => \mmcm_lock_count[7]_i_2__2_n_0\,
      D => \p_0_in__0\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_mmcm_lock_reclocked_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
\pll_reset_asserted_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000DFDF0010"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(3),
      I2 => tx_state(0),
      I3 => GT0_QPLLREFCLKLOST_IN,
      I4 => pll_reset_asserted_reg_n_0,
      I5 => tx_state(2),
      O => \pll_reset_asserted_i_1__2_n_0\
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \pll_reset_asserted_i_1__2_n_0\,
      Q => pll_reset_asserted_reg_n_0,
      R => SOFT_RESET_TX_IN
    );
\reset_time_out_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"440000FF50505050"
    )
        port map (
      I0 => tx_state(3),
      I1 => txresetdone_s3,
      I2 => init_wait_done_reg_n_0,
      I3 => tx_state(1),
      I4 => tx_state(2),
      I5 => tx_state(0),
      O => \reset_time_out_i_2__2_n_0\
    );
reset_time_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => sync_QPLLLOCK_n_1,
      Q => \reset_time_out__0\,
      R => SOFT_RESET_TX_IN
    );
\run_phase_alignment_int_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0002"
    )
        port map (
      I0 => tx_state(3),
      I1 => tx_state(0),
      I2 => tx_state(1),
      I3 => tx_state(2),
      I4 => \^gt3_run_tx_phalignment_i\,
      O => \run_phase_alignment_int_i_1__6_n_0\
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \run_phase_alignment_int_i_1__6_n_0\,
      Q => \^gt3_run_tx_phalignment_i\,
      R => SOFT_RESET_TX_IN
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => data_out,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
sync_QPLLLOCK: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block
     port map (
      E(0) => sync_QPLLLOCK_n_0,
      \FSM_sequential_tx_state_reg[0]\ => \FSM_sequential_tx_state[3]_i_3__2_n_0\,
      \FSM_sequential_tx_state_reg[0]_0\ => \FSM_sequential_tx_state[3]_i_4__2_n_0\,
      \FSM_sequential_tx_state_reg[0]_1\ => \FSM_sequential_tx_state[3]_i_5__2_n_0\,
      \FSM_sequential_tx_state_reg[0]_2\ => \FSM_sequential_tx_state[3]_i_7__2_n_0\,
      \FSM_sequential_tx_state_reg[0]_3\ => pll_reset_asserted_reg_n_0,
      \FSM_sequential_tx_state_reg[0]_4\ => \FSM_sequential_tx_state[3]_i_9__2_n_0\,
      \FSM_sequential_tx_state_reg[0]_5\ => \FSM_sequential_tx_state[0]_i_2__2_n_0\,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      Q(3 downto 0) => tx_state(3 downto 0),
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      \reset_time_out__0\ => \reset_time_out__0\,
      reset_time_out_reg => sync_QPLLLOCK_n_1,
      reset_time_out_reg_0 => init_wait_done_reg_n_0,
      reset_time_out_reg_1 => \reset_time_out_i_2__2_n_0\,
      txresetdone_s3 => txresetdone_s3
    );
sync_TXRESETDONE: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_out => txresetdone_s2,
      gt3_txresetdone_out => gt3_txresetdone_out
    );
sync_mmcm_lock_reclocked: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13
     port map (
      Q(1 downto 0) => mmcm_lock_count_reg(7 downto 6),
      SR(0) => sync_mmcm_lock_reclocked_n_0,
      SYSCLK_IN => SYSCLK_IN,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1,
      mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__2_n_0\
    );
sync_run_phase_alignment_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14
     port map (
      data_in => \^gt3_run_tx_phalignment_i\,
      data_out => data_out,
      gt3_txusrclk_in => gt3_txusrclk_in
    );
sync_time_out_wait_bypass: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15
     port map (
      SYSCLK_IN => SYSCLK_IN,
      data_in => time_out_wait_bypass_reg_n_0,
      data_out => time_out_wait_bypass_s2
    );
sync_tx_fsm_reset_done_int: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16
     port map (
      GT3_TX_FSM_RESET_DONE_OUT => \^gt3_tx_fsm_reset_done_out\,
      data_out => tx_fsm_reset_done_int_s2,
      gt3_txusrclk_in => gt3_txusrclk_in
    );
\time_out_2ms_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => \time_out_2ms_i_2__2_n_0\,
      I2 => \time_out_counter[0]_i_3__2_n_0\,
      I3 => \reset_time_out__0\,
      O => \time_out_2ms_i_1__6_n_0\
    );
\time_out_2ms_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(12),
      I4 => \time_out_counter[0]_i_4__6_n_0\,
      O => \time_out_2ms_i_2__2_n_0\
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_2ms_i_1__6_n_0\,
      Q => time_out_2ms_reg_n_0,
      R => '0'
    );
\time_out_500us_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAEA"
    )
        port map (
      I0 => time_out_500us_reg_n_0,
      I1 => \time_out_500us_i_2__2_n_0\,
      I2 => time_out_counter_reg(1),
      I3 => time_out_counter_reg(3),
      I4 => \time_out_counter[0]_i_3__2_n_0\,
      I5 => \reset_time_out__0\,
      O => \time_out_500us_i_1__2_n_0\
    );
\time_out_500us_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(12),
      I2 => time_out_counter_reg(4),
      I3 => time_out_counter_reg(6),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_out_500us_i_2__2_n_0\
    );
time_out_500us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_out_500us_i_1__2_n_0\,
      Q => time_out_500us_reg_n_0,
      R => '0'
    );
\time_out_counter[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(12),
      I2 => \time_out_counter[0]_i_3__2_n_0\,
      I3 => time_out_counter_reg(15),
      I4 => time_out_counter_reg(16),
      I5 => \time_out_counter[0]_i_4__6_n_0\,
      O => time_out_counter
    );
\time_out_counter[0]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBF"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(14),
      I3 => \time_tlock_max_i_2__2_n_0\,
      O => \time_out_counter[0]_i_3__2_n_0\
    );
\time_out_counter[0]_i_4__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => time_out_counter_reg(3),
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(6),
      I3 => time_out_counter_reg(9),
      O => \time_out_counter[0]_i_4__6_n_0\
    );
\time_out_counter[0]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5__2_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__2_n_7\,
      Q => time_out_counter_reg(0),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[0]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2__2_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2__2_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2__2_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2__2_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2__2_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2__2_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2__2_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5__2_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__2_n_5\,
      Q => time_out_counter_reg(10),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__2_n_4\,
      Q => time_out_counter_reg(11),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__2_n_7\,
      Q => time_out_counter_reg(12),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[12]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1__2_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1__2_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1__2_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1__2_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1__2_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1__2_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1__2_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1__2_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__2_n_6\,
      Q => time_out_counter_reg(13),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__2_n_5\,
      Q => time_out_counter_reg(14),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1__2_n_4\,
      Q => time_out_counter_reg(15),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1__2_n_7\,
      Q => time_out_counter_reg(16),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[16]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1__2_n_0\,
      CO(3 downto 0) => \NLW_time_out_counter_reg[16]_i_1__2_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_time_out_counter_reg[16]_i_1__2_O_UNCONNECTED\(3 downto 1),
      O(0) => \time_out_counter_reg[16]_i_1__2_n_7\,
      S(3 downto 1) => B"000",
      S(0) => time_out_counter_reg(16)
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__2_n_6\,
      Q => time_out_counter_reg(1),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__2_n_5\,
      Q => time_out_counter_reg(2),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2__2_n_4\,
      Q => time_out_counter_reg(3),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__2_n_7\,
      Q => time_out_counter_reg(4),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[4]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2__2_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1__2_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1__2_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1__2_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1__2_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1__2_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1__2_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1__2_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__2_n_6\,
      Q => time_out_counter_reg(5),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__2_n_5\,
      Q => time_out_counter_reg(6),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1__2_n_4\,
      Q => time_out_counter_reg(7),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__2_n_7\,
      Q => time_out_counter_reg(8),
      R => \reset_time_out__0\
    );
\time_out_counter_reg[8]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1__2_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1__2_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1__2_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1__2_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1__2_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1__2_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1__2_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1__2_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1__2_n_6\,
      Q => time_out_counter_reg(9),
      R => \reset_time_out__0\
    );
\time_out_wait_bypass_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass_reg_n_0,
      I1 => \wait_bypass_count[0]_i_4__2_n_0\,
      I2 => tx_fsm_reset_done_int_s3,
      I3 => run_phase_alignment_int_s3,
      O => \time_out_wait_bypass_i_1__2_n_0\
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => \time_out_wait_bypass_i_1__2_n_0\,
      Q => time_out_wait_bypass_reg_n_0,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
\time_tlock_max_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AABAAAAA"
    )
        port map (
      I0 => time_tlock_max_reg_n_0,
      I1 => \time_tlock_max_i_2__2_n_0\,
      I2 => time_out_counter_reg(1),
      I3 => \time_out_counter[0]_i_4__6_n_0\,
      I4 => \time_tlock_max_i_3__2_n_0\,
      I5 => \reset_time_out__0\,
      O => \time_tlock_max_i_1__6_n_0\
    );
\time_tlock_max_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      I2 => time_out_counter_reg(7),
      I3 => time_out_counter_reg(8),
      I4 => time_out_counter_reg(2),
      I5 => time_out_counter_reg(0),
      O => \time_tlock_max_i_2__2_n_0\
    );
\time_tlock_max_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(14),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(12),
      I4 => time_out_counter_reg(16),
      I5 => time_out_counter_reg(15),
      O => \time_tlock_max_i_3__2_n_0\
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \time_tlock_max_i_1__6_n_0\,
      Q => time_tlock_max_reg_n_0,
      R => '0'
    );
\tx_fsm_reset_done_int_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => tx_state(0),
      I1 => tx_state(3),
      I2 => tx_state(2),
      I3 => tx_state(1),
      I4 => \^gt3_tx_fsm_reset_done_out\,
      O => \tx_fsm_reset_done_int_i_1__2_n_0\
    );
tx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => \tx_fsm_reset_done_int_i_1__2_n_0\,
      Q => \^gt3_tx_fsm_reset_done_out\,
      R => SOFT_RESET_TX_IN
    );
tx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt3_txusrclk_in,
      CE => '1',
      D => tx_fsm_reset_done_int_s2,
      Q => tx_fsm_reset_done_int_s3,
      R => '0'
    );
txdone_clear_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt3_run_tx_phalignment_i\,
      I1 => gt0_run_tx_phalignment_i,
      O => run_phase_alignment_int_reg_0
    );
txresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => '1',
      D => txresetdone_s2,
      Q => txresetdone_s3,
      R => '0'
    );
\wait_bypass_count[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4__2_n_0\,
      I1 => tx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2__2_n_0\
    );
\wait_bypass_count[0]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6__2_n_0\,
      I1 => \wait_bypass_count[0]_i_7__2_n_0\,
      I2 => \wait_bypass_count[0]_i_8__2_n_0\,
      I3 => \wait_bypass_count[0]_i_9__2_n_0\,
      O => \wait_bypass_count[0]_i_4__2_n_0\
    );
\wait_bypass_count[0]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5__2_n_0\
    );
\wait_bypass_count[0]_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => wait_bypass_count_reg(4),
      I1 => wait_bypass_count_reg(3),
      I2 => wait_bypass_count_reg(6),
      I3 => wait_bypass_count_reg(5),
      O => \wait_bypass_count[0]_i_6__2_n_0\
    );
\wait_bypass_count[0]_i_7__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      I1 => wait_bypass_count_reg(15),
      I2 => wait_bypass_count_reg(16),
      I3 => wait_bypass_count_reg(2),
      I4 => wait_bypass_count_reg(1),
      O => \wait_bypass_count[0]_i_7__2_n_0\
    );
\wait_bypass_count[0]_i_8__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(12),
      I1 => wait_bypass_count_reg(11),
      I2 => wait_bypass_count_reg(14),
      I3 => wait_bypass_count_reg(13),
      O => \wait_bypass_count[0]_i_8__2_n_0\
    );
\wait_bypass_count[0]_i_9__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => wait_bypass_count_reg(8),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(10),
      I3 => wait_bypass_count_reg(9),
      O => \wait_bypass_count[0]_i_9__2_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__2_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3__2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3__2_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3__2_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3__2_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3__2_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3__2_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3__2_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3__2_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5__2_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__2_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__2_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__2_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1__2_n_0\,
      CO(3) => \wait_bypass_count_reg[12]_i_1__2_n_0\,
      CO(2) => \wait_bypass_count_reg[12]_i_1__2_n_1\,
      CO(1) => \wait_bypass_count_reg[12]_i_1__2_n_2\,
      CO(0) => \wait_bypass_count_reg[12]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[12]_i_1__2_n_4\,
      O(2) => \wait_bypass_count_reg[12]_i_1__2_n_5\,
      O(1) => \wait_bypass_count_reg[12]_i_1__2_n_6\,
      O(0) => \wait_bypass_count_reg[12]_i_1__2_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(15 downto 12)
    );
\wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__2_n_6\,
      Q => wait_bypass_count_reg(13),
      R => clear
    );
\wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__2_n_5\,
      Q => wait_bypass_count_reg(14),
      R => clear
    );
\wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1__2_n_4\,
      Q => wait_bypass_count_reg(15),
      R => clear
    );
\wait_bypass_count_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[16]_i_1__2_n_7\,
      Q => wait_bypass_count_reg(16),
      R => clear
    );
\wait_bypass_count_reg[16]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[12]_i_1__2_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[16]_i_1__2_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[16]_i_1__2_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[16]_i_1__2_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(16)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__2_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__2_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3__2_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__2_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3__2_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1__2_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1__2_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1__2_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1__2_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1__2_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1__2_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1__2_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__2_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__2_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1__2_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__2_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1__2_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1__2_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1__2_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1__2_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1__2_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1__2_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1__2_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1__2_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => gt3_txusrclk_in,
      CE => \wait_bypass_count[0]_i_2__2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1__2_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => tx_state(1),
      I1 => tx_state(2),
      I2 => tx_state(3),
      I3 => tx_state(0),
      O => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt[6]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4__2_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4__2_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4__2_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1__6_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => SYSCLK_IN,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1__6_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt is
  port (
    gt3_rxphaligndone_out : out STD_LOGIC;
    gt1_rxphaligndone_out : out STD_LOGIC;
    gt2_rxphaligndone_out : out STD_LOGIC;
    gt0_drpclk_in_0 : out STD_LOGIC;
    gt0_txphinitdone_out : out STD_LOGIC;
    gt1_drpclk_in_0 : out STD_LOGIC;
    gt1_txphinitdone_out : out STD_LOGIC;
    gt2_drpclk_in_0 : out STD_LOGIC;
    gt2_txphinitdone_out : out STD_LOGIC;
    gt3_drpclk_in_0 : out STD_LOGIC;
    gt3_txphinitdone_out : out STD_LOGIC;
    gt0_drprdy_out : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_gthtxn_out : out STD_LOGIC;
    gt0_gthtxp_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxbyterealign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxdlysresetdone_out : out STD_LOGIC;
    gt0_rxoutclk_out : out STD_LOGIC;
    gt0_rxoutclkfabric_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_rxsyncdone_out : out STD_LOGIC;
    gt0_txdlysresetdone_out : out STD_LOGIC;
    gt0_txoutclk_out : out STD_LOGIC;
    gt0_txoutclkfabric_out : out STD_LOGIC;
    gt0_txoutclkpcs_out : out STD_LOGIC;
    gt0_txphaligndone_out : out STD_LOGIC;
    gt0_txresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_drprdy_out : out STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_gthtxn_out : out STD_LOGIC;
    gt1_gthtxp_out : out STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gt1_rxbyterealign_out : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxdlysresetdone_out : out STD_LOGIC;
    gt1_rxoutclk_out : out STD_LOGIC;
    gt1_rxoutclkfabric_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_txdlysresetdone_out : out STD_LOGIC;
    gt1_txoutclk_out : out STD_LOGIC;
    gt1_txoutclkfabric_out : out STD_LOGIC;
    gt1_txoutclkpcs_out : out STD_LOGIC;
    gt1_txphaligndone_out : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_drprdy_out : out STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_gthtxn_out : out STD_LOGIC;
    gt2_gthtxp_out : out STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gt2_rxbyterealign_out : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxdlysresetdone_out : out STD_LOGIC;
    gt2_rxoutclk_out : out STD_LOGIC;
    gt2_rxoutclkfabric_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    gt2_txdlysresetdone_out : out STD_LOGIC;
    gt2_txoutclk_out : out STD_LOGIC;
    gt2_txoutclkfabric_out : out STD_LOGIC;
    gt2_txoutclkpcs_out : out STD_LOGIC;
    gt2_txphaligndone_out : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_drprdy_out : out STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_gthtxn_out : out STD_LOGIC;
    gt3_gthtxp_out : out STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gt3_rxbyterealign_out : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxdlysresetdone_out : out STD_LOGIC;
    gt3_rxoutclk_out : out STD_LOGIC;
    gt3_rxoutclkfabric_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_txdlysresetdone_out : out STD_LOGIC;
    gt3_txoutclk_out : out STD_LOGIC;
    gt3_txoutclkfabric_out : out STD_LOGIC;
    gt3_txoutclkpcs_out : out STD_LOGIC;
    gt3_txphaligndone_out : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_drpclk_in : in STD_LOGIC;
    gt0_drpen_in : in STD_LOGIC;
    gt0_drpwe_in : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_gthrxn_in : in STD_LOGIC;
    gt0_gthrxp_in : in STD_LOGIC;
    gt0_gtnorthrefclk0_in : in STD_LOGIC;
    gt0_gtnorthrefclk1_in : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt0_gtsouthrefclk0_in : in STD_LOGIC;
    gt0_gtsouthrefclk1_in : in STD_LOGIC;
    gt0_gttxreset_in : in STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC;
    gt0_rxdlysreset_in : in STD_LOGIC;
    gt0_rxuserrdy_in : in STD_LOGIC;
    gt0_rxusrclk_in : in STD_LOGIC;
    gt0_rxusrclk2_in : in STD_LOGIC;
    gt0_txdlyen_in : in STD_LOGIC;
    U0_TXDLYSRESET : in STD_LOGIC_VECTOR ( 3 downto 0 );
    U0_TXPHALIGN : in STD_LOGIC_VECTOR ( 3 downto 0 );
    U0_TXPHINIT : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_txuserrdy_in : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC;
    gt0_txusrclk2_in : in STD_LOGIC;
    gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt1_drpclk_in : in STD_LOGIC;
    gt1_drpen_in : in STD_LOGIC;
    gt1_drpwe_in : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_gthrxn_in : in STD_LOGIC;
    gt1_gthrxp_in : in STD_LOGIC;
    gt1_gtnorthrefclk0_in : in STD_LOGIC;
    gt1_gtnorthrefclk1_in : in STD_LOGIC;
    gt1_gtrxreset_in : in STD_LOGIC;
    gt1_gtsouthrefclk0_in : in STD_LOGIC;
    gt1_gtsouthrefclk1_in : in STD_LOGIC;
    gt1_gttxreset_in : in STD_LOGIC;
    gt1_rxdlysreset_in : in STD_LOGIC;
    gt1_rxuserrdy_in : in STD_LOGIC;
    gt1_rxusrclk_in : in STD_LOGIC;
    gt1_rxusrclk2_in : in STD_LOGIC;
    gt1_txuserrdy_in : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC;
    gt1_txusrclk2_in : in STD_LOGIC;
    gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt2_drpclk_in : in STD_LOGIC;
    gt2_drpen_in : in STD_LOGIC;
    gt2_drpwe_in : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt2_gthrxn_in : in STD_LOGIC;
    gt2_gthrxp_in : in STD_LOGIC;
    gt2_gtnorthrefclk0_in : in STD_LOGIC;
    gt2_gtnorthrefclk1_in : in STD_LOGIC;
    gt2_gtrxreset_in : in STD_LOGIC;
    gt2_gtsouthrefclk0_in : in STD_LOGIC;
    gt2_gtsouthrefclk1_in : in STD_LOGIC;
    gt2_gttxreset_in : in STD_LOGIC;
    gt2_rxdlysreset_in : in STD_LOGIC;
    gt2_rxuserrdy_in : in STD_LOGIC;
    gt2_rxusrclk_in : in STD_LOGIC;
    gt2_rxusrclk2_in : in STD_LOGIC;
    gt2_txuserrdy_in : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC;
    gt2_txusrclk2_in : in STD_LOGIC;
    gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt3_drpclk_in : in STD_LOGIC;
    gt3_drpen_in : in STD_LOGIC;
    gt3_drpwe_in : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_gthrxn_in : in STD_LOGIC;
    gt3_gthrxp_in : in STD_LOGIC;
    gt3_gtnorthrefclk0_in : in STD_LOGIC;
    gt3_gtnorthrefclk1_in : in STD_LOGIC;
    gt3_gtrxreset_in : in STD_LOGIC;
    gt3_gtsouthrefclk0_in : in STD_LOGIC;
    gt3_gtsouthrefclk1_in : in STD_LOGIC;
    gt3_gttxreset_in : in STD_LOGIC;
    gt3_rxdlysreset_in : in STD_LOGIC;
    gt3_rxuserrdy_in : in STD_LOGIC;
    gt3_rxusrclk_in : in STD_LOGIC;
    gt3_rxusrclk2_in : in STD_LOGIC;
    gt3_txuserrdy_in : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC;
    gt3_txusrclk2_in : in STD_LOGIC;
    gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt : entity is "mgt11g2_tx_rx_cfpga_multi_gt";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt is
  signal gt0_rxphaligndone_out : STD_LOGIC;
  signal gt0_rxsyncallin_in : STD_LOGIC;
  signal gt0_rxsyncout_i : STD_LOGIC;
  signal \^gt1_rxphaligndone_out\ : STD_LOGIC;
  signal \^gt2_rxphaligndone_out\ : STD_LOGIC;
begin
  gt1_rxphaligndone_out <= \^gt1_rxphaligndone_out\;
  gt2_rxphaligndone_out <= \^gt2_rxphaligndone_out\;
gt0_mgt11g2_tx_rx_cfpga_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT
     port map (
      GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
      GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
      SR(0) => SR(0),
      U0_TXDLYSRESET(0) => U0_TXDLYSRESET(0),
      U0_TXPHALIGN(0) => U0_TXPHALIGN(0),
      U0_TXPHINIT(0) => U0_TXPHINIT(0),
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_drpaddr_in(8 downto 0) => gt0_drpaddr_in(8 downto 0),
      gt0_drpclk_in => gt0_drpclk_in,
      gt0_drpclk_in_0 => gt0_drpclk_in_0,
      gt0_drpdi_in(15 downto 0) => gt0_drpdi_in(15 downto 0),
      gt0_drpdo_out(15 downto 0) => gt0_drpdo_out(15 downto 0),
      gt0_drpen_in => gt0_drpen_in,
      gt0_drprdy_out => gt0_drprdy_out,
      gt0_drpwe_in => gt0_drpwe_in,
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_gthrxn_in => gt0_gthrxn_in,
      gt0_gthrxp_in => gt0_gthrxp_in,
      gt0_gthtxn_out => gt0_gthtxn_out,
      gt0_gthtxp_out => gt0_gthtxp_out,
      gt0_gtnorthrefclk0_in => gt0_gtnorthrefclk0_in,
      gt0_gtnorthrefclk1_in => gt0_gtnorthrefclk1_in,
      gt0_gtsouthrefclk0_in => gt0_gtsouthrefclk0_in,
      gt0_gtsouthrefclk1_in => gt0_gtsouthrefclk1_in,
      gt0_gttxreset_in => gt0_gttxreset_in,
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxbyterealign_out => gt0_rxbyterealign_out,
      gt0_rxchariscomma_out(3 downto 0) => gt0_rxchariscomma_out(3 downto 0),
      gt0_rxcharisk_out(3 downto 0) => gt0_rxcharisk_out(3 downto 0),
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdata_out(31 downto 0) => gt0_rxdata_out(31 downto 0),
      gt0_rxdisperr_out(3 downto 0) => gt0_rxdisperr_out(3 downto 0),
      gt0_rxdlysreset_in => gt0_rxdlysreset_in,
      gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_out,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxnotintable_out(3 downto 0) => gt0_rxnotintable_out(3 downto 0),
      gt0_rxoutclk_out => gt0_rxoutclk_out,
      gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out,
      gt0_rxpd_in(1 downto 0) => gt0_rxpd_in(1 downto 0),
      gt0_rxphaligndone_out => gt0_rxphaligndone_out,
      gt0_rxphmonitor_out(4 downto 0) => gt0_rxphmonitor_out(4 downto 0),
      gt0_rxphslipmonitor_out(4 downto 0) => gt0_rxphslipmonitor_out(4 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt0_rxsyncallin_in => gt0_rxsyncallin_in,
      gt0_rxsyncdone_out => gt0_rxsyncdone_out,
      gt0_rxsyncout_i => gt0_rxsyncout_i,
      gt0_rxuserrdy_in => gt0_rxuserrdy_in,
      gt0_rxusrclk2_in => gt0_rxusrclk2_in,
      gt0_rxusrclk_in => gt0_rxusrclk_in,
      gt0_txcharisk_in(3 downto 0) => gt0_txcharisk_in(3 downto 0),
      gt0_txdata_in(31 downto 0) => gt0_txdata_in(31 downto 0),
      gt0_txdlyen_in => gt0_txdlyen_in,
      gt0_txdlysresetdone_out => gt0_txdlysresetdone_out,
      gt0_txoutclk_out => gt0_txoutclk_out,
      gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
      gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
      gt0_txpd_in(1 downto 0) => gt0_txpd_in(1 downto 0),
      gt0_txphaligndone_out => gt0_txphaligndone_out,
      gt0_txphinitdone_out => gt0_txphinitdone_out,
      gt0_txresetdone_out => gt0_txresetdone_out,
      gt0_txuserrdy_in => gt0_txuserrdy_in,
      gt0_txusrclk2_in => gt0_txusrclk2_in,
      gt0_txusrclk_in => gt0_txusrclk_in
    );
gt1_mgt11g2_tx_rx_cfpga_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9
     port map (
      GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
      GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
      U0_TXDLYSRESET(0) => U0_TXDLYSRESET(1),
      U0_TXPHALIGN(0) => U0_TXPHALIGN(1),
      U0_TXPHINIT(0) => U0_TXPHINIT(1),
      gt0_rxsyncallin_in => gt0_rxsyncallin_in,
      gt0_rxsyncout_i => gt0_rxsyncout_i,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_drpaddr_in(8 downto 0) => gt1_drpaddr_in(8 downto 0),
      gt1_drpclk_in => gt1_drpclk_in,
      gt1_drpclk_in_0 => gt1_drpclk_in_0,
      gt1_drpdi_in(15 downto 0) => gt1_drpdi_in(15 downto 0),
      gt1_drpdo_out(15 downto 0) => gt1_drpdo_out(15 downto 0),
      gt1_drpen_in => gt1_drpen_in,
      gt1_drprdy_out => gt1_drprdy_out,
      gt1_drpwe_in => gt1_drpwe_in,
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_gthrxn_in => gt1_gthrxn_in,
      gt1_gthrxp_in => gt1_gthrxp_in,
      gt1_gthtxn_out => gt1_gthtxn_out,
      gt1_gthtxp_out => gt1_gthtxp_out,
      gt1_gtnorthrefclk0_in => gt1_gtnorthrefclk0_in,
      gt1_gtnorthrefclk1_in => gt1_gtnorthrefclk1_in,
      gt1_gtrxreset_in => gt1_gtrxreset_in,
      gt1_gtsouthrefclk0_in => gt1_gtsouthrefclk0_in,
      gt1_gtsouthrefclk1_in => gt1_gtsouthrefclk1_in,
      gt1_gttxreset_in => gt1_gttxreset_in,
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxbyterealign_out => gt1_rxbyterealign_out,
      gt1_rxchariscomma_out(3 downto 0) => gt1_rxchariscomma_out(3 downto 0),
      gt1_rxcharisk_out(3 downto 0) => gt1_rxcharisk_out(3 downto 0),
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdata_out(31 downto 0) => gt1_rxdata_out(31 downto 0),
      gt1_rxdisperr_out(3 downto 0) => gt1_rxdisperr_out(3 downto 0),
      gt1_rxdlysreset_in => gt1_rxdlysreset_in,
      gt1_rxdlysresetdone_out => gt1_rxdlysresetdone_out,
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxnotintable_out(3 downto 0) => gt1_rxnotintable_out(3 downto 0),
      gt1_rxoutclk_out => gt1_rxoutclk_out,
      gt1_rxoutclkfabric_out => gt1_rxoutclkfabric_out,
      gt1_rxpd_in(1 downto 0) => gt1_rxpd_in(1 downto 0),
      gt1_rxphaligndone_out => \^gt1_rxphaligndone_out\,
      gt1_rxphmonitor_out(4 downto 0) => gt1_rxphmonitor_out(4 downto 0),
      gt1_rxphslipmonitor_out(4 downto 0) => gt1_rxphslipmonitor_out(4 downto 0),
      gt1_rxresetdone_out => gt1_rxresetdone_out,
      gt1_rxuserrdy_in => gt1_rxuserrdy_in,
      gt1_rxusrclk2_in => gt1_rxusrclk2_in,
      gt1_rxusrclk_in => gt1_rxusrclk_in,
      gt1_txcharisk_in(3 downto 0) => gt1_txcharisk_in(3 downto 0),
      gt1_txdata_in(31 downto 0) => gt1_txdata_in(31 downto 0),
      gt1_txdlysresetdone_out => gt1_txdlysresetdone_out,
      gt1_txoutclk_out => gt1_txoutclk_out,
      gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
      gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
      gt1_txpd_in(1 downto 0) => gt1_txpd_in(1 downto 0),
      gt1_txphaligndone_out => gt1_txphaligndone_out,
      gt1_txphinitdone_out => gt1_txphinitdone_out,
      gt1_txresetdone_out => gt1_txresetdone_out,
      gt1_txuserrdy_in => gt1_txuserrdy_in,
      gt1_txusrclk2_in => gt1_txusrclk2_in,
      gt1_txusrclk_in => gt1_txusrclk_in
    );
gt2_mgt11g2_tx_rx_cfpga_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10
     port map (
      GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
      GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
      U0_TXDLYSRESET(0) => U0_TXDLYSRESET(2),
      U0_TXPHALIGN(0) => U0_TXPHALIGN(2),
      U0_TXPHINIT(0) => U0_TXPHINIT(2),
      gt0_rxsyncallin_in => gt0_rxsyncallin_in,
      gt0_rxsyncout_i => gt0_rxsyncout_i,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_drpaddr_in(8 downto 0) => gt2_drpaddr_in(8 downto 0),
      gt2_drpclk_in => gt2_drpclk_in,
      gt2_drpclk_in_0 => gt2_drpclk_in_0,
      gt2_drpdi_in(15 downto 0) => gt2_drpdi_in(15 downto 0),
      gt2_drpdo_out(15 downto 0) => gt2_drpdo_out(15 downto 0),
      gt2_drpen_in => gt2_drpen_in,
      gt2_drprdy_out => gt2_drprdy_out,
      gt2_drpwe_in => gt2_drpwe_in,
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_gthrxn_in => gt2_gthrxn_in,
      gt2_gthrxp_in => gt2_gthrxp_in,
      gt2_gthtxn_out => gt2_gthtxn_out,
      gt2_gthtxp_out => gt2_gthtxp_out,
      gt2_gtnorthrefclk0_in => gt2_gtnorthrefclk0_in,
      gt2_gtnorthrefclk1_in => gt2_gtnorthrefclk1_in,
      gt2_gtrxreset_in => gt2_gtrxreset_in,
      gt2_gtsouthrefclk0_in => gt2_gtsouthrefclk0_in,
      gt2_gtsouthrefclk1_in => gt2_gtsouthrefclk1_in,
      gt2_gttxreset_in => gt2_gttxreset_in,
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxbyterealign_out => gt2_rxbyterealign_out,
      gt2_rxchariscomma_out(3 downto 0) => gt2_rxchariscomma_out(3 downto 0),
      gt2_rxcharisk_out(3 downto 0) => gt2_rxcharisk_out(3 downto 0),
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdata_out(31 downto 0) => gt2_rxdata_out(31 downto 0),
      gt2_rxdisperr_out(3 downto 0) => gt2_rxdisperr_out(3 downto 0),
      gt2_rxdlysreset_in => gt2_rxdlysreset_in,
      gt2_rxdlysresetdone_out => gt2_rxdlysresetdone_out,
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxnotintable_out(3 downto 0) => gt2_rxnotintable_out(3 downto 0),
      gt2_rxoutclk_out => gt2_rxoutclk_out,
      gt2_rxoutclkfabric_out => gt2_rxoutclkfabric_out,
      gt2_rxpd_in(1 downto 0) => gt2_rxpd_in(1 downto 0),
      gt2_rxphaligndone_out => \^gt2_rxphaligndone_out\,
      gt2_rxphmonitor_out(4 downto 0) => gt2_rxphmonitor_out(4 downto 0),
      gt2_rxphslipmonitor_out(4 downto 0) => gt2_rxphslipmonitor_out(4 downto 0),
      gt2_rxresetdone_out => gt2_rxresetdone_out,
      gt2_rxuserrdy_in => gt2_rxuserrdy_in,
      gt2_rxusrclk2_in => gt2_rxusrclk2_in,
      gt2_rxusrclk_in => gt2_rxusrclk_in,
      gt2_txcharisk_in(3 downto 0) => gt2_txcharisk_in(3 downto 0),
      gt2_txdata_in(31 downto 0) => gt2_txdata_in(31 downto 0),
      gt2_txdlysresetdone_out => gt2_txdlysresetdone_out,
      gt2_txoutclk_out => gt2_txoutclk_out,
      gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
      gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
      gt2_txpd_in(1 downto 0) => gt2_txpd_in(1 downto 0),
      gt2_txphaligndone_out => gt2_txphaligndone_out,
      gt2_txphinitdone_out => gt2_txphinitdone_out,
      gt2_txresetdone_out => gt2_txresetdone_out,
      gt2_txuserrdy_in => gt2_txuserrdy_in,
      gt2_txusrclk2_in => gt2_txusrclk2_in,
      gt2_txusrclk_in => gt2_txusrclk_in
    );
gt3_mgt11g2_tx_rx_cfpga_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11
     port map (
      GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
      GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
      U0_TXDLYSRESET(0) => U0_TXDLYSRESET(3),
      U0_TXPHALIGN(0) => U0_TXPHALIGN(3),
      U0_TXPHINIT(0) => U0_TXPHINIT(3),
      gt0_rxphaligndone_out => gt0_rxphaligndone_out,
      gt0_rxsyncallin_in => gt0_rxsyncallin_in,
      gt0_rxsyncout_i => gt0_rxsyncout_i,
      gt1_rxphaligndone_out => \^gt1_rxphaligndone_out\,
      gt2_rxphaligndone_out => \^gt2_rxphaligndone_out\,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_drpaddr_in(8 downto 0) => gt3_drpaddr_in(8 downto 0),
      gt3_drpclk_in => gt3_drpclk_in,
      gt3_drpclk_in_0 => gt3_drpclk_in_0,
      gt3_drpdi_in(15 downto 0) => gt3_drpdi_in(15 downto 0),
      gt3_drpdo_out(15 downto 0) => gt3_drpdo_out(15 downto 0),
      gt3_drpen_in => gt3_drpen_in,
      gt3_drprdy_out => gt3_drprdy_out,
      gt3_drpwe_in => gt3_drpwe_in,
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_gthrxn_in => gt3_gthrxn_in,
      gt3_gthrxp_in => gt3_gthrxp_in,
      gt3_gthtxn_out => gt3_gthtxn_out,
      gt3_gthtxp_out => gt3_gthtxp_out,
      gt3_gtnorthrefclk0_in => gt3_gtnorthrefclk0_in,
      gt3_gtnorthrefclk1_in => gt3_gtnorthrefclk1_in,
      gt3_gtrxreset_in => gt3_gtrxreset_in,
      gt3_gtsouthrefclk0_in => gt3_gtsouthrefclk0_in,
      gt3_gtsouthrefclk1_in => gt3_gtsouthrefclk1_in,
      gt3_gttxreset_in => gt3_gttxreset_in,
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxbyterealign_out => gt3_rxbyterealign_out,
      gt3_rxchariscomma_out(3 downto 0) => gt3_rxchariscomma_out(3 downto 0),
      gt3_rxcharisk_out(3 downto 0) => gt3_rxcharisk_out(3 downto 0),
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdata_out(31 downto 0) => gt3_rxdata_out(31 downto 0),
      gt3_rxdisperr_out(3 downto 0) => gt3_rxdisperr_out(3 downto 0),
      gt3_rxdlysreset_in => gt3_rxdlysreset_in,
      gt3_rxdlysresetdone_out => gt3_rxdlysresetdone_out,
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxnotintable_out(3 downto 0) => gt3_rxnotintable_out(3 downto 0),
      gt3_rxoutclk_out => gt3_rxoutclk_out,
      gt3_rxoutclkfabric_out => gt3_rxoutclkfabric_out,
      gt3_rxpd_in(1 downto 0) => gt3_rxpd_in(1 downto 0),
      gt3_rxphaligndone_out => gt3_rxphaligndone_out,
      gt3_rxphmonitor_out(4 downto 0) => gt3_rxphmonitor_out(4 downto 0),
      gt3_rxphslipmonitor_out(4 downto 0) => gt3_rxphslipmonitor_out(4 downto 0),
      gt3_rxresetdone_out => gt3_rxresetdone_out,
      gt3_rxuserrdy_in => gt3_rxuserrdy_in,
      gt3_rxusrclk2_in => gt3_rxusrclk2_in,
      gt3_rxusrclk_in => gt3_rxusrclk_in,
      gt3_txcharisk_in(3 downto 0) => gt3_txcharisk_in(3 downto 0),
      gt3_txdata_in(31 downto 0) => gt3_txdata_in(31 downto 0),
      gt3_txdlysresetdone_out => gt3_txdlysresetdone_out,
      gt3_txoutclk_out => gt3_txoutclk_out,
      gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
      gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
      gt3_txpd_in(1 downto 0) => gt3_txpd_in(1 downto 0),
      gt3_txphaligndone_out => gt3_txphaligndone_out,
      gt3_txphinitdone_out => gt3_txphinitdone_out,
      gt3_txresetdone_out => gt3_txresetdone_out,
      gt3_txuserrdy_in => gt3_txuserrdy_in,
      gt3_txusrclk2_in => gt3_txusrclk2_in,
      gt3_txusrclk_in => gt3_txusrclk_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init is
  port (
    SYSCLK_IN : in STD_LOGIC;
    SOFT_RESET_TX_IN : in STD_LOGIC;
    SOFT_RESET_RX_IN : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT0_DATA_VALID_IN : in STD_LOGIC;
    GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT1_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT1_DATA_VALID_IN : in STD_LOGIC;
    GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT2_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT2_DATA_VALID_IN : in STD_LOGIC;
    GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT3_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT3_DATA_VALID_IN : in STD_LOGIC;
    gt0_gtnorthrefclk0_in : in STD_LOGIC;
    gt0_gtnorthrefclk1_in : in STD_LOGIC;
    gt0_gtsouthrefclk0_in : in STD_LOGIC;
    gt0_gtsouthrefclk1_in : in STD_LOGIC;
    gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt0_drpclk_in : in STD_LOGIC;
    gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_drpen_in : in STD_LOGIC;
    gt0_drprdy_out : out STD_LOGIC;
    gt0_drpwe_in : in STD_LOGIC;
    gt0_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_rxuserrdy_in : in STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_rxusrclk_in : in STD_LOGIC;
    gt0_rxusrclk2_in : in STD_LOGIC;
    gt0_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_gthrxn_in : in STD_LOGIC;
    gt0_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxbyterealign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxoutclk_out : out STD_LOGIC;
    gt0_rxoutclkfabric_out : out STD_LOGIC;
    gt0_gtrxreset_in : in STD_LOGIC;
    gt0_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_gthrxp_in : in STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_gttxreset_in : in STD_LOGIC;
    gt0_txuserrdy_in : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC;
    gt0_txusrclk2_in : in STD_LOGIC;
    gt0_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_gthtxn_out : out STD_LOGIC;
    gt0_gthtxp_out : out STD_LOGIC;
    gt0_txoutclk_out : out STD_LOGIC;
    gt0_txoutclkfabric_out : out STD_LOGIC;
    gt0_txoutclkpcs_out : out STD_LOGIC;
    gt0_txresetdone_out : out STD_LOGIC;
    gt0_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_gtnorthrefclk0_in : in STD_LOGIC;
    gt1_gtnorthrefclk1_in : in STD_LOGIC;
    gt1_gtsouthrefclk0_in : in STD_LOGIC;
    gt1_gtsouthrefclk1_in : in STD_LOGIC;
    gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt1_drpclk_in : in STD_LOGIC;
    gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_drpen_in : in STD_LOGIC;
    gt1_drprdy_out : out STD_LOGIC;
    gt1_drpwe_in : in STD_LOGIC;
    gt1_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_rxuserrdy_in : in STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt1_rxusrclk_in : in STD_LOGIC;
    gt1_rxusrclk2_in : in STD_LOGIC;
    gt1_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_gthrxn_in : in STD_LOGIC;
    gt1_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gt1_rxbyterealign_out : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxoutclk_out : out STD_LOGIC;
    gt1_rxoutclkfabric_out : out STD_LOGIC;
    gt1_gtrxreset_in : in STD_LOGIC;
    gt1_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_gthrxp_in : in STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_gttxreset_in : in STD_LOGIC;
    gt1_txuserrdy_in : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC;
    gt1_txusrclk2_in : in STD_LOGIC;
    gt1_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_gthtxn_out : out STD_LOGIC;
    gt1_gthtxp_out : out STD_LOGIC;
    gt1_txoutclk_out : out STD_LOGIC;
    gt1_txoutclkfabric_out : out STD_LOGIC;
    gt1_txoutclkpcs_out : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    gt1_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_gtnorthrefclk0_in : in STD_LOGIC;
    gt2_gtnorthrefclk1_in : in STD_LOGIC;
    gt2_gtsouthrefclk0_in : in STD_LOGIC;
    gt2_gtsouthrefclk1_in : in STD_LOGIC;
    gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt2_drpclk_in : in STD_LOGIC;
    gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_drpen_in : in STD_LOGIC;
    gt2_drprdy_out : out STD_LOGIC;
    gt2_drpwe_in : in STD_LOGIC;
    gt2_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_rxuserrdy_in : in STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt2_rxusrclk_in : in STD_LOGIC;
    gt2_rxusrclk2_in : in STD_LOGIC;
    gt2_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_gthrxn_in : in STD_LOGIC;
    gt2_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gt2_rxbyterealign_out : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxoutclk_out : out STD_LOGIC;
    gt2_rxoutclkfabric_out : out STD_LOGIC;
    gt2_gtrxreset_in : in STD_LOGIC;
    gt2_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_gthrxp_in : in STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    gt2_gttxreset_in : in STD_LOGIC;
    gt2_txuserrdy_in : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC;
    gt2_txusrclk2_in : in STD_LOGIC;
    gt2_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_gthtxn_out : out STD_LOGIC;
    gt2_gthtxp_out : out STD_LOGIC;
    gt2_txoutclk_out : out STD_LOGIC;
    gt2_txoutclkfabric_out : out STD_LOGIC;
    gt2_txoutclkpcs_out : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    gt2_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_gtnorthrefclk0_in : in STD_LOGIC;
    gt3_gtnorthrefclk1_in : in STD_LOGIC;
    gt3_gtsouthrefclk0_in : in STD_LOGIC;
    gt3_gtsouthrefclk1_in : in STD_LOGIC;
    gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt3_drpclk_in : in STD_LOGIC;
    gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_drpen_in : in STD_LOGIC;
    gt3_drprdy_out : out STD_LOGIC;
    gt3_drpwe_in : in STD_LOGIC;
    gt3_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_rxuserrdy_in : in STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt3_rxusrclk_in : in STD_LOGIC;
    gt3_rxusrclk2_in : in STD_LOGIC;
    gt3_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_gthrxn_in : in STD_LOGIC;
    gt3_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gt3_rxbyterealign_out : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxoutclk_out : out STD_LOGIC;
    gt3_rxoutclkfabric_out : out STD_LOGIC;
    gt3_gtrxreset_in : in STD_LOGIC;
    gt3_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_gthrxp_in : in STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_gttxreset_in : in STD_LOGIC;
    gt3_txuserrdy_in : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC;
    gt3_txusrclk2_in : in STD_LOGIC;
    gt3_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_gthtxn_out : out STD_LOGIC;
    gt3_gthtxp_out : out STD_LOGIC;
    gt3_txoutclk_out : out STD_LOGIC;
    gt3_txoutclkfabric_out : out STD_LOGIC;
    gt3_txoutclkpcs_out : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    gt3_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    GT0_QPLLREFCLKLOST_IN : in STD_LOGIC;
    GT0_QPLLRESET_OUT : out STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC
  );
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init : entity is 0;
  attribute EXAMPLE_SIM_GTRESET_SPEEDUP : string;
  attribute EXAMPLE_SIM_GTRESET_SPEEDUP of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init : entity is "TRUE";
  attribute EXAMPLE_USE_CHIPSCOPE : integer;
  attribute EXAMPLE_USE_CHIPSCOPE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init : entity is "mgt11g2_tx_rx_cfpga_init";
  attribute STABLE_CLOCK_PERIOD : integer;
  attribute STABLE_CLOCK_PERIOD of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init : entity is 16;
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init : entity is "yes";
end mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init is
  signal \^gt2_rx_fsm_reset_done_out\ : STD_LOGIC;
  signal RESET_PHALIGNMENT : STD_LOGIC;
  signal U0_TXDLYEN : STD_LOGIC;
  signal U0_TXDLYSRESET : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal U0_TXPHALIGN : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal U0_TXPHINIT : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gt0_gtrxreset_t : STD_LOGIC;
  signal gt0_gttxreset_t : STD_LOGIC;
  signal gt0_rst_tx_phalignment_i : STD_LOGIC;
  signal gt0_run_rx_phalignment_i : STD_LOGIC;
  signal gt0_run_tx_phalignment_i : STD_LOGIC;
  signal gt0_rx_cdrlock_counter : STD_LOGIC;
  signal \gt0_rx_cdrlock_counter[9]_i_3_n_0\ : STD_LOGIC;
  signal \gt0_rx_cdrlock_counter[9]_i_4_n_0\ : STD_LOGIC;
  signal gt0_rx_cdrlock_counter_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal gt0_rx_cdrlocked_i_2_n_0 : STD_LOGIC;
  signal gt0_rx_cdrlocked_i_3_n_0 : STD_LOGIC;
  signal gt0_rx_cdrlocked_reg_n_0 : STD_LOGIC;
  signal gt0_rxdlysreset_i : STD_LOGIC;
  signal gt0_rxdlysresetdone_i : STD_LOGIC;
  signal \^gt0_rxresetdone_out\ : STD_LOGIC;
  signal gt0_rxresetfsm_i_n_3 : STD_LOGIC;
  signal gt0_rxresetfsm_i_n_4 : STD_LOGIC;
  signal gt0_rxsyncdone_i : STD_LOGIC;
  signal gt0_rxuserrdy_t : STD_LOGIC;
  signal gt0_tx_phalignment_done_i : STD_LOGIC;
  signal gt0_txdlysresetdone_out : STD_LOGIC;
  signal gt0_txphaligndone_out : STD_LOGIC;
  signal gt0_txphinitdone_out : STD_LOGIC;
  signal \^gt0_txresetdone_out\ : STD_LOGIC;
  signal gt0_txuserrdy_t : STD_LOGIC;
  signal gt1_gtrxreset_t : STD_LOGIC;
  signal gt1_gttxreset_t : STD_LOGIC;
  signal gt1_rst_tx_phalignment_i : STD_LOGIC;
  signal gt1_run_rx_phalignment_i : STD_LOGIC;
  signal gt1_run_tx_phalignment_i : STD_LOGIC;
  signal gt1_rxdlysreset_i : STD_LOGIC;
  signal gt1_rxdlysresetdone_i : STD_LOGIC;
  signal gt1_rxphaligndone_i : STD_LOGIC;
  signal \^gt1_rxresetdone_out\ : STD_LOGIC;
  signal gt1_rxresetfsm_i_n_3 : STD_LOGIC;
  signal gt1_rxuserrdy_t : STD_LOGIC;
  signal gt1_txdlysresetdone_out : STD_LOGIC;
  signal gt1_txphaligndone_out : STD_LOGIC;
  signal gt1_txphinitdone_out : STD_LOGIC;
  signal \^gt1_txresetdone_out\ : STD_LOGIC;
  signal gt1_txresetfsm_i_n_5 : STD_LOGIC;
  signal gt1_txuserrdy_t : STD_LOGIC;
  signal gt2_gtrxreset_t : STD_LOGIC;
  signal gt2_gttxreset_t : STD_LOGIC;
  signal gt2_rst_tx_phalignment_i : STD_LOGIC;
  signal gt2_run_rx_phalignment_i : STD_LOGIC;
  signal gt2_run_tx_phalignment_i : STD_LOGIC;
  signal gt2_rxdlysreset_i : STD_LOGIC;
  signal gt2_rxdlysresetdone_i : STD_LOGIC;
  signal gt2_rxphaligndone_i : STD_LOGIC;
  signal \^gt2_rxresetdone_out\ : STD_LOGIC;
  signal gt2_rxresetfsm_i_n_3 : STD_LOGIC;
  signal gt2_rxuserrdy_t : STD_LOGIC;
  signal gt2_txdlysresetdone_out : STD_LOGIC;
  signal gt2_txphaligndone_out : STD_LOGIC;
  signal gt2_txphinitdone_out : STD_LOGIC;
  signal \^gt2_txresetdone_out\ : STD_LOGIC;
  signal gt2_txuserrdy_t : STD_LOGIC;
  signal gt3_gtrxreset_t : STD_LOGIC;
  signal gt3_gttxreset_t : STD_LOGIC;
  signal gt3_run_rx_phalignment_i : STD_LOGIC;
  signal gt3_run_tx_phalignment_i : STD_LOGIC;
  signal gt3_rxdlysreset_i : STD_LOGIC;
  signal gt3_rxdlysresetdone_i : STD_LOGIC;
  signal gt3_rxphaligndone_i : STD_LOGIC;
  signal \^gt3_rxresetdone_out\ : STD_LOGIC;
  signal gt3_rxresetfsm_i_n_3 : STD_LOGIC;
  signal gt3_rxuserrdy_t : STD_LOGIC;
  signal gt3_txdlysresetdone_out : STD_LOGIC;
  signal gt3_txphaligndone_out : STD_LOGIC;
  signal gt3_txphinitdone_out : STD_LOGIC;
  signal \^gt3_txresetdone_out\ : STD_LOGIC;
  signal gt3_txresetfsm_i_n_5 : STD_LOGIC;
  signal gt3_txuserrdy_t : STD_LOGIC;
  signal mgt11g2_tx_rx_cfpga_i_n_3 : STD_LOGIC;
  signal mgt11g2_tx_rx_cfpga_i_n_5 : STD_LOGIC;
  signal mgt11g2_tx_rx_cfpga_i_n_7 : STD_LOGIC;
  signal mgt11g2_tx_rx_cfpga_i_n_9 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[1]_i_1\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[2]_i_1\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[3]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[4]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[6]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[7]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[8]_i_1\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[9]_i_2\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \gt0_rx_cdrlock_counter[9]_i_3\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of gt0_rx_cdrlocked_i_2 : label is "soft_lutpair123";
begin
  GT0_RX_FSM_RESET_DONE_OUT <= \^gt2_rx_fsm_reset_done_out\;
  GT1_RX_FSM_RESET_DONE_OUT <= \^gt2_rx_fsm_reset_done_out\;
  GT2_RX_FSM_RESET_DONE_OUT <= \^gt2_rx_fsm_reset_done_out\;
  GT3_RX_FSM_RESET_DONE_OUT <= \^gt2_rx_fsm_reset_done_out\;
  gt0_rxresetdone_out <= \^gt0_rxresetdone_out\;
  gt0_txresetdone_out <= \^gt0_txresetdone_out\;
  gt1_rxresetdone_out <= \^gt1_rxresetdone_out\;
  gt1_txresetdone_out <= \^gt1_txresetdone_out\;
  gt2_rxresetdone_out <= \^gt2_rxresetdone_out\;
  gt2_txresetdone_out <= \^gt2_txresetdone_out\;
  gt3_rxresetdone_out <= \^gt3_rxresetdone_out\;
  gt3_txresetdone_out <= \^gt3_txresetdone_out\;
gt0_rx_auto_phase_align_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN
     port map (
      PHASE_ALIGNMENT_DONE_reg_0 => \^gt2_rx_fsm_reset_done_out\,
      PHASE_ALIGNMENT_DONE_reg_1 => gt0_rx_cdrlocked_reg_n_0,
      SS(0) => gt0_rxresetfsm_i_n_3,
      SYSCLK_IN => SYSCLK_IN,
      gt0_run_rx_phalignment_i => gt0_run_rx_phalignment_i,
      gt0_rxdlysreset_in => gt0_rxdlysreset_i,
      gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_i,
      gt0_rxsyncdone_out => gt0_rxsyncdone_i
    );
\gt0_rx_cdrlock_counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(0),
      O => p_0_in(0)
    );
\gt0_rx_cdrlock_counter[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(0),
      I1 => gt0_rx_cdrlock_counter_reg(1),
      O => p_0_in(1)
    );
\gt0_rx_cdrlock_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(1),
      I1 => gt0_rx_cdrlock_counter_reg(0),
      I2 => gt0_rx_cdrlock_counter_reg(2),
      O => p_0_in(2)
    );
\gt0_rx_cdrlock_counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(2),
      I1 => gt0_rx_cdrlock_counter_reg(0),
      I2 => gt0_rx_cdrlock_counter_reg(1),
      I3 => gt0_rx_cdrlock_counter_reg(3),
      O => p_0_in(3)
    );
\gt0_rx_cdrlock_counter[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(3),
      I1 => gt0_rx_cdrlock_counter_reg(1),
      I2 => gt0_rx_cdrlock_counter_reg(0),
      I3 => gt0_rx_cdrlock_counter_reg(2),
      I4 => gt0_rx_cdrlock_counter_reg(4),
      O => p_0_in(4)
    );
\gt0_rx_cdrlock_counter[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(4),
      I1 => gt0_rx_cdrlock_counter_reg(2),
      I2 => gt0_rx_cdrlock_counter_reg(0),
      I3 => gt0_rx_cdrlock_counter_reg(1),
      I4 => gt0_rx_cdrlock_counter_reg(3),
      I5 => gt0_rx_cdrlock_counter_reg(5),
      O => p_0_in(5)
    );
\gt0_rx_cdrlock_counter[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \gt0_rx_cdrlock_counter[9]_i_4_n_0\,
      I1 => gt0_rx_cdrlock_counter_reg(6),
      O => p_0_in(6)
    );
\gt0_rx_cdrlock_counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(6),
      I1 => \gt0_rx_cdrlock_counter[9]_i_4_n_0\,
      I2 => gt0_rx_cdrlock_counter_reg(7),
      O => p_0_in(7)
    );
\gt0_rx_cdrlock_counter[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(7),
      I1 => \gt0_rx_cdrlock_counter[9]_i_4_n_0\,
      I2 => gt0_rx_cdrlock_counter_reg(6),
      I3 => gt0_rx_cdrlock_counter_reg(8),
      O => p_0_in(8)
    );
\gt0_rx_cdrlock_counter[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(0),
      I1 => gt0_rx_cdrlock_counter_reg(1),
      I2 => gt0_rx_cdrlock_counter_reg(2),
      I3 => gt0_rx_cdrlock_counter_reg(3),
      I4 => gt0_rx_cdrlock_counter_reg(4),
      I5 => \gt0_rx_cdrlock_counter[9]_i_3_n_0\,
      O => gt0_rx_cdrlock_counter
    );
\gt0_rx_cdrlock_counter[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CC6CCCCC"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(8),
      I1 => gt0_rx_cdrlock_counter_reg(9),
      I2 => gt0_rx_cdrlock_counter_reg(6),
      I3 => \gt0_rx_cdrlock_counter[9]_i_4_n_0\,
      I4 => gt0_rx_cdrlock_counter_reg(7),
      O => p_0_in(9)
    );
\gt0_rx_cdrlock_counter[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(5),
      I1 => gt0_rx_cdrlock_counter_reg(6),
      I2 => gt0_rx_cdrlock_counter_reg(8),
      I3 => gt0_rx_cdrlock_counter_reg(9),
      I4 => gt0_rx_cdrlock_counter_reg(7),
      O => \gt0_rx_cdrlock_counter[9]_i_3_n_0\
    );
\gt0_rx_cdrlock_counter[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(4),
      I1 => gt0_rx_cdrlock_counter_reg(2),
      I2 => gt0_rx_cdrlock_counter_reg(0),
      I3 => gt0_rx_cdrlock_counter_reg(1),
      I4 => gt0_rx_cdrlock_counter_reg(3),
      I5 => gt0_rx_cdrlock_counter_reg(5),
      O => \gt0_rx_cdrlock_counter[9]_i_4_n_0\
    );
\gt0_rx_cdrlock_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(0),
      Q => gt0_rx_cdrlock_counter_reg(0),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(1),
      Q => gt0_rx_cdrlock_counter_reg(1),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(2),
      Q => gt0_rx_cdrlock_counter_reg(2),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(3),
      Q => gt0_rx_cdrlock_counter_reg(3),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(4),
      Q => gt0_rx_cdrlock_counter_reg(4),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(5),
      Q => gt0_rx_cdrlock_counter_reg(5),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(6),
      Q => gt0_rx_cdrlock_counter_reg(6),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(7),
      Q => gt0_rx_cdrlock_counter_reg(7),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(8),
      Q => gt0_rx_cdrlock_counter_reg(8),
      R => gt0_gtrxreset_t
    );
\gt0_rx_cdrlock_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => SYSCLK_IN,
      CE => gt0_rx_cdrlock_counter,
      D => p_0_in(9),
      Q => gt0_rx_cdrlock_counter_reg(9),
      R => gt0_gtrxreset_t
    );
gt0_rx_cdrlocked_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(8),
      I1 => gt0_rx_cdrlock_counter_reg(9),
      O => gt0_rx_cdrlocked_i_2_n_0
    );
gt0_rx_cdrlocked_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => gt0_rx_cdrlock_counter_reg(4),
      I1 => gt0_rx_cdrlock_counter_reg(5),
      I2 => gt0_rx_cdrlock_counter_reg(3),
      I3 => gt0_rx_cdrlock_counter_reg(2),
      I4 => gt0_rx_cdrlock_counter_reg(7),
      I5 => gt0_rx_cdrlock_counter_reg(6),
      O => gt0_rx_cdrlocked_i_3_n_0
    );
gt0_rx_cdrlocked_reg: unisim.vcomponents.FDRE
     port map (
      C => SYSCLK_IN,
      CE => '1',
      D => gt0_rxresetfsm_i_n_4,
      Q => gt0_rx_cdrlocked_reg_n_0,
      R => '0'
    );
gt0_rxresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM
     port map (
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      \FSM_onehot_phalign_state_reg[1]\ => gt0_rx_cdrlocked_reg_n_0,
      GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      PHALIGNMENT_DONE_i_reg_0 => \^gt2_rx_fsm_reset_done_out\,
      Q(1 downto 0) => gt0_rx_cdrlock_counter_reg(1 downto 0),
      SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
      SR(0) => gt0_gtrxreset_t,
      SS(0) => gt0_rxresetfsm_i_n_3,
      SYSCLK_IN => SYSCLK_IN,
      gt0_run_rx_phalignment_i => gt0_run_rx_phalignment_i,
      gt0_rx_cdrlocked_reg => gt0_rxresetfsm_i_n_4,
      gt0_rx_cdrlocked_reg_0 => gt0_rx_cdrlocked_i_2_n_0,
      gt0_rx_cdrlocked_reg_1 => gt0_rx_cdrlocked_i_3_n_0,
      gt0_rxresetdone_out => \^gt0_rxresetdone_out\,
      gt0_rxuserrdy_in => gt0_rxuserrdy_t,
      gt0_rxusrclk_in => gt0_rxusrclk_in
    );
gt0_tx_manual_phase_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN
     port map (
      \FSM_sequential_tx_phalign_manual_state_reg[0]_0\ => gt1_txresetfsm_i_n_5,
      RESET_PHALIGNMENT => RESET_PHALIGNMENT,
      SYSCLK_IN => SYSCLK_IN,
      U0_TXDLYSRESET(3 downto 0) => U0_TXDLYSRESET(3 downto 0),
      U0_TXPHALIGN(3 downto 0) => U0_TXPHALIGN(3 downto 0),
      U0_TXPHINIT(3 downto 0) => U0_TXPHINIT(3 downto 0),
      gt0_run_tx_phalignment_i => gt0_run_tx_phalignment_i,
      gt0_tx_phalignment_done_i => gt0_tx_phalignment_done_i,
      gt0_txdlyen_in => U0_TXDLYEN,
      gt0_txdlysresetdone_out => gt0_txdlysresetdone_out,
      gt0_txphaligndone_out => gt0_txphaligndone_out,
      gt0_txphinitdone_out => gt0_txphinitdone_out,
      gt1_run_tx_phalignment_i => gt1_run_tx_phalignment_i,
      gt1_txdlysresetdone_out => gt1_txdlysresetdone_out,
      gt1_txphaligndone_out => gt1_txphaligndone_out,
      gt1_txphinitdone_out => gt1_txphinitdone_out,
      gt2_run_tx_phalignment_i => gt2_run_tx_phalignment_i,
      gt2_txdlysresetdone_out => gt2_txdlysresetdone_out,
      gt2_txphaligndone_out => gt2_txphaligndone_out,
      gt2_txphinitdone_out => gt2_txphinitdone_out,
      gt3_run_tx_phalignment_i => gt3_run_tx_phalignment_i,
      gt3_txdlysresetdone_out => gt3_txdlysresetdone_out,
      gt3_txphaligndone_out => gt3_txphaligndone_out,
      gt3_txphinitdone_out => gt3_txphinitdone_out,
      \stretch_r_reg[2]\ => mgt11g2_tx_rx_cfpga_i_n_3,
      \stretch_r_reg[2]_0\ => mgt11g2_tx_rx_cfpga_i_n_5,
      \stretch_r_reg[2]_1\ => mgt11g2_tx_rx_cfpga_i_n_7,
      \stretch_r_reg[2]_2\ => mgt11g2_tx_rx_cfpga_i_n_9,
      txdone_clear_reg_0 => gt3_txresetfsm_i_n_5
    );
gt0_txresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM
     port map (
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_IN,
      GT0_QPLLRESET_OUT => GT0_QPLLRESET_OUT,
      GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
      SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt0_gttxreset_in => gt0_gttxreset_t,
      gt0_rst_tx_phalignment_i => gt0_rst_tx_phalignment_i,
      gt0_run_tx_phalignment_i => gt0_run_tx_phalignment_i,
      gt0_tx_phalignment_done_i => gt0_tx_phalignment_done_i,
      gt0_txresetdone_out => \^gt0_txresetdone_out\,
      gt0_txuserrdy_in => gt0_txuserrdy_t,
      gt0_txusrclk_in => gt0_txusrclk_in
    );
gt1_rx_auto_phase_align_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0
     port map (
      \FSM_onehot_phalign_state_reg[0]_0\ => gt1_rxresetfsm_i_n_3,
      \FSM_onehot_phalign_state_reg[1]_0\ => gt0_rx_cdrlocked_reg_n_0,
      SYSCLK_IN => SYSCLK_IN,
      gt1_run_rx_phalignment_i => gt1_run_rx_phalignment_i,
      gt1_rxdlysreset_in => gt1_rxdlysreset_i,
      gt1_rxdlysresetdone_out => gt1_rxdlysresetdone_i,
      gt1_rxphaligndone_out => gt1_rxphaligndone_i
    );
gt1_rxresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1
     port map (
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT1_DATA_VALID_IN => GT1_DATA_VALID_IN,
      PHALIGNMENT_DONE_i_reg_0 => \^gt2_rx_fsm_reset_done_out\,
      SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt1_gtrxreset_in => gt1_gtrxreset_t,
      gt1_run_rx_phalignment_i => gt1_run_rx_phalignment_i,
      gt1_rxresetdone_out => \^gt1_rxresetdone_out\,
      gt1_rxuserrdy_in => gt1_rxuserrdy_t,
      gt1_rxusrclk_in => gt1_rxusrclk_in,
      reset_time_out_reg_0 => gt0_rx_cdrlocked_reg_n_0,
      run_phase_alignment_int_reg_0 => gt1_rxresetfsm_i_n_3
    );
gt1_txresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2
     port map (
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_IN,
      GT1_TX_FSM_RESET_DONE_OUT => GT1_TX_FSM_RESET_DONE_OUT,
      SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt0_run_tx_phalignment_i => gt0_run_tx_phalignment_i,
      gt0_tx_phalignment_done_i => gt0_tx_phalignment_done_i,
      gt1_gttxreset_in => gt1_gttxreset_t,
      gt1_rst_tx_phalignment_i => gt1_rst_tx_phalignment_i,
      gt1_run_tx_phalignment_i => gt1_run_tx_phalignment_i,
      gt1_txresetdone_out => \^gt1_txresetdone_out\,
      gt1_txuserrdy_in => gt1_txuserrdy_t,
      gt1_txusrclk_in => gt1_txusrclk_in,
      gt2_run_tx_phalignment_i => gt2_run_tx_phalignment_i,
      gt3_run_tx_phalignment_i => gt3_run_tx_phalignment_i,
      run_phase_alignment_int_reg_0 => gt1_txresetfsm_i_n_5
    );
gt2_rx_auto_phase_align_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3
     port map (
      \FSM_onehot_phalign_state_reg[0]_0\ => gt2_rxresetfsm_i_n_3,
      \FSM_onehot_phalign_state_reg[1]_0\ => gt0_rx_cdrlocked_reg_n_0,
      SYSCLK_IN => SYSCLK_IN,
      gt2_run_rx_phalignment_i => gt2_run_rx_phalignment_i,
      gt2_rxdlysreset_in => gt2_rxdlysreset_i,
      gt2_rxdlysresetdone_out => gt2_rxdlysresetdone_i,
      gt2_rxphaligndone_out => gt2_rxphaligndone_i
    );
gt2_rxresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4
     port map (
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT2_DATA_VALID_IN => GT2_DATA_VALID_IN,
      PHALIGNMENT_DONE_i_reg_0 => \^gt2_rx_fsm_reset_done_out\,
      SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt2_gtrxreset_in => gt2_gtrxreset_t,
      gt2_run_rx_phalignment_i => gt2_run_rx_phalignment_i,
      gt2_rxresetdone_out => \^gt2_rxresetdone_out\,
      gt2_rxuserrdy_in => gt2_rxuserrdy_t,
      gt2_rxusrclk_in => gt2_rxusrclk_in,
      reset_time_out_reg_0 => gt0_rx_cdrlocked_reg_n_0,
      run_phase_alignment_int_reg_0 => gt2_rxresetfsm_i_n_3
    );
gt2_txresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5
     port map (
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_IN,
      GT2_TX_FSM_RESET_DONE_OUT => GT2_TX_FSM_RESET_DONE_OUT,
      SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt0_tx_phalignment_done_i => gt0_tx_phalignment_done_i,
      gt2_gttxreset_in => gt2_gttxreset_t,
      gt2_rst_tx_phalignment_i => gt2_rst_tx_phalignment_i,
      gt2_run_tx_phalignment_i => gt2_run_tx_phalignment_i,
      gt2_txresetdone_out => \^gt2_txresetdone_out\,
      gt2_txuserrdy_in => gt2_txuserrdy_t,
      gt2_txusrclk_in => gt2_txusrclk_in
    );
gt3_rx_auto_phase_align_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6
     port map (
      \FSM_onehot_phalign_state_reg[0]_0\ => gt3_rxresetfsm_i_n_3,
      \FSM_onehot_phalign_state_reg[1]_0\ => gt0_rx_cdrlocked_reg_n_0,
      SYSCLK_IN => SYSCLK_IN,
      gt3_run_rx_phalignment_i => gt3_run_rx_phalignment_i,
      gt3_rxdlysreset_in => gt3_rxdlysreset_i,
      gt3_rxdlysresetdone_out => gt3_rxdlysresetdone_i,
      gt3_rxphaligndone_out => gt3_rxphaligndone_i
    );
gt3_rxresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7
     port map (
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT3_DATA_VALID_IN => GT3_DATA_VALID_IN,
      PHALIGNMENT_DONE_i_reg_0 => \^gt2_rx_fsm_reset_done_out\,
      SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt3_gtrxreset_in => gt3_gtrxreset_t,
      gt3_run_rx_phalignment_i => gt3_run_rx_phalignment_i,
      gt3_rxresetdone_out => \^gt3_rxresetdone_out\,
      gt3_rxuserrdy_in => gt3_rxuserrdy_t,
      gt3_rxusrclk_in => gt3_rxusrclk_in,
      reset_time_out_reg_0 => gt0_rx_cdrlocked_reg_n_0,
      run_phase_alignment_int_reg_0 => gt3_rxresetfsm_i_n_3
    );
gt3_txresetfsm_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8
     port map (
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_IN,
      GT3_TX_FSM_RESET_DONE_OUT => GT3_TX_FSM_RESET_DONE_OUT,
      RESET_PHALIGNMENT => RESET_PHALIGNMENT,
      SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt0_rst_tx_phalignment_i => gt0_rst_tx_phalignment_i,
      gt0_run_tx_phalignment_i => gt0_run_tx_phalignment_i,
      gt0_tx_phalignment_done_i => gt0_tx_phalignment_done_i,
      gt1_rst_tx_phalignment_i => gt1_rst_tx_phalignment_i,
      gt2_rst_tx_phalignment_i => gt2_rst_tx_phalignment_i,
      gt3_gttxreset_in => gt3_gttxreset_t,
      gt3_run_tx_phalignment_i => gt3_run_tx_phalignment_i,
      gt3_txresetdone_out => \^gt3_txresetdone_out\,
      gt3_txuserrdy_in => gt3_txuserrdy_t,
      gt3_txusrclk_in => gt3_txusrclk_in,
      run_phase_alignment_int_reg_0 => gt3_txresetfsm_i_n_5
    );
mgt11g2_tx_rx_cfpga_i: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt
     port map (
      GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
      GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
      SR(0) => gt0_gtrxreset_t,
      U0_TXDLYSRESET(3 downto 0) => U0_TXDLYSRESET(3 downto 0),
      U0_TXPHALIGN(3 downto 0) => U0_TXPHALIGN(3 downto 0),
      U0_TXPHINIT(3 downto 0) => U0_TXPHINIT(3 downto 0),
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_drpaddr_in(8 downto 0) => gt0_drpaddr_in(8 downto 0),
      gt0_drpclk_in => gt0_drpclk_in,
      gt0_drpclk_in_0 => mgt11g2_tx_rx_cfpga_i_n_3,
      gt0_drpdi_in(15 downto 0) => gt0_drpdi_in(15 downto 0),
      gt0_drpdo_out(15 downto 0) => gt0_drpdo_out(15 downto 0),
      gt0_drpen_in => gt0_drpen_in,
      gt0_drprdy_out => gt0_drprdy_out,
      gt0_drpwe_in => gt0_drpwe_in,
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_gthrxn_in => gt0_gthrxn_in,
      gt0_gthrxp_in => gt0_gthrxp_in,
      gt0_gthtxn_out => gt0_gthtxn_out,
      gt0_gthtxp_out => gt0_gthtxp_out,
      gt0_gtnorthrefclk0_in => gt0_gtnorthrefclk0_in,
      gt0_gtnorthrefclk1_in => gt0_gtnorthrefclk1_in,
      gt0_gtsouthrefclk0_in => gt0_gtsouthrefclk0_in,
      gt0_gtsouthrefclk1_in => gt0_gtsouthrefclk1_in,
      gt0_gttxreset_in => gt0_gttxreset_t,
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxbyterealign_out => gt0_rxbyterealign_out,
      gt0_rxchariscomma_out(3 downto 0) => gt0_rxchariscomma_out(3 downto 0),
      gt0_rxcharisk_out(3 downto 0) => gt0_rxcharisk_out(3 downto 0),
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdata_out(31 downto 0) => gt0_rxdata_out(31 downto 0),
      gt0_rxdisperr_out(3 downto 0) => gt0_rxdisperr_out(3 downto 0),
      gt0_rxdlysreset_in => gt0_rxdlysreset_i,
      gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_i,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxnotintable_out(3 downto 0) => gt0_rxnotintable_out(3 downto 0),
      gt0_rxoutclk_out => gt0_rxoutclk_out,
      gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out,
      gt0_rxpd_in(1 downto 0) => gt0_rxpd_in(1 downto 0),
      gt0_rxphmonitor_out(4 downto 0) => gt0_rxphmonitor_out(4 downto 0),
      gt0_rxphslipmonitor_out(4 downto 0) => gt0_rxphslipmonitor_out(4 downto 0),
      gt0_rxresetdone_out => \^gt0_rxresetdone_out\,
      gt0_rxsyncdone_out => gt0_rxsyncdone_i,
      gt0_rxuserrdy_in => gt0_rxuserrdy_t,
      gt0_rxusrclk2_in => gt0_rxusrclk2_in,
      gt0_rxusrclk_in => gt0_rxusrclk_in,
      gt0_txcharisk_in(3 downto 0) => gt0_txcharisk_in(3 downto 0),
      gt0_txdata_in(31 downto 0) => gt0_txdata_in(31 downto 0),
      gt0_txdlyen_in => U0_TXDLYEN,
      gt0_txdlysresetdone_out => gt0_txdlysresetdone_out,
      gt0_txoutclk_out => gt0_txoutclk_out,
      gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
      gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
      gt0_txpd_in(1 downto 0) => gt0_txpd_in(1 downto 0),
      gt0_txphaligndone_out => gt0_txphaligndone_out,
      gt0_txphinitdone_out => gt0_txphinitdone_out,
      gt0_txresetdone_out => \^gt0_txresetdone_out\,
      gt0_txuserrdy_in => gt0_txuserrdy_t,
      gt0_txusrclk2_in => gt0_txusrclk2_in,
      gt0_txusrclk_in => gt0_txusrclk_in,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_drpaddr_in(8 downto 0) => gt1_drpaddr_in(8 downto 0),
      gt1_drpclk_in => gt1_drpclk_in,
      gt1_drpclk_in_0 => mgt11g2_tx_rx_cfpga_i_n_5,
      gt1_drpdi_in(15 downto 0) => gt1_drpdi_in(15 downto 0),
      gt1_drpdo_out(15 downto 0) => gt1_drpdo_out(15 downto 0),
      gt1_drpen_in => gt1_drpen_in,
      gt1_drprdy_out => gt1_drprdy_out,
      gt1_drpwe_in => gt1_drpwe_in,
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_gthrxn_in => gt1_gthrxn_in,
      gt1_gthrxp_in => gt1_gthrxp_in,
      gt1_gthtxn_out => gt1_gthtxn_out,
      gt1_gthtxp_out => gt1_gthtxp_out,
      gt1_gtnorthrefclk0_in => gt1_gtnorthrefclk0_in,
      gt1_gtnorthrefclk1_in => gt1_gtnorthrefclk1_in,
      gt1_gtrxreset_in => gt1_gtrxreset_t,
      gt1_gtsouthrefclk0_in => gt1_gtsouthrefclk0_in,
      gt1_gtsouthrefclk1_in => gt1_gtsouthrefclk1_in,
      gt1_gttxreset_in => gt1_gttxreset_t,
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxbyterealign_out => gt1_rxbyterealign_out,
      gt1_rxchariscomma_out(3 downto 0) => gt1_rxchariscomma_out(3 downto 0),
      gt1_rxcharisk_out(3 downto 0) => gt1_rxcharisk_out(3 downto 0),
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdata_out(31 downto 0) => gt1_rxdata_out(31 downto 0),
      gt1_rxdisperr_out(3 downto 0) => gt1_rxdisperr_out(3 downto 0),
      gt1_rxdlysreset_in => gt1_rxdlysreset_i,
      gt1_rxdlysresetdone_out => gt1_rxdlysresetdone_i,
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxnotintable_out(3 downto 0) => gt1_rxnotintable_out(3 downto 0),
      gt1_rxoutclk_out => gt1_rxoutclk_out,
      gt1_rxoutclkfabric_out => gt1_rxoutclkfabric_out,
      gt1_rxpd_in(1 downto 0) => gt1_rxpd_in(1 downto 0),
      gt1_rxphaligndone_out => gt1_rxphaligndone_i,
      gt1_rxphmonitor_out(4 downto 0) => gt1_rxphmonitor_out(4 downto 0),
      gt1_rxphslipmonitor_out(4 downto 0) => gt1_rxphslipmonitor_out(4 downto 0),
      gt1_rxresetdone_out => \^gt1_rxresetdone_out\,
      gt1_rxuserrdy_in => gt1_rxuserrdy_t,
      gt1_rxusrclk2_in => gt1_rxusrclk2_in,
      gt1_rxusrclk_in => gt1_rxusrclk_in,
      gt1_txcharisk_in(3 downto 0) => gt1_txcharisk_in(3 downto 0),
      gt1_txdata_in(31 downto 0) => gt1_txdata_in(31 downto 0),
      gt1_txdlysresetdone_out => gt1_txdlysresetdone_out,
      gt1_txoutclk_out => gt1_txoutclk_out,
      gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
      gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
      gt1_txpd_in(1 downto 0) => gt1_txpd_in(1 downto 0),
      gt1_txphaligndone_out => gt1_txphaligndone_out,
      gt1_txphinitdone_out => gt1_txphinitdone_out,
      gt1_txresetdone_out => \^gt1_txresetdone_out\,
      gt1_txuserrdy_in => gt1_txuserrdy_t,
      gt1_txusrclk2_in => gt1_txusrclk2_in,
      gt1_txusrclk_in => gt1_txusrclk_in,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_drpaddr_in(8 downto 0) => gt2_drpaddr_in(8 downto 0),
      gt2_drpclk_in => gt2_drpclk_in,
      gt2_drpclk_in_0 => mgt11g2_tx_rx_cfpga_i_n_7,
      gt2_drpdi_in(15 downto 0) => gt2_drpdi_in(15 downto 0),
      gt2_drpdo_out(15 downto 0) => gt2_drpdo_out(15 downto 0),
      gt2_drpen_in => gt2_drpen_in,
      gt2_drprdy_out => gt2_drprdy_out,
      gt2_drpwe_in => gt2_drpwe_in,
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_gthrxn_in => gt2_gthrxn_in,
      gt2_gthrxp_in => gt2_gthrxp_in,
      gt2_gthtxn_out => gt2_gthtxn_out,
      gt2_gthtxp_out => gt2_gthtxp_out,
      gt2_gtnorthrefclk0_in => gt2_gtnorthrefclk0_in,
      gt2_gtnorthrefclk1_in => gt2_gtnorthrefclk1_in,
      gt2_gtrxreset_in => gt2_gtrxreset_t,
      gt2_gtsouthrefclk0_in => gt2_gtsouthrefclk0_in,
      gt2_gtsouthrefclk1_in => gt2_gtsouthrefclk1_in,
      gt2_gttxreset_in => gt2_gttxreset_t,
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxbyterealign_out => gt2_rxbyterealign_out,
      gt2_rxchariscomma_out(3 downto 0) => gt2_rxchariscomma_out(3 downto 0),
      gt2_rxcharisk_out(3 downto 0) => gt2_rxcharisk_out(3 downto 0),
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdata_out(31 downto 0) => gt2_rxdata_out(31 downto 0),
      gt2_rxdisperr_out(3 downto 0) => gt2_rxdisperr_out(3 downto 0),
      gt2_rxdlysreset_in => gt2_rxdlysreset_i,
      gt2_rxdlysresetdone_out => gt2_rxdlysresetdone_i,
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxnotintable_out(3 downto 0) => gt2_rxnotintable_out(3 downto 0),
      gt2_rxoutclk_out => gt2_rxoutclk_out,
      gt2_rxoutclkfabric_out => gt2_rxoutclkfabric_out,
      gt2_rxpd_in(1 downto 0) => gt2_rxpd_in(1 downto 0),
      gt2_rxphaligndone_out => gt2_rxphaligndone_i,
      gt2_rxphmonitor_out(4 downto 0) => gt2_rxphmonitor_out(4 downto 0),
      gt2_rxphslipmonitor_out(4 downto 0) => gt2_rxphslipmonitor_out(4 downto 0),
      gt2_rxresetdone_out => \^gt2_rxresetdone_out\,
      gt2_rxuserrdy_in => gt2_rxuserrdy_t,
      gt2_rxusrclk2_in => gt2_rxusrclk2_in,
      gt2_rxusrclk_in => gt2_rxusrclk_in,
      gt2_txcharisk_in(3 downto 0) => gt2_txcharisk_in(3 downto 0),
      gt2_txdata_in(31 downto 0) => gt2_txdata_in(31 downto 0),
      gt2_txdlysresetdone_out => gt2_txdlysresetdone_out,
      gt2_txoutclk_out => gt2_txoutclk_out,
      gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
      gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
      gt2_txpd_in(1 downto 0) => gt2_txpd_in(1 downto 0),
      gt2_txphaligndone_out => gt2_txphaligndone_out,
      gt2_txphinitdone_out => gt2_txphinitdone_out,
      gt2_txresetdone_out => \^gt2_txresetdone_out\,
      gt2_txuserrdy_in => gt2_txuserrdy_t,
      gt2_txusrclk2_in => gt2_txusrclk2_in,
      gt2_txusrclk_in => gt2_txusrclk_in,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_drpaddr_in(8 downto 0) => gt3_drpaddr_in(8 downto 0),
      gt3_drpclk_in => gt3_drpclk_in,
      gt3_drpclk_in_0 => mgt11g2_tx_rx_cfpga_i_n_9,
      gt3_drpdi_in(15 downto 0) => gt3_drpdi_in(15 downto 0),
      gt3_drpdo_out(15 downto 0) => gt3_drpdo_out(15 downto 0),
      gt3_drpen_in => gt3_drpen_in,
      gt3_drprdy_out => gt3_drprdy_out,
      gt3_drpwe_in => gt3_drpwe_in,
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_gthrxn_in => gt3_gthrxn_in,
      gt3_gthrxp_in => gt3_gthrxp_in,
      gt3_gthtxn_out => gt3_gthtxn_out,
      gt3_gthtxp_out => gt3_gthtxp_out,
      gt3_gtnorthrefclk0_in => gt3_gtnorthrefclk0_in,
      gt3_gtnorthrefclk1_in => gt3_gtnorthrefclk1_in,
      gt3_gtrxreset_in => gt3_gtrxreset_t,
      gt3_gtsouthrefclk0_in => gt3_gtsouthrefclk0_in,
      gt3_gtsouthrefclk1_in => gt3_gtsouthrefclk1_in,
      gt3_gttxreset_in => gt3_gttxreset_t,
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxbyterealign_out => gt3_rxbyterealign_out,
      gt3_rxchariscomma_out(3 downto 0) => gt3_rxchariscomma_out(3 downto 0),
      gt3_rxcharisk_out(3 downto 0) => gt3_rxcharisk_out(3 downto 0),
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdata_out(31 downto 0) => gt3_rxdata_out(31 downto 0),
      gt3_rxdisperr_out(3 downto 0) => gt3_rxdisperr_out(3 downto 0),
      gt3_rxdlysreset_in => gt3_rxdlysreset_i,
      gt3_rxdlysresetdone_out => gt3_rxdlysresetdone_i,
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxnotintable_out(3 downto 0) => gt3_rxnotintable_out(3 downto 0),
      gt3_rxoutclk_out => gt3_rxoutclk_out,
      gt3_rxoutclkfabric_out => gt3_rxoutclkfabric_out,
      gt3_rxpd_in(1 downto 0) => gt3_rxpd_in(1 downto 0),
      gt3_rxphaligndone_out => gt3_rxphaligndone_i,
      gt3_rxphmonitor_out(4 downto 0) => gt3_rxphmonitor_out(4 downto 0),
      gt3_rxphslipmonitor_out(4 downto 0) => gt3_rxphslipmonitor_out(4 downto 0),
      gt3_rxresetdone_out => \^gt3_rxresetdone_out\,
      gt3_rxuserrdy_in => gt3_rxuserrdy_t,
      gt3_rxusrclk2_in => gt3_rxusrclk2_in,
      gt3_rxusrclk_in => gt3_rxusrclk_in,
      gt3_txcharisk_in(3 downto 0) => gt3_txcharisk_in(3 downto 0),
      gt3_txdata_in(31 downto 0) => gt3_txdata_in(31 downto 0),
      gt3_txdlysresetdone_out => gt3_txdlysresetdone_out,
      gt3_txoutclk_out => gt3_txoutclk_out,
      gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
      gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
      gt3_txpd_in(1 downto 0) => gt3_txpd_in(1 downto 0),
      gt3_txphaligndone_out => gt3_txphaligndone_out,
      gt3_txphinitdone_out => gt3_txphinitdone_out,
      gt3_txresetdone_out => \^gt3_txresetdone_out\,
      gt3_txuserrdy_in => gt3_txuserrdy_t,
      gt3_txusrclk2_in => gt3_txusrclk2_in,
      gt3_txusrclk_in => gt3_txusrclk_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mgt11g2_tx_rx_cfpga is
  port (
    SYSCLK_IN : in STD_LOGIC;
    SOFT_RESET_TX_IN : in STD_LOGIC;
    SOFT_RESET_RX_IN : in STD_LOGIC;
    DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC;
    GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT0_DATA_VALID_IN : in STD_LOGIC;
    GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT1_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT1_DATA_VALID_IN : in STD_LOGIC;
    GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT2_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT2_DATA_VALID_IN : in STD_LOGIC;
    GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT3_RX_FSM_RESET_DONE_OUT : out STD_LOGIC;
    GT3_DATA_VALID_IN : in STD_LOGIC;
    gt0_gtnorthrefclk0_in : in STD_LOGIC;
    gt0_gtnorthrefclk1_in : in STD_LOGIC;
    gt0_gtsouthrefclk0_in : in STD_LOGIC;
    gt0_gtsouthrefclk1_in : in STD_LOGIC;
    gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt0_drpclk_in : in STD_LOGIC;
    gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_drpen_in : in STD_LOGIC;
    gt0_drprdy_out : out STD_LOGIC;
    gt0_drpwe_in : in STD_LOGIC;
    gt0_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_rxuserrdy_in : in STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_rxusrclk_in : in STD_LOGIC;
    gt0_rxusrclk2_in : in STD_LOGIC;
    gt0_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_gthrxn_in : in STD_LOGIC;
    gt0_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxbyterealign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxoutclk_out : out STD_LOGIC;
    gt0_rxoutclkfabric_out : out STD_LOGIC;
    gt0_gtrxreset_in : in STD_LOGIC;
    gt0_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_gthrxp_in : in STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_gttxreset_in : in STD_LOGIC;
    gt0_txuserrdy_in : in STD_LOGIC;
    gt0_txusrclk_in : in STD_LOGIC;
    gt0_txusrclk2_in : in STD_LOGIC;
    gt0_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_gthtxn_out : out STD_LOGIC;
    gt0_gthtxp_out : out STD_LOGIC;
    gt0_txoutclk_out : out STD_LOGIC;
    gt0_txoutclkfabric_out : out STD_LOGIC;
    gt0_txoutclkpcs_out : out STD_LOGIC;
    gt0_txresetdone_out : out STD_LOGIC;
    gt0_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_gtnorthrefclk0_in : in STD_LOGIC;
    gt1_gtnorthrefclk1_in : in STD_LOGIC;
    gt1_gtsouthrefclk0_in : in STD_LOGIC;
    gt1_gtsouthrefclk1_in : in STD_LOGIC;
    gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt1_drpclk_in : in STD_LOGIC;
    gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_drpen_in : in STD_LOGIC;
    gt1_drprdy_out : out STD_LOGIC;
    gt1_drpwe_in : in STD_LOGIC;
    gt1_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_rxuserrdy_in : in STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt1_rxusrclk_in : in STD_LOGIC;
    gt1_rxusrclk2_in : in STD_LOGIC;
    gt1_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_gthrxn_in : in STD_LOGIC;
    gt1_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gt1_rxbyterealign_out : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxoutclk_out : out STD_LOGIC;
    gt1_rxoutclkfabric_out : out STD_LOGIC;
    gt1_gtrxreset_in : in STD_LOGIC;
    gt1_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt1_gthrxp_in : in STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_gttxreset_in : in STD_LOGIC;
    gt1_txuserrdy_in : in STD_LOGIC;
    gt1_txusrclk_in : in STD_LOGIC;
    gt1_txusrclk2_in : in STD_LOGIC;
    gt1_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt1_gthtxn_out : out STD_LOGIC;
    gt1_gthtxp_out : out STD_LOGIC;
    gt1_txoutclk_out : out STD_LOGIC;
    gt1_txoutclkfabric_out : out STD_LOGIC;
    gt1_txoutclkpcs_out : out STD_LOGIC;
    gt1_txresetdone_out : out STD_LOGIC;
    gt1_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_gtnorthrefclk0_in : in STD_LOGIC;
    gt2_gtnorthrefclk1_in : in STD_LOGIC;
    gt2_gtsouthrefclk0_in : in STD_LOGIC;
    gt2_gtsouthrefclk1_in : in STD_LOGIC;
    gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt2_drpclk_in : in STD_LOGIC;
    gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_drpen_in : in STD_LOGIC;
    gt2_drprdy_out : out STD_LOGIC;
    gt2_drpwe_in : in STD_LOGIC;
    gt2_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_rxuserrdy_in : in STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt2_rxusrclk_in : in STD_LOGIC;
    gt2_rxusrclk2_in : in STD_LOGIC;
    gt2_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_gthrxn_in : in STD_LOGIC;
    gt2_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gt2_rxbyterealign_out : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxoutclk_out : out STD_LOGIC;
    gt2_rxoutclkfabric_out : out STD_LOGIC;
    gt2_gtrxreset_in : in STD_LOGIC;
    gt2_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt2_gthrxp_in : in STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    gt2_gttxreset_in : in STD_LOGIC;
    gt2_txuserrdy_in : in STD_LOGIC;
    gt2_txusrclk_in : in STD_LOGIC;
    gt2_txusrclk2_in : in STD_LOGIC;
    gt2_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt2_gthtxn_out : out STD_LOGIC;
    gt2_gthtxp_out : out STD_LOGIC;
    gt2_txoutclk_out : out STD_LOGIC;
    gt2_txoutclkfabric_out : out STD_LOGIC;
    gt2_txoutclkpcs_out : out STD_LOGIC;
    gt2_txresetdone_out : out STD_LOGIC;
    gt2_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_gtnorthrefclk0_in : in STD_LOGIC;
    gt3_gtnorthrefclk1_in : in STD_LOGIC;
    gt3_gtsouthrefclk0_in : in STD_LOGIC;
    gt3_gtsouthrefclk1_in : in STD_LOGIC;
    gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gt3_drpclk_in : in STD_LOGIC;
    gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_drpen_in : in STD_LOGIC;
    gt3_drprdy_out : out STD_LOGIC;
    gt3_drpwe_in : in STD_LOGIC;
    gt3_rxpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_txpd_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_rxuserrdy_in : in STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt3_rxusrclk_in : in STD_LOGIC;
    gt3_rxusrclk2_in : in STD_LOGIC;
    gt3_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_gthrxn_in : in STD_LOGIC;
    gt3_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gt3_rxbyterealign_out : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxoutclk_out : out STD_LOGIC;
    gt3_rxoutclkfabric_out : out STD_LOGIC;
    gt3_gtrxreset_in : in STD_LOGIC;
    gt3_rxchariscomma_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt3_gthrxp_in : in STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_gttxreset_in : in STD_LOGIC;
    gt3_txuserrdy_in : in STD_LOGIC;
    gt3_txusrclk_in : in STD_LOGIC;
    gt3_txusrclk2_in : in STD_LOGIC;
    gt3_txdata_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    gt3_gthtxn_out : out STD_LOGIC;
    gt3_gthtxp_out : out STD_LOGIC;
    gt3_txoutclk_out : out STD_LOGIC;
    gt3_txoutclkfabric_out : out STD_LOGIC;
    gt3_txoutclkpcs_out : out STD_LOGIC;
    gt3_txresetdone_out : out STD_LOGIC;
    gt3_txcharisk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    GT0_QPLLLOCK_IN : in STD_LOGIC;
    GT0_QPLLREFCLKLOST_IN : in STD_LOGIC;
    GT0_QPLLRESET_OUT : out STD_LOGIC;
    GT0_QPLLOUTCLK_IN : in STD_LOGIC;
    GT0_QPLLOUTREFCLK_IN : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of mgt11g2_tx_rx_cfpga : entity is true;
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of mgt11g2_tx_rx_cfpga : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of mgt11g2_tx_rx_cfpga : entity is "mgt11g2_tx_rx_cfpga,gtwizard_v3_6_11,{protocol_file=Start_from_scratch}";
end mgt11g2_tx_rx_cfpga;

architecture STRUCTURE of mgt11g2_tx_rx_cfpga is
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of U0 : label is 0;
  attribute EXAMPLE_SIM_GTRESET_SPEEDUP : string;
  attribute EXAMPLE_SIM_GTRESET_SPEEDUP of U0 : label is "TRUE";
  attribute EXAMPLE_USE_CHIPSCOPE : integer;
  attribute EXAMPLE_USE_CHIPSCOPE of U0 : label is 0;
  attribute STABLE_CLOCK_PERIOD : integer;
  attribute STABLE_CLOCK_PERIOD of U0 : label is 16;
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init
     port map (
      DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
      GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
      GT0_QPLLLOCK_IN => GT0_QPLLLOCK_IN,
      GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
      GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
      GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_IN,
      GT0_QPLLRESET_OUT => GT0_QPLLRESET_OUT,
      GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
      GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
      GT1_DATA_VALID_IN => GT1_DATA_VALID_IN,
      GT1_RX_FSM_RESET_DONE_OUT => GT1_RX_FSM_RESET_DONE_OUT,
      GT1_TX_FSM_RESET_DONE_OUT => GT1_TX_FSM_RESET_DONE_OUT,
      GT2_DATA_VALID_IN => GT2_DATA_VALID_IN,
      GT2_RX_FSM_RESET_DONE_OUT => GT2_RX_FSM_RESET_DONE_OUT,
      GT2_TX_FSM_RESET_DONE_OUT => GT2_TX_FSM_RESET_DONE_OUT,
      GT3_DATA_VALID_IN => GT3_DATA_VALID_IN,
      GT3_RX_FSM_RESET_DONE_OUT => GT3_RX_FSM_RESET_DONE_OUT,
      GT3_TX_FSM_RESET_DONE_OUT => GT3_TX_FSM_RESET_DONE_OUT,
      SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
      SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
      SYSCLK_IN => SYSCLK_IN,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_drpaddr_in(8 downto 0) => gt0_drpaddr_in(8 downto 0),
      gt0_drpclk_in => gt0_drpclk_in,
      gt0_drpdi_in(15 downto 0) => gt0_drpdi_in(15 downto 0),
      gt0_drpdo_out(15 downto 0) => gt0_drpdo_out(15 downto 0),
      gt0_drpen_in => gt0_drpen_in,
      gt0_drprdy_out => gt0_drprdy_out,
      gt0_drpwe_in => gt0_drpwe_in,
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_gthrxn_in => gt0_gthrxn_in,
      gt0_gthrxp_in => gt0_gthrxp_in,
      gt0_gthtxn_out => gt0_gthtxn_out,
      gt0_gthtxp_out => gt0_gthtxp_out,
      gt0_gtnorthrefclk0_in => gt0_gtnorthrefclk0_in,
      gt0_gtnorthrefclk1_in => gt0_gtnorthrefclk1_in,
      gt0_gtrxreset_in => gt0_gtrxreset_in,
      gt0_gtsouthrefclk0_in => gt0_gtsouthrefclk0_in,
      gt0_gtsouthrefclk1_in => gt0_gtsouthrefclk1_in,
      gt0_gttxreset_in => gt0_gttxreset_in,
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxbyterealign_out => gt0_rxbyterealign_out,
      gt0_rxchariscomma_out(3 downto 0) => gt0_rxchariscomma_out(3 downto 0),
      gt0_rxcharisk_out(3 downto 0) => gt0_rxcharisk_out(3 downto 0),
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdata_out(31 downto 0) => gt0_rxdata_out(31 downto 0),
      gt0_rxdisperr_out(3 downto 0) => gt0_rxdisperr_out(3 downto 0),
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxnotintable_out(3 downto 0) => gt0_rxnotintable_out(3 downto 0),
      gt0_rxoutclk_out => gt0_rxoutclk_out,
      gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out,
      gt0_rxpd_in(1 downto 0) => gt0_rxpd_in(1 downto 0),
      gt0_rxphmonitor_out(4 downto 0) => gt0_rxphmonitor_out(4 downto 0),
      gt0_rxphslipmonitor_out(4 downto 0) => gt0_rxphslipmonitor_out(4 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt0_rxuserrdy_in => gt0_rxuserrdy_in,
      gt0_rxusrclk2_in => gt0_rxusrclk2_in,
      gt0_rxusrclk_in => gt0_rxusrclk_in,
      gt0_txcharisk_in(3 downto 0) => gt0_txcharisk_in(3 downto 0),
      gt0_txdata_in(31 downto 0) => gt0_txdata_in(31 downto 0),
      gt0_txoutclk_out => gt0_txoutclk_out,
      gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
      gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
      gt0_txpd_in(1 downto 0) => gt0_txpd_in(1 downto 0),
      gt0_txresetdone_out => gt0_txresetdone_out,
      gt0_txuserrdy_in => gt0_txuserrdy_in,
      gt0_txusrclk2_in => gt0_txusrclk2_in,
      gt0_txusrclk_in => gt0_txusrclk_in,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_drpaddr_in(8 downto 0) => gt1_drpaddr_in(8 downto 0),
      gt1_drpclk_in => gt1_drpclk_in,
      gt1_drpdi_in(15 downto 0) => gt1_drpdi_in(15 downto 0),
      gt1_drpdo_out(15 downto 0) => gt1_drpdo_out(15 downto 0),
      gt1_drpen_in => gt1_drpen_in,
      gt1_drprdy_out => gt1_drprdy_out,
      gt1_drpwe_in => gt1_drpwe_in,
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_gthrxn_in => gt1_gthrxn_in,
      gt1_gthrxp_in => gt1_gthrxp_in,
      gt1_gthtxn_out => gt1_gthtxn_out,
      gt1_gthtxp_out => gt1_gthtxp_out,
      gt1_gtnorthrefclk0_in => gt1_gtnorthrefclk0_in,
      gt1_gtnorthrefclk1_in => gt1_gtnorthrefclk1_in,
      gt1_gtrxreset_in => gt1_gtrxreset_in,
      gt1_gtsouthrefclk0_in => gt1_gtsouthrefclk0_in,
      gt1_gtsouthrefclk1_in => gt1_gtsouthrefclk1_in,
      gt1_gttxreset_in => gt1_gttxreset_in,
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxbyterealign_out => gt1_rxbyterealign_out,
      gt1_rxchariscomma_out(3 downto 0) => gt1_rxchariscomma_out(3 downto 0),
      gt1_rxcharisk_out(3 downto 0) => gt1_rxcharisk_out(3 downto 0),
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdata_out(31 downto 0) => gt1_rxdata_out(31 downto 0),
      gt1_rxdisperr_out(3 downto 0) => gt1_rxdisperr_out(3 downto 0),
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxnotintable_out(3 downto 0) => gt1_rxnotintable_out(3 downto 0),
      gt1_rxoutclk_out => gt1_rxoutclk_out,
      gt1_rxoutclkfabric_out => gt1_rxoutclkfabric_out,
      gt1_rxpd_in(1 downto 0) => gt1_rxpd_in(1 downto 0),
      gt1_rxphmonitor_out(4 downto 0) => gt1_rxphmonitor_out(4 downto 0),
      gt1_rxphslipmonitor_out(4 downto 0) => gt1_rxphslipmonitor_out(4 downto 0),
      gt1_rxresetdone_out => gt1_rxresetdone_out,
      gt1_rxuserrdy_in => gt1_rxuserrdy_in,
      gt1_rxusrclk2_in => gt1_rxusrclk2_in,
      gt1_rxusrclk_in => gt1_rxusrclk_in,
      gt1_txcharisk_in(3 downto 0) => gt1_txcharisk_in(3 downto 0),
      gt1_txdata_in(31 downto 0) => gt1_txdata_in(31 downto 0),
      gt1_txoutclk_out => gt1_txoutclk_out,
      gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
      gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
      gt1_txpd_in(1 downto 0) => gt1_txpd_in(1 downto 0),
      gt1_txresetdone_out => gt1_txresetdone_out,
      gt1_txuserrdy_in => gt1_txuserrdy_in,
      gt1_txusrclk2_in => gt1_txusrclk2_in,
      gt1_txusrclk_in => gt1_txusrclk_in,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_drpaddr_in(8 downto 0) => gt2_drpaddr_in(8 downto 0),
      gt2_drpclk_in => gt2_drpclk_in,
      gt2_drpdi_in(15 downto 0) => gt2_drpdi_in(15 downto 0),
      gt2_drpdo_out(15 downto 0) => gt2_drpdo_out(15 downto 0),
      gt2_drpen_in => gt2_drpen_in,
      gt2_drprdy_out => gt2_drprdy_out,
      gt2_drpwe_in => gt2_drpwe_in,
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_gthrxn_in => gt2_gthrxn_in,
      gt2_gthrxp_in => gt2_gthrxp_in,
      gt2_gthtxn_out => gt2_gthtxn_out,
      gt2_gthtxp_out => gt2_gthtxp_out,
      gt2_gtnorthrefclk0_in => gt2_gtnorthrefclk0_in,
      gt2_gtnorthrefclk1_in => gt2_gtnorthrefclk1_in,
      gt2_gtrxreset_in => gt2_gtrxreset_in,
      gt2_gtsouthrefclk0_in => gt2_gtsouthrefclk0_in,
      gt2_gtsouthrefclk1_in => gt2_gtsouthrefclk1_in,
      gt2_gttxreset_in => gt2_gttxreset_in,
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxbyterealign_out => gt2_rxbyterealign_out,
      gt2_rxchariscomma_out(3 downto 0) => gt2_rxchariscomma_out(3 downto 0),
      gt2_rxcharisk_out(3 downto 0) => gt2_rxcharisk_out(3 downto 0),
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdata_out(31 downto 0) => gt2_rxdata_out(31 downto 0),
      gt2_rxdisperr_out(3 downto 0) => gt2_rxdisperr_out(3 downto 0),
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxnotintable_out(3 downto 0) => gt2_rxnotintable_out(3 downto 0),
      gt2_rxoutclk_out => gt2_rxoutclk_out,
      gt2_rxoutclkfabric_out => gt2_rxoutclkfabric_out,
      gt2_rxpd_in(1 downto 0) => gt2_rxpd_in(1 downto 0),
      gt2_rxphmonitor_out(4 downto 0) => gt2_rxphmonitor_out(4 downto 0),
      gt2_rxphslipmonitor_out(4 downto 0) => gt2_rxphslipmonitor_out(4 downto 0),
      gt2_rxresetdone_out => gt2_rxresetdone_out,
      gt2_rxuserrdy_in => gt2_rxuserrdy_in,
      gt2_rxusrclk2_in => gt2_rxusrclk2_in,
      gt2_rxusrclk_in => gt2_rxusrclk_in,
      gt2_txcharisk_in(3 downto 0) => gt2_txcharisk_in(3 downto 0),
      gt2_txdata_in(31 downto 0) => gt2_txdata_in(31 downto 0),
      gt2_txoutclk_out => gt2_txoutclk_out,
      gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
      gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
      gt2_txpd_in(1 downto 0) => gt2_txpd_in(1 downto 0),
      gt2_txresetdone_out => gt2_txresetdone_out,
      gt2_txuserrdy_in => gt2_txuserrdy_in,
      gt2_txusrclk2_in => gt2_txusrclk2_in,
      gt2_txusrclk_in => gt2_txusrclk_in,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_drpaddr_in(8 downto 0) => gt3_drpaddr_in(8 downto 0),
      gt3_drpclk_in => gt3_drpclk_in,
      gt3_drpdi_in(15 downto 0) => gt3_drpdi_in(15 downto 0),
      gt3_drpdo_out(15 downto 0) => gt3_drpdo_out(15 downto 0),
      gt3_drpen_in => gt3_drpen_in,
      gt3_drprdy_out => gt3_drprdy_out,
      gt3_drpwe_in => gt3_drpwe_in,
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_gthrxn_in => gt3_gthrxn_in,
      gt3_gthrxp_in => gt3_gthrxp_in,
      gt3_gthtxn_out => gt3_gthtxn_out,
      gt3_gthtxp_out => gt3_gthtxp_out,
      gt3_gtnorthrefclk0_in => gt3_gtnorthrefclk0_in,
      gt3_gtnorthrefclk1_in => gt3_gtnorthrefclk1_in,
      gt3_gtrxreset_in => gt3_gtrxreset_in,
      gt3_gtsouthrefclk0_in => gt3_gtsouthrefclk0_in,
      gt3_gtsouthrefclk1_in => gt3_gtsouthrefclk1_in,
      gt3_gttxreset_in => gt3_gttxreset_in,
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxbyterealign_out => gt3_rxbyterealign_out,
      gt3_rxchariscomma_out(3 downto 0) => gt3_rxchariscomma_out(3 downto 0),
      gt3_rxcharisk_out(3 downto 0) => gt3_rxcharisk_out(3 downto 0),
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdata_out(31 downto 0) => gt3_rxdata_out(31 downto 0),
      gt3_rxdisperr_out(3 downto 0) => gt3_rxdisperr_out(3 downto 0),
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxnotintable_out(3 downto 0) => gt3_rxnotintable_out(3 downto 0),
      gt3_rxoutclk_out => gt3_rxoutclk_out,
      gt3_rxoutclkfabric_out => gt3_rxoutclkfabric_out,
      gt3_rxpd_in(1 downto 0) => gt3_rxpd_in(1 downto 0),
      gt3_rxphmonitor_out(4 downto 0) => gt3_rxphmonitor_out(4 downto 0),
      gt3_rxphslipmonitor_out(4 downto 0) => gt3_rxphslipmonitor_out(4 downto 0),
      gt3_rxresetdone_out => gt3_rxresetdone_out,
      gt3_rxuserrdy_in => gt3_rxuserrdy_in,
      gt3_rxusrclk2_in => gt3_rxusrclk2_in,
      gt3_rxusrclk_in => gt3_rxusrclk_in,
      gt3_txcharisk_in(3 downto 0) => gt3_txcharisk_in(3 downto 0),
      gt3_txdata_in(31 downto 0) => gt3_txdata_in(31 downto 0),
      gt3_txoutclk_out => gt3_txoutclk_out,
      gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
      gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
      gt3_txpd_in(1 downto 0) => gt3_txpd_in(1 downto 0),
      gt3_txresetdone_out => gt3_txresetdone_out,
      gt3_txuserrdy_in => gt3_txuserrdy_in,
      gt3_txusrclk2_in => gt3_txusrclk2_in,
      gt3_txusrclk_in => gt3_txusrclk_in
    );
end STRUCTURE;
