--------------------------------------------------------------------------------
-- Title      : CDC Sync Block
-- Project    : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File       : temac_gbe_v9_0_syncer_level.vhd
-- Author     : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to another, this
--              is a multiple flip-flop pipeline, with all flops placed together
--              into the same slice.  Thus the routing delay between the two is
--              minimum to safe-guard against metastability issues.
-- -----------------------------------------------------------------------------
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library ieee;
use ieee.std_logic_1164.all;

library unisim;
use unisim.vcomponents.all;

entity temac_gbe_v9_0_syncer_level is
generic (
  WIDTH       : integer   := 1;
  RESET_VALUE : std_logic := '1'
 );
port (
  clk       : in  std_logic;
  reset     : in  std_logic;

  datain    : in  std_logic_vector(WIDTH-1 downto 0);
  dataout   : out std_logic_vector(WIDTH-1 downto 0)
);

  attribute dont_touch : string;
  attribute dont_touch of  temac_gbe_v9_0_syncer_level : entity is "yes";

end temac_gbe_v9_0_syncer_level;  

architecture rtl of temac_gbe_v9_0_syncer_level is 

  signal  dataout_reg : std_logic_vector(WIDTH-1 downto 0);
  signal  meta_nxt    : std_logic_vector(WIDTH-1 downto 0);
  signal  dataout_nxt : std_logic_vector(WIDTH-1 downto 0);

  signal  meta        : std_logic_vector(WIDTH-1 downto 0);
  signal  meta2       : std_logic_vector(WIDTH-1 downto 0);

  attribute async_reg : string;
  attribute async_reg of dataout_reg  : signal is "true";
  attribute async_reg of meta         : signal is "true";
  attribute async_reg of meta2        : signal is "true";

begin

  meta_nxt <= datain;

  process(clk)
  begin
    if(rising_edge(clk)) then
      if(reset = '1') then 
        meta  <= (others => RESET_VALUE);
        meta2 <= (others => RESET_VALUE);
      else
        meta  <= meta_nxt;
        meta2 <= meta;
      end if;
    end if;
  end process;

  dataout_nxt <= meta2;

  process(clk)
  begin
    if(rising_edge(clk)) then
      if(reset = '1') then
        dataout_reg <= (others => RESET_VALUE);
      else
        dataout_reg <= dataout_nxt;
      end if;
    end if;
  end process;

  dataout <= dataout_reg;

end rtl;


