*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2520.078 ; gain = 0.000 ; free physical = 74340 ; free virtual = 78985 INFO: [Netlist 29-17] Analyzing 324 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3139.262 ; gain = 563.164 ; free physical = 72418 ; free virtual = 77066 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.262 ; gain = 0.000 ; free physical = 72415 ; free virtual = 77062 INFO: [Project 1-111] Unisim Transformation Summary: A total of 49 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 17 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 3139.262 ; gain = 619.191 ; free physical = 72415 ; free virtual = 77062 source /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3147.266 ; gain = 8.000 ; free physical = 72348 ; free virtual = 76996 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 105ffc034 Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.61 . Memory (MB): peak = 3147.266 ; gain = 0.000 ; free physical = 72301 ; free virtual = 76949 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 2 inverter(s) to 3 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: ae5ddbe8 Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72174 ; free virtual = 76822 INFO: [Opt 31-389] Phase Retarget created 44 cells and removed 344 cells INFO: [Opt 31-1021] In phase Retarget, 66 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 12f0898ca Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72213 ; free virtual = 76860 INFO: [Opt 31-389] Phase Constant propagation created 153 cells and removed 437 cells INFO: [Opt 31-1021] In phase Constant propagation, 58 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 88bc4738 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72208 ; free virtual = 76855 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 233 cells INFO: [Opt 31-1021] In phase Sweep, 187 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 4 BUFG optimization | Checksum: 12c9e1f8c Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72206 ; free virtual = 76853 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 12c9e1f8c Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72206 ; free virtual = 76853 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: b0ae0bc6 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72206 ; free virtual = 76853 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 59 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 44 | 344 | 66 | | Constant propagation | 153 | 437 | 58 | | Sweep | 2 | 233 | 187 | | BUFG optimization | 0 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 59 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3285.266 ; gain = 0.000 ; free physical = 72211 ; free virtual = 76858 Ending Logic Optimization Task | Checksum: 75b7a884 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3285.266 ; gain = 0.004 ; free physical = 72211 ; free virtual = 76858 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 23 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 46 Ending PowerOpt Patch Enables Task | Checksum: 11d850155 Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72145 ; free virtual = 76795 Ending Power Optimization Task | Checksum: 11d850155 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3617.363 ; gain = 332.098 ; free physical = 72151 ; free virtual = 76801 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 5816ce26 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72114 ; free virtual = 76774 Ending Final Cleanup Task | Checksum: 5816ce26 Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72114 ; free virtual = 76774 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72114 ; free virtual = 76774 Ending Netlist Obfuscation Task | Checksum: 5816ce26 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72114 ; free virtual = 76774 INFO: [Common 17-83] Releasing license: Implementation 51 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3617.363 ; gain = 478.102 ; free physical = 72114 ; free virtual = 76775 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72091 ; free virtual = 76759 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72407 ; free virtual = 77071 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 47c64c97 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72407 ; free virtual = 77071 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72407 ; free virtual = 77071 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1288feaa1 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72505 ; free virtual = 77169 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1529fb290 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 73355 ; free virtual = 78019 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1529fb290 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 73353 ; free virtual = 78017 Phase 1 Placer Initialization | Checksum: 1529fb290 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 73340 ; free virtual = 78004 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 15579d0f6 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 73344 ; free virtual = 78008 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: f6b53a54 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 73341 ; free virtual = 78005 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 401 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 167 nets or cells. Created 0 new cell, deleted 167 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72802 ; free virtual = 77466 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 167 | 167 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 167 | 167 | 0 | 3 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1bbeea8e0 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72756 ; free virtual = 77453 Phase 2.3 Global Placement Core | Checksum: 1ef606d47 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72715 ; free virtual = 77442 Phase 2 Global Placement | Checksum: 1ef606d47 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72720 ; free virtual = 77448 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2335e38c8 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72667 ; free virtual = 77439 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24a3d553d Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 71771 ; free virtual = 76669 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18fc5b816 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 71707 ; free virtual = 76615 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1d2395ea9 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 71694 ; free virtual = 76604 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 298e53c78 Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72216 ; free virtual = 77179 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 23c576564 Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72423 ; free virtual = 77116 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 15278b0cb Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72414 ; free virtual = 77107 Phase 3 Detail Placement | Checksum: 15278b0cb Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72410 ; free virtual = 77103 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: b055ddbe Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.891 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 909d8f9c Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.84 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72552 ; free virtual = 77253 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 67eb4f22 Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.89 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72546 ; free virtual = 77247 Phase 4.1.1.1 BUFG Insertion | Checksum: b055ddbe Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72541 ; free virtual = 77242 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.891. For the most accurate timing information please run report_timing. Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72551 ; free virtual = 77252 Phase 4.1 Post Commit Optimization | Checksum: 6e62f880 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72537 ; free virtual = 77238 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 6e62f880 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72542 ; free virtual = 77243 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 6e62f880 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72537 ; free virtual = 77238 Phase 4.3 Placer Reporting | Checksum: 6e62f880 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72537 ; free virtual = 77239 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72537 ; free virtual = 77239 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72537 ; free virtual = 77239 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 146cc6a46 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72533 ; free virtual = 77235 Ending Placer Task | Checksum: 130043f59 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72530 ; free virtual = 77233 INFO: [Common 17-83] Releasing license: Implementation 84 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72558 ; free virtual = 77261 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.60 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72491 ; free virtual = 77203 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72466 ; free virtual = 77165 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72488 ; free virtual = 77188 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 96 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.61 . Memory (MB): peak = 3617.363 ; gain = 0.000 ; free physical = 72266 ; free virtual = 76970 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 3008cfb1 ConstDB: 0 ShapeSum: fffb6fa8 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 11314797e Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3728.469 ; gain = 111.105 ; free physical = 72622 ; free virtual = 77314 Post Restoration Checksum: NetGraph: e9c72e69 NumContArr: 294d4b15 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 11314797e Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 3728.469 ; gain = 111.105 ; free physical = 72578 ; free virtual = 77270 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 11314797e Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 3730.469 ; gain = 113.105 ; free physical = 72550 ; free virtual = 77242 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 11314797e Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 3730.469 ; gain = 113.105 ; free physical = 72565 ; free virtual = 77257 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 143181aa4 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 72200 ; free virtual = 76892 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=-0.258 | THS=-318.019| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1d3237f8d Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 72054 ; free virtual = 76746 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 114212da0 Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 72054 ; free virtual = 76745 Phase 2 Router Initialization | Checksum: 15e0e235b Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 72054 ; free virtual = 76745 Router Utilization Summary Global Vertical Routing Utilization = 7.78877e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 9927 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 9925 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 15e0e235b Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 72030 ; free virtual = 76721 Phase 3 Initial Routing | Checksum: f5a1cb24 Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 71881 ; free virtual = 76573 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 845 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 2520e91ad Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70425 ; free virtual = 75116 Phase 4 Rip-up And Reroute | Checksum: 2520e91ad Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70407 ; free virtual = 75098 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 2520e91ad Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70379 ; free virtual = 75070 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 2520e91ad Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70363 ; free virtual = 75054 Phase 5 Delay and Skew Optimization | Checksum: 2520e91ad Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70347 ; free virtual = 75038 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 2550d2de7 Time (s): cpu = 00:00:59 ; elapsed = 00:01:00 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 69840 ; free virtual = 74531 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.054 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 2bf2511a7 Time (s): cpu = 00:00:59 ; elapsed = 00:01:00 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 69838 ; free virtual = 74529 Phase 6 Post Hold Fix | Checksum: 2bf2511a7 Time (s): cpu = 00:00:59 ; elapsed = 00:01:00 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 69838 ; free virtual = 74529 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.536425 % Global Horizontal Routing Utilization = 0.601585 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 2bf2511a7 Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 69821 ; free virtual = 74512 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 2bf2511a7 Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 69817 ; free virtual = 74508 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 2bdd0b6b4 Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70363 ; free virtual = 75083 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.054 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 2bdd0b6b4 Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70396 ; free virtual = 75120 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70407 ; free virtual = 75132 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 111 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:06 . Memory (MB): peak = 3797.680 ; gain = 180.316 ; free physical = 70407 ; free virtual = 75132 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.0.0-hogd6f4f62 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_golden_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] The git SHA value d6f4f62 will be set as bitstream USERID. INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.0.0-hogd6f4f62 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_control-v1.0.0-hogd6f4f62... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.