Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Thu Jul 21 20:40:17 2022 | Host : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.1.0-hogac022a1/reports/hierarchical_utilization.txt | Design : top_efex_control | Device : 7vx330tffg1157-2 | Design State : Routed ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-----------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------+---------------+-------------+------------+---------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-----------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------+---------------+-------------+------------+---------------+-------------+-----------+------------+ | top_efex_control | (top) | 27441(13.45%) | 25088(12.30%) | 1440(2.05%) | 913(1.30%) | 45814(11.23%) | 297(39.60%) | 19(1.27%) | 0(0.00%) | | (top_efex_control) | (top) | 149(0.07%) | 89(0.04%) | 0(0.00%) | 60(0.09%) | 782(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.MGT_TX_RX | top_mgt_cfpga | 1892(0.93%) | 1885(0.92%) | 0(0.00%) | 7(0.01%) | 3641(0.89%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.MGT_TX_RX) | top_mgt_cfpga | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 272(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_11G2 | mgt11g2_tx_rx_cfpga_gen | 1247(0.61%) | 1247(0.61%) | 0(0.00%) | 0(0.00%) | 2242(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_1quad_Rx_Tx | mgt11g2_tx_rx_cfpga_wrapper__xdcDup__1 | 624(0.31%) | 624(0.31%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_support_i | mgt11g2_tx_rx_cfpga_support__xdcDup__1 | 624(0.31%) | 624(0.31%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (mgt11g2_tx_rx_cfpga_support_i) | mgt11g2_tx_rx_cfpga_support__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | mgt11g2_tx_rx_cfpga_common_106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | mgt11g2_tx_rx_cfpga_common_reset_107 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE_108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_init_i | mgt11g2_tx_rx_cfpga_HD383 | 609(0.30%) | 609(0.30%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init_HD384 | 609(0.30%) | 609(0.30%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init_HD384 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_HD385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_HD385 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81_HD387 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_HD388 | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_HD388 | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73_HD389 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74_HD390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75_HD391 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76_HD392 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77_HD393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN_HD396 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN_HD396 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62_HD397 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63_HD398 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_HD399 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64_HD400 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65_HD401 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66_HD402 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67_HD403 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68_HD404 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69_HD405 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70_HD406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71_HD407 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72_HD408 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_HD409 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_HD409 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56_HD410 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58_HD412 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59_HD413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0_HD416 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0_HD416 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54_HD417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55_HD418 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1_HD419 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1_HD419 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47_HD420 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49_HD422 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50_HD423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51_HD424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52_HD425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53_HD426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2_HD427 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2_HD427 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41_HD428 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43_HD430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44_HD431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45_HD432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46_HD433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3_HD434 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3_HD434 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39_HD435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40_HD436 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4_HD437 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4_HD437 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32_HD438 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33_HD439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34_HD440 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35_HD441 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36_HD442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37_HD443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5_HD445 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5_HD445 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26_HD446 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28_HD448 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29_HD449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30_HD450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6_HD452 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6_HD452 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25_HD454 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7_HD455 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7_HD455 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17_HD456 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18_HD457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19_HD458 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20_HD459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21_HD460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22_HD461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23_HD462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8_HD463 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8_HD463 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_HD464 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12_HD465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13_HD466 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14_HD467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15_HD468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16_HD469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt_HD470 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_HD471 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9_HD472 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10_HD473 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11_HD474 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[1].mgt_1quad_Rx_Tx | mgt11g2_tx_rx_cfpga_wrapper | 623(0.31%) | 623(0.31%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_support_i | mgt11g2_tx_rx_cfpga_support | 623(0.31%) | 623(0.31%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (mgt11g2_tx_rx_cfpga_support_i) | mgt11g2_tx_rx_cfpga_support | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | mgt11g2_tx_rx_cfpga_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | mgt11g2_tx_rx_cfpga_common_reset | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_init_i | mgt11g2_tx_rx_cfpga | 608(0.30%) | 608(0.30%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init | 608(0.30%) | 608(0.30%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_81 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_73 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_75 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_76 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_63 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_pulse_72 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_56 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_47 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_41 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_34 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_26 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_19 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_sync_block_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_multi_gt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_mgt11g2_tx_rx_cfpga_GT_11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_6G4 | MGT_quad_gen | 637(0.31%) | 630(0.31%) | 0(0.00%) | 7(0.01%) | 1127(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_quad_Rx_Tx | mgt_tx_rx_6g4_wrapper | 637(0.31%) | 630(0.31%) | 0(0.00%) | 7(0.01%) | 1127(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | MGT_TX_RX_6G4_support | 637(0.31%) | 630(0.31%) | 0(0.00%) | 7(0.01%) | 1127(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | MGT_TX_RX_6G4_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_6G4_init_i | MGT_TX_RX_6G4 | 627(0.31%) | 620(0.30%) | 0(0.00%) | 7(0.01%) | 1115(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | MGT_TX_RX_6G4_MGT_TX_RX_6G4_init | 627(0.31%) | 620(0.30%) | 0(0.00%) | 7(0.01%) | 1115(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_init | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_multi_gt | 14(0.01%) | 7(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_cpll_railing | 9(0.01%) | 2(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_GT_79 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_GT_80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_GT_81 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_78 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_70 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_72 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_73 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_MANUAL_PHASE_ALIGN | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_59 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_60 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_61 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_pulse_63 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_53 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM_1 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM_1 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_44 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_46 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_47 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM_2 | 66(0.03%) | 66(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM_2 | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_38 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_40 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM_4 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM_4 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_29 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_31 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_32 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM_5 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM_5 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_23 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_22 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM_7 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_RX_STARTUP_FSM_7 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_14 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_16 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM_8 | 67(0.03%) | 67(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | MGT_TX_RX_6G4_MGT_TX_RX_6G4_TX_STARTUP_FSM_8 | 61(0.03%) | 61(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_MGT_TX_RX_6G4_sync_block_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | MGT_TX_RX_6G4_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | MGT_TX_RX_6G4_common_reset | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | MGT_TX_RX_6G4_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.backplane_reg | backplane_registers | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 256(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora1_gt0 | ipbus_ctrlreg_v__parameterized2_98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora1_gt1 | ipbus_ctrlreg_v__parameterized2_99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora1_gt2 | ipbus_ctrlreg_v__parameterized2_100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora1_gt3 | ipbus_ctrlreg_v__parameterized2_101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora2_gt0 | ipbus_ctrlreg_v__parameterized2_102 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora2_gt1 | ipbus_ctrlreg_v__parameterized2_103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora2_gt2 | ipbus_ctrlreg_v__parameterized2_104 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora2_gt3 | ipbus_ctrlreg_v__parameterized2_105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.combined_ttc_ila | ila_0 | 677(0.33%) | 549(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.combined_ttc_ila) | ila_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_11_ila | 677(0.33%) | 549(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_11_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_11_ila_core | 676(0.33%) | 548(0.27%) | 0(0.00%) | 128(0.18%) | 1293(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_11_ila_core | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_11_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_0_cfglut6__parameterized0 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_0_cfglut7_29 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_11_ila_cap_addrgen | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_11_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_11_ila_cap_sample_counter | 32(0.02%) | 19(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_11_ila_cap_sample_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_0_cfglut4_36 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_0_cfglut5_37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_0_cfglut6_38 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_0_match_nodelay_39 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_11_ila_cap_window_counter | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.03%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_11_ila_cap_window_counter | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_0_cfglut5_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_32 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_34 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_35 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_0_match_nodelay_31 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_11_ila_register | 433(0.21%) | 432(0.21%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_11_ila_register | 104(0.05%) | 103(0.05%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized0 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_2_xsdbs | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_2_reg__parameterized26 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_27 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_2_reg__parameterized27 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_26 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_2_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_2_reg__parameterized29 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_24 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_2_reg__parameterized30 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_23 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_2_reg__parameterized31 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_22 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_2_reg__parameterized11 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_21 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_2_reg__parameterized12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_2_reg__parameterized13 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_20 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_2_reg__parameterized32 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_19 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_2_reg__parameterized33 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_18 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_2_reg__parameterized34 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_2_reg__parameterized35 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_17 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_2_reg__parameterized36 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_16 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_2_reg__parameterized37 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_15 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_2_reg__parameterized39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_14 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_2_reg__parameterized41 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_2_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_2_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_2_reg__parameterized14 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_12 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized1 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_2_reg_stream | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_2_reg_stream__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_11_ila_reset_ctrl | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_11_ila_reset_ctrl | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_11_ila_trigger | 51(0.03%) | 9(0.01%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_11_ila_trigger | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_0_match | 6(0.01%) | 1(0.01%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_0_match | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_11_ila_trig_match | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_0_match__parameterized0 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_0_generic_memrd | 66(0.03%) | 64(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.crc_checker_hub1 | cntrl_crc_checker | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 133(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.crc_checker_hub1) | cntrl_crc_checker | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_96 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_sm | ttc_crc_sm_97 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.crc_checker_hub2 | cntrl_crc_checker_0 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 133(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.crc_checker_hub2) | cntrl_crc_checker_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_sm | ttc_crc_sm | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub1_axi_stream_fifo | axi_stream_fifo | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (GOLDEN_IF.hub1_axi_stream_fifo) | axi_stream_fifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_stream_fifo_fifo_generator_v13_2_5 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | axi_stream_fifo_fifo_generator_v13_2_5_synth | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | axi_stream_fifo_fifo_generator_top | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | grf.rf | axi_stream_fifo_fifo_generator_ramfifo | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | axi_stream_fifo_clk_x_pntrs | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | axi_stream_fifo_clk_x_pntrs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | axi_stream_fifo_rd_logic | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | axi_stream_fifo_rd_fwft | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | axi_stream_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | axi_stream_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | axi_stream_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | axi_stream_fifo_rd_bin_cntr | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | axi_stream_fifo_wr_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | axi_stream_fifo_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | axi_stream_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | axi_stream_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | axi_stream_fifo_wr_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | axi_stream_fifo_memory | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 81(0.02%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | axi_stream_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | axi_stream_fifo_blk_mem_gen_v8_4_4 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | axi_stream_fifo_blk_mem_gen_v8_4_4_synth | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_stream_fifo_blk_mem_gen_top | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | valid.cstr | axi_stream_fifo_blk_mem_gen_generic_cstr | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | axi_stream_fifo_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[1].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[2].ram.r) | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | axi_stream_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | axi_stream_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | axi_stream_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | axi_stream_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub1_ufc_block | ufc_controller__1 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub2_axi_stream_fifo | axi_stream_fifo_HD347 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | U0 | axi_stream_fifo_fifo_generator_v13_2_5_HD348 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | axi_stream_fifo_fifo_generator_v13_2_5_synth_HD349 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | axi_stream_fifo_fifo_generator_top_HD350 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | grf.rf | axi_stream_fifo_fifo_generator_ramfifo_HD351 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | axi_stream_fifo_clk_x_pntrs_HD352 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | axi_stream_fifo_clk_x_pntrs_HD352 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray_HD353 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray__2_HD354 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | axi_stream_fifo_rd_logic_HD355 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | axi_stream_fifo_rd_fwft_HD356 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | axi_stream_fifo_rd_status_flags_as_HD357 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | axi_stream_fifo_rd_status_flags_as_HD357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | axi_stream_fifo_compare_1_HD358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare_2_HD359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | axi_stream_fifo_rd_bin_cntr_HD360 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | axi_stream_fifo_wr_logic_HD361 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | axi_stream_fifo_wr_status_flags_as_HD362 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | axi_stream_fifo_wr_status_flags_as_HD362 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare_HD363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | axi_stream_fifo_compare_0_HD364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | axi_stream_fifo_wr_bin_cntr_HD365 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | axi_stream_fifo_memory_HD366 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 81(0.02%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | axi_stream_fifo_memory_HD366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | axi_stream_fifo_blk_mem_gen_v8_4_4_HD367 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | axi_stream_fifo_blk_mem_gen_v8_4_4_synth_HD368 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_stream_fifo_blk_mem_gen_top_HD369 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | valid.cstr | axi_stream_fifo_blk_mem_gen_generic_cstr_HD370 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | axi_stream_fifo_blk_mem_gen_prim_width_HD371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper_HD372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[1].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized0_HD373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized0_HD374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1_HD375 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[2].ram.r) | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1_HD375 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized1_HD376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | axi_stream_fifo_reset_blk_ramfifo_HD377 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | axi_stream_fifo_reset_blk_ramfifo_HD377 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | axi_stream_fifo_xpm_cdc_single_HD378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | axi_stream_fifo_xpm_cdc_single__2_HD379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst_HD380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst__2_HD381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub2_ufc_block | ufc_controller | 37(0.02%) | 37(0.02%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.mgt_slaves | mgt_cntrl_slaves | 600(0.29%) | 600(0.29%) | 0(0.00%) | 0(0.00%) | 967(0.24%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fabric | ipbus_fabric_sel__parameterized3 | 49(0.02%) | 49(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | quad_0 | cntrl_mgt_quad_slaves | 195(0.10%) | 195(0.10%) | 0(0.00%) | 0(0.00%) | 345(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (quad_0) | cntrl_mgt_quad_slaves | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information_72 | 40(0.02%) | 40(0.02%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_92 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_93 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_94 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter_95 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information_73 | 40(0.02%) | 40(0.02%) | 0(0.00%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_88 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_89 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_90 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter_91 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information_74 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_85 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_86 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_87 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information_75 | 39(0.02%) | 39(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_82 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_83 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_84 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_76 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_77 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_81 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | quad_1 | cntrl_mgt_quad_slaves__parameterized0 | 186(0.09%) | 186(0.09%) | 0(0.00%) | 0(0.00%) | 311(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (quad_1) | cntrl_mgt_quad_slaves__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information_50 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_69 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_70 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_71 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information_51 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_66 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_67 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_68 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information_52 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_63 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_64 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_65 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information_53 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_60 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_61 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_62 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_54 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_55 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_59 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | quad_2 | cntrl_mgt_quad_slaves__parameterized1 | 170(0.08%) | 170(0.08%) | 0(0.00%) | 0(0.00%) | 311(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (quad_2) | cntrl_mgt_quad_slaves__parameterized1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_47 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_48 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_49 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information_31 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_44 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_45 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_46 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information_32 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_41 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_42 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_43 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information_33 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_39 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_40 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_34 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_35 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_37 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_38 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.output_channel1_ila | ila_0_HD4 | 682(0.33%) | 554(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.output_channel1_ila) | ila_0_HD4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_11_ila_HD5 | 682(0.33%) | 554(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_11_ila_HD5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_11_ila_core_HD6 | 681(0.33%) | 553(0.27%) | 0(0.00%) | 128(0.18%) | 1293(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_11_ila_core_HD6 | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_11_ila_trace_memory_HD7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_4_HD8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_synth_HD9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_top_HD10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr_HD11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width_HD12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper_HD13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0_HD14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0_HD15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy_HD16 | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy_HD16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_0_cfglut6__parameterized0_HD17 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_0_cfglut7_HD18 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_0_cfglut7_29_HD19 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_11_ila_cap_addrgen_HD20 | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_11_ila_cap_addrgen_HD20 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_0_cfglut6_HD21 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_11_ila_cap_sample_counter_HD22 | 32(0.02%) | 19(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_11_ila_cap_sample_counter_HD22 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_0_cfglut4_36_HD23 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_0_cfglut5_37_HD24 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_0_cfglut6_38_HD25 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_0_match_nodelay_39_HD26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40_HD27 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40_HD27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41_HD28 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41_HD28 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_42_HD29 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_43_HD30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_11_ila_cap_window_counter_HD31 | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.03%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_11_ila_cap_window_counter_HD31 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_0_cfglut4_HD32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_0_cfglut5_HD33 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_0_cfglut5_30_HD34 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_0_match_nodelay_HD35 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_32_HD36 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33_HD37 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33_HD37 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_34_HD38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_35_HD39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_0_match_nodelay_31_HD40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_HD41 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_HD41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_HD42 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_HD42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_11_ila_register_HD45 | 438(0.21%) | 437(0.21%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_11_ila_register_HD45 | 107(0.05%) | 106(0.05%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s_HD46 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized0_HD47 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_2_xsdbs_HD48 | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_2_reg__parameterized26_HD49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_27_HD50 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_2_reg__parameterized27_HD51 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_26_HD52 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_2_reg__parameterized28_HD53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_25_HD54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_2_reg__parameterized29_HD55 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_24_HD56 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_2_reg__parameterized30_HD57 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_23_HD58 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_2_reg__parameterized31_HD59 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_22_HD60 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_2_reg__parameterized11_HD61 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_21_HD62 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_2_reg__parameterized12_HD63 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized0_HD64 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_2_reg__parameterized13_HD65 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_20_HD66 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_2_reg__parameterized32_HD67 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_19_HD68 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_2_reg__parameterized33_HD69 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_18_HD70 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_2_reg__parameterized34_HD71 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_HD72 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_2_reg__parameterized35_HD73 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_17_HD74 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_2_reg__parameterized36_HD75 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_16_HD76 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_2_reg__parameterized37_HD77 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_15_HD78 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_2_reg__parameterized39_HD79 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_14_HD80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_2_reg__parameterized41_HD81 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_13_HD82 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_2_reg__parameterized44_HD83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_2_reg__parameterized44_HD83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_28_HD84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_2_reg__parameterized14_HD85 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_12_HD86 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized1_HD87 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_2_reg_stream_HD88 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_HD89 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_2_reg_stream__parameterized0_HD90 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_HD91 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_11_ila_reset_ctrl_HD92 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_11_ila_reset_ctrl_HD92 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_HD93 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_HD94 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_8_HD95 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_9_HD96 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_10_HD97 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_11_HD98 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_11_ila_trigger_HD99 | 51(0.03%) | 9(0.01%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_11_ila_trigger_HD99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_0_match_HD100 | 6(0.01%) | 1(0.01%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_0_match_HD100 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_HD101 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_HD101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA_HD102 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA_HD102 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_7_HD103 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_11_ila_trig_match_HD104 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_0_match__parameterized0_HD105 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_0_match__parameterized0_HD105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0_HD106 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0_HD106 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized0_HD107 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized0_HD107 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD108 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD109 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD110 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD111 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_3_HD112 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD113 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD114 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_6_HD115 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_HD116 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_0_generic_memrd_HD117 | 66(0.03%) | 64(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.payload_channel1_ila | ila_0_HD118 | 684(0.34%) | 556(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.payload_channel1_ila) | ila_0_HD118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_11_ila_HD119 | 684(0.34%) | 556(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_11_ila_HD119 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_11_ila_core_HD120 | 683(0.33%) | 555(0.27%) | 0(0.00%) | 128(0.18%) | 1293(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_11_ila_core_HD120 | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_11_ila_trace_memory_HD121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_4_HD122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_synth_HD123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_top_HD124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr_HD125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width_HD126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper_HD127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0_HD128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0_HD129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy_HD130 | 79(0.04%) | 32(0.02%) | 0(0.00%) | 47(0.07%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy_HD130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_0_cfglut6__parameterized0_HD131 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_0_cfglut7_HD132 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_0_cfglut7_29_HD133 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_11_ila_cap_addrgen_HD134 | 64(0.03%) | 27(0.01%) | 0(0.00%) | 37(0.05%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_11_ila_cap_addrgen_HD134 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_0_cfglut6_HD135 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_11_ila_cap_sample_counter_HD136 | 32(0.02%) | 19(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_11_ila_cap_sample_counter_HD136 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_0_cfglut4_36_HD137 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_0_cfglut5_37_HD138 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_0_cfglut6_38_HD139 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_0_match_nodelay_39_HD140 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40_HD141 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40_HD141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41_HD142 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41_HD142 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_42_HD143 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_43_HD144 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_11_ila_cap_window_counter_HD145 | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.03%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_11_ila_cap_window_counter_HD145 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_0_cfglut4_HD146 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_0_cfglut5_HD147 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_0_cfglut5_30_HD148 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_0_match_nodelay_HD149 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_32_HD150 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33_HD151 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33_HD151 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_34_HD152 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_35_HD153 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_0_match_nodelay_31_HD154 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_HD155 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_HD155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_HD156 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_HD156 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD157 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD158 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_11_ila_register_HD159 | 439(0.22%) | 438(0.21%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_11_ila_register_HD159 | 106(0.05%) | 105(0.05%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s_HD160 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized0_HD161 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_2_xsdbs_HD162 | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_2_reg__parameterized26_HD163 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_27_HD164 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_2_reg__parameterized27_HD165 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_26_HD166 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_2_reg__parameterized28_HD167 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_25_HD168 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_2_reg__parameterized29_HD169 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_24_HD170 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_2_reg__parameterized30_HD171 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_23_HD172 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_2_reg__parameterized31_HD173 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_22_HD174 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_2_reg__parameterized11_HD175 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_21_HD176 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_2_reg__parameterized12_HD177 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized0_HD178 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_2_reg__parameterized13_HD179 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_20_HD180 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_2_reg__parameterized32_HD181 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_19_HD182 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_2_reg__parameterized33_HD183 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_18_HD184 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_2_reg__parameterized34_HD185 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_HD186 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_2_reg__parameterized35_HD187 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_17_HD188 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_2_reg__parameterized36_HD189 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_16_HD190 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_2_reg__parameterized37_HD191 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_15_HD192 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_2_reg__parameterized39_HD193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_14_HD194 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_2_reg__parameterized41_HD195 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_13_HD196 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_2_reg__parameterized44_HD197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_2_reg__parameterized44_HD197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_28_HD198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_2_reg__parameterized14_HD199 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_12_HD200 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized1_HD201 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_2_reg_stream_HD202 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_HD203 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_2_reg_stream__parameterized0_HD204 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_HD205 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_11_ila_reset_ctrl_HD206 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_11_ila_reset_ctrl_HD206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_HD207 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_HD208 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_8_HD209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_9_HD210 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_10_HD211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_11_HD212 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_11_ila_trigger_HD213 | 51(0.03%) | 9(0.01%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_11_ila_trigger_HD213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_0_match_HD214 | 6(0.01%) | 1(0.01%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_0_match_HD214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_HD215 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_HD215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA_HD216 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA_HD216 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_7_HD217 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_11_ila_trig_match_HD218 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_0_match__parameterized0_HD219 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_0_match__parameterized0_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0_HD220 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0_HD220 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized0_HD221 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized0_HD221 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD222 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD223 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD224 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD225 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_3_HD226 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD227 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD228 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_6_HD229 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_HD230 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_0_generic_memrd_HD231 | 66(0.03%) | 64(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.payload_channel2_ila | ila_0_HD232 | 678(0.33%) | 550(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.payload_channel2_ila) | ila_0_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_11_ila_HD233 | 678(0.33%) | 550(0.27%) | 0(0.00%) | 128(0.18%) | 1299(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_11_ila_HD233 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_11_ila_core_HD234 | 677(0.33%) | 549(0.27%) | 0(0.00%) | 128(0.18%) | 1293(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_11_ila_core_HD234 | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_11_ila_trace_memory_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_4_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_synth_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_top_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr_HD239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width_HD240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper_HD241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy_HD244 | 79(0.04%) | 32(0.02%) | 0(0.00%) | 47(0.07%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_11_ila_cap_ctrl_legacy_HD244 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_0_cfglut6__parameterized0_HD245 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_0_cfglut7_HD246 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_0_cfglut7_29_HD247 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_11_ila_cap_addrgen_HD248 | 64(0.03%) | 27(0.01%) | 0(0.00%) | 37(0.05%) | 111(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_11_ila_cap_addrgen_HD248 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_0_cfglut6_HD249 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_11_ila_cap_sample_counter_HD250 | 32(0.02%) | 19(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_11_ila_cap_sample_counter_HD250 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_0_cfglut4_36_HD251 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_0_cfglut5_37_HD252 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_0_cfglut6_38_HD253 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_0_match_nodelay_39_HD254 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40_HD255 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_40_HD255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41_HD256 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_41_HD256 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_42_HD257 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_43_HD258 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_11_ila_cap_window_counter_HD259 | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.03%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_11_ila_cap_window_counter_HD259 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_0_cfglut4_HD260 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_0_cfglut5_HD261 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_0_cfglut5_30_HD262 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_0_match_nodelay_HD263 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_32_HD264 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33_HD265 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_33_HD265 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_34_HD266 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_35_HD267 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_0_match_nodelay_31_HD268 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_HD269 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_nodelay_HD269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_HD270 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized1_HD270 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized1_HD271 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized2_HD272 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_11_ila_register_HD273 | 433(0.21%) | 432(0.21%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_11_ila_register_HD273 | 104(0.05%) | 103(0.05%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s_HD274 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized0_HD275 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_2_xsdbs_HD276 | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_2_reg__parameterized26_HD277 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_27_HD278 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_2_reg__parameterized27_HD279 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_26_HD280 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_2_reg__parameterized28_HD281 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_25_HD282 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_2_reg__parameterized29_HD283 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_24_HD284 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_2_reg__parameterized30_HD285 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_23_HD286 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_2_reg__parameterized31_HD287 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_22_HD288 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_2_reg__parameterized11_HD289 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_21_HD290 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_2_reg__parameterized12_HD291 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized0_HD292 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_2_reg__parameterized13_HD293 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_20_HD294 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_2_reg__parameterized32_HD295 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_19_HD296 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_2_reg__parameterized33_HD297 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_18_HD298 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_2_reg__parameterized34_HD299 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl__parameterized1_HD300 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_2_reg__parameterized35_HD301 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_17_HD302 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_2_reg__parameterized36_HD303 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_16_HD304 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_2_reg__parameterized37_HD305 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_15_HD306 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_2_reg__parameterized39_HD307 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_14_HD308 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_2_reg__parameterized41_HD309 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_13_HD310 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_2_reg__parameterized44_HD311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_2_reg__parameterized44_HD311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_28_HD312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_2_reg__parameterized14_HD313 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_12_HD314 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_2_reg_p2s__parameterized1_HD315 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_2_reg_stream_HD316 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_2_reg_ctl_HD317 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_2_reg_stream__parameterized0_HD318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_2_reg_stat_HD319 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_11_ila_reset_ctrl_HD320 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_11_ila_reset_ctrl_HD320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_HD321 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_HD322 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_8_HD323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_9_HD324 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_0_async_edge_xfer_10_HD325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_0_rising_edge_detection_11_HD326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_11_ila_trigger_HD327 | 51(0.03%) | 9(0.01%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_11_ila_trigger_HD327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_0_match_HD328 | 6(0.01%) | 1(0.01%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_0_match_HD328 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA_HD329 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA_HD329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA_HD330 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA_HD330 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_7_HD331 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_11_ila_trig_match_HD332 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_0_match__parameterized0_HD333 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_0_match__parameterized0_HD333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0_HD334 | 45(0.02%) | 8(0.01%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_0_ltlib_v1_0_0_allx_typeA__parameterized0_HD334 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_0_all_typeA__parameterized0_HD335 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_0_all_typeA__parameterized0_HD335 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_HD336 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_0_HD337 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_1_HD338 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_2_HD339 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_3_HD340 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_4_HD341 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_5_HD342 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice__parameterized0_6_HD343 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_0_all_typeA_slice_HD344 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_0_generic_memrd_HD345 | 66(0.03%) | 64(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.readout_packet_block | packet_block | 14953(7.33%) | 13471(6.60%) | 1320(1.88%) | 162(0.23%) | 25023(6.13%) | 263(35.07%) | 16(1.07%) | 0(0.00%) | | (GOLDEN_IF.readout_packet_block) | packet_block | 25(0.01%) | 24(0.01%) | 0(0.00%) | 1(0.01%) | 119(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].MGT_object | mgt_buffer | 338(0.17%) | 335(0.16%) | 0(0.00%) | 3(0.01%) | 779(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[0].MGT_object) | mgt_buffer | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_291 | 36(0.02%) | 36(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver_292 | 134(0.07%) | 133(0.07%) | 0(0.00%) | 1(0.01%) | 255(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_A | packet_fifo | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_B | packet_fifo_114 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_selector | fifo_selector | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_ram_fifo | packet_ram_fifo__parameterized1 | 114(0.06%) | 114(0.06%) | 0(0.00%) | 0(0.00%) | 200(0.05%) | 7(0.93%) | 1(0.07%) | 0(0.00%) | | Bulk_sources[1].MGT_object | mgt_buffer__parameterized1 | 302(0.15%) | 299(0.15%) | 0(0.00%) | 3(0.01%) | 787(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[1].MGT_object) | mgt_buffer__parameterized1 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_289 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized1_290 | 134(0.07%) | 133(0.07%) | 0(0.00%) | 1(0.01%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD482 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD483 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD484 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD484 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD485 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD486 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD487 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD487 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD488 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD489 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD490 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD491 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD492 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD493 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD495 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD496 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD497 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD501 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD502 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD503 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD504 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD505 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD506 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD507 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD507 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD509 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD509 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD515 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD516 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD516 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD521 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_A | packet_fifo_115 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_B | packet_fifo_116 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_selector | fifo_selector_117 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_ram_fifo | packet_ram_fifo__parameterized1_118 | 115(0.06%) | 115(0.06%) | 0(0.00%) | 0(0.00%) | 202(0.05%) | 7(0.93%) | 1(0.07%) | 0(0.00%) | | Bulk_sources[2].MGT_object | mgt_buffer__parameterized3 | 304(0.15%) | 301(0.15%) | 0(0.00%) | 3(0.01%) | 780(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[2].MGT_object) | mgt_buffer__parameterized3 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_287 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized3_288 | 134(0.07%) | 133(0.07%) | 0(0.00%) | 1(0.01%) | 256(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD570 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD571 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD572 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD572 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD573 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD574 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD575 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD575 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD576 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD577 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD578 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD579 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD581 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD583 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD584 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD585 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD585 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD587 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD589 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD590 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD590 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD591 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD592 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD593 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD594 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD595 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD595 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD597 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD597 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD603 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD604 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD604 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD609 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_A | packet_fifo_119 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_B | packet_fifo_120 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_selector | fifo_selector_121 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 138(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_ram_fifo | packet_ram_fifo__parameterized1_122 | 115(0.06%) | 115(0.06%) | 0(0.00%) | 0(0.00%) | 203(0.05%) | 7(0.93%) | 1(0.07%) | 0(0.00%) | | Bulk_sources[3].MGT_object | mgt_buffer__parameterized5 | 305(0.15%) | 302(0.15%) | 0(0.00%) | 3(0.01%) | 787(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[3].MGT_object) | mgt_buffer__parameterized5 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_285 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized5_286 | 136(0.07%) | 135(0.07%) | 0(0.00%) | 1(0.01%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD658 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD659 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD660 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD660 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD661 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD662 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD663 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD663 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD664 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD665 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD666 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD667 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD671 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD672 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD673 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD673 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD675 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD677 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD678 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD679 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD680 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD681 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD682 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD683 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD683 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD685 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD685 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD691 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD692 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD692 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD697 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_A | packet_fifo_123 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_B | packet_fifo_124 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_selector | fifo_selector_125 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_ram_fifo | packet_ram_fifo__parameterized1_126 | 116(0.06%) | 116(0.06%) | 0(0.00%) | 0(0.00%) | 200(0.05%) | 7(0.93%) | 1(0.07%) | 0(0.00%) | | IPBusblock | packet_status_block | 1501(0.74%) | 1501(0.74%) | 0(0.00%) | 0(0.00%) | 5355(1.31%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IPBusblock) | packet_status_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_rdout_ipb_slave | rdout_ipb_slave | 1430(0.70%) | 1430(0.70%) | 0(0.00%) | 0(0.00%) | 3083(0.76%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_rdout_ipb_slave) | rdout_ipb_slave | 81(0.04%) | 81(0.04%) | 0(0.00%) | 0(0.00%) | 2603(0.64%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U10_TOB_FIFO_BUSY_XOFF_CNT_A | ipbus_ctrlreg_v__parameterized8 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U10_TOB_FIFO_BUSY_XOFF_CNT_B | ipbus_ctrlreg_v__parameterized8_276 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U11_MERGED_FIFO_BUSY_XOFF_CNT | ipbus_ctrlreg_v__parameterized9 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_RAW_FIFO_BUSY_XOFF_CNT | ipbus_ctrlreg_v__parameterized8_277 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U13_TOB_MERGING_CNT_BUS_A | ipbus_ctrlreg_v__parameterized7 | 128(0.06%) | 128(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U13_TOB_MERGING_CNT_BUS_B | ipbus_ctrlreg_v__parameterized7_278 | 128(0.06%) | 128(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_UPDATE_COUNTING_REGISTERS | ipbus_ctrlreg_v__parameterized2_279 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_BUSY_FIFO_CONTROL | ipbus_ctrlreg_v__parameterized4 | 187(0.09%) | 187(0.09%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XOFF_FIFO_CONTROL | ipbus_ctrlreg_v__parameterized5 | 270(0.13%) | 270(0.13%) | 0(0.00%) | 0(0.00%) | 256(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_SPY_RAM_CONTROL | ipbus_ctrlreg_v__parameterized6 | 95(0.05%) | 95(0.05%) | 0(0.00%) | 0(0.00%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_TOB_FIFO_STATUS_A | ipbus_ctrlreg_v__parameterized7_280 | 81(0.04%) | 81(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_TOB_FIFO_STATUS_B | ipbus_ctrlreg_v__parameterized7_281 | 81(0.04%) | 81(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_MERGED_FIFO_STATUS_A | ipbus_ctrlreg_v__parameterized8_282 | 55(0.03%) | 55(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_MERGED_FIFO_STATUS_B | ipbus_ctrlreg_v__parameterized8_283 | 55(0.03%) | 55(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_RAW_FIFO_STATUS | ipbus_ctrlreg_v__parameterized7_284 | 78(0.04%) | 78(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rdout_err_cnt | rdout_err_cnt | 42(0.02%) | 42(0.02%) | 0(0.00%) | 0(0.00%) | 1344(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U2_tob_fifo_error_A | cntr_generic | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U3_tob_fifo_error_B | cntr_generic_235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U4_raw_fifo_error | cntr_generic_236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U2_tob_fifo_error_A | cntr_generic_237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U3_tob_fifo_error_B | cntr_generic_238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U4_raw_fifo_error | cntr_generic_239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U2_tob_fifo_error_A | cntr_generic_240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U3_tob_fifo_error_B | cntr_generic_241 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U4_raw_fifo_error | cntr_generic_242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U2_tob_fifo_error_A | cntr_generic_243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U3_tob_fifo_error_B | cntr_generic_244 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U4_raw_fifo_error | cntr_generic_245 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[0].U5_merged_fifo_error_A | cntr_generic_246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[0].U6_merged_fifo_error_B | cntr_generic_247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[1].U5_merged_fifo_error_A | cntr_generic_248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[1].U6_merged_fifo_error_B | cntr_generic_249 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U2_TOB_packet_merged_A | cntr_generic_250 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U3_TOB_packet_missing_A | cntr_generic_251 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U4_debug_packet_created_A | cntr_generic_252 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U5_TOB_packet_merged_B | cntr_generic_253 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U6_TOB_packet_missing_B | cntr_generic_254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U7_debug_packet_created_B | cntr_generic_255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U2_TOB_packet_merged_A | cntr_generic_256 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U3_TOB_packet_missing_A | cntr_generic_257 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U4_debug_packet_created_A | cntr_generic_258 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U5_TOB_packet_merged_B | cntr_generic_259 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U6_TOB_packet_missing_B | cntr_generic_260 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U7_debug_packet_created_B | cntr_generic_261 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U2_TOB_packet_merged_A | cntr_generic_262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U3_TOB_packet_missing_A | cntr_generic_263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U4_debug_packet_created_A | cntr_generic_264 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U5_TOB_packet_merged_B | cntr_generic_265 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U6_TOB_packet_missing_B | cntr_generic_266 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U7_debug_packet_created_B | cntr_generic_267 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U2_TOB_packet_merged_A | cntr_generic_268 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U3_TOB_packet_missing_A | cntr_generic_269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U4_debug_packet_created_A | cntr_generic_270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U5_TOB_packet_merged_B | cntr_generic_271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U6_TOB_packet_missing_B | cntr_generic_272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U7_debug_packet_created_B | cntr_generic_273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1A_cnt_merger_A_block | cntr_generic_274 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1A_cnt_merger_B_block | cntr_generic_275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_monitoring_block | rdout_monitor | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 864(0.21%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U3_monitoring_block) | rdout_monitor | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U2_tob_busy_cnt_a | cntr_generic__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U4_tob_busy_cnt_b | cntr_generic__parameterized0_212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U2_tob_busy_cnt_a | cntr_generic__parameterized0_213 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U4_tob_busy_cnt_b | cntr_generic__parameterized0_214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U2_tob_busy_cnt_a | cntr_generic__parameterized0_215 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U4_tob_busy_cnt_b | cntr_generic__parameterized0_216 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U2_tob_busy_cnt_a | cntr_generic__parameterized0_217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U4_tob_busy_cnt_b | cntr_generic__parameterized0_218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[0].U4_tob_xoff_cnt_b | cntr_generic__parameterized0_219 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[1].U4_tob_xoff_cnt_b | cntr_generic__parameterized0_220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[2].U4_tob_xoff_cnt_b | cntr_generic__parameterized0_221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[3].U4_tob_xoff_cnt_b | cntr_generic__parameterized0_222 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U1_merged_xoff_cnt_a | cntr_generic__parameterized0_223 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U2_merged_xoff_cnt_b | cntr_generic__parameterized0_224 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U1_merged_xoff_cnt_a | cntr_generic__parameterized0_225 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U2_merged_xoff_cnt_b | cntr_generic__parameterized0_226 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].U2_raw_busy_cnt_a | cntr_generic__parameterized0_227 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].U4_raw_xoff_cnt_b | cntr_generic__parameterized0_228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].U2_raw_busy_cnt_a | cntr_generic__parameterized0_229 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].U4_raw_xoff_cnt_b | cntr_generic__parameterized0_230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].U2_raw_busy_cnt_a | cntr_generic__parameterized0_231 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].U4_raw_xoff_cnt_b | cntr_generic__parameterized0_232 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].U2_raw_busy_cnt_a | cntr_generic__parameterized0_233 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].U4_raw_xoff_cnt_b | cntr_generic__parameterized0_234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[0].MUX_register_A | fwft_register | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[0].MUX_register_B | fwft_register_127 | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[1].MUX_register_A | fwft_register_128 | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[1].MUX_register_B | fwft_register_129 | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[2].MUX_register_A | fwft_register_130 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[2].MUX_register_B | fwft_register_131 | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[3].MUX_register_A | fwft_register_132 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[3].MUX_register_B | fwft_register_133 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[4].MUX_register_A | fwft_register_134 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[4].MUX_register_B | fwft_register_135 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[5].MUX_register_A | fwft_register_136 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[5].MUX_register_B | fwft_register_137 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Merged_FIFOs[0].merged_fifo_A | packet_fifo_block | 311(0.15%) | 245(0.12%) | 66(0.09%) | 0(0.00%) | 309(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[0].merged_fifo_A) | packet_fifo_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_210 | 185(0.09%) | 119(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_211 | 126(0.06%) | 126(0.06%) | 0(0.00%) | 0(0.00%) | 211(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[0].merged_fifo_B | packet_fifo_block_138 | 311(0.15%) | 245(0.12%) | 66(0.09%) | 0(0.00%) | 309(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[0].merged_fifo_B) | packet_fifo_block_138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_208 | 184(0.09%) | 118(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_209 | 127(0.06%) | 127(0.06%) | 0(0.00%) | 0(0.00%) | 211(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[1].merged_fifo_A | packet_fifo_block_139 | 313(0.15%) | 247(0.12%) | 66(0.09%) | 0(0.00%) | 310(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[1].merged_fifo_A) | packet_fifo_block_139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_206 | 183(0.09%) | 117(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_207 | 130(0.06%) | 130(0.06%) | 0(0.00%) | 0(0.00%) | 212(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[1].merged_fifo_B | packet_fifo_block_140 | 320(0.16%) | 254(0.12%) | 66(0.09%) | 0(0.00%) | 310(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[1].merged_fifo_B) | packet_fifo_block_140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_204 | 190(0.09%) | 124(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_205 | 130(0.06%) | 130(0.06%) | 0(0.00%) | 0(0.00%) | 212(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Packet_MUX_A | efex_packet_mux__parameterized1 | 147(0.07%) | 147(0.07%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_MUX_B | efex_packet_mux__parameterized1_141 | 147(0.07%) | 147(0.07%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[0].Packet_Builder | efex_packet_builder | 483(0.24%) | 483(0.24%) | 0(0.00%) | 0(0.00%) | 412(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[0].Packet_Builder) | efex_packet_builder | 190(0.09%) | 190(0.09%) | 0(0.00%) | 0(0.00%) | 354(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_block | CRC20__parameterized1_202 | 221(0.11%) | 221(0.11%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc9_block | CRC20_203 | 80(0.04%) | 80(0.04%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[0].Packet_Builder_register | fwft_register_142 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[0].built_fifo_spy | fifo_spy | 136(0.07%) | 136(0.07%) | 0(0.00%) | 0(0.00%) | 236(0.06%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[0].built_fifo_spy) | fifo_spy | 84(0.04%) | 84(0.04%) | 0(0.00%) | 0(0.00%) | 235(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram64_201 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | Packet_builders[1].Packet_Builder | efex_packet_builder_143 | 411(0.20%) | 411(0.20%) | 0(0.00%) | 0(0.00%) | 412(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[1].Packet_Builder) | efex_packet_builder_143 | 119(0.06%) | 119(0.06%) | 0(0.00%) | 0(0.00%) | 354(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_block | CRC20__parameterized1 | 224(0.11%) | 224(0.11%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc9_block | CRC20 | 84(0.04%) | 84(0.04%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[1].Packet_Builder_register | fwft_register_144 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[1].built_fifo_spy | fifo_spy_145 | 118(0.06%) | 118(0.06%) | 0(0.00%) | 0(0.00%) | 236(0.06%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[1].built_fifo_spy) | fifo_spy_145 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 235(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram64 | 36(0.02%) | 36(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].MGT_object | mgt_buffer__xdcDup__1 | 303(0.15%) | 300(0.15%) | 0(0.00%) | 3(0.01%) | 786(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[0].MGT_object) | mgt_buffer__xdcDup__1 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_200 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver | 131(0.06%) | 130(0.06%) | 0(0.00%) | 1(0.01%) | 262(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD746 | 145(0.07%) | 143(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD747 | 145(0.07%) | 143(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD748 | 145(0.07%) | 143(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD748 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD749 | 98(0.05%) | 96(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD750 | 98(0.05%) | 96(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD751 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD751 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD752 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD753 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD754 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD755 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD756 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD757 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD759 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD760 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD761 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD761 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD765 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD766 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD767 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD768 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD769 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD770 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD771 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD771 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD773 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD773 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD779 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD780 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD780 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD785 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].TOB_register_A | fwft_register_146 | 104(0.05%) | 104(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].TOB_register_B | fwft_register_147 | 103(0.05%) | 103(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_fifo_A | packet_fifo_block_148 | 316(0.15%) | 250(0.12%) | 66(0.09%) | 0(0.00%) | 310(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[0].tob_fifo_A) | packet_fifo_block_148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_198 | 187(0.09%) | 121(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_199 | 128(0.06%) | 128(0.06%) | 0(0.00%) | 0(0.00%) | 211(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[0].tob_fifo_B | packet_fifo_block_149 | 321(0.16%) | 255(0.13%) | 66(0.09%) | 0(0.00%) | 247(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[0].tob_fifo_B) | packet_fifo_block_149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_196 | 185(0.09%) | 119(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_197 | 136(0.07%) | 136(0.07%) | 0(0.00%) | 0(0.00%) | 148(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[0].tob_fifo_selector | fifo_selector_150 | 37(0.02%) | 5(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].MGT_object | mgt_buffer__parameterized1__xdcDup__1 | 304(0.15%) | 301(0.15%) | 0(0.00%) | 3(0.01%) | 787(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[1].MGT_object) | mgt_buffer__parameterized1__xdcDup__1 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_195 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized1 | 135(0.07%) | 134(0.07%) | 0(0.00%) | 1(0.01%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD526 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD527 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD528 | 143(0.07%) | 141(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD528 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD529 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD530 | 97(0.05%) | 95(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD531 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD531 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD532 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD533 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD534 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD535 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD536 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD537 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD539 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD540 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD541 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD541 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD545 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD546 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD547 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD548 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD549 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD550 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD551 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD551 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD553 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD553 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD559 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD560 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD560 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD565 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].TOB_register_A | fwft_register_151 | 103(0.05%) | 103(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].TOB_register_B | fwft_register_152 | 104(0.05%) | 104(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_fifo_A | packet_fifo_block_153 | 314(0.15%) | 248(0.12%) | 66(0.09%) | 0(0.00%) | 311(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[1].tob_fifo_A) | packet_fifo_block_153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_193 | 185(0.09%) | 119(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_194 | 128(0.06%) | 128(0.06%) | 0(0.00%) | 0(0.00%) | 212(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[1].tob_fifo_B | packet_fifo_block_154 | 321(0.16%) | 255(0.13%) | 66(0.09%) | 0(0.00%) | 247(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[1].tob_fifo_B) | packet_fifo_block_154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_191 | 184(0.09%) | 118(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_192 | 136(0.07%) | 136(0.07%) | 0(0.00%) | 0(0.00%) | 148(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[1].tob_fifo_selector | fifo_selector_155 | 37(0.02%) | 5(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].MGT_object | mgt_buffer__parameterized3__xdcDup__1 | 304(0.15%) | 301(0.15%) | 0(0.00%) | 3(0.01%) | 787(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[2].MGT_object) | mgt_buffer__parameterized3__xdcDup__1 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_190 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized3 | 134(0.07%) | 133(0.07%) | 0(0.00%) | 1(0.01%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD614 | 144(0.07%) | 142(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD615 | 144(0.07%) | 142(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD616 | 144(0.07%) | 142(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD616 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD617 | 98(0.05%) | 96(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD618 | 98(0.05%) | 96(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD619 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD619 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD620 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD621 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD622 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD623 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD624 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD625 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD627 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD628 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD629 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD629 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD631 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD633 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD634 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD635 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD636 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD637 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD638 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD639 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD639 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD641 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD641 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD647 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD648 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD648 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].TOB_register_A | fwft_register_156 | 104(0.05%) | 104(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].TOB_register_B | fwft_register_157 | 105(0.05%) | 105(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_fifo_A | packet_fifo_block_158 | 313(0.15%) | 247(0.12%) | 66(0.09%) | 0(0.00%) | 310(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[2].tob_fifo_A) | packet_fifo_block_158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_188 | 184(0.09%) | 118(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_189 | 128(0.06%) | 128(0.06%) | 0(0.00%) | 0(0.00%) | 211(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[2].tob_fifo_B | packet_fifo_block_159 | 319(0.16%) | 253(0.12%) | 66(0.09%) | 0(0.00%) | 247(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[2].tob_fifo_B) | packet_fifo_block_159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_186 | 184(0.09%) | 118(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_187 | 134(0.07%) | 134(0.07%) | 0(0.00%) | 0(0.00%) | 148(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[2].tob_fifo_selector | fifo_selector_160 | 37(0.02%) | 5(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].MGT_object | mgt_buffer__parameterized5__xdcDup__1 | 307(0.15%) | 304(0.15%) | 0(0.00%) | 3(0.01%) | 780(0.19%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[3].MGT_object) | mgt_buffer__parameterized5__xdcDup__1 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 204(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized5 | 137(0.07%) | 136(0.07%) | 0(0.00%) | 1(0.01%) | 256(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD702 | 144(0.07%) | 142(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_5_HD703 | 144(0.07%) | 142(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD704 | 144(0.07%) | 142(0.07%) | 0(0.00%) | 2(0.01%) | 319(0.08%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (inst_fifo_gen) | mgt_axi_fifo_fifo_generator_v13_2_5_synth_HD704 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD705 | 98(0.05%) | 96(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD706 | 98(0.05%) | 96(0.05%) | 0(0.00%) | 2(0.01%) | 228(0.06%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD707 | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD707 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__4_HD708 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__3_HD709 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD710 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD711 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_2_HD713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_3_HD714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD715 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD716 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD717 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c3 | mgt_axi_fifo_compare_1_HD720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD721 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD722 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_4_HD723 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_4_synth_HD724 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD725 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD726 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD727 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD727 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD729 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo__parameterized0_HD729 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single__parameterized2_HD730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__parameterized2__2_HD731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst | mgt_axi_fifo_xpm_cdc_single__parameterized4_HD734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst | mgt_axi_fifo_xpm_cdc_gray_HD735 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD736 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD736 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst_HD737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__6_HD739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | mgt_axi_fifo_xpm_cdc_async_rst__4_HD740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen_ic.rstblk_ic | mgt_axi_fifo_reset_blk_ramfifo__xdcDup__1_HD741 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].TOB_register_A | fwft_register_161 | 102(0.05%) | 102(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].TOB_register_B | fwft_register_162 | 103(0.05%) | 103(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_fifo_A | packet_fifo_block_163 | 315(0.15%) | 249(0.12%) | 66(0.09%) | 0(0.00%) | 310(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[3].tob_fifo_A) | packet_fifo_block_163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_184 | 185(0.09%) | 119(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_185 | 129(0.06%) | 129(0.06%) | 0(0.00%) | 0(0.00%) | 211(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[3].tob_fifo_B | packet_fifo_block_164 | 322(0.16%) | 256(0.13%) | 66(0.09%) | 0(0.00%) | 247(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[3].tob_fifo_B) | packet_fifo_block_164 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_183 | 186(0.09%) | 120(0.06%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo | 135(0.07%) | 135(0.07%) | 0(0.00%) | 0(0.00%) | 148(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[3].tob_fifo_selector | fifo_selector_165 | 37(0.02%) | 5(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_merge_A | efex_tob_merger | 1002(0.49%) | 1002(0.49%) | 0(0.00%) | 0(0.00%) | 938(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tob_merge_A) | efex_tob_merger | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 218(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_MUX | efex_packet_mux_173 | 217(0.11%) | 217(0.11%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_merger | efex_packet_merger__parameterized1_174 | 215(0.11%) | 215(0.11%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_processer | efex_tob_processer_175 | 120(0.06%) | 120(0.06%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[0].tob_processer) | efex_tob_processer_175 | 99(0.05%) | 99(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_182 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_processer | efex_tob_processer_176 | 120(0.06%) | 120(0.06%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[1].tob_processer) | efex_tob_processer_176 | 98(0.05%) | 98(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_181 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_processer | efex_tob_processer_177 | 182(0.09%) | 182(0.09%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[2].tob_processer) | efex_tob_processer_177 | 99(0.05%) | 99(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_180 | 83(0.04%) | 83(0.04%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_processer | efex_tob_processer_178 | 131(0.06%) | 131(0.06%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[3].tob_processer) | efex_tob_processer_178 | 110(0.05%) | 110(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_179 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_merge_B | efex_tob_merger_166 | 1007(0.49%) | 1007(0.49%) | 0(0.00%) | 0(0.00%) | 938(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tob_merge_B) | efex_tob_merger_166 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 218(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_MUX | efex_packet_mux | 218(0.11%) | 218(0.11%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_merger | efex_packet_merger__parameterized1 | 215(0.11%) | 215(0.11%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_processer | efex_tob_processer | 120(0.06%) | 120(0.06%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[0].tob_processer) | efex_tob_processer | 99(0.05%) | 99(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_172 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_processer | efex_tob_processer_167 | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[1].tob_processer) | efex_tob_processer_167 | 99(0.05%) | 99(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_171 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_processer | efex_tob_processer_168 | 184(0.09%) | 184(0.09%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[2].tob_processer) | efex_tob_processer_168 | 101(0.05%) | 101(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_170 | 83(0.04%) | 83(0.04%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_processer | efex_tob_processer_169 | 131(0.06%) | 131(0.06%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[3].tob_processer) | efex_tob_processer_169 | 110(0.05%) | 110(0.05%) | 0(0.00%) | 0(0.00%) | 163(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifos | ttc_fifo_block | 21(0.01%) | 12(0.01%) | 0(0.00%) | 9(0.01%) | 95(0.02%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (ttc_fifos) | ttc_fifo_block | 12(0.01%) | 6(0.01%) | 0(0.00%) | 6(0.01%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_A | fifo_40M_160M | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | fifo_40M_160M_fifo_generator_v13_2_5 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_40M_160M_fifo_generator_v13_2_5_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_40M_160M_fifo_generator_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gbi.bi | fifo_40M_160M_fifo_generator_v13_2_5_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | fifo_40M_160M_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | fifo_40M_160M_builtin_top_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_B | fifo_40M_160M_HD792 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | fifo_40M_160M_fifo_generator_v13_2_5_HD793 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_40M_160M_fifo_generator_v13_2_5_synth_HD794 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_40M_160M_fifo_generator_top_HD795 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gbi.bi | fifo_40M_160M_fifo_generator_v13_2_5_builtin_HD796 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | fifo_40M_160M_reset_builtin_HD797 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | fifo_40M_160M_builtin_top_v6_HD798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_HD799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_HD800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_delay | fifo_40M_160M_HD801 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | fifo_40M_160M_fifo_generator_v13_2_5_HD802 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_40M_160M_fifo_generator_v13_2_5_synth_HD803 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_40M_160M_fifo_generator_top_HD804 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gbi.bi | fifo_40M_160M_fifo_generator_v13_2_5_builtin_HD805 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | fifo_40M_160M_reset_builtin_HD806 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | fifo_40M_160M_builtin_top_v6_HD807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_HD808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_HD809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.synch_hub2_combined_ttc | top_cntrl_synch | 32(0.02%) | 12(0.01%) | 0(0.00%) | 20(0.03%) | 317(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.synch_hub2_combined_ttc) | top_cntrl_synch | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_26 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | ctrl_synch_latch_27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_28 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | first_stage_synch_29 | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 293(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | first_stage_synch_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 293(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_ctrl | SRL16E_cntrl_30 | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.synch_ttc_combined | top_cntrl_synch_1 | 32(0.02%) | 12(0.01%) | 0(0.00%) | 20(0.03%) | 317(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.synch_ttc_combined) | top_cntrl_synch_1 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | ctrl_synch_latch | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | first_stage_synch | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 293(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | first_stage_synch | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 293(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_ctrl | SRL16E_cntrl | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.top_aurora_hub1 | aurora_hub2__xdcDup__1 | 466(0.23%) | 428(0.21%) | 0(0.00%) | 38(0.05%) | 930(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_core | aurora_wrapper_hub2__xdcDup__1 | 402(0.20%) | 364(0.18%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | efex_aurora_hub2_support__xdcDup__1 | 402(0.20%) | 364(0.18%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | efex_aurora_hub2_support__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | efex_aurora_hub2_CLOCK_MODULE_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_i | efex_aurora_hub2_HD811 | 400(0.20%) | 362(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | efex_aurora_hub2_efex_aurora_hub2_core_HD812 | 400(0.20%) | 362(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | efex_aurora_hub2_efex_aurora_hub2_core_HD812 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_to_ll_pdu_i | efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL_HD813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC_HD814 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC_HD814 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23_HD815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24_HD816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_HD817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER_HD818 | 126(0.06%) | 94(0.05%) | 0(0.00%) | 32(0.05%) | 175(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER_HD818 | 6(0.01%) | 2(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_multi_gt_i | efex_aurora_hub2_efex_aurora_hub2_multi_gt_HD819 | 49(0.02%) | 21(0.01%) | 0(0.00%) | 28(0.04%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_HD820 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_20_HD821 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_21_HD822 | 13(0.01%) | 6(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_22_HD823 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_txresetfsm_i | efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm_HD824 | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_txresetfsm_i) | efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm_HD824 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13_HD825 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15_HD827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16_HD828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17_HD829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18_HD830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19_HD831 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0_HD833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | standard_cc_module_i | efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE_HD834 | 13(0.01%) | 11(0.01%) | 0(0.00%) | 2(0.01%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_0_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_HD835 | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10_HD836 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11_HD837 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12_HD838 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_1_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1_HD839 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7_HD840 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8_HD841 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9_HD842 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_2_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2_HD843 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4_HD844 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5_HD845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6_HD846 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_3_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3_HD847 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_HD848 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_HD849 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_HD850 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_global_logic_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX_HD851 | 51(0.03%) | 47(0.02%) | 0(0.00%) | 4(0.01%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | idle_and_ver_gen_i | efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN_HD852 | 12(0.01%) | 10(0.01%) | 0(0.00%) | 2(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX_HD853 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_init_sm_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX_HD854 | 32(0.02%) | 30(0.01%) | 0(0.00%) | 2(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_i | efex_aurora_hub2_efex_aurora_hub2_TX_LL_HD855 | 50(0.02%) | 50(0.02%) | 0(0.00%) | 0(0.00%) | 281(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_control_i | efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL_HD856 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_datapath_i | efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH_HD857 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 244(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_common_support | efex_aurora_hub2_gt_common_wrapper_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | efex_aurora_hub2_SUPPORT_RESET_LOGIC_112 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | efex_aurora_hub2_SUPPORT_RESET_LOGIC_112 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | efex_aurora_hub2_cdc_sync_exdes_113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_109 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.top_aurora_hub2 | aurora_hub2 | 487(0.24%) | 449(0.22%) | 0(0.00%) | 38(0.05%) | 930(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_core | aurora_wrapper_hub2 | 425(0.21%) | 387(0.19%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | efex_aurora_hub2_support | 425(0.21%) | 387(0.19%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | efex_aurora_hub2_support | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | efex_aurora_hub2_CLOCK_MODULE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_i | efex_aurora_hub2 | 398(0.20%) | 360(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | efex_aurora_hub2_efex_aurora_hub2_core | 398(0.20%) | 360(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | efex_aurora_hub2_efex_aurora_hub2_core | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_to_ll_pdu_i | efex_aurora_hub2_efex_aurora_hub2_AXI_TO_LL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | efex_aurora_hub2_efex_aurora_hub2_RESET_LOGIC | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER | 125(0.06%) | 93(0.05%) | 0(0.00%) | 32(0.05%) | 175(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | efex_aurora_hub2_efex_aurora_hub2_GT_WRAPPER | 6(0.01%) | 2(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_multi_gt_i | efex_aurora_hub2_efex_aurora_hub2_multi_gt | 49(0.02%) | 21(0.01%) | 0(0.00%) | 28(0.04%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_20 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_21 | 13(0.01%) | 6(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_efex_aurora_hub2_i | efex_aurora_hub2_efex_aurora_hub2_gt_22 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_txresetfsm_i | efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_txresetfsm_i) | efex_aurora_hub2_efex_aurora_hub2_tx_startup_fsm | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_13 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync__parameterized2_19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | efex_aurora_hub2_efex_aurora_hub2_cdc_sync_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | standard_cc_module_i | efex_aurora_hub2_efex_aurora_hub2_STANDARD_CC_MODULE | 13(0.01%) | 11(0.01%) | 0(0.00%) | 2(0.01%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_0_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5 | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_10 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_1_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_7 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_2_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN_4 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_3_i | efex_aurora_hub2_efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_efex_aurora_hub2_SYM_GEN | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_global_logic_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX | 51(0.03%) | 47(0.02%) | 0(0.00%) | 4(0.01%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | idle_and_ver_gen_i | efex_aurora_hub2_efex_aurora_hub2_IDLE_AND_VER_GEN | 12(0.01%) | 10(0.01%) | 0(0.00%) | 2(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_err_detect_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_init_sm_simplex_i | efex_aurora_hub2_efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX | 32(0.02%) | 30(0.01%) | 0(0.00%) | 2(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_i | efex_aurora_hub2_efex_aurora_hub2_TX_LL | 48(0.02%) | 48(0.02%) | 0(0.00%) | 0(0.00%) | 281(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_control_i | efex_aurora_hub2_efex_aurora_hub2_TX_LL_CONTROL | 31(0.02%) | 31(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_datapath_i | efex_aurora_hub2_efex_aurora_hub2_TX_LL_DATAPATH | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 244(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_common_support | efex_aurora_hub2_gt_common_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | efex_aurora_hub2_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | efex_aurora_hub2_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | efex_aurora_hub2_cdc_sync_exdes | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset | 62(0.03%) | 62(0.03%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | top_udp_config_FPGA | 3478(1.70%) | 3359(1.65%) | 80(0.11%) | 39(0.06%) | 3596(0.88%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | U_0 | interface_proc_fpga | 97(0.05%) | 77(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_24 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_25 | 91(0.04%) | 71(0.03%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interface_proc_fpga_16 | 98(0.05%) | 78(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_22 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_23 | 90(0.04%) | 70(0.03%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | interface_proc_fpga_17 | 98(0.05%) | 78(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_20 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_21 | 93(0.05%) | 73(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_3 | interface_proc_fpga_18 | 98(0.05%) | 78(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo | 93(0.05%) | 73(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_4 | mac_arbiter | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_5 | ipbus_ctrl | 2961(1.45%) | 2922(1.43%) | 0(0.00%) | 39(0.06%) | 3237(0.79%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | (U_5) | ipbus_ctrl | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 788(0.39%) | 788(0.39%) | 0(0.00%) | 0(0.00%) | 322(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cfg__0 | transactor_cfg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 159(0.08%) | 159(0.08%) | 0(0.00%) | 0(0.00%) | 135(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 636(0.31%) | 636(0.31%) | 0(0.00%) | 0(0.00%) | 185(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 2171(1.06%) | 2132(1.05%) | 0(0.00%) | 39(0.06%) | 2915(0.71%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 235(0.12%) | 235(0.12%) | 0(0.00%) | 0(0.00%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 183(0.09%) | 183(0.09%) | 0(0.00%) | 0(0.00%) | 196(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ARP | udp_build_arp | 90(0.04%) | 90(0.04%) | 0(0.00%) | 0(0.00%) | 134(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.IPAM_block | udp_ipam_block | 275(0.13%) | 275(0.13%) | 0(0.00%) | 0(0.00%) | 168(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ping | udp_build_ping | 117(0.06%) | 117(0.06%) | 0(0.00%) | 0(0.00%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 257(0.13%) | 220(0.11%) | 0(0.00%) | 37(0.05%) | 517(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 140(0.07%) | 140(0.07%) | 0(0.00%) | 0(0.00%) | 171(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 232(0.11%) | 232(0.11%) | 0(0.00%) | 0(0.00%) | 433(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_19 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 216(0.11%) | 216(0.11%) | 0(0.00%) | 0(0.00%) | 222(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 103(0.05%) | 103(0.05%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.06%) | 130(0.06%) | 0(0.00%) | 0(0.00%) | 264(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_6 | udp_hub_rarp | 83(0.04%) | 83(0.04%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_7 | unique_address | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_14 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_15 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | interconnect_2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_2) | interconnect_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_12 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_13 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_3 | interconnect_3 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_3) | interconnect_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_10 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_11 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_4 | interconnect_4 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_4) | interconnect_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 82(0.04%) | 81(0.04%) | 0(0.00%) | 1(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 51(0.03%) | 51(0.03%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 31(0.02%) | 30(0.01%) | 0(0.00%) | 1(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_hub | dbg_hub | 480(0.24%) | 456(0.22%) | 24(0.03%) | 0(0.00%) | 776(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_hub) | dbg_hub | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dbg_hub_xsdbm_v3_0_0_xsdbm | 480(0.24%) | 456(0.22%) | 24(0.03%) | 0(0.00%) | 776(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BSCANID.u_xsdbm_id | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 480(0.24%) | 456(0.22%) | 24(0.03%) | 0(0.00%) | 776(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BSCANID.u_xsdbm_id) | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.UUT_MASTER | dbg_hub_xsdbm_v3_0_0_icon2xsdb | 303(0.15%) | 279(0.14%) | 24(0.03%) | 0(0.00%) | 589(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_ICON_INTERFACE | dbg_hub_xsdbm_v3_0_0_if | 174(0.09%) | 150(0.07%) | 24(0.03%) | 0(0.00%) | 468(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_ICON_INTERFACE) | dbg_hub_xsdbm_v3_0_0_if | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD1 | dbg_hub_xsdbm_v3_0_0_ctl_reg | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD2 | dbg_hub_xsdbm_v3_0_0_stat_reg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD3 | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized0 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD4 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized0 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD5 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_RD | dbg_hub_xsdbm_v3_0_0_rdreg | 69(0.03%) | 57(0.03%) | 12(0.02%) | 0(0.00%) | 134(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_RD) | dbg_hub_xsdbm_v3_0_0_rdreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_FIFO | dbg_hub_xsdbm_v3_0_0_rdfifo | 67(0.03%) | 55(0.03%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_RD_FIFO) | dbg_hub_xsdbm_v3_0_0_rdfifo | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst) | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs_6 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs_6 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | dbg_hub_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr_17 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as_13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory__parameterized0 | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | dbg_hub_memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem_12 | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo_7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_WR | dbg_hub_xsdbm_v3_0_0_wrreg | 45(0.02%) | 33(0.02%) | 12(0.02%) | 0(0.00%) | 110(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_WR) | dbg_hub_xsdbm_v3_0_0_wrreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WR_FIFO | dbg_hub_xsdbm_v3_0_0_wrfifo | 43(0.02%) | 31(0.02%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_WR_FIFO) | dbg_hub_xsdbm_v3_0_0_wrfifo | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst | dbg_hub_fifo_generator_v13_1_4 | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst) | dbg_hub_fifo_generator_v13_1_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_CTL | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_STAT | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STATIC_STATUS | dbg_hub_xsdbm_v3_0_0_if_static_status | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_ADDRESS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_addr_ctl | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BURST_WD_LEN_CONTROLLER | dbg_hub_xsdbm_v3_0_0_burst_wdlen_ctl | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_bus_ctl | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_CONTROLLER) | dbg_hub_xsdbm_v3_0_0_bus_ctl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_ABORT_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_REQ_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TIMER | dbg_hub_xsdbm_v3_0_0_bus_ctl_cnt | 52(0.03%) | 52(0.03%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_MSTR2SL_PORT_IFACE | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_MSTR2SL_PORT_IFACE) | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_DIN_BUS_MUX | dbg_hub_ltlib_v1_0_0_generic_mux | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.U_ICON | dbg_hub_xsdbm_v3_0_0_icon | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CORE_XSDB.U_ICON) | dbg_hub_xsdbm_v3_0_0_icon | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD | dbg_hub_xsdbm_v3_0_0_cmd_decode | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STAT | dbg_hub_xsdbm_v3_0_0_stat | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SYNC | dbg_hub_xsdbm_v3_0_0_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_inst | dbg_hub_ltlib_v1_0_0_bscan | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_switch | dbg_hub_xsdbm_v3_0_0_bscan_switch | 125(0.06%) | 125(0.06%) | 0(0.00%) | 0(0.00%) | 125(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eth | eth_7s_gmii | 583(0.29%) | 555(0.27%) | 16(0.02%) | 12(0.02%) | 793(0.19%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (eth) | eth_7s_gmii | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | emac0 | temac_gbe_v9_0 | 530(0.26%) | 505(0.25%) | 16(0.02%) | 9(0.01%) | 679(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | temac_gbe_v9_0_temac_gbe_v9_0_block | 530(0.26%) | 505(0.25%) | 16(0.02%) | 9(0.01%) | 679(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_interface | temac_gbe_v9_0_temac_gbe_v9_0_gmii_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | temac_gbe_v9_0_core | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17 | 530(0.26%) | 505(0.25%) | 16(0.02%) | 9(0.01%) | 679(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (temac_gbe_v9_0_core) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_filter_top | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_addr_filter_wrap | 43(0.02%) | 26(0.01%) | 16(0.02%) | 1(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | address_filter_inst | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_addr_filter | 43(0.02%) | 26(0.01%) | 16(0.02%) | 1(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (address_filter_inst) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_addr_filter | 42(0.02%) | 25(0.01%) | 16(0.02%) | 1(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resync_promiscuous_mode | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | flow | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_control | 123(0.06%) | 123(0.06%) | 0(0.00%) | 0(0.00%) | 156(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (flow) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_control | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pfc_tx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_pfc_tx_cntl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx_cntl | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_pause | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx_sync_req | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_enable | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_enable | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_cntl | 53(0.03%) | 53(0.03%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_pause | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_pause | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_pause) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_pause | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_good_rx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block_6 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_rx_gen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_gmii_mii_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_tx_gen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_gmii_mii_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_avb_tx_axi_intf.tx_axi_shim | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_axi_intf | 80(0.04%) | 80(0.04%) | 0(0.00%) | 0(0.00%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_axi_shim | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx_axi_intf | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxgen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx | 155(0.08%) | 147(0.07%) | 0(0.00%) | 8(0.01%) | 181(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rxgen) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx | 26(0.01%) | 18(0.01%) | 0(0.00%) | 8(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FCS_CHECK | temac_gbe_v9_0_CRC32_8 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_CHECKER | temac_gbe_v9_0_PARAM_CHECK | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_DECODER | temac_gbe_v9_0_DECODE_FRAME | 42(0.02%) | 42(0.02%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX_SM | temac_gbe_v9_0_STATE_MACHINES | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_axi_rx_rstn_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_rx_rst_mgmt_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_tx_rst_mgmt_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_axi_rstn_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0_4 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txgen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txgen) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TX_SM1 | temac_gbe_v9_0_TX_STATE_MACH | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 126(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TX_SM1) | temac_gbe_v9_0_TX_STATE_MACH | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CRCGEN | temac_gbe_v9_0_CRC32_8__1 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo | mac_fifo_axi4 | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | U0 | mac_fifo_axi4_fifo_generator_v13_2_5 | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | mac_fifo_axi4_fifo_generator_v13_2_5_synth | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mac_fifo_axi4_fifo_generator_top | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | grf.rf | mac_fifo_axi4_fifo_generator_ramfifo | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mac_fifo_axi4_clk_x_pntrs | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mac_fifo_axi4_clk_x_pntrs | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mac_fifo_axi4_xpm_cdc_gray | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mac_fifo_axi4_xpm_cdc_gray__2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mac_fifo_axi4_rd_logic | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mac_fifo_axi4_rd_fwft | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mac_fifo_axi4_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mac_fifo_axi4_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mac_fifo_axi4_wr_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mac_fifo_axi4_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mac_fifo_axi4_wr_bin_cntr | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mac_fifo_axi4_memory | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 18(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mac_fifo_axi4_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mac_fifo_axi4_blk_mem_gen_v8_4_4 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | mac_fifo_axi4_blk_mem_gen_v8_4_4_synth | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mac_fifo_axi4_blk_mem_gen_top | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | valid.cstr | mac_fifo_axi4_blk_mem_gen_generic_cstr | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | mac_fifo_axi4_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (ramloop[0].ram.r) | mac_fifo_axi4_blk_mem_gen_prim_width | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mac_fifo_axi4_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | rstblk | mac_fifo_axi4_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mac_fifo_axi4_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mac_fifo_axi4_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mac_fifo_axi4_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mac_fifo_axi4_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mac_fifo_axi4_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | infrastructure_control | infrastructure_slaves_cntrl | 942(0.46%) | 942(0.46%) | 0(0.00%) | 0(0.00%) | 1258(0.31%) | 5(0.67%) | 0(0.00%) | 0(0.00%) | | (infrastructure_control) | infrastructure_slaves_cntrl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | i2c_0 | ipbus_i2c_master_arb | 200(0.10%) | 200(0.10%) | 0(0.00%) | 0(0.00%) | 221(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 81(0.04%) | 81(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | i2c_arp | ipbus_i2c_master | 119(0.06%) | 119(0.06%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | i2c | i2c_master_top | 119(0.06%) | 119(0.06%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (i2c) | i2c_master_top | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bit_controller | i2c_master_bit_ctrl | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | byte_controller | i2c_master_byte_ctrl | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | registers | i2c_master_registers | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig | ipbus_ctrlreg_v__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32__parameterized0 | 274(0.13%) | 274(0.13%) | 0(0.00%) | 0(0.00%) | 304(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog_5 | 131(0.06%) | 131(0.06%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized2 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control__parameterized0 | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_pll | ipbus_spi32 | 262(0.13%) | 262(0.13%) | 0(0.00%) | 0(0.00%) | 299(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (spi_pll) | ipbus_spi32 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog_6 | 130(0.06%) | 130(0.06%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3_8 | 36(0.02%) | 36(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync_9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 159(0.08%) | 159(0.08%) | 0(0.00%) | 0(0.00%) | 367(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 159(0.08%) | 159(0.08%) | 0(0.00%) | 0(0.00%) | 366(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pll_sel | pll_selector | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_pll | nreset_pll | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reset_pll) | nreset_pll | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen | nreset_gen | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_clk | clk_ttc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_ttc_clk_ttc_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-----------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------+---------------+-------------+------------+---------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining