*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_182b_512/DPR_182b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3359.316 ; gain = 25.988 ; free physical = 83099 ; free virtual = 89835 INFO: [Netlist 29-17] Analyzing 29763 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay2'. The XDC file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay'. The XDC file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'FIFO_209b_512'. The XDC file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] get_clocks: Time (s): cpu = 00:00:42 ; elapsed = 00:00:26 . Memory (MB): peak = 5623.023 ; gain = 1513.270 ; free physical = 81024 ; free virtual = 87760 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:07 . Memory (MB): peak = 5773.023 ; gain = 150.000 ; free physical = 80872 ; free virtual = 87608 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] create_generated_clock: Time (s): cpu = 00:00:17 ; elapsed = 00:00:08 . Memory (MB): peak = 5920.023 ; gain = 147.000 ; free physical = 80720 ; free virtual = 87456 Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] create_generated_clock: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 6135.023 ; gain = 215.000 ; free physical = 80505 ; free virtual = 87241 Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga4.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga4.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga4.xdc] get_pins: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7246.953 ; gain = 1103.930 ; free physical = 79455 ; free virtual = 86191 Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga4.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga4.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga4.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga4.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga4.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_182b_512/FIFO_182b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7310.957 ; gain = 0.000 ; free physical = 81118 ; free virtual = 87854 INFO: [Project 1-111] Unisim Transformation Summary: A total of 66 instances were transformed. OBUFDS => OBUFDS: 66 instances 25 Infos, 10 Warnings, 3 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:06:16 ; elapsed = 00:06:30 . Memory (MB): peak = 7310.957 ; gain = 4813.102 ; free physical = 81118 ; free virtual = 87854 source /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 7326.965 ; gain = 8.004 ; free physical = 81116 ; free virtual = 87852 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1b1303003 Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80256 ; free virtual = 86992 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1de58d061 Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80688 ; free virtual = 87424 INFO: [Opt 31-389] Phase Retarget created 165 cells and removed 835 cells INFO: [Opt 31-1021] In phase Retarget, 225 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 20fa28c76 Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80688 ; free virtual = 87424 INFO: [Opt 31-389] Phase Constant propagation created 54 cells and removed 250 cells INFO: [Opt 31-1021] In phase Constant propagation, 157 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 17c02a4d8 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80702 ; free virtual = 87438 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 3263 cells INFO: [Opt 31-1021] In phase Sweep, 899 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 4 BUFG optimization | Checksum: 1ddbe2119 Time (s): cpu = 00:00:59 ; elapsed = 00:00:59 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80701 ; free virtual = 87437 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 13f68a11a Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80701 ; free virtual = 87437 INFO: [Opt 31-389] Phase Shift Register Optimization created 64 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1a175ac5c Time (s): cpu = 00:01:02 ; elapsed = 00:01:03 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80701 ; free virtual = 87437 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 301 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 165 | 835 | 225 | | Constant propagation | 54 | 250 | 157 | | Sweep | 2 | 3263 | 899 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 64 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 301 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.98 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80707 ; free virtual = 87444 Ending Logic Optimization Task | Checksum: f2c3ed3e Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 7326.965 ; gain = 0.000 ; free physical = 80707 ; free virtual = 87444 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 756 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 97 newly gated: 170 Total Ports: 1512 Ending PowerOpt Patch Enables Task | Checksum: 1c2288ca8 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 9984.105 ; gain = 0.000 ; free physical = 79621 ; free virtual = 86357 Ending Power Optimization Task | Checksum: 1c2288ca8 Time (s): cpu = 00:04:07 ; elapsed = 00:03:27 . Memory (MB): peak = 9984.105 ; gain = 2657.141 ; free physical = 80109 ; free virtual = 86846 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 7a2ec413 Time (s): cpu = 00:01:02 ; elapsed = 00:01:04 . Memory (MB): peak = 9984.105 ; gain = 0.000 ; free physical = 79762 ; free virtual = 86499 Ending Final Cleanup Task | Checksum: 7a2ec413 Time (s): cpu = 00:01:06 ; elapsed = 00:01:09 . Memory (MB): peak = 9984.105 ; gain = 0.000 ; free physical = 79761 ; free virtual = 86498 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 9984.105 ; gain = 0.000 ; free physical = 79763 ; free virtual = 86500 Ending Netlist Obfuscation Task | Checksum: 7a2ec413 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 9984.105 ; gain = 0.000 ; free physical = 79764 ; free virtual = 86500 INFO: [Common 17-83] Releasing license: Implementation 59 Infos, 10 Warnings, 3 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:07:21 ; elapsed = 00:06:46 . Memory (MB): peak = 9984.105 ; gain = 2673.148 ; free physical = 79765 ; free virtual = 86502 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 9984.105 ; gain = 0.000 ; free physical = 78343 ; free virtual = 85490 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:10:27 ; elapsed = 00:10:58 . Memory (MB): peak = 9984.109 ; gain = 0.004 ; free physical = 78639 ; free virtual = 85502 INFO: [runtcl-4] Executing : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:54 ; elapsed = 00:01:56 . Memory (MB): peak = 9984.109 ; gain = 0.000 ; free physical = 78238 ; free virtual = 85101 Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[10] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[9]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[11] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[10]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[12] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[11]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[13] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[12]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[1] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[0]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[2] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[1]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[3] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[2]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[4] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[3]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[5] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[4]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[6] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[5]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[7] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[6]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[8] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[7]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[9] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[8]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[10] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[9]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[11] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[10]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[12] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[11]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[13] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[12]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[7] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[6]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[8] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[7]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[9] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[8]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 78233 ; free virtual = 85097 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 6f2db0fa Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 78233 ; free virtual = 85096 Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 78233 ; free virtual = 85096 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14564b5c0 Time (s): cpu = 00:01:48 ; elapsed = 00:01:50 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 78406 ; free virtual = 85270 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1743229ce Time (s): cpu = 00:03:51 ; elapsed = 00:03:55 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 78010 ; free virtual = 84873 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1743229ce Time (s): cpu = 00:03:53 ; elapsed = 00:03:57 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 78007 ; free virtual = 84871 Phase 1 Placer Initialization | Checksum: 1743229ce Time (s): cpu = 00:03:54 ; elapsed = 00:03:58 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77993 ; free virtual = 84857 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1c9aa3690 Time (s): cpu = 00:04:40 ; elapsed = 00:04:45 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77792 ; free virtual = 84656 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 264765ed3 Time (s): cpu = 00:05:15 ; elapsed = 00:05:20 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77801 ; free virtual = 84665 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 116 LUTNM shape to break, 12418 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 63, two critical 53, total 116, new lutff created 4 INFO: [Physopt 32-775] End 1 Pass. Optimized 5147 nets or cells. Created 116 new cells, deleted 5031 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/O178. Replicated 72 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 72 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start. Replicated 30 times. INFO: [Physopt 32-232] Optimized 3 nets. Created 174 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 174 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77726 ; free virtual = 84590 INFO: [Physopt 32-76] Pass 1. Identified 34 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1026[8]. Replicated 5 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1024[12]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[7]. Replicated 5 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/enb. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1035[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1036[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1081[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1035[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1080[3]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1080[6]. Replicated 7 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1080[11]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1037[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1026[9]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1037[7]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[5]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1024[15]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1080[9]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1057[7]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1036[10]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1036[6]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1037[11]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1036[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1036[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1035[14]. Replicated 8 times. INFO: [Physopt 32-232] Optimized 34 nets. Created 263 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 34 nets or cells. Created 263 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77727 ; free virtual = 84591 INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/tmp_ram_rd_en could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/tmp_ram_rd_en could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-46] Identified 9 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[0]_rep_n_0. Replicated 1 times. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[2]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[4]_rep_n_0 was not replicated. INFO: [Physopt 32-232] Optimized 1 net. Created 1 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 1 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.49 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77728 ; free virtual = 84592 INFO: [Physopt 32-457] Pass 1. Identified 12 candidate cells for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 12 nets or cells. Created 272 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77727 ; free virtual = 84591 INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 51 nets or cells. Created 82 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77726 ; free virtual = 84590 INFO: [Physopt 32-527] Pass 1: Identified 1 candidate cell for BRAM register optimization INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 28 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 28 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77727 ; free virtual = 84591 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77744 ; free virtual = 84608 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 116 | 5031 | 5147 | 0 | 1 | 00:00:13 | | Very High Fanout | 174 | 0 | 3 | 0 | 1 | 00:00:15 | | Fanout | 263 | 0 | 34 | 0 | 1 | 00:00:21 | | Critical Cell | 1 | 0 | 1 | 0 | 1 | 00:00:00 | | DSP Register | 272 | 0 | 12 | 0 | 1 | 00:00:02 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 82 | 0 | 51 | 0 | 1 | 00:00:02 | | BRAM Register | 28 | 0 | 1 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 936 | 5031 | 5249 | 0 | 10 | 00:00:54 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: a195f5b1 Time (s): cpu = 00:13:28 ; elapsed = 00:13:50 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77748 ; free virtual = 84612 Phase 2.3 Global Placement Core | Checksum: fc485c6c Time (s): cpu = 00:13:46 ; elapsed = 00:14:08 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77723 ; free virtual = 84587 Phase 2 Global Placement | Checksum: fc485c6c Time (s): cpu = 00:13:47 ; elapsed = 00:14:08 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77886 ; free virtual = 84750 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: f90325f6 Time (s): cpu = 00:14:34 ; elapsed = 00:14:56 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77867 ; free virtual = 84731 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 8db1fcfa Time (s): cpu = 00:16:14 ; elapsed = 00:16:37 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77758 ; free virtual = 84622 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: d66b7e91 Time (s): cpu = 00:16:21 ; elapsed = 00:16:43 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77755 ; free virtual = 84620 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 5e949bcf Time (s): cpu = 00:16:22 ; elapsed = 00:16:45 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77756 ; free virtual = 84620 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: e2d8466b Time (s): cpu = 00:17:51 ; elapsed = 00:18:15 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77751 ; free virtual = 84616 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1e1bbab25 Time (s): cpu = 00:21:12 ; elapsed = 00:21:37 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77438 ; free virtual = 84302 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 18d2edf52 Time (s): cpu = 00:21:36 ; elapsed = 00:22:01 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77456 ; free virtual = 84320 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 71928990 Time (s): cpu = 00:21:42 ; elapsed = 00:22:08 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77455 ; free virtual = 84320 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 168bc0637 Time (s): cpu = 00:24:27 ; elapsed = 00:24:54 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77420 ; free virtual = 84284 Phase 3 Detail Placement | Checksum: 168bc0637 Time (s): cpu = 00:24:31 ; elapsed = 00:24:57 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 77422 ; free virtual = 84286 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1c862fcb7 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.418 | TNS=-39.312 | Phase 1 Physical Synthesis Initialization | Checksum: 1a3d05d1f Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 76889 ; free virtual = 83753 INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 15686c42a Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 76884 ; free virtual = 83748 Phase 4.1.1.1 BUFG Insertion | Checksum: 1c862fcb7 Time (s): cpu = 00:28:09 ; elapsed = 00:28:38 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 76903 ; free virtual = 83768 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.079. For the most accurate timing information please run report_timing. Time (s): cpu = 00:33:58 ; elapsed = 00:34:27 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 76917 ; free virtual = 83781 Phase 4.1 Post Commit Optimization | Checksum: 27f4962aa Time (s): cpu = 00:34:01 ; elapsed = 00:34:30 . Memory (MB): peak = 9984.125 ; gain = 0.000 ; free physical = 76917 ; free virtual = 83782 Post Placement Optimization Initialization | Checksum: 1a747fdd5 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.698 | TNS=-387.182 | Phase 1 Physical Synthesis Initialization | Checksum: fd26fac4 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 10081.379 ; gain = 0.000 ; free physical = 76979 ; free virtual = 83843 INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1dc1527a3 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 10081.379 ; gain = 0.000 ; free physical = 76974 ; free virtual = 83838 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.760. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 163c804eb Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.760 | TNS=-175.245 | Phase 1 Physical Synthesis Initialization | Checksum: ee58a6ba Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 10081.379 ; gain = 0.000 ; free physical = 76979 ; free virtual = 83843 INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1a76382c3 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 10081.379 ; gain = 0.000 ; free physical = 76974 ; free virtual = 83838 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.760. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 107796831 Time (s): cpu = 01:11:23 ; elapsed = 01:11:55 . Memory (MB): peak = 10081.379 ; gain = 97.254 ; free physical = 77006 ; free virtual = 83870 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 32x32| 4x4| |___________|___________________|___________________| | South| 32x32| 8x8| |___________|___________________|___________________| | East| 8x8| 8x8| |___________|___________________|___________________| | West| 4x4| 8x8| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 107796831 Time (s): cpu = 01:11:27 ; elapsed = 01:11:59 . Memory (MB): peak = 10081.379 ; gain = 97.254 ; free physical = 77009 ; free virtual = 83873 Phase 4.3 Placer Reporting | Checksum: 107796831 Time (s): cpu = 01:11:30 ; elapsed = 01:12:02 . Memory (MB): peak = 10081.379 ; gain = 97.254 ; free physical = 77009 ; free virtual = 83874 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.52 . Memory (MB): peak = 10081.379 ; gain = 0.000 ; free physical = 77016 ; free virtual = 83881 Time (s): cpu = 01:11:31 ; elapsed = 01:12:03 . Memory (MB): peak = 10081.379 ; gain = 97.254 ; free physical = 77016 ; free virtual = 83881 Phase 4 Post Placement Optimization and Clean-Up | Checksum: dda8bf59 Time (s): cpu = 01:11:34 ; elapsed = 01:12:06 . Memory (MB): peak = 10081.379 ; gain = 97.254 ; free physical = 77016 ; free virtual = 83881 Ending Placer Task | Checksum: 7a12b21f Time (s): cpu = 01:11:34 ; elapsed = 01:12:06 . Memory (MB): peak = 10081.379 ; gain = 97.254 ; free physical = 77016 ; free virtual = 83881 INFO: [Common 17-83] Releasing license: Implementation 178 Infos, 52 Warnings, 3 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 01:12:06 ; elapsed = 01:12:39 . Memory (MB): peak = 10081.379 ; gain = 97.270 ; free physical = 77354 ; free virtual = 84219 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 10081.379 ; gain = 0.000 ; free physical = 76419 ; free virtual = 84136 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:48 ; elapsed = 00:03:11 . Memory (MB): peak = 10081.383 ; gain = 0.004 ; free physical = 77125 ; free virtual = 84161 INFO: [runtcl-4] Executing : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.88 . Memory (MB): peak = 10081.383 ; gain = 0.000 ; free physical = 77086 ; free virtual = 84122 INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 10081.383 ; gain = 0.000 ; free physical = 77128 ; free virtual = 84166 INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_placed_1.rpt -pb top_efex_processor_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 77005 ; free virtual = 84043 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.760 | TNS=-27.039 | Phase 1 Physical Synthesis Initialization | Checksum: 164437263 Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76845 ; free virtual = 83883 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.760 | TNS=-27.039 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 164437263 Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76819 ; free virtual = 83857 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.760 | TNS=-27.039 | INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in142[123]. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5][157] INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in142[123]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3 INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_n_0. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.659 | TNS=-26.233 | INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3 INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.620 | TNS=-26.161 | INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0_repN_1. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_comp_1 INFO: [Physopt 32-134] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0_repN_1. Rewiring did not optimize the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0_repN_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_comp INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.581 | TNS=-25.965 | INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_n_0. Replicated 1 times. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.522 | TNS=-26.738 | INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_comp INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0. Replicated 1 times. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.507 | TNS=-26.140 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0_repN. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_comp INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_3_n_0_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.339 | TNS=-24.555 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][0]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][0] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.339 | TNS=-24.216 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][10]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][10] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][10]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.339 | TNS=-23.289 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][11]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][11] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][11]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.339 | TNS=-22.950 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][17]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][17] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][17]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.335 | TNS=-22.610 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][2]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][2] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.335 | TNS=-22.275 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][5]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][5] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.335 | TNS=-21.940 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][6]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][6] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.335 | TNS=-21.604 | INFO: [Physopt 32-662] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][7]. Did not re-place instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3][7] INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg_n_0_[3][7]. Optimizations did not improve timing on the net. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3]0. Replicated 2 times. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER/FastFifo_2/mem_reg[3]0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.243 | TNS=-20.966 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_7_n_0. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_7 INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/U2_TOB_payld_length/D[8]. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/U2_TOB_payld_length/TOBs_out_i[8]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_7_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.229 | TNS=-20.887 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/prog_full. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/geqOp. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/geqOp_carry__0_i_6_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.223 | TNS=-20.879 | INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0_repN. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_comp_replica INFO: [Physopt 32-601] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0_repN. Net driver READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_comp_replica was replaced. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][169]_i_1_n_0_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.221 | TNS=-20.621 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry__0_i_6_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.198 | TNS=-20.598 | INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry__0_i_6_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.177 | TNS=-20.577 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry_i_5_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.177 | TNS=-20.577 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/geqOp_carry_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/geqOp_carry_i_5_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.175 | TNS=-20.548 | INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_n_0_repN. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_comp_replica INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_n_0_repN. Replicated 1 times. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][135]_i_1_n_0_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.164 | TNS=-20.286 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_11_n_0. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_11 INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_11_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.161 | TNS=-20.271 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in148[68]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[2][102] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in148[68]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.161 | TNS=-20.109 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in148[70]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[2][104] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in148[70]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.161 | TNS=-19.948 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in148[71]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[2][105] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/in148[71]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.161 | TNS=-19.787 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/OUT_Data_reg[31]_0[28]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/OneOrTwo1__5. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/OneOrTwo1_carry_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/S[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.160 | TNS=-19.126 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/Q[10]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1__5. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1_carry_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_1[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.159 | TNS=-18.333 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_0_[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_8__8. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_2__10 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_8__8. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.156 | TNS=-18.027 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg_n_0_[59]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg[59] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg_n_0_[59]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.154 | TNS=-17.385 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/mem_reg[3]_1044[23]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/mem_reg[3][23] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/mem_reg[3]_1044[23]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.154 | TNS=-17.231 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/mem_reg[3]_1044[30]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/mem_reg[3][30] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER/FastFifo_1/mem_reg[3]_1044[30]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.149 | TNS=-17.076 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_11_n_0. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_11 INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_11_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_12_n_0. Did not re-place instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_12 INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[8]_i_12_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-17.004 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/mem_reg[1]_1060[5]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/mem_reg[1][5] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/mem_reg[1]_1060[5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-16.897 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/prog_full. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry__0_i_6_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf4.gpf4b.prog_full_i_i_1_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8]. Did not re-place instance READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gdiff.diff_pntr_pad_reg[9] INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-16.897 | Phase 3 Critical Path Optimization | Checksum: 164437263 Time (s): cpu = 00:01:48 ; elapsed = 00:01:49 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76822 ; free virtual = 83861 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-16.897 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/prog_full. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry__0_i_6_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf4.gpf4b.prog_full_i_i_1_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8]. Did not re-place instance READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gdiff.diff_pntr_pad_reg[9] INFO: [Physopt 32-572] Net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/prog_full. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/ltOp_carry__0_i_6_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf4.gpf4b.prog_full_i_i_1_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8]. Did not re-place instance READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gdiff.diff_pntr_pad_reg[9] INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/diff_pntr[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-16.897 | Phase 4 Critical Path Optimization | Checksum: 164437263 Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76822 ; free virtual = 83861 Netlist sorting complete. Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.20 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76841 ; free virtual = 83879 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.148 | TNS=-16.897 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:05 | | Critical Path | 0.612 | 10.142 | 5 | 0 | 34 | 0 | 2 | 00:00:19 | | Total | 0.612 | 10.142 | 5 | 0 | 34 | 0 | 3 | 00:00:24 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76841 ; free virtual = 83879 Ending Physical Synthesis Task | Checksum: 18bd19e86 Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76841 ; free virtual = 83879 INFO: [Common 17-83] Releasing license: Implementation 346 Infos, 52 Warnings, 3 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:04:03 ; elapsed = 00:04:05 . Memory (MB): peak = 10081.398 ; gain = 0.016 ; free physical = 77122 ; free virtual = 84160 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76224 ; free virtual = 84088 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:48 ; elapsed = 00:03:12 . Memory (MB): peak = 10081.398 ; gain = 0.000 ; free physical = 76904 ; free virtual = 84111 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 9bc49bdb ConstDB: 0 ShapeSum: cbe96901 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 199c08d3b Time (s): cpu = 00:02:12 ; elapsed = 00:02:12 . Memory (MB): peak = 10112.777 ; gain = 0.000 ; free physical = 76299 ; free virtual = 83505 Post Restoration Checksum: NetGraph: cd62e921 NumContArr: cc5da41a Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 199c08d3b Time (s): cpu = 00:02:16 ; elapsed = 00:02:17 . Memory (MB): peak = 10112.777 ; gain = 0.000 ; free physical = 76522 ; free virtual = 83728 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 199c08d3b Time (s): cpu = 00:02:19 ; elapsed = 00:02:20 . Memory (MB): peak = 10112.777 ; gain = 0.000 ; free physical = 76494 ; free virtual = 83700 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 199c08d3b Time (s): cpu = 00:02:20 ; elapsed = 00:02:21 . Memory (MB): peak = 10112.777 ; gain = 0.000 ; free physical = 76494 ; free virtual = 83700 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 21b63b32f Time (s): cpu = 00:05:57 ; elapsed = 00:06:00 . Memory (MB): peak = 10396.777 ; gain = 284.000 ; free physical = 76337 ; free virtual = 83544 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.183 | TNS=-7.636 | WHS=-0.467 | THS=-11152.300| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 24cdb13c3 Time (s): cpu = 00:08:03 ; elapsed = 00:08:07 . Memory (MB): peak = 10396.777 ; gain = 284.000 ; free physical = 76254 ; free virtual = 83461 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.183 | TNS=-1.498 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 21cd82fff Time (s): cpu = 00:08:04 ; elapsed = 00:08:09 . Memory (MB): peak = 10396.777 ; gain = 284.000 ; free physical = 76250 ; free virtual = 83456 Phase 2 Router Initialization | Checksum: e30adfa0 Time (s): cpu = 00:08:05 ; elapsed = 00:08:10 . Memory (MB): peak = 10396.777 ; gain = 284.000 ; free physical = 76250 ; free virtual = 83456 Router Utilization Summary Global Vertical Routing Utilization = 1.20441e-05 % Global Horizontal Routing Utilization = 4.91507e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 402270 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 402268 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: e30adfa0 Time (s): cpu = 00:08:09 ; elapsed = 00:08:14 . Memory (MB): peak = 10396.777 ; gain = 284.000 ; free physical = 76246 ; free virtual = 83453 Phase 3 Initial Routing | Checksum: c9a65a55 Time (s): cpu = 00:11:19 ; elapsed = 00:11:26 . Memory (MB): peak = 10396.777 ; gain = 284.000 ; free physical = 76203 ; free virtual = 83410 INFO: [Route 35-580] Design has 5 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk280 | clk280 |DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER/FastFifo_2/ReadAddress_reg[0]/D| | clk280 | clk280 |DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER/FastFifo_2/ReadAddress_reg[1]/D| | clk40 | clk200 |DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/column_for[0].row_for[6].layer0_for[0].EnergyConverter0/ENCODING_IF.special_reg[0]/D| | clk280 | clk280 |DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER/OUT_Data_reg[14]/D| | clk40 | clk200 |DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/column_for[0].row_for[6].layer0_for[0].EnergyConverter0/ENCODING_IF.special_reg[1]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 35997 Number of Nodes with overlaps = 2768 Number of Nodes with overlaps = 496 Number of Nodes with overlaps = 118 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.290 | TNS=-12.731| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 16021103f Time (s): cpu = 00:23:56 ; elapsed = 00:24:11 . Memory (MB): peak = 10435.184 ; gain = 322.406 ; free physical = 76213 ; free virtual = 83420 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 89 Number of Nodes with overlaps = 52 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.275 | TNS=-4.879 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1fb1b7881 Time (s): cpu = 00:25:51 ; elapsed = 00:26:10 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76201 ; free virtual = 83408 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 69 Number of Nodes with overlaps = 158 Number of Nodes with overlaps = 82 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.248 | TNS=-2.410 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: e9f707f3 Time (s): cpu = 00:28:36 ; elapsed = 00:29:00 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76201 ; free virtual = 83408 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 97 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.246 | TNS=-2.298 | WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 185849961 Time (s): cpu = 00:30:44 ; elapsed = 00:31:12 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76201 ; free virtual = 83408 Phase 4.5 Global Iteration 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.294 | TNS=-2.358 | WHS=N/A | THS=N/A | Phase 4.5 Global Iteration 4 | Checksum: 24f4f7255 Time (s): cpu = 00:31:05 ; elapsed = 00:31:33 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76200 ; free virtual = 83407 Phase 4 Rip-up And Reroute | Checksum: 24f4f7255 Time (s): cpu = 00:31:06 ; elapsed = 00:31:34 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76200 ; free virtual = 83407 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 15577f568 Time (s): cpu = 00:31:50 ; elapsed = 00:32:19 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76136 ; free virtual = 83344 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.124 | TNS=-0.450 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 195e69457 Time (s): cpu = 00:31:56 ; elapsed = 00:32:25 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76164 ; free virtual = 83371 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 195e69457 Time (s): cpu = 00:31:57 ; elapsed = 00:32:26 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76165 ; free virtual = 83372 Phase 5 Delay and Skew Optimization | Checksum: 195e69457 Time (s): cpu = 00:31:59 ; elapsed = 00:32:27 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76165 ; free virtual = 83372 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: f09d231d Time (s): cpu = 00:32:50 ; elapsed = 00:33:18 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76188 ; free virtual = 83396 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.124 | TNS=-0.450 | WHS=0.017 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 10744a411 Time (s): cpu = 00:32:51 ; elapsed = 00:33:20 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76187 ; free virtual = 83394 Phase 6 Post Hold Fix | Checksum: 10744a411 Time (s): cpu = 00:32:52 ; elapsed = 00:33:21 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76187 ; free virtual = 83394 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1a0832aca Time (s): cpu = 00:34:10 ; elapsed = 00:34:39 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76189 ; free virtual = 83396 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.124 | TNS=-0.450 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 1a0832aca Time (s): cpu = 00:34:12 ; elapsed = 00:34:41 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76189 ; free virtual = 83396 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 26.5886 % Global Horizontal Routing Utilization = 26.6159 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 2x2 Area, Max Cong = 90.5405%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X76Y318 -> INT_R_X77Y319 INT_L_X82Y316 -> INT_R_X83Y317 INT_L_X86Y304 -> INT_R_X87Y305 INT_L_X86Y302 -> INT_R_X87Y303 INT_L_X62Y274 -> INT_R_X63Y275 South Dir 8x8 Area, Max Cong = 87.4437%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_FEEDTHRU_2_X147Y279 -> INT_R_X63Y275 INT_L_X88Y196 -> INT_R_X95Y203 INT_L_X80Y188 -> INT_R_X87Y195 East Dir 4x4 Area, Max Cong = 90.7169%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X68Y176 -> INT_R_X71Y179 INT_L_X68Y172 -> INT_R_X71Y175 INT_L_X68Y168 -> INT_R_X71Y171 INT_L_X68Y164 -> INT_R_X71Y167 West Dir 2x2 Area, Max Cong = 86.3971%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X48Y268 -> INT_R_X49Y269 INT_L_X48Y260 -> INT_R_X49Y261 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 1 Effective congestion level: 2 Aspect Ratio: 0.75 Sparse Ratio: 1.5 Direction: South ---------------- Congested clusters found at Level 2 Effective congestion level: 4 Aspect Ratio: 0.555556 Sparse Ratio: 1.625 Direction: East ---------------- Congested clusters found at Level 2 Effective congestion level: 3 Aspect Ratio: 0.4 Sparse Ratio: 1.5 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 1 Sparse Ratio: 0.9375 Phase 8 Route finalize | Checksum: 1a0832aca Time (s): cpu = 00:34:15 ; elapsed = 00:34:44 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76184 ; free virtual = 83392 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1a0832aca Time (s): cpu = 00:34:16 ; elapsed = 00:34:45 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76180 ; free virtual = 83388 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 13eb96810 Time (s): cpu = 00:34:56 ; elapsed = 00:35:25 . Memory (MB): peak = 10460.395 ; gain = 347.617 ; free physical = 76146 ; free virtual = 83353 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 10460.395 ; gain = 0.000 ; free physical = 75892 ; free virtual = 83100 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.105. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: cd9c45e9 Time (s): cpu = 00:07:38 ; elapsed = 00:07:41 . Memory (MB): peak = 11201.074 ; gain = 740.680 ; free physical = 75829 ; free virtual = 83036 Phase 11 Incr Placement Change | Checksum: 13eb96810 Time (s): cpu = 00:42:45 ; elapsed = 00:43:18 . Memory (MB): peak = 11203.148 ; gain = 1090.371 ; free physical = 75829 ; free virtual = 83036 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: 9fab3eac Time (s): cpu = 00:43:44 ; elapsed = 00:44:18 . Memory (MB): peak = 11203.148 ; gain = 1090.371 ; free physical = 75661 ; free virtual = 82868 Post Restoration Checksum: NetGraph: d94c8b84 NumContArr: 21660892 Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: fab29416 Time (s): cpu = 00:44:02 ; elapsed = 00:44:36 . Memory (MB): peak = 11203.148 ; gain = 1090.371 ; free physical = 75749 ; free virtual = 82957 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: fab29416 Time (s): cpu = 00:44:06 ; elapsed = 00:44:39 . Memory (MB): peak = 11203.148 ; gain = 1090.371 ; free physical = 75722 ; free virtual = 82929 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: 1a2619fcd Time (s): cpu = 00:44:09 ; elapsed = 00:44:42 . Memory (MB): peak = 11203.148 ; gain = 1090.371 ; free physical = 75722 ; free virtual = 82929 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: 1486c5a0d Time (s): cpu = 00:48:19 ; elapsed = 00:48:54 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75401 ; free virtual = 82609 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.005 | TNS=0.000 | WHS=-0.467 | THS=-11082.558| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 19af75271 Time (s): cpu = 00:50:27 ; elapsed = 00:51:03 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75324 ; free virtual = 82531 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.005 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: 18656024e Time (s): cpu = 00:50:29 ; elapsed = 00:51:05 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75318 ; free virtual = 82525 Phase 13 Router Initialization | Checksum: 1a593ad15 Time (s): cpu = 00:50:32 ; elapsed = 00:51:08 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75349 ; free virtual = 82556 Router Utilization Summary Global Vertical Routing Utilization = 26.5127 % Global Horizontal Routing Utilization = 26.5576 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 921 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 579 Number of Partially Routed Nets = 342 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14.1 Global Routing Phase 14.1 Global Routing | Checksum: 1a593ad15 Time (s): cpu = 00:50:36 ; elapsed = 00:51:12 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75371 ; free virtual = 82579 Phase 14 Initial Routing | Checksum: 249132fee Time (s): cpu = 00:50:44 ; elapsed = 00:51:20 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75357 ; free virtual = 82565 INFO: [Route 35-580] Design has 157 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U2_PISO_RAW/RAW_data_in_i_reg[107]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U2_PISO_RAW/RAW_data_in_i_reg[142]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U2_PISO_RAW/RAW_data_in_i_reg[175]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U2_PISO_RAW/RAW_data_in_i_reg[21]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U2_PISO_RAW/RAW_data_in_i_reg[125]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 1745 Number of Nodes with overlaps = 562 Number of Nodes with overlaps = 229 Number of Nodes with overlaps = 94 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.050 | TNS=-0.262 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: 2215e4634 Time (s): cpu = 00:54:37 ; elapsed = 00:55:19 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75374 ; free virtual = 82582 Phase 15.2 Global Iteration 1 Number of Nodes with overlaps = 3118 Number of Nodes with overlaps = 1089 Number of Nodes with overlaps = 425 Number of Nodes with overlaps = 194 Number of Nodes with overlaps = 98 Number of Nodes with overlaps = 120 Number of Nodes with overlaps = 47 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.136 | TNS=-0.440 | WHS=N/A | THS=N/A | Phase 15.2 Global Iteration 1 | Checksum: 102906e1c Time (s): cpu = 00:57:50 ; elapsed = 00:58:38 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75376 ; free virtual = 82584 Phase 15 Rip-up And Reroute | Checksum: 102906e1c Time (s): cpu = 00:57:51 ; elapsed = 00:58:39 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75376 ; free virtual = 82584 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 1d4115693 Time (s): cpu = 00:58:38 ; elapsed = 00:59:26 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75303 ; free virtual = 82511 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.007 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 16.1 Delay CleanUp | Checksum: 1a8c90fba Time (s): cpu = 00:58:40 ; elapsed = 00:59:27 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75336 ; free virtual = 82544 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: 1a8c90fba Time (s): cpu = 00:58:41 ; elapsed = 00:59:29 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75336 ; free virtual = 82544 Phase 16 Delay and Skew Optimization | Checksum: 1a8c90fba Time (s): cpu = 00:58:42 ; elapsed = 00:59:30 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75336 ; free virtual = 82544 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 178c42e30 Time (s): cpu = 00:59:34 ; elapsed = 01:00:22 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75358 ; free virtual = 82566 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.007 | TNS=0.000 | WHS=0.017 | THS=0.000 | Phase 17.1 Hold Fix Iter | Checksum: 150f579f5 Time (s): cpu = 00:59:36 ; elapsed = 01:00:24 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75357 ; free virtual = 82565 Phase 17 Post Hold Fix | Checksum: 150f579f5 Time (s): cpu = 00:59:37 ; elapsed = 01:00:25 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75357 ; free virtual = 82565 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 1693b5971 Time (s): cpu = 01:00:56 ; elapsed = 01:01:44 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75357 ; free virtual = 82565 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.007 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 1693b5971 Time (s): cpu = 01:00:57 ; elapsed = 01:01:45 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75357 ; free virtual = 82565 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 26.6126 % Global Horizontal Routing Utilization = 26.624 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 1693b5971 Time (s): cpu = 01:01:00 ; elapsed = 01:01:49 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75353 ; free virtual = 82561 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 1693b5971 Time (s): cpu = 01:01:02 ; elapsed = 01:01:50 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75349 ; free virtual = 82557 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: 1533dd36b Time (s): cpu = 01:01:47 ; elapsed = 01:02:36 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75345 ; free virtual = 82553 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.006 | TNS=0.000 | WHS=0.017 | THS=0.000 | Phase 22 Post Router Timing | Checksum: 1352385cb Time (s): cpu = 01:05:55 ; elapsed = 01:06:44 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 75596 ; free virtual = 82804 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+--------+--------+-------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+--------+--------+-------+-----+--------+--------------+-------------------+ | 1 | -0.124 | -0.450 | 0.017 | - | Pass | 00:33:11 | | +------+--------+--------+-------+-----+--------+--------------+-------------------+ | 2 | 0.007 | 0.000 | 0.017 | - | Pass | 00:18:04 | x | +------+--------+--------+-------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 01:05:56 ; elapsed = 01:06:45 . Memory (MB): peak = 11299.148 ; gain = 1186.371 ; free physical = 76225 ; free virtual = 83433 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 381 Infos, 52 Warnings, 3 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 01:09:07 ; elapsed = 01:09:58 . Memory (MB): peak = 11299.148 ; gain = 1217.750 ; free physical = 76226 ; free virtual = 83434 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.4... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.4 clean. INFO: [Hog:Msg-0] Git describe set to: v1.1.0-hog641a037 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_processor.4 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.4 clean. INFO: [Hog:Msg-0] The git SHA value 641a037 will be set as bitstream USERID. INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.4... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.4 clean. INFO: [Hog:Msg-0] Git describe set to: v1.1.0-hog641a037 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.4-v1.1.0-hog641a037... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 11299.148 ; gain = 0.000 ; free physical = 76224 ; free virtual = 83435