## efex_processor.4 Synthesis Utilization report
                                                                                     
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |   
| ---    |         ---  |        --- |         ---  |             ---  |             
| Slice  LUTs*     |    181946   |   0         |    346400        |    52.52     |   
| Slice  Registers |    255125   |   0         |    692800        |    36.83     |   
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03
| DSPs   |         7    |        0   |         2880 |             0.24 |             
| Bonded IOB       |    478      |   0         |    600           |    79.67     |   
                                                                                     
## efex_processor.4 Implementation Utilization report
                                                                                        
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         ---  |             ---  |              
| Slice  LUTs      |    189403   |     0         |    346400        |    54.68     |    
| Slice  Registers |    279801   |     0         |    692800        |    40.39     |    
| Block  RAM       Tile |        731.5 |         0    |             1180 |         61.99
| DSPs   |         127  |        0     |         2880 |             4.41 |              
| Bonded IOB       |    228      |     226       |    600           |    38.00     |