## Repository info - Merge request number: 283 - Branch name: feature-fix-tob-bcn-fifo-threshold ## MR Description added latency check in after input MGT and latency check out just before output MGT. added signals to test points and to ILA. Modify BUSY counters to stop wrap around, and latch for reading using bit 9 of readout pulse register MINOR_VERSION ## Changelog ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 641a037 | 1.1.0 | | Constraints | 6033fb92 | 1.1.0 | | IPbus XML | 15f9ce5 | 1.1.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | c3aa34c | 6.17.4 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.0 | | **Lib:** TOB_rdout_lib | 010114a | 1.1.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 641a037 | 1.1.0 | | Constraints | f12abe46 | 1.0.0 | | IPbus XML | 15f9ce5 | 1.1.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | c3aa34c | 6.17.4 | | **Lib:** TOB_rdout_lib | 010114a | 1.1.0 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 8447d2e | 1.1.0 | | Constraints | 8447d2e5 | 1.1.0 | | IPbus XML | 15f9ce5 | 1.1.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | c3aa34c | 6.17.4 | | **Lib:** TOB_rdout_lib | 010114a | 1.1.0 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 4f580cd | 1.1.0 | | Constraints | 4f580cd2 | 1.1.0 | | IPbus XML | 15f9ce5 | 1.1.0 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | c3aa34c | 6.17.4 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.0 | | **Lib:** TOB_rdout_lib | 010114a | 1.1.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | ac022a1 | 1.1.0 | | Constraints | 8080fc5a | 0.17.0 | | IPbus XML | 0ffb67f | 0.17.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | c3aa34c | 6.17.4 | | **Lib:** infrastructure_lib | ac022a1 | 1.1.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.006198 | | TNS: | 0.000000 | | WHS: | 0.016916 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.053965 | | TNS: | 0.000000 | | WHS: | 0.016389 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.033560 | | TNS: | 0.000000 | | WHS: | 0.015229 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.054220 | | TNS: | 0.000000 | | WHS: | 0.016644 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.128353 | | TNS: | 0.000000 | | WHS: | 0.051177 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181946 | 0 | 346400 | 52.52 | | Slice Registers | 255125 | 0 | 692800 | 36.83 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189403 | 0 | 346400 | 54.68 | | Slice Registers | 279801 | 0 | 692800 | 40.39 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181950 | 0 | 346400 | 52.53 | | Slice Registers | 255128 | 0 | 692800 | 36.83 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189221 | 0 | 346400 | 54.63 | | Slice Registers | 280050 | 0 | 692800 | 40.42 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186067 | 0 | 346400 | 53.71 | | Slice Registers | 266702 | 0 | 692800 | 38.50 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192739 | 0 | 346400 | 55.64 | | Slice Registers | 292202 | 0 | 692800 | 42.18 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186006 | 0 | 346400 | 53.70 | | Slice Registers | 266684 | 0 | 692800 | 38.49 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 193121 | 0 | 346400 | 55.75 | | Slice Registers | 291804 | 0 | 692800 | 42.12 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 21679 | 0 | 204000 | 10.63 | | Slice Registers | 30942 | 0 | 408000 | 7.58 | | Block RAM Tile | 282 | 0 | 750 | 37.60 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 282 | 0 | 600 | 47.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 27441 | 0 | 204000 | 13.45 | | Slice Registers | 45814 | 0 | 408000 | 11.23 | | Block RAM Tile | 306.5 | 0 | 750 | 40.87 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 250 | 238 | 600 | 41.67 |