*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.85 . Memory (MB): peak = 2521.082 ; gain = 0.000 ; free physical = 65576 ; free virtual = 73014 INFO: [Netlist 29-17] Analyzing 4319 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.payload_channel1_ila UUID: 0df12a89-7d50-56a7-b477-7a1cc58c8f1f INFO: [Chipscope 16-324] Core: GOLDEN_IF.payload_channel2_ila UUID: 8da22044-be2e-580d-90d3-f798718f212e Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 3406.645 ; gain = 636.066 ; free physical = 64794 ; free virtual = 72189 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3428.648 ; gain = 0.000 ; free physical = 64825 ; free virtual = 72220 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1685 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 320 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:58 . Memory (MB): peak = 3428.648 ; gain = 907.570 ; free physical = 64818 ; free virtual = 72212 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3436.652 ; gain = 8.000 ; free physical = 64845 ; free virtual = 72229 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 20b14c178 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3436.652 ; gain = 0.000 ; free physical = 64720 ; free virtual = 72098 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3649.402 ; gain = 0.000 ; free physical = 62751 ; free virtual = 70772 Phase 1 Generate And Synthesize Debug Cores | Checksum: 19b02d5c6 Time (s): cpu = 00:01:57 ; elapsed = 00:02:35 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62751 ; free virtual = 70773 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 236c19ef7 Time (s): cpu = 00:02:02 ; elapsed = 00:02:40 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62783 ; free virtual = 70805 INFO: [Opt 31-389] Phase Retarget created 109 cells and removed 304 cells INFO: [Opt 31-1021] In phase Retarget, 281 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 1 inverter(s) to 3 load pin(s). Phase 3 Constant propagation | Checksum: 248be5437 Time (s): cpu = 00:02:03 ; elapsed = 00:02:41 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62756 ; free virtual = 70804 INFO: [Opt 31-389] Phase Constant propagation created 167 cells and removed 570 cells INFO: [Opt 31-1021] In phase Constant propagation, 132 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 1abf0817d Time (s): cpu = 00:02:05 ; elapsed = 00:02:43 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62690 ; free virtual = 70787 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 604 cells INFO: [Opt 31-1021] In phase Sweep, 3361 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 24c2e9967 Time (s): cpu = 00:02:06 ; elapsed = 00:02:44 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62684 ; free virtual = 70812 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 25d5d77bd Time (s): cpu = 00:02:06 ; elapsed = 00:02:44 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62685 ; free virtual = 70817 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 232acc032 Time (s): cpu = 00:02:06 ; elapsed = 00:02:45 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62687 ; free virtual = 70826 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 368 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 109 | 304 | 281 | | Constant propagation | 167 | 570 | 132 | | Sweep | 2 | 604 | 3361 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 368 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3649.402 ; gain = 0.000 ; free physical = 62678 ; free virtual = 70851 Ending Logic Optimization Task | Checksum: 176d727de Time (s): cpu = 00:02:08 ; elapsed = 00:02:46 . Memory (MB): peak = 3649.402 ; gain = 43.785 ; free physical = 62666 ; free virtual = 70838 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 20 BRAM(s) out of a total of 315 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 263 newly gated: 22 Total Ports: 630 Ending PowerOpt Patch Enables Task | Checksum: 1e96eee3e Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4540.137 ; gain = 0.000 ; free physical = 61365 ; free virtual = 69731 Ending Power Optimization Task | Checksum: 1e96eee3e Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 4540.137 ; gain = 890.734 ; free physical = 61420 ; free virtual = 69786 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1896bd80a Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4540.137 ; gain = 0.000 ; free physical = 61350 ; free virtual = 69881 Ending Final Cleanup Task | Checksum: 1896bd80a Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 4540.137 ; gain = 0.000 ; free physical = 61342 ; free virtual = 69874 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4540.137 ; gain = 0.000 ; free physical = 61339 ; free virtual = 69870 Ending Netlist Obfuscation Task | Checksum: 1896bd80a Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4540.137 ; gain = 0.000 ; free physical = 61341 ; free virtual = 69872 INFO: [Common 17-83] Releasing license: Implementation 69 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:03:35 ; elapsed = 00:04:12 . Memory (MB): peak = 4540.137 ; gain = 1111.488 ; free physical = 61358 ; free virtual = 69889 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4540.137 ; gain = 0.000 ; free physical = 60795 ; free virtual = 69365 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 4540.141 ; gain = 0.004 ; free physical = 60902 ; free virtual = 69445 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60752 ; free virtual = 69287 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60754 ; free virtual = 69291 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1700885c4 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60761 ; free virtual = 69298 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60761 ; free virtual = 69297 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11d00d439 Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60788 ; free virtual = 69337 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1cf454c71 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60735 ; free virtual = 69284 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1cf454c71 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60719 ; free virtual = 69269 Phase 1 Placer Initialization | Checksum: 1cf454c71 Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60728 ; free virtual = 69277 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 17528f62b Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60663 ; free virtual = 69206 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1caf6c324 Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60658 ; free virtual = 69199 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 34 LUTNM shape to break, 2278 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 31, two critical 3, total 34, new lutff created 1 INFO: [Physopt 32-775] End 1 Pass. Optimized 902 nets or cells. Created 34 new cells, deleted 868 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 23 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg_3. Replicated 15 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 38 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 38 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60729 ; free virtual = 69193 INFO: [Physopt 32-76] Pass 1. Identified 7 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 7 nets. Created 35 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 35 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60722 ; free virtual = 69186 INFO: [Physopt 32-117] Net eth/emac0/U0/temac_gbe_v9_0_core/no_avb_tx_axi_intf.tx_axi_shim/tx_mac_tready_int could not be optimized because driver eth/emac0/U0/temac_gbe_v9_0_core/no_avb_tx_axi_intf.tx_axi_shim/tx_mac_tready_int_inferred__0_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2 could not be replicated INFO: [Physopt 32-46] Identified 17 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0 was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-232] Optimized 1 net. Created 1 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 1 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60719 ; free virtual = 69183 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 29 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_7. 2 registers were pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_16. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_7. 2 registers were pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 14 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60722 ; free virtual = 69186 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60731 ; free virtual = 69189 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 34 | 868 | 902 | 0 | 1 | 00:00:02 | | Very High Fanout | 38 | 0 | 2 | 0 | 1 | 00:00:02 | | Fanout | 35 | 0 | 7 | 0 | 1 | 00:00:01 | | Critical Cell | 1 | 0 | 1 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 14 | 0 | 12 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 122 | 868 | 924 | 0 | 10 | 00:00:06 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1bdf07605 Time (s): cpu = 00:02:11 ; elapsed = 00:02:13 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60715 ; free virtual = 69172 Phase 2.3 Global Placement Core | Checksum: 254c689e7 Time (s): cpu = 00:02:14 ; elapsed = 00:02:17 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60695 ; free virtual = 69152 Phase 2 Global Placement | Checksum: 254c689e7 Time (s): cpu = 00:02:15 ; elapsed = 00:02:17 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60733 ; free virtual = 69191 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2081ca79d Time (s): cpu = 00:02:22 ; elapsed = 00:02:24 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60761 ; free virtual = 69142 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 271c75aa8 Time (s): cpu = 00:02:35 ; elapsed = 00:02:38 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60741 ; free virtual = 69106 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 20790bf1a Time (s): cpu = 00:02:37 ; elapsed = 00:02:39 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60774 ; free virtual = 69140 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 24587434d Time (s): cpu = 00:02:37 ; elapsed = 00:02:40 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60775 ; free virtual = 69142 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 242a852ba Time (s): cpu = 00:02:53 ; elapsed = 00:02:56 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60778 ; free virtual = 69131 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: 1dd1ce357 Time (s): cpu = 00:03:20 ; elapsed = 00:03:23 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60705 ; free virtual = 68948 Phase 3.6 Small Shape Detail Placement | Checksum: 1dd1ce357 Time (s): cpu = 00:03:21 ; elapsed = 00:03:24 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60753 ; free virtual = 68995 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1e17e0188 Time (s): cpu = 00:03:24 ; elapsed = 00:03:27 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60750 ; free virtual = 68982 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 218e0fb6d Time (s): cpu = 00:03:25 ; elapsed = 00:03:28 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60708 ; free virtual = 68981 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 13c61ef1c Time (s): cpu = 00:03:55 ; elapsed = 00:03:58 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60491 ; free virtual = 68900 Phase 3 Detail Placement | Checksum: 13c61ef1c Time (s): cpu = 00:03:55 ; elapsed = 00:03:59 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60495 ; free virtual = 68902 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 9742bf81 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.324 | TNS=-12.390 | Phase 1 Physical Synthesis Initialization | Checksum: 7df4ea81 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60232 ; free virtual = 68809 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 5b653200 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60224 ; free virtual = 68801 Phase 4.1.1.1 BUFG Insertion | Checksum: 9742bf81 Time (s): cpu = 00:04:29 ; elapsed = 00:04:33 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60250 ; free virtual = 68827 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.167. For the most accurate timing information please run report_timing. Time (s): cpu = 00:06:25 ; elapsed = 00:06:29 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 59774 ; free virtual = 68540 Phase 4.1 Post Commit Optimization | Checksum: 2b749afa Time (s): cpu = 00:06:26 ; elapsed = 00:06:29 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 59767 ; free virtual = 68532 Post Placement Optimization Initialization | Checksum: 5eb8bb26 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.167 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 66ebe3cc Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 59657 ; free virtual = 68422 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 39e4345a Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 59647 ; free virtual = 68413 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.194. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: fdd96885 Time (s): cpu = 00:08:06 ; elapsed = 00:08:11 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60599 ; free virtual = 69321 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: fdd96885 Time (s): cpu = 00:08:07 ; elapsed = 00:08:11 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60592 ; free virtual = 69314 Phase 4.3 Placer Reporting | Checksum: fdd96885 Time (s): cpu = 00:08:08 ; elapsed = 00:08:12 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60592 ; free virtual = 69314 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60593 ; free virtual = 69315 Time (s): cpu = 00:08:08 ; elapsed = 00:08:12 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60593 ; free virtual = 69315 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a88b2c10 Time (s): cpu = 00:08:08 ; elapsed = 00:08:12 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60585 ; free virtual = 69307 Ending Placer Task | Checksum: 16c5c9996 Time (s): cpu = 00:08:08 ; elapsed = 00:08:12 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60537 ; free virtual = 69259 INFO: [Common 17-83] Releasing license: Implementation 174 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:08:13 ; elapsed = 00:08:18 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 60557 ; free virtual = 69279 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 61861 ; free virtual = 70660 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 61759 ; free virtual = 70464 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.43 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 61672 ; free virtual = 70376 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.50 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 61883 ; free virtual = 70589 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 187 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 63369 ; free virtual = 72032 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 63296 ; free virtual = 72081 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 63221 ; free virtual = 72007 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: ade5cb93 ConstDB: 0 ShapeSum: be76ce03 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 19c2882bd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62068 ; free virtual = 71460 Post Restoration Checksum: NetGraph: cbc7dd81 NumContArr: d060a53c Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 19c2882bd Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62121 ; free virtual = 71514 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 19c2882bd Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62147 ; free virtual = 71540 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 19c2882bd Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62159 ; free virtual = 71553 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1ec22fefa Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62864 ; free virtual = 72334 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.149 | TNS=0.000 | WHS=-2.845 | THS=-4468.167| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 2212d26a1 Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62495 ; free virtual = 72668 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.149 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1fc43b45e Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62492 ; free virtual = 72666 Phase 2 Router Initialization | Checksum: 22ca5d598 Time (s): cpu = 00:01:49 ; elapsed = 00:01:50 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62496 ; free virtual = 72670 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 68833 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 68831 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 22ca5d598 Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 62491 ; free virtual = 72666 Phase 3 Initial Routing | Checksum: 28f4ccefb Time (s): cpu = 00:03:27 ; elapsed = 00:03:29 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69692 ; free virtual = 76994 INFO: [Route 35-580] Design has 24 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[1]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[2]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[3]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 5704 Number of Nodes with overlaps = 440 Number of Nodes with overlaps = 85 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.048 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 11e743fc6 Time (s): cpu = 00:04:43 ; elapsed = 00:04:45 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 70064 ; free virtual = 76542 Phase 4 Rip-up And Reroute | Checksum: 11e743fc6 Time (s): cpu = 00:04:43 ; elapsed = 00:04:45 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 70062 ; free virtual = 76540 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 11e743fc6 Time (s): cpu = 00:04:43 ; elapsed = 00:04:46 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 70055 ; free virtual = 76533 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 11e743fc6 Time (s): cpu = 00:04:43 ; elapsed = 00:04:46 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 70052 ; free virtual = 76529 Phase 5 Delay and Skew Optimization | Checksum: 11e743fc6 Time (s): cpu = 00:04:43 ; elapsed = 00:04:46 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 70049 ; free virtual = 76526 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: b3543bed Time (s): cpu = 00:04:53 ; elapsed = 00:04:55 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69851 ; free virtual = 76328 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.076 | TNS=0.000 | WHS=-1.040 | THS=-35.809| Phase 6.1 Hold Fix Iter | Checksum: 196a9e27c Time (s): cpu = 00:04:54 ; elapsed = 00:04:56 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69836 ; free virtual = 76313 Phase 6 Post Hold Fix | Checksum: 24a31b02c Time (s): cpu = 00:04:54 ; elapsed = 00:04:57 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69828 ; free virtual = 76306 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1b708bb11 Time (s): cpu = 00:05:05 ; elapsed = 00:05:08 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69363 ; free virtual = 75841 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.076 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 1b708bb11 Time (s): cpu = 00:05:06 ; elapsed = 00:05:08 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69351 ; free virtual = 75828 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.35399 % Global Horizontal Routing Utilization = 5.78922 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 1b708bb11 Time (s): cpu = 00:05:06 ; elapsed = 00:05:09 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69334 ; free virtual = 75812 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1b708bb11 Time (s): cpu = 00:05:07 ; elapsed = 00:05:09 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69333 ; free virtual = 75811 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 1e6287d73 Time (s): cpu = 00:05:13 ; elapsed = 00:05:15 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 69242 ; free virtual = 75719 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.076 | TNS=0.000 | WHS=0.056 | THS=0.000 | Phase 11 Post Router Timing | Checksum: 276c32ee9 Time (s): cpu = 00:05:43 ; elapsed = 00:05:45 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 67102 ; free virtual = 73579 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 1 | 0.076 | 0.000 | -1.040 | - | Pass | 00:04:32 | x | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:05:43 ; elapsed = 00:05:46 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 67289 ; free virtual = 73767 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 206 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:05:57 ; elapsed = 00:06:01 . Memory (MB): peak = 4540.141 ; gain = 0.000 ; free physical = 67289 ; free virtual = 73767 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetVerFromSHA-0] No tag contains B635372, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 864E2DA, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:GetVerFromSHA-0] No tag contains 864e2da, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:Msg-0] Git describe set to: v1.1.4-hog864e2da INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetVerFromSHA-0] No tag contains B635372, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 864E2DA, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:Msg-0] The git SHA value 864e2da will be set as bitstream USERID. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetVerFromSHA-0] No tag contains B635372, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 864E2DA, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:GetVerFromSHA-0] No tag contains 864e2da, will use most recent tag v1.1.3. As this is an official tag, patch will be incremented to 4. INFO: [Hog:Msg-0] Git describe set to: v1.1.4-hog864e2da INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.1.4-hog864e2da... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.