## Repository info - Merge request number: 287 - Branch name: feature-fix-safe-mode-read-error ## MR Description fix safe mode read with multi-slice readout and update test bench ## Changelog - fix safe mode read with multi-slice readout and update test bench - add FIFO delay credit mechanism to efex_tob_merger state machine - explicit register for slice suppression in mgt_readout_receiver and increase IFG in efex_tob_merger - extend IFG in packet_ram_fifo - fix issue with back to back packets in mgt_readout_receiver - increase TOB merging delay by another 32 BC - tweak Round Robin MUX and MGT Ready logic ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | b635372 | 1.1.4 | | Constraints | 6033fb92 | 1.1.1 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** TOB_rdout_lib | 99d27a6 | 1.1.4 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | b635372 | 1.1.4 | | Constraints | f12abe46 | 1.0.0 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** TOB_rdout_lib | 99d27a6 | 1.1.4 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 864e2da | 1.1.4 | | Constraints | 8080fc5a | 0.17.0 | | IPbus XML | df21a4d | 1.1.2 | | Top Directory | d88faa0 | 0.15.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** infrastructure_lib | 864e2da | 1.1.4 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | b635372 | 1.1.4 | | Constraints | 8447d2e5 | 1.1.1 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** TOB_rdout_lib | 99d27a6 | 1.1.4 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | b635372 | 1.1.4 | | Constraints | 4f580cd2 | 1.1.1 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** TOB_rdout_lib | 99d27a6 | 1.1.4 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.017694 | | TNS: | 0.000000 | | WHS: | 0.035447 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.007326 | | TNS: | 0.000000 | | WHS: | 0.008165 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.075558 | | TNS: | 0.000000 | | WHS: | 0.055652 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.091510 | | TNS: | 0.000000 | | WHS: | 0.009269 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.068358 | | TNS: | 0.000000 | | WHS: | 0.024023 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181954 | 0 | 346400 | 52.53 | | Slice Registers | 255125 | 0 | 692800 | 36.83 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189589 | 0 | 346400 | 54.73 | | Slice Registers | 280438 | 0 | 692800 | 40.48 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181956 | 0 | 346400 | 52.53 | | Slice Registers | 255128 | 0 | 692800 | 36.83 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189516 | 0 | 346400 | 54.71 | | Slice Registers | 280261 | 0 | 692800 | 40.45 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 21854 | 0 | 204000 | 10.71 | | Slice Registers | 31106 | 0 | 408000 | 7.62 | | Block RAM Tile | 282 | 0 | 750 | 37.60 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 282 | 0 | 600 | 47.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 27947 | 0 | 204000 | 13.70 | | Slice Registers | 46488 | 0 | 408000 | 11.39 | | Block RAM Tile | 308.5 | 0 | 750 | 41.13 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 250 | 238 | 600 | 41.67 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186079 | 0 | 346400 | 53.72 | | Slice Registers | 266702 | 0 | 692800 | 38.50 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192666 | 0 | 346400 | 55.62 | | Slice Registers | 292180 | 0 | 692800 | 42.17 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186004 | 0 | 346400 | 53.70 | | Slice Registers | 266684 | 0 | 692800 | 38.49 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192624 | 0 | 346400 | 55.61 | | Slice Registers | 292038 | 0 | 692800 | 42.15 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 424 | 424 | 600 | 70.67 |