## Repository info
- Merge request number: 289
- Branch name: feature-split-aurora

## MR Description
MINOR_VERSION:
Allow different mapping of TOB and Raw readout onto Aurora channels
Add tide marks in the upper 16 bits of each FIFO register


## Changelog

- split TOB and Raw Aurora mapping and add tide marks to FIFO registers

## efex_control Version Table
| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | bd4fdea        | 1.3.0       |
| Constraints                 | 8080fc5a       | 0.17.0      |
| IPbus XML                   | 6da16cc        | 1.3.0       |
| Top Directory               | d88faa0        | 0.15.0      |
| Hog                         | b07df97        | 6.19.3      |
| **Lib:** infrastructure_lib | bd4fdea        | 1.3.0       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |



## efex_control Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.027800       |
| TNS:          | 0.000000       |
| WHS:          | 0.059597       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_control Synthesis Utilization report
                                                                                      
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         ---  |             ---  |              
| Slice  LUTs*     |    22510    |   0         |    204000        |    11.03     |    
| Slice  Registers |    32500    |   0         |    408000        |    7.97      |    
| Block  RAM       Tile |        318 |         0    |             750  |         42.40
| DSPs   |         0    |        0   |         1120 |             0.00 |              
| Bonded IOB       |    282      |   0         |    600           |    47.00     |    
                                                                                      
## efex_control Implementation Utilization report
                                                                                        
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         ---  |             ---  |              
| Slice  LUTs      |    28666    |     0         |    204000        |    14.05     |    
| Slice  Registers |    47905    |     0         |    408000        |    11.74     |    
| Block  RAM       Tile |        344.5 |         0    |             750  |         45.93
| DSPs   |         0    |        0     |         1120 |             0.00 |              
| Bonded IOB       |    250      |     238       |    600           |    41.67     |