## Repository info - Merge request number: 290 - Branch name: feature-fix-no-tob-event-trailer-error ## MR Description ## Changelog - fix corrective trailer length calculation in mgt_readout_receiver ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | cc0180a | 1.3.1 | | Constraints | f12abe46 | 1.0.0 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** TOB_rdout_lib | cc0180a | 1.3.1 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | c11f297 | 1.3.1 | | Constraints | c11f2976 | 1.3.1 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** TOB_rdout_lib | cc0180a | 1.3.1 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | cc0180a | 1.3.1 | | Constraints | 4f580cd2 | 1.1.1 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** TOB_rdout_lib | cc0180a | 1.3.1 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | cc0180a | 1.3.1 | | Constraints | 6033fb92 | 1.1.1 | | IPbus XML | 15f9ce5 | 1.1.1 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** TOB_rdout_lib | cc0180a | 1.3.1 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | dfb0728 | 1.3.1 | | Constraints | 8080fc5a | 0.17.0 | | IPbus XML | 6da16cc | 1.3.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** infrastructure_lib | dfb0728 | 1.3.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.021790 | | TNS: | 0.000000 | | WHS: | 0.029852 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.030870 | | TNS: | 0.000000 | | WHS: | 0.009268 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.075260 | | TNS: | 0.000000 | | WHS: | 0.023074 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.070097 | | TNS: | 0.000000 | | WHS: | 0.020128 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.015754 | | TNS: | 0.000000 | | WHS: | 0.060949 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181948 | 0 | 346400 | 52.53 | | Slice Registers | 255129 | 0 | 692800 | 36.83 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189444 | 0 | 346400 | 54.69 | | Slice Registers | 280203 | 0 | 692800 | 40.45 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186076 | 0 | 346400 | 53.72 | | Slice Registers | 266694 | 0 | 692800 | 38.50 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 193584 | 0 | 346400 | 55.88 | | Slice Registers | 291250 | 0 | 692800 | 42.04 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186007 | 0 | 346400 | 53.70 | | Slice Registers | 266686 | 0 | 692800 | 38.49 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192990 | 0 | 346400 | 55.71 | | Slice Registers | 292568 | 0 | 692800 | 42.23 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181947 | 0 | 346400 | 52.53 | | Slice Registers | 255130 | 0 | 692800 | 36.83 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 7 | 0 | 2880 | 0.24 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 188890 | 0 | 346400 | 54.53 | | Slice Registers | 279761 | 0 | 692800 | 40.38 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 127 | 0 | 2880 | 4.41 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 22774 | 0 | 204000 | 11.16 | | Slice Registers | 32449 | 0 | 408000 | 7.95 | | Block RAM Tile | 318 | 0 | 750 | 42.40 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 282 | 0 | 600 | 47.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 28922 | 0 | 204000 | 14.18 | | Slice Registers | 47851 | 0 | 408000 | 11.73 | | Block RAM Tile | 344.5 | 0 | 750 | 45.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 250 | 238 | 600 | 41.67 |