*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2514.098 ; gain = 0.000 ; free physical = 49643 ; free virtual = 92617 INFO: [Netlist 29-17] Analyzing 4546 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.payload_channel1_ila UUID: 0df12a89-7d50-56a7-b477-7a1cc58c8f1f INFO: [Chipscope 16-324] Core: GOLDEN_IF.payload_channel2_ila UUID: 8da22044-be2e-580d-90d3-f798718f212e Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 3412.543 ; gain = 635.090 ; free physical = 48040 ; free virtual = 91472 Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3434.547 ; gain = 0.000 ; free physical = 48094 ; free virtual = 91526 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1685 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 320 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:09 . Memory (MB): peak = 3434.547 ; gain = 920.453 ; free physical = 48094 ; free virtual = 91526 source /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3442.551 ; gain = 7.984 ; free physical = 48072 ; free virtual = 91497 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1dd9a6d2e Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3442.551 ; gain = 0.000 ; free physical = 47923 ; free virtual = 91346 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3655.301 ; gain = 0.000 ; free physical = 45247 ; free virtual = 89461 Phase 1 Generate And Synthesize Debug Cores | Checksum: 1735c38e6 Time (s): cpu = 00:02:11 ; elapsed = 00:03:15 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45244 ; free virtual = 89458 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1ab54fcc3 Time (s): cpu = 00:02:17 ; elapsed = 00:03:21 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45311 ; free virtual = 89513 INFO: [Opt 31-389] Phase Retarget created 109 cells and removed 352 cells INFO: [Opt 31-1021] In phase Retarget, 281 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 1 inverter(s) to 3 load pin(s). Phase 3 Constant propagation | Checksum: 171b95402 Time (s): cpu = 00:02:18 ; elapsed = 00:03:22 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45321 ; free virtual = 89523 INFO: [Opt 31-389] Phase Constant propagation created 167 cells and removed 570 cells INFO: [Opt 31-1021] In phase Constant propagation, 132 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 1983d4772 Time (s): cpu = 00:02:20 ; elapsed = 00:03:24 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45301 ; free virtual = 89498 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 608 cells INFO: [Opt 31-1021] In phase Sweep, 3361 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 1d4bd460d Time (s): cpu = 00:02:22 ; elapsed = 00:03:26 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45314 ; free virtual = 89511 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 174b2ccad Time (s): cpu = 00:02:22 ; elapsed = 00:03:26 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45314 ; free virtual = 89511 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 19041b5f1 Time (s): cpu = 00:02:23 ; elapsed = 00:03:26 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45301 ; free virtual = 89498 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 368 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 109 | 352 | 281 | | Constant propagation | 167 | 570 | 132 | | Sweep | 2 | 608 | 3361 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 368 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3655.301 ; gain = 0.000 ; free physical = 45311 ; free virtual = 89508 Ending Logic Optimization Task | Checksum: 1e6a0ba9b Time (s): cpu = 00:02:25 ; elapsed = 00:03:29 . Memory (MB): peak = 3655.301 ; gain = 43.785 ; free physical = 45310 ; free virtual = 89507 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 20 BRAM(s) out of a total of 351 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 299 newly gated: 22 Total Ports: 702 Ending PowerOpt Patch Enables Task | Checksum: 17734e8b3 Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4611.090 ; gain = 0.000 ; free physical = 45142 ; free virtual = 89344 Ending Power Optimization Task | Checksum: 17734e8b3 Time (s): cpu = 00:01:03 ; elapsed = 00:01:00 . Memory (MB): peak = 4611.090 ; gain = 955.789 ; free physical = 45208 ; free virtual = 89410 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: f24a62ae Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4611.090 ; gain = 0.000 ; free physical = 45176 ; free virtual = 89373 Ending Final Cleanup Task | Checksum: f24a62ae Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 4611.090 ; gain = 0.000 ; free physical = 45201 ; free virtual = 89399 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4611.090 ; gain = 0.000 ; free physical = 45194 ; free virtual = 89392 Ending Netlist Obfuscation Task | Checksum: f24a62ae Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4611.090 ; gain = 0.000 ; free physical = 45199 ; free virtual = 89397 INFO: [Common 17-83] Releasing license: Implementation 69 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:02 ; elapsed = 00:05:05 . Memory (MB): peak = 4611.090 ; gain = 1176.543 ; free physical = 45199 ; free virtual = 89397 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4611.090 ; gain = 0.000 ; free physical = 45138 ; free virtual = 89222 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 4611.094 ; gain = 0.004 ; free physical = 45153 ; free virtual = 89207 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 4611.094 ; gain = 0.000 ; free physical = 45047 ; free virtual = 89088 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45051 ; free virtual = 89087 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f11f0e61 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45045 ; free virtual = 89081 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45036 ; free virtual = 89072 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 182b737f4 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45099 ; free virtual = 89126 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 215d12cfd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45021 ; free virtual = 89031 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 215d12cfd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45032 ; free virtual = 89023 Phase 1 Placer Initialization | Checksum: 215d12cfd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45035 ; free virtual = 89019 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 15f21b80c Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44737 ; free virtual = 88934 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 20afcc793 Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44529 ; free virtual = 88825 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 35 LUTNM shape to break, 2286 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 30, two critical 5, total 35, new lutff created 1 INFO: [Physopt 32-775] End 1 Pass. Optimized 909 nets or cells. Created 35 new cells, deleted 874 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 17 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg_3. Replicated 20 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 37 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 37 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.27 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44368 ; free virtual = 88636 INFO: [Physopt 32-76] Pass 1. Identified 12 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 11 nets. Created 57 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 57 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44351 ; free virtual = 88620 INFO: [Physopt 32-117] Net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-46] Identified 87 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 2 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44328 ; free virtual = 88596 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44321 ; free virtual = 88589 INFO: [Physopt 32-736] Net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg_30 has fanout of one; hence not performing Critical-cell optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44296 ; free virtual = 88564 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 35 | 874 | 909 | 0 | 1 | 00:00:02 | | Very High Fanout | 37 | 0 | 2 | 0 | 1 | 00:00:02 | | Fanout | 57 | 0 | 11 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 2 | 0 | 2 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 131 | 874 | 924 | 0 | 11 | 00:00:06 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1688729cd Time (s): cpu = 00:02:33 ; elapsed = 00:02:36 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44491 ; free virtual = 88757 Phase 2.3 Global Placement Core | Checksum: 1ebd31972 Time (s): cpu = 00:02:37 ; elapsed = 00:02:40 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44499 ; free virtual = 88765 Phase 2 Global Placement | Checksum: 1ebd31972 Time (s): cpu = 00:02:37 ; elapsed = 00:02:40 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44532 ; free virtual = 88798 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1692bb9ff Time (s): cpu = 00:02:46 ; elapsed = 00:02:50 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44512 ; free virtual = 88780 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: a86ef765 Time (s): cpu = 00:03:04 ; elapsed = 00:03:07 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44274 ; free virtual = 88669 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 197be04e0 Time (s): cpu = 00:03:05 ; elapsed = 00:03:09 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44229 ; free virtual = 88678 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1301b2da1 Time (s): cpu = 00:03:06 ; elapsed = 00:03:09 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44227 ; free virtual = 88679 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: c90edce9 Time (s): cpu = 00:03:27 ; elapsed = 00:03:31 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44136 ; free virtual = 88591 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: b6e437b4 Time (s): cpu = 00:03:59 ; elapsed = 00:04:03 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43843 ; free virtual = 88296 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 15aa7a552 Time (s): cpu = 00:04:03 ; elapsed = 00:04:07 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43806 ; free virtual = 88259 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1559685c2 Time (s): cpu = 00:04:04 ; elapsed = 00:04:08 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43799 ; free virtual = 88250 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 18ccbdaab Time (s): cpu = 00:04:43 ; elapsed = 00:04:48 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45498 ; free virtual = 89947 Phase 3 Detail Placement | Checksum: 18ccbdaab Time (s): cpu = 00:04:44 ; elapsed = 00:04:49 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45510 ; free virtual = 89959 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 2a11b8c8d Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.342 | TNS=-22.475 | Phase 1 Physical Synthesis Initialization | Checksum: 26c92aff3 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 46283 ; free virtual = 90652 INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 278a6e3c3 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 46293 ; free virtual = 90663 Phase 4.1.1.1 BUFG Insertion | Checksum: 2a11b8c8d Time (s): cpu = 00:05:39 ; elapsed = 00:05:43 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 46290 ; free virtual = 90660 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.043. For the most accurate timing information please run report_timing. Time (s): cpu = 00:08:21 ; elapsed = 00:08:26 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 46423 ; free virtual = 92136 Phase 4.1 Post Commit Optimization | Checksum: 2411200b9 Time (s): cpu = 00:08:22 ; elapsed = 00:08:27 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 46411 ; free virtual = 92125 Post Placement Optimization Initialization | Checksum: 20f15ea84 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.485 | TNS=-19.916 | Phase 1 Physical Synthesis Initialization | Checksum: 28d159371 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 54642 ; free virtual = 98202 INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1c61e5e3c Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 54492 ; free virtual = 98058 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.037. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1b228005d Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.037 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1e40cfea0 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 54452 ; free virtual = 96584 INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 2123908e6 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 53632 ; free virtual = 95764 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.037. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1d98ddb04 Time (s): cpu = 00:14:08 ; elapsed = 00:14:14 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 53195 ; free virtual = 95327 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1d98ddb04 Time (s): cpu = 00:14:09 ; elapsed = 00:14:15 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 53107 ; free virtual = 95239 Phase 4.3 Placer Reporting | Checksum: 1d98ddb04 Time (s): cpu = 00:14:10 ; elapsed = 00:14:15 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 52885 ; free virtual = 95018 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 52878 ; free virtual = 95011 Time (s): cpu = 00:14:10 ; elapsed = 00:14:15 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 52878 ; free virtual = 95011 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d47c7cc6 Time (s): cpu = 00:14:10 ; elapsed = 00:14:16 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 52815 ; free virtual = 94948 Ending Placer Task | Checksum: 1591db4dc Time (s): cpu = 00:14:10 ; elapsed = 00:14:16 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 52745 ; free virtual = 94878 INFO: [Common 17-83] Releasing license: Implementation 176 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:14:16 ; elapsed = 00:14:22 . Memory (MB): peak = 4611.109 ; gain = 0.016 ; free physical = 52783 ; free virtual = 94915 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 49616 ; free virtual = 91874 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 49528 ; free virtual = 91689 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.50 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 49424 ; free virtual = 91584 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.52 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 49528 ; free virtual = 91690 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 189 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 46065 ; free virtual = 88227 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45667 ; free virtual = 87955 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 45758 ; free virtual = 87947 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 8224f789 ConstDB: 0 ShapeSum: d6f8bd53 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: d2dfbfe0 Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44841 ; free virtual = 87031 Post Restoration Checksum: NetGraph: 9fe7655 NumContArr: c8e1498b Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: d2dfbfe0 Time (s): cpu = 00:00:54 ; elapsed = 00:00:55 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44818 ; free virtual = 87008 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: d2dfbfe0 Time (s): cpu = 00:00:55 ; elapsed = 00:00:55 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44735 ; free virtual = 86924 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: d2dfbfe0 Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44693 ; free virtual = 86883 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 10e4a6f9d Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 44733 ; free virtual = 86923 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.049 | TNS=0.000 | WHS=-2.781 | THS=-4506.408| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: dfe64f24 Time (s): cpu = 00:02:12 ; elapsed = 00:02:13 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43731 ; free virtual = 85921 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.049 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: ee4c567c Time (s): cpu = 00:02:12 ; elapsed = 00:02:14 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43738 ; free virtual = 85928 Phase 2 Router Initialization | Checksum: 13d788fb9 Time (s): cpu = 00:02:13 ; elapsed = 00:02:14 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43719 ; free virtual = 85909 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 70534 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 70532 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 13d788fb9 Time (s): cpu = 00:02:14 ; elapsed = 00:02:15 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 43713 ; free virtual = 85904 Phase 3 Initial Routing | Checksum: 17f2504fb Time (s): cpu = 00:05:43 ; elapsed = 00:05:46 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39367 ; free virtual = 81557 INFO: [Route 35-580] Design has 27 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[1]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[2]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 5918 Number of Nodes with overlaps = 561 Number of Nodes with overlaps = 147 Number of Nodes with overlaps = 55 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.158 | TNS=-2.258 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: c0fec886 Time (s): cpu = 00:07:32 ; elapsed = 00:07:37 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 37685 ; free virtual = 79876 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 814 Number of Nodes with overlaps = 155 Number of Nodes with overlaps = 60 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.066 | TNS=-0.445 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 2376eb705 Time (s): cpu = 00:08:05 ; elapsed = 00:08:10 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 41012 ; free virtual = 83202 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 450 Number of Nodes with overlaps = 29 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.055 | TNS=-0.222 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 21bea349c Time (s): cpu = 00:08:28 ; elapsed = 00:08:34 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 40338 ; free virtual = 82529 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 537 Number of Nodes with overlaps = 64 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.010 | TNS=-0.042 | WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 1202dbf31 Time (s): cpu = 00:08:56 ; elapsed = 00:09:03 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39802 ; free virtual = 81992 Phase 4.5 Global Iteration 4 Number of Nodes with overlaps = 410 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.027 | TNS=-0.110 | WHS=N/A | THS=N/A | Phase 4.5 Global Iteration 4 | Checksum: 1cb41bef4 Time (s): cpu = 00:09:09 ; elapsed = 00:09:16 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 40171 ; free virtual = 82361 Phase 4 Rip-up And Reroute | Checksum: 1cb41bef4 Time (s): cpu = 00:09:09 ; elapsed = 00:09:17 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 40162 ; free virtual = 82353 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 18654f499 Time (s): cpu = 00:09:19 ; elapsed = 00:09:26 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39802 ; free virtual = 81993 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.077 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 1b69a16ce Time (s): cpu = 00:09:19 ; elapsed = 00:09:26 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39761 ; free virtual = 81951 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1b69a16ce Time (s): cpu = 00:09:19 ; elapsed = 00:09:27 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39758 ; free virtual = 81948 Phase 5 Delay and Skew Optimization | Checksum: 1b69a16ce Time (s): cpu = 00:09:20 ; elapsed = 00:09:27 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39984 ; free virtual = 82175 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 19a228b2f Time (s): cpu = 00:09:30 ; elapsed = 00:09:38 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39628 ; free virtual = 81819 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.077 | TNS=0.000 | WHS=-1.380 | THS=-101.872| Phase 6.1 Hold Fix Iter | Checksum: 144b8c377 Time (s): cpu = 00:09:31 ; elapsed = 00:09:39 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39623 ; free virtual = 81814 Phase 6 Post Hold Fix | Checksum: 1e2609f02 Time (s): cpu = 00:09:32 ; elapsed = 00:09:39 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 39627 ; free virtual = 81818 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 16be2f28f Time (s): cpu = 00:09:47 ; elapsed = 00:09:54 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38841 ; free virtual = 81031 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.077 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 16be2f28f Time (s): cpu = 00:09:47 ; elapsed = 00:09:54 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38836 ; free virtual = 81027 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.8192 % Global Horizontal Routing Utilization = 6.57003 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 16be2f28f Time (s): cpu = 00:09:48 ; elapsed = 00:09:55 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38814 ; free virtual = 81005 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 16be2f28f Time (s): cpu = 00:09:48 ; elapsed = 00:09:56 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38807 ; free virtual = 80998 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 1237a8c2c Time (s): cpu = 00:09:56 ; elapsed = 00:10:03 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38784 ; free virtual = 80974 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.077 | TNS=0.000 | WHS=0.054 | THS=0.000 | Phase 11 Post Router Timing | Checksum: f5bad46d Time (s): cpu = 00:10:34 ; elapsed = 00:10:41 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38206 ; free virtual = 80397 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 1 | 0.077 | 0.000 | -1.380 | - | Pass | 00:09:09 | x | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:10:34 ; elapsed = 00:10:42 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38404 ; free virtual = 80595 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 213 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:10:52 ; elapsed = 00:11:01 . Memory (MB): peak = 4611.109 ; gain = 0.000 ; free physical = 38404 ; free virtual = 80595 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains C901C07, will use most recent tag v1.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetVerFromSHA-0] No tag contains c901c07, will use most recent tag v1.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] Git describe set to: v1.3.2-hogc901c07 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains C901C07, will use most recent tag v1.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] The git SHA value c901c07 will be set as bitstream USERID. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains C901C07, will use most recent tag v1.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetVerFromSHA-0] No tag contains c901c07, will use most recent tag v1.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] Git describe set to: v1.3.2-hogc901c07 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.3.2-hogc901c07... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.