## efex_processor.1 Synthesis Utilization report
                                                                                     
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |   
| ---    |         ---  |        --- |         ---  |             ---  |             
| Slice  LUTs*     |    185972   |   0         |    346400        |    53.69     |   
| Slice  Registers |    267004   |   0         |    692800        |    38.54     |   
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03
| DSPs   |         0    |        0   |         2880 |             0.00 |             
| Bonded IOB       |    476      |   0         |    600           |    79.33     |   
                                                                                     
## efex_processor.1 Implementation Utilization report
                                                                                        
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         ---  |             ---  |              
| Slice  LUTs      |    192719   |     0         |    346400        |    55.63     |    
| Slice  Registers |    292156   |     0         |    692800        |    42.17     |    
| Block  RAM       Tile |        742.5 |         0    |             1180 |         62.92
| DSPs   |         120  |        0     |         2880 |             4.17 |              
| Bonded IOB       |    424      |     424       |    600           |    70.67     |