## Repository info - Merge request number: 291 - Branch name: feature-modify-spy-ram-capture ## MR Description macro counters need two enable pulses to initially move from ZERO to ONE on output. so replaced these with generic counters to remove the need for double pulse after every reset. update TOB Readout to incorporate doubel word detection. ## Changelog - Increase Control FPGA TTC FIFO depth and update mgt_readout_receiver to set Header Mismatch if TOB or xTOB BCN mismatch ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 45985b7 | 1.3.2 | | Constraints | 4f580cd2 | 1.1.1 | | IPbus XML | 4f974f4 | 1.3.2 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** TOB_rdout_lib | 45985b7 | 1.3.2 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 272569c | 1.3.2 | | Constraints | 272569cc | 1.3.2 | | IPbus XML | 4f974f4 | 1.3.2 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** TOB_rdout_lib | 45985b7 | 1.3.2 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 45985b7 | 1.3.2 | | Constraints | f12abe46 | 1.0.0 | | IPbus XML | 4f974f4 | 1.3.2 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** TOB_rdout_lib | 45985b7 | 1.3.2 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 272569c | 1.3.2 | | Constraints | 272569cc | 1.3.2 | | IPbus XML | 4f974f4 | 1.3.2 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** algolib | 1c7c445 | 0.17.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 19290a0 | 1.1.1 | | **Lib:** TOB_rdout_lib | 45985b7 | 1.3.2 | | **Lib:** usr_ip | 79a2482 | 0.12.0 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | c901c07 | 1.3.2 | | Constraints | 8080fc5a | 0.17.0 | | IPbus XML | 6da16cc | 1.3.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | b07df97 | 6.19.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | c901c07 | 1.3.2 | ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.014068 | | TNS: | 0.000000 | | WHS: | 0.015630 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.076632 | | TNS: | 0.000000 | | WHS: | 0.025852 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.026559 | | TNS: | 0.000000 | | WHS: | 0.008378 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.030979 | | TNS: | 0.000000 | | WHS: | 0.031442 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.076700 | | TNS: | 0.000000 | | WHS: | 0.053564 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 185972 | 0 | 346400 | 53.69 | | Slice Registers | 267004 | 0 | 692800 | 38.54 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192719 | 0 | 346400 | 55.63 | | Slice Registers | 292156 | 0 | 692800 | 42.17 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186039 | 0 | 346400 | 53.71 | | Slice Registers | 267016 | 0 | 692800 | 38.54 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 476 | 0 | 600 | 79.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192654 | 0 | 346400 | 55.62 | | Slice Registers | 292010 | 0 | 692800 | 42.15 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 424 | 424 | 600 | 70.67 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181906 | 0 | 346400 | 52.51 | | Slice Registers | 255445 | 0 | 692800 | 36.87 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 188589 | 0 | 346400 | 54.44 | | Slice Registers | 280089 | 0 | 692800 | 40.43 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 181908 | 0 | 346400 | 52.51 | | Slice Registers | 255448 | 0 | 692800 | 36.87 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 478 | 0 | 600 | 79.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189872 | 0 | 346400 | 54.81 | | Slice Registers | 280900 | 0 | 692800 | 40.55 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 228 | 226 | 600 | 38.00 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 22654 | 0 | 204000 | 11.10 | | Slice Registers | 32448 | 0 | 408000 | 7.95 | | Block RAM Tile | 318 | 0 | 750 | 42.40 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 282 | 0 | 600 | 47.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 28797 | 0 | 204000 | 14.12 | | Slice Registers | 47838 | 0 | 408000 | 11.73 | | Block RAM Tile | 356.5 | 0 | 750 | 47.53 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 250 | 238 | 600 | 41.67 |