*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2535.859 ; gain = 0.000 ; free physical = 60439 ; free virtual = 82818 INFO: [Netlist 29-17] Analyzing 4782 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub2 UUID: 8598a6d1-95cf-5345-9854-ca1943451f96 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.payload_channel1_ila UUID: 0df12a89-7d50-56a7-b477-7a1cc58c8f1f INFO: [Chipscope 16-324] Core: GOLDEN_IF.payload_channel2_ila UUID: 8da22044-be2e-580d-90d3-f798718f212e INFO: [Chipscope 16-324] Core: GOLDEN_IF.ttc_broadcast_ila UUID: 8f9aad1d-eae7-58c7-ba1a-649e94f45b11 Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.payload_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub2/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.ttc_broadcast_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.ttc_broadcast_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub2/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.ttc_broadcast_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.ttc_broadcast_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 3447.227 ; gain = 645.059 ; free physical = 59667 ; free virtual = 82042 Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3469.230 ; gain = 0.000 ; free physical = 59853 ; free virtual = 82074 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1829 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 464 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:11 ; elapsed = 00:01:16 . Memory (MB): peak = 3469.230 ; gain = 955.160 ; free physical = 59853 ; free virtual = 82076 source /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 3477.234 ; gain = 7.984 ; free physical = 59845 ; free virtual = 82061 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 4cff2b00 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3477.234 ; gain = 0.000 ; free physical = 59750 ; free virtual = 81958 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3687.945 ; gain = 0.000 ; free physical = 58599 ; free virtual = 81295 Phase 1 Generate And Synthesize Debug Cores | Checksum: c700eb9a Time (s): cpu = 00:02:12 ; elapsed = 00:03:18 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58599 ; free virtual = 81295 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 16dc6e364 Time (s): cpu = 00:02:18 ; elapsed = 00:03:24 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58621 ; free virtual = 81316 INFO: [Opt 31-389] Phase Retarget created 121 cells and removed 367 cells INFO: [Opt 31-1021] In phase Retarget, 434 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 1 inverter(s) to 3 load pin(s). Phase 3 Constant propagation | Checksum: 1151a75aa Time (s): cpu = 00:02:19 ; elapsed = 00:03:25 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58647 ; free virtual = 81344 INFO: [Opt 31-389] Phase Constant propagation created 167 cells and removed 618 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: b4abacec Time (s): cpu = 00:02:22 ; elapsed = 00:03:28 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58592 ; free virtual = 81289 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 754 cells INFO: [Opt 31-1021] In phase Sweep, 4729 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 161f2659b Time (s): cpu = 00:02:24 ; elapsed = 00:03:30 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58485 ; free virtual = 81182 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: e00b0f66 Time (s): cpu = 00:02:24 ; elapsed = 00:03:30 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58467 ; free virtual = 81164 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 10f076b1f Time (s): cpu = 00:02:25 ; elapsed = 00:03:30 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58436 ; free virtual = 81133 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 377 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 121 | 367 | 434 | | Constant propagation | 167 | 618 | 141 | | Sweep | 2 | 754 | 4729 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 377 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 3687.945 ; gain = 0.000 ; free physical = 58371 ; free virtual = 81065 Ending Logic Optimization Task | Checksum: affdac66 Time (s): cpu = 00:02:27 ; elapsed = 00:03:33 . Memory (MB): peak = 3687.945 ; gain = 43.777 ; free physical = 58370 ; free virtual = 81064 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 24 BRAM(s) out of a total of 354 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 302 newly gated: 22 Total Ports: 708 Ending PowerOpt Patch Enables Task | Checksum: 15f1dd486 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4656.211 ; gain = 0.000 ; free physical = 57753 ; free virtual = 80447 Ending Power Optimization Task | Checksum: 15f1dd486 Time (s): cpu = 00:01:04 ; elapsed = 00:01:01 . Memory (MB): peak = 4656.211 ; gain = 968.266 ; free physical = 57929 ; free virtual = 80623 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: e66c0494 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4656.211 ; gain = 0.000 ; free physical = 58004 ; free virtual = 80698 Ending Final Cleanup Task | Checksum: e66c0494 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 4656.211 ; gain = 0.000 ; free physical = 58000 ; free virtual = 80695 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.211 ; gain = 0.000 ; free physical = 58000 ; free virtual = 80694 Ending Netlist Obfuscation Task | Checksum: e66c0494 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.211 ; gain = 0.000 ; free physical = 58000 ; free virtual = 80694 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:07 ; elapsed = 00:05:11 . Memory (MB): peak = 4656.211 ; gain = 1186.980 ; free physical = 58001 ; free virtual = 80695 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4656.211 ; gain = 0.000 ; free physical = 61080 ; free virtual = 83743 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 4656.215 ; gain = 0.004 ; free physical = 61048 ; free virtual = 83683 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 4656.215 ; gain = 0.000 ; free physical = 60261 ; free virtual = 82895 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60200 ; free virtual = 82834 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 27a606ed Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60200 ; free virtual = 82834 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60200 ; free virtual = 82834 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b0d8d8bd Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61344 ; free virtual = 83937 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 233a41e6b Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60722 ; free virtual = 83312 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 233a41e6b Time (s): cpu = 00:00:56 ; elapsed = 00:00:56 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60721 ; free virtual = 83311 Phase 1 Placer Initialization | Checksum: 233a41e6b Time (s): cpu = 00:00:56 ; elapsed = 00:00:56 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60706 ; free virtual = 83296 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2b94fd01e Time (s): cpu = 00:01:06 ; elapsed = 00:01:06 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60604 ; free virtual = 83194 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2bb4714b5 Time (s): cpu = 00:01:14 ; elapsed = 00:01:15 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 60657 ; free virtual = 83247 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 18 LUTNM shape to break, 2386 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 17, two critical 1, total 18, new lutff created 2 INFO: [Physopt 32-775] End 1 Pass. Optimized 926 nets or cells. Created 18 new cells, deleted 908 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 15 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg_3. Replicated 20 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 35 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 35 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61340 ; free virtual = 85282 INFO: [Physopt 32-76] Pass 1. Identified 10 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-232] Optimized 10 nets. Created 52 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 10 nets or cells. Created 52 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61380 ; free virtual = 85324 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-46] Identified 88 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 5 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 5 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61412 ; free virtual = 85356 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61418 ; free virtual = 85363 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 18 | 908 | 926 | 0 | 1 | 00:00:02 | | Very High Fanout | 35 | 0 | 2 | 0 | 1 | 00:00:02 | | Fanout | 52 | 0 | 10 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 5 | 0 | 5 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 110 | 908 | 943 | 0 | 10 | 00:00:06 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 222111e10 Time (s): cpu = 00:02:59 ; elapsed = 00:03:02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61744 ; free virtual = 85830 Phase 2.3 Global Placement Core | Checksum: 1cd6d6b78 Time (s): cpu = 00:03:03 ; elapsed = 00:03:07 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61539 ; free virtual = 85811 Phase 2 Global Placement | Checksum: 1cd6d6b78 Time (s): cpu = 00:03:03 ; elapsed = 00:03:07 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61566 ; free virtual = 85843 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 14813ba98 Time (s): cpu = 00:03:13 ; elapsed = 00:03:17 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61175 ; free virtual = 85876 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a0c61010 Time (s): cpu = 00:03:33 ; elapsed = 00:03:36 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61825 ; free virtual = 85909 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1df864850 Time (s): cpu = 00:03:34 ; elapsed = 00:03:38 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61816 ; free virtual = 85900 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 10d1a4f50 Time (s): cpu = 00:03:34 ; elapsed = 00:03:38 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 61824 ; free virtual = 85908 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1a997c113 Time (s): cpu = 00:03:57 ; elapsed = 00:04:01 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 62638 ; free virtual = 86059 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 261d45b4a Time (s): cpu = 00:04:30 ; elapsed = 00:04:34 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 69539 ; free virtual = 92100 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1ce6cd370 Time (s): cpu = 00:04:34 ; elapsed = 00:04:39 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 69555 ; free virtual = 92128 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 15fec6e58 Time (s): cpu = 00:04:35 ; elapsed = 00:04:40 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 69545 ; free virtual = 92124 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 21fae6540 Time (s): cpu = 00:05:18 ; elapsed = 00:05:23 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 68384 ; free virtual = 90287 Phase 3 Detail Placement | Checksum: 21fae6540 Time (s): cpu = 00:05:19 ; elapsed = 00:05:24 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 68377 ; free virtual = 90279 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: c3dd4cf5 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.402 | TNS=-40.505 | Phase 1 Physical Synthesis Initialization | Checksum: 123d91b1a Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 71532 ; free virtual = 91972 INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 14eddf909 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 71362 ; free virtual = 91801 Phase 4.1.1.1 BUFG Insertion | Checksum: c3dd4cf5 Time (s): cpu = 00:06:05 ; elapsed = 00:06:10 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 71314 ; free virtual = 91753 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.236. For the most accurate timing information please run report_timing. Time (s): cpu = 00:08:54 ; elapsed = 00:09:00 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 67312 ; free virtual = 86927 Phase 4.1 Post Commit Optimization | Checksum: e1e254cc Time (s): cpu = 00:08:55 ; elapsed = 00:09:00 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 67166 ; free virtual = 86781 Post Placement Optimization Initialization | Checksum: 1568134bd Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.236 | TNS=-8.767 | Phase 1 Physical Synthesis Initialization | Checksum: 166264216 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 58834 ; free virtual = 78450 INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/U4_SPY_RAM_CONTROL/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 19f34b9d5 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 58832 ; free virtual = 78448 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.214. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 170c722a8 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.176 | Phase 1 Physical Synthesis Initialization | Checksum: 1bdc2e72e Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 55100 ; free virtual = 74763 INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/U4_SPY_RAM_CONTROL/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 161de02a8 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 54054 ; free virtual = 73717 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.214. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: e11001f8 Time (s): cpu = 00:16:21 ; elapsed = 00:16:27 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53767 ; free virtual = 73454 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 4x4| |___________|___________________|___________________| | West| 1x1| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: e11001f8 Time (s): cpu = 00:16:22 ; elapsed = 00:16:28 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53703 ; free virtual = 73390 Phase 4.3 Placer Reporting | Checksum: e11001f8 Time (s): cpu = 00:16:23 ; elapsed = 00:16:29 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53755 ; free virtual = 73442 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53750 ; free virtual = 73437 Time (s): cpu = 00:16:23 ; elapsed = 00:16:29 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53750 ; free virtual = 73437 Phase 4 Post Placement Optimization and Clean-Up | Checksum: bf4ff088 Time (s): cpu = 00:16:24 ; elapsed = 00:16:29 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53722 ; free virtual = 73409 Ending Placer Task | Checksum: 93fa4e08 Time (s): cpu = 00:16:24 ; elapsed = 00:16:29 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53707 ; free virtual = 73394 INFO: [Common 17-83] Releasing license: Implementation 203 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:16:31 ; elapsed = 00:16:37 . Memory (MB): peak = 4656.230 ; gain = 0.016 ; free physical = 53774 ; free virtual = 73461 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 54647 ; free virtual = 74454 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 54528 ; free virtual = 74229 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.56 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 54450 ; free virtual = 74152 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.58 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 54393 ; free virtual = 74096 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56895 ; free virtual = 76581 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.176 | Phase 1 Physical Synthesis Initialization | Checksum: 159438dde Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 57044 ; free virtual = 76732 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.176 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 159438dde Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 57017 ; free virtual = 76705 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.176 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[20]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[19] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[20]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.234 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[21]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[20] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.292 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[22]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[21] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[22]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.350 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[23]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[22] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[23]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.408 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[26]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[25] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[26]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.466 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[27]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[26] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[27]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.524 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[28]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[27] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.214 | TNS=-6.582 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[29]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[29]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.213 | TNS=-6.640 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[11]. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[10] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[11]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_veto_clk320_reg_1. Did not re-place instance GOLDEN_IF.readout_packet_block/ttc_fifos/state_machine.fifo_delay[2]_i_4__0 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_veto_clk320_reg_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-5.941 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr[31]_i_5__0_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr[31]_i_5__0 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/rst_320_sig_reg_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_1__8_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr[31]_i_5__0_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.178 | TNS=-5.645 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_6__0_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_6__0 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/rst_320_sig_reg_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_1__8_comp_1. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_6__0_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-1.183 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[20]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[19] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[20]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-1.108 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[21]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[20] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-1.034 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[22]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[21] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[22]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-0.960 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[23]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[22] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[23]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-0.886 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[26]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[25] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[26]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-0.812 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[27]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[26] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[27]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-0.738 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[28]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[27] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-0.664 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[29]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[29]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-0.590 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[21]. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/state_machine.delay_slr_reg[20] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/p_1_in__0[21]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/empty. Did not re-place instance GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/empty_i INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_4__0_comp_1. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/empty. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.039 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[28]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.033 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[29]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[29] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[29]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.026 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[30]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[30] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[30]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.020 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[31]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[31]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.013 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[20]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[20] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[20]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.012 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[21]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[21] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.011 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[22]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[22] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[22]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.009 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[23]. Re-placed instance GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[23] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U2_rdout_err_cnt/GENERATE_1[0].U2_tob_fifo_error_A/temp_reg[31]_0[23]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.008 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_6__0_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_6__0 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/rst_320_sig_reg. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_2__8_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/state_machine.delay_slr[31]_i_6__0_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 | Phase 3 Critical Path Optimization | Checksum: 159438dde Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56748 ; free virtual = 76436 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 | Phase 4 Critical Path Optimization | Checksum: 159438dde Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56748 ; free virtual = 76436 Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56750 ; free virtual = 76438 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.000 | TNS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.214 | 6.176 | 0 | 0 | 29 | 0 | 2 | 00:00:07 | | Total | 0.214 | 6.176 | 0 | 0 | 29 | 0 | 3 | 00:00:07 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56833 ; free virtual = 76521 Ending Physical Synthesis Task | Checksum: 12f17ab81 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56833 ; free virtual = 76521 INFO: [Common 17-83] Releasing license: Implementation 323 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 56884 ; free virtual = 76572 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 59146 ; free virtual = 78951 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 59045 ; free virtual = 78747 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 53be1102 ConstDB: 0 ShapeSum: aba2b0c7 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 136de5494 Time (s): cpu = 00:00:54 ; elapsed = 00:00:55 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 51692 ; free virtual = 71394 Post Restoration Checksum: NetGraph: e04e80b4 NumContArr: 568fd3e0 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 136de5494 Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 51671 ; free virtual = 71373 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 136de5494 Time (s): cpu = 00:00:56 ; elapsed = 00:00:56 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 51636 ; free virtual = 71338 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 136de5494 Time (s): cpu = 00:00:56 ; elapsed = 00:00:57 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 51624 ; free virtual = 71326 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 2137b7f08 Time (s): cpu = 00:01:50 ; elapsed = 00:01:51 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 48126 ; free virtual = 67828 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.027 | TNS=0.000 | WHS=-2.797 | THS=-4470.774| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1c26283f6 Time (s): cpu = 00:02:18 ; elapsed = 00:02:20 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 46291 ; free virtual = 65993 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.027 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 26a50bd37 Time (s): cpu = 00:02:19 ; elapsed = 00:02:20 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 46258 ; free virtual = 65960 Phase 2 Router Initialization | Checksum: 14df7ea21 Time (s): cpu = 00:02:19 ; elapsed = 00:02:21 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 46254 ; free virtual = 65956 Router Utilization Summary Global Vertical Routing Utilization = 7.78877e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 76031 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 76029 Number of Partially Routed Nets = 2 Number of Node Overlaps = 1 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 14df7ea21 Time (s): cpu = 00:02:20 ; elapsed = 00:02:22 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 46335 ; free virtual = 66037 Phase 3 Initial Routing | Checksum: 1088a585b Time (s): cpu = 00:05:33 ; elapsed = 00:05:37 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52172 ; free virtual = 71874 INFO: [Route 35-580] Design has 24 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[2]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[2]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[3]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 5170 Number of Nodes with overlaps = 198 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.162 | TNS=-5.716 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 16d5cf874 Time (s): cpu = 00:07:18 ; elapsed = 00:07:23 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52585 ; free virtual = 72287 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 580 Number of Nodes with overlaps = 119 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.061 | TNS=-0.769 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 207783a46 Time (s): cpu = 00:07:54 ; elapsed = 00:07:59 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 53181 ; free virtual = 72884 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 598 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.078 | TNS=-0.627 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1a91b912e Time (s): cpu = 00:08:20 ; elapsed = 00:08:26 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52665 ; free virtual = 72368 Phase 4 Rip-up And Reroute | Checksum: 1a91b912e Time (s): cpu = 00:08:21 ; elapsed = 00:08:27 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52665 ; free virtual = 72367 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 16abf18b1 Time (s): cpu = 00:08:31 ; elapsed = 00:08:37 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52172 ; free virtual = 71874 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.040 | TNS=-0.040 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: b021365f Time (s): cpu = 00:08:32 ; elapsed = 00:08:39 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52169 ; free virtual = 71872 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: b021365f Time (s): cpu = 00:08:33 ; elapsed = 00:08:39 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52169 ; free virtual = 71872 Phase 5 Delay and Skew Optimization | Checksum: b021365f Time (s): cpu = 00:08:33 ; elapsed = 00:08:39 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52169 ; free virtual = 71872 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1098b87cd Time (s): cpu = 00:08:46 ; elapsed = 00:08:52 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52180 ; free virtual = 71882 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.033 | TNS=-0.033 | WHS=-1.316 | THS=-17.565| Phase 6.1 Hold Fix Iter | Checksum: 17d90c7af Time (s): cpu = 00:08:46 ; elapsed = 00:08:53 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52177 ; free virtual = 71879 Phase 6 Post Hold Fix | Checksum: 20ceee568 Time (s): cpu = 00:08:47 ; elapsed = 00:08:53 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52205 ; free virtual = 71908 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 21823d3c1 Time (s): cpu = 00:09:03 ; elapsed = 00:09:09 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52176 ; free virtual = 71879 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.033 | TNS=-0.033 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 21823d3c1 Time (s): cpu = 00:09:04 ; elapsed = 00:09:10 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52177 ; free virtual = 71880 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 6.27968 % Global Horizontal Routing Utilization = 6.72444 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 88.2883%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X49Y81 -> INT_R_X49Y81 South Dir 1x1 Area, Max Cong = 73.8739%, No Congested Regions. East Dir 1x1 Area, Max Cong = 77.9412%, No Congested Regions. West Dir 1x1 Area, Max Cong = 82.3529%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 8 Route finalize | Checksum: 21823d3c1 Time (s): cpu = 00:09:04 ; elapsed = 00:09:11 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52175 ; free virtual = 71878 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 21823d3c1 Time (s): cpu = 00:09:05 ; elapsed = 00:09:11 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52201 ; free virtual = 71904 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 1ce214c18 Time (s): cpu = 00:09:14 ; elapsed = 00:09:20 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52172 ; free virtual = 71875 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4656.230 ; gain = 0.000 ; free physical = 52157 ; free virtual = 71859 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.006. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: fba92c9a Time (s): cpu = 00:01:42 ; elapsed = 00:01:43 . Memory (MB): peak = 4674.727 ; gain = 18.496 ; free physical = 52138 ; free virtual = 71841 Phase 11 Incr Placement Change | Checksum: 1ce214c18 Time (s): cpu = 00:10:58 ; elapsed = 00:11:05 . Memory (MB): peak = 4676.801 ; gain = 20.570 ; free physical = 52167 ; free virtual = 71869 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: 19ef73f25 Time (s): cpu = 00:11:11 ; elapsed = 00:11:18 . Memory (MB): peak = 4676.801 ; gain = 20.570 ; free physical = 52134 ; free virtual = 71836 Post Restoration Checksum: NetGraph: e8212ad8 NumContArr: f7f135cd Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: 1e01260a5 Time (s): cpu = 00:11:15 ; elapsed = 00:11:22 . Memory (MB): peak = 4676.801 ; gain = 20.570 ; free physical = 52091 ; free virtual = 71794 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: 1e01260a5 Time (s): cpu = 00:11:15 ; elapsed = 00:11:22 . Memory (MB): peak = 4676.801 ; gain = 20.570 ; free physical = 52080 ; free virtual = 71783 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: c986fbd9 Time (s): cpu = 00:11:16 ; elapsed = 00:11:23 . Memory (MB): peak = 4676.801 ; gain = 20.570 ; free physical = 52080 ; free virtual = 71783 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: 122e871c3 Time (s): cpu = 00:12:10 ; elapsed = 00:12:17 . Memory (MB): peak = 4738.020 ; gain = 81.789 ; free physical = 52036 ; free virtual = 71739 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.009 | TNS=-0.019 | WHS=-2.797 | THS=-4460.148| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 14b005122 Time (s): cpu = 00:12:38 ; elapsed = 00:12:45 . Memory (MB): peak = 4738.020 ; gain = 81.789 ; free physical = 52022 ; free virtual = 71725 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.009 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: 7dbf006c Time (s): cpu = 00:12:39 ; elapsed = 00:12:46 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52021 ; free virtual = 71724 Phase 13 Router Initialization | Checksum: 12800f5af Time (s): cpu = 00:12:39 ; elapsed = 00:12:47 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52024 ; free virtual = 71727 Router Utilization Summary Global Vertical Routing Utilization = 6.27363 % Global Horizontal Routing Utilization = 6.72194 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 102 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 17 Number of Partially Routed Nets = 85 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14.1 Global Routing Phase 14.1 Global Routing | Checksum: 12800f5af Time (s): cpu = 00:12:41 ; elapsed = 00:12:48 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52024 ; free virtual = 71727 Phase 14 Initial Routing | Checksum: 124ea3516 Time (s): cpu = 00:12:43 ; elapsed = 00:12:50 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52014 ; free virtual = 71717 INFO: [Route 35-580] Design has 40 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Reg_enable_reg/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[1]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[0]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 51 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.011 | TNS=-0.030 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: fe5590a6 Time (s): cpu = 00:13:20 ; elapsed = 00:13:28 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52019 ; free virtual = 71722 Phase 15.2 Global Iteration 1 Number of Nodes with overlaps = 803 Number of Nodes with overlaps = 123 Number of Nodes with overlaps = 58 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.084 | TNS=-1.108 | WHS=N/A | THS=N/A | Phase 15.2 Global Iteration 1 | Checksum: 11584d260 Time (s): cpu = 00:13:46 ; elapsed = 00:13:55 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52014 ; free virtual = 71717 Phase 15 Rip-up And Reroute | Checksum: 11584d260 Time (s): cpu = 00:13:46 ; elapsed = 00:13:55 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52050 ; free virtual = 71753 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: daa18f8c Time (s): cpu = 00:13:56 ; elapsed = 00:14:05 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52034 ; free virtual = 71737 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.004 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 16.1 Delay CleanUp | Checksum: 3389c060 Time (s): cpu = 00:13:57 ; elapsed = 00:14:06 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52013 ; free virtual = 71716 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: 3389c060 Time (s): cpu = 00:13:57 ; elapsed = 00:14:06 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52013 ; free virtual = 71716 Phase 16 Delay and Skew Optimization | Checksum: 3389c060 Time (s): cpu = 00:13:57 ; elapsed = 00:14:06 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 51999 ; free virtual = 71702 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 6726ff73 Time (s): cpu = 00:14:09 ; elapsed = 00:14:18 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52022 ; free virtual = 71725 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.004 | TNS=0.000 | WHS=-0.153 | THS=-3.250 | Phase 17.1 Hold Fix Iter | Checksum: 5d49733e Time (s): cpu = 00:14:09 ; elapsed = 00:14:18 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52022 ; free virtual = 71725 Phase 17 Post Hold Fix | Checksum: acb60e7d Time (s): cpu = 00:14:10 ; elapsed = 00:14:18 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52022 ; free virtual = 71725 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 6ab7b74d Time (s): cpu = 00:14:25 ; elapsed = 00:14:34 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52023 ; free virtual = 71726 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.004 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 6ab7b74d Time (s): cpu = 00:14:26 ; elapsed = 00:14:34 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52024 ; free virtual = 71727 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 6.28227 % Global Horizontal Routing Utilization = 6.72709 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 6ab7b74d Time (s): cpu = 00:14:27 ; elapsed = 00:14:35 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52022 ; free virtual = 71725 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 6ab7b74d Time (s): cpu = 00:14:27 ; elapsed = 00:14:36 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52021 ; free virtual = 71724 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: 1275b2c6f Time (s): cpu = 00:14:34 ; elapsed = 00:14:43 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 52013 ; free virtual = 71716 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.005 | TNS=0.000 | WHS=0.051 | THS=0.000 | Phase 22 Post Router Timing | Checksum: 126f2066f Time (s): cpu = 00:15:17 ; elapsed = 00:15:26 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 51346 ; free virtual = 71764 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+--------+--------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 1 | -0.033 | -0.033 | -1.316 | - | Pass | 00:08:25 | | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 2 | 0.004 | 0.000 | -0.153 | - | Pass | 00:03:22 | x | +------+--------+--------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:15:17 ; elapsed = 00:15:26 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 51568 ; free virtual = 71987 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 356 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:15:59 ; elapsed = 00:16:09 . Memory (MB): peak = 4754.020 ; gain = 97.789 ; free physical = 51568 ; free virtual = 71987 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetVerFromSHA-0] No tag contains DDC0595, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 42B38CE, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains 161BCE0, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains 161BCE0E, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains ddc0595, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:Msg-0] Git describe set to: v1.3.3-hogddc0595 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetVerFromSHA-0] No tag contains DDC0595, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 42B38CE, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains 161BCE0, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains 161BCE0E, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:Msg-0] The git SHA value ddc0595 will be set as bitstream USERID. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetVerFromSHA-0] No tag contains DDC0595, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 42B38CE, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains 161BCE0, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains 161BCE0E, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:GetVerFromSHA-0] No tag contains ddc0595, will use most recent tag v1.3.2. As this is an official tag, patch will be incremented to 3. INFO: [Hog:Msg-0] Git describe set to: v1.3.3-hogddc0595 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.3.3-hogddc0595... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.