<!-- Top level of data path structure  -->
<!-- version: 1.3.0     sha: 6DA16CC -->

<node id="efex_cntrl_data_path" fwinfo="endpoint;width=16">

  <node id="update_counting_registers"    address="0x0" permission="rw" fwinfo="endpoint;width=0" description="Control Register to freeze the FIFO status counters for IPBus to read" >
    <node id="update_counter_reg"           mask="0x00000001" description="Update all registers holdong counter values" />
  </node>

  <node id="busy_fifo_control" address="0x20" description="BUSY FIFO threshold registers"  fwinfo="endpoint;width=3">
   <node id="tob_fifo_prog_full_thresh_assert"		address="0x0" permission="rw" description="tob_fifo_fill_level BUSY assertion threshold"/>
   <node id="tob_fifo_prog_full_thresh_negate"		address="0x1" permission="rw" description="tob_fifo_fill_level BUSY negation threshold"/>
   <node id="raw_fifo_prog_full_thresh_assert"		address="0x2" permission="rw" description="raw_fifo_fill_level BUSY assertion threshold"/>
   <node id="raw_fifo_prog_full_thresh_negate"		address="0x3" permission="rw" description="raw_fifo_fill_level BUSY negation threshold"/>
  </node>

  <node id="xoff_fifo_control" address="0x40" description="XOFF FIFO threshold registers"  fwinfo="endpoint;width=3">
   <node id="tob_fifo_xoff_thresh_assert"		address="0x0" permission="rw" description="tob_fifo_fill_level XOFF assertion threshold"/>
   <node id="tob_fifo_xoff_thresh_negate"		address="0x1" permission="rw" description="tob_fifo_fill_level XOFF negation threshold"/>
   <node id="merged_fifo_xoff_thresh_assert"	address="0x2" permission="rw" description="merged_tob_fifo_fill_level XOFF assertion threshold"/>
   <node id="merged_fifo_xoff_thresh_negate"	address="0x3" permission="rw" description="merged_tob_fifo_fill_level XOFF negation threshold"/>
   <node id="raw_fifo_xoff_thresh_assert"		address="0x4" permission="rw" description="raw_fifo_fill_level XOFF assertion threshold"/>
   <node id="raw_fifo_xoff_thresh_negate"		address="0x5" permission="rw" description="raw_fifo_fill_level XOFF negation threshold"/>
   <node id="dbg_fifo_xoff_thresh_assert"		address="0x6" permission="rw" description="debug_fifo_fill_level XOFF assertion threshold"/>
   <node id="dbg_fifo_xoff_thresh_negate"		address="0x7" permission="rw" description="debug_fifo_fill_level XOFF negation threshold"/>
  </node>

  <node id="tob_fifo_status_a" address="0x60" description="TOB FIFO status block A"  fwinfo="endpoint;width=5">
   <node id="tob_fifo_0_fill_level_a"	address="0x0" permission="r" description="TOB fifo fill level for P0"/>
   <node id="tob_fifo_1_fill_level_a"	address="0x1" permission="r" description="TOB fifo fill level for P1"/>
   <node id="tob_fifo_2_fill_level_a"	address="0x2" permission="r" description="TOB fifo fill level for P2"/>
   <node id="tob_fifo_3_fill_level_a"	address="0x3" permission="r" description="TOB fifo fill level for P3"/>
   <node id="tob_packet_count_0_a"		address="0x4" permission="r" description="TOB fifo packet count for P0"/>
   <node id="tob_packet_count_1_a"		address="0x5" permission="r" description="TOB fifo packet count for P1"/>
   <node id="tob_packet_count_2_a"		address="0x6" permission="r" description="TOB fifo packet count for P2"/>
   <node id="tob_packet_count_3_a"		address="0x7" permission="r" description="TOB fifo packet count for P3"/>
   <node id="tob_fifo_0_error_a"		address="0x8" permission="r" description="TOB fifo error count for P0"/>
   <node id="tob_fifo_1_error_a"		address="0x9" permission="r" description="TOB fifo error count for P1"/>
   <node id="tob_fifo_2_error_a"		address="0xA" permission="r" description="TOB fifo error count for P2"/>
   <node id="tob_fifo_3_error_a"		address="0xB" permission="r" description="TOB fifo error count for P3"/>
  </node>

  <node id="tob_fifo_status_b" address="0x80" description="TOB FIFO status block B"  fwinfo="endpoint;width=5">
   <node id="tob_fifo_0_fill_level_b"	address="0x0" permission="r" description="TOB fifo fill level for P0"/>
   <node id="tob_fifo_1_fill_level_b"	address="0x1" permission="r" description="TOB fifo fill level for P1"/>
   <node id="tob_fifo_2_fill_level_b"	address="0x2" permission="r" description="TOB fifo fill level for P2"/>
   <node id="tob_fifo_3_fill_level_b"	address="0x3" permission="r" description="TOB fifo fill level for P3"/>
   <node id="tob_packet_count_0_b"		address="0x4" permission="r" description="TOB fifo packet count for P0"/>
   <node id="tob_packet_count_1_b"		address="0x5" permission="r" description="TOB fifo packet count for P1"/>
   <node id="tob_packet_count_2_b"		address="0x6" permission="r" description="TOB fifo packet count for P2"/>
   <node id="tob_packet_count_3_b"		address="0x7" permission="r" description="TOB fifo packet count for P3"/>
   <node id="tob_fifo_0_error_b"		address="0x8" permission="r" description="TOB fifo error count for P0"/>
   <node id="tob_fifo_1_error_b"		address="0x9" permission="r" description="TOB fifo error count for P1"/>
   <node id="tob_fifo_2_error_b"		address="0xA" permission="r" description="TOB fifo error count for P2"/>
   <node id="tob_fifo_3_error_b"		address="0xB" permission="r" description="TOB fifo error count for P3"/>
  </node>

  <node id="merged_fifo_status_a" address="0xA0" description="Merged FIFO status block A"  fwinfo="endpoint;width=5">
   <node id="merged_fifo_0_fill_level_a" address="0x0" permission="r" description="merged fifo 0 fill level"/>
   <node id="merged_fifo_1_fill_level_a" address="0x1" permission="r" description="merged fifo 1 fill level"/>
   <node id="merged_packet_count_0_a"	 address="0x2" permission="r" description="merged fifo 0 packet count"/>
   <node id="merged_packet_count_1_a"	 address="0x3" permission="r" description="merged fifo 1 packet count"/>
   <node id="merged_fifo_0_error_a"		 address="0x4" permission="r" description="merged fifo 0 error count"/>
   <node id="merged_fifo_1_error_a"		 address="0x5" permission="r" description="merged fifo 1 error count"/>
   <node id="l1a_cnt_merger_a"			 address="0x6" permission="r" description="L1A processed through merger B count"/>
   <node id="last_l1id_merger_a"		 address="0x7" permission="r" description="Last L1ID processed through merger A"/>
  </node>

  <node id="merged_fifo_status_b" address="0xC0" description="Merged FIFO status block B"  fwinfo="endpoint;width=5">
   <node id="merged_fifo_0_fill_level_b" address="0x0" permission="r" description="merged fifo 0 fill level"/>
   <node id="merged_fifo_1_fill_level_b" address="0x1" permission="r" description="merged fifo 1 fill level"/>
   <node id="merged_packet_count_0_b"	 address="0x2" permission="r" description="merged fifo 0 packet count"/>
   <node id="merged_packet_count_1_b"	 address="0x3" permission="r" description="merged fifo 1 packet count"/>
   <node id="merged_fifo_0_error_b"		 address="0x4" permission="r" description="merged fifo 0 error count"/>
   <node id="merged_fifo_1_error_b"		 address="0x5" permission="r" description="merged fifo 1 error count"/>
   <node id="l1a_cnt_merger_b"			 address="0x6" permission="r" description="L1A processed through merger B count"/>
   <node id="last_l1id_merger_b"		 address="0x7" permission="r" description="Last L1ID processed through merger B"/>
  </node>

  <node id="raw_fifo_status" address="0xE0" description="Raw FIFO status block"  fwinfo="endpoint;width=5">
   <node id="raw_fifo_0_fill_level"	address="0x0" permission="r" description="RAW fifo fill level for P0"/>
   <node id="raw_fifo_1_fill_level"	address="0x1" permission="r" description="RAW fifo fill level for P1"/>
   <node id="raw_fifo_2_fill_level"	address="0x2" permission="r" description="RAW fifo fill level for P2"/>
   <node id="raw_fifo_3_fill_level"	address="0x3" permission="r" description="RAW fifo fill level for P3"/>
   <node id="raw_packet_count_0"	address="0x4" permission="r" description="RAW fifo packet count for P0"/>
   <node id="raw_packet_count_1"	address="0x5" permission="r" description="RAW fifo packet count for P1"/>
   <node id="raw_packet_count_2"	address="0x6" permission="r" description="RAW fifo packet count for P2"/>
   <node id="raw_packet_count_3"	address="0x7" permission="r" description="RAW fifo packet count for P3"/>
   <node id="raw_fifo_0_error"		address="0x8" permission="r" description="RAW fifo error count for P0"/>
   <node id="raw_fifo_1_error"		address="0x9" permission="r" description="RAW fifo error count for P1"/>
   <node id="raw_fifo_2_error"		address="0xA" permission="r" description="RAW fifo error count for P2"/>
   <node id="raw_fifo_3_error"		address="0xB" permission="r" description="RAW fifo error count for P3"/>
  </node>

  <node id="tob_fifo_busy_xoff_cnt_a" address="0x100" description="TOB FIFOs BUSY and XOFF Bus A counters"  fwinfo="endpoint;width=5">
   <node id="tob_busy_cnt_a_32b_p0"	address="0x0" permission="r" description="TOB fifo BUSY Bus A count for P0"/>
   <node id="tob_busy_cnt_a_32b_p1"	address="0x1" permission="r" description="TOB fifo BUSY Bus A count for P1"/>
   <node id="tob_busy_cnt_a_32b_p2"	address="0x2" permission="r" description="TOB fifo BUSY Bus A count for P2"/>
   <node id="tob_busy_cnt_a_32b_p3"	address="0x3" permission="r" description="TOB fifo BUSY Bus A count for P3"/>
   <node id="tob_xoff_cnt_a_32b_p0"	address="0x4" permission="r" description="TOB fifo XOFF Bus A count for P0"/>
   <node id="tob_xoff_cnt_a_32b_p1"	address="0x5" permission="r" description="TOB fifo XOFF Bus A count for P1"/>
   <node id="tob_xoff_cnt_a_32b_p2"	address="0x6" permission="r" description="TOB fifo XOFF Bus A count for P2"/>
   <node id="tob_xoff_cnt_a_32b_p3"	address="0x7" permission="r" description="TOB fifo XOFF Bus A count for P3"/>
  </node>

  <node id="tob_fifo_busy_xoff_cnt_b" address="0x120" description="TOB FIFOs BUSY and XOFF Bus B counters"  fwinfo="endpoint;width=5">
   <node id="tob_busy_cnt_b_32b_p0"	address="0x0" permission="r" description="TOB fifo BUSY Bus B count for P0"/>
   <node id="tob_busy_cnt_b_32b_p1"	address="0x1" permission="r" description="TOB fifo BUSY Bus B count for P1"/>
   <node id="tob_busy_cnt_b_32b_p2"	address="0x2" permission="r" description="TOB fifo BUSY Bus B count for P2"/>
   <node id="tob_busy_cnt_b_32b_p3"	address="0x3" permission="r" description="TOB fifo BUSY Bus B count for P3"/>
   <node id="tob_xoff_cnt_b_32b_p0"	address="0x4" permission="r" description="TOB fifo XOFF Bus B count for P0"/>
   <node id="tob_xoff_cnt_b_32b_p1"	address="0x5" permission="r" description="TOB fifo XOFF Bus B count for P1"/>
   <node id="tob_xoff_cnt_b_32b_p2"	address="0x6" permission="r" description="TOB fifo XOFF Bus B count for P2"/>
   <node id="tob_xoff_cnt_b_32b_p3"	address="0x7" permission="r" description="TOB fifo XOFF Bus B count for P3"/>
  </node>

  <node id="merged_fifo_busy_xoff_cnt" address="0x140" description="Merged FIFOs XOFF counters"  fwinfo="endpoint;width=5">
   <node id="merged_xoff_cnt_a_tob"	address="0x0" permission="r" description="Merged fifo block A XOFF count TOB"/>
   <node id="merged_xoff_cnt_a_debug"	address="0x1" permission="r" description="Merged fifo block A XOFF count Debug"/>
   <node id="merged_xoff_cnt_b_tob"	address="0x2" permission="r" description="Merged fifo block B XOFF count TOB"/>
   <node id="merged_xoff_cnt_b_debug"	address="0x3" permission="r" description="Merged fifo block B XOFF count Debug"/>
  </node>

  <node id="raw_fifo_busy_xoff_cnt" address="0x160" description="RAW FIFOs BUSY and XOFF counters"  fwinfo="endpoint;width=5">
   <node id="raw_busy_cnt_32b_p0"	address="0x0" permission="r" description="RAW fifo BUSY count for P0"/>
   <node id="raw_busy_cnt_32b_p1"	address="0x1" permission="r" description="RAW fifo BUSY count for P1"/>
   <node id="raw_busy_cnt_32b_p2"	address="0x2" permission="r" description="RAW fifo BUSY count for P2"/>
   <node id="raw_busy_cnt_32b_p3"	address="0x3" permission="r" description="RAW fifo BUSY count for P3"/>
   <node id="raw_xoff_cnt_32b_p0"	address="0x4" permission="r" description="RAW fifo XOFF count for P0"/>
   <node id="raw_xoff_cnt_32b_p1"	address="0x5" permission="r" description="RAW fifo XOFF count for P1"/>
   <node id="raw_xoff_cnt_32b_p2"	address="0x6" permission="r" description="RAW fifo XOFF count for P2"/>
   <node id="raw_xoff_cnt_32b_p3"	address="0x7" permission="r" description="RAW fifo XOFF count for P3"/>
  </node>

  <node id="tob_merging_cnt_a" address="0x180" description="TOB merging counts per Processor FPGA Bus A"  fwinfo="endpoint;width=5">
   <node id="tob_packet_merged_cnt_a_p0"	address="0x0" permission="r" description="TOB packet merged count for P0"/>
   <node id="tob_packet_merged_cnt_a_p1"	address="0x1" permission="r" description="TOB packet merged count for P1"/>
   <node id="tob_packet_merged_cnt_a_p2"	address="0x2" permission="r" description="TOB packet merged count for P2"/>
   <node id="tob_packet_merged_cnt_a_p3"	address="0x3" permission="r" description="TOB packet merged count for P3"/>
   <node id="tob_packet_missing_cnt_a_p0"	address="0x4" permission="r" description="TOB packet missing count for P0"/>
   <node id="tob_packet_missing_cnt_a_p1"	address="0x5" permission="r" description="TOB packet missing count for P1"/>
   <node id="tob_packet_missing_cnt_a_p2"	address="0x6" permission="r" description="TOB packet missing count for P2"/>
   <node id="tob_packet_missing_cnt_a_p3"	address="0x7" permission="r" description="TOB packet missing count for P3"/>
   <node id="debug_packet_created_cnt_a_p0"	address="0x8" permission="r" description="Debug packet created count for P0"/>
   <node id="debug_packet_created_cnt_a_p1"	address="0x9" permission="r" description="Debug packet created count for P1"/>
   <node id="debug_packet_created_cnt_a_p2"	address="0xA" permission="r" description="Debug packet created count for P2"/>
   <node id="debug_packet_created_cnt_a_p3"	address="0xB" permission="r" description="Debug packet created count for P3"/>
  </node>

  <node id="tob_merging_cnt_b" address="0x1A0" description="TOB merging counts per Processor FPGA Bus B"  fwinfo="endpoint;width=5">
   <node id="tob_packet_merged_cnt_b_p0"	address="0x0" permission="r" description="TOB packet merged count for P0"/>
   <node id="tob_packet_merged_cnt_b_p1"	address="0x1" permission="r" description="TOB packet merged count for P1"/>
   <node id="tob_packet_merged_cnt_b_p2"	address="0x2" permission="r" description="TOB packet merged count for P2"/>
   <node id="tob_packet_merged_cnt_b_p3"	address="0x3" permission="r" description="TOB packet merged count for P3"/>
   <node id="tob_packet_missing_cnt_b_p0"	address="0x4" permission="r" description="TOB packet missing count for P0"/>
   <node id="tob_packet_missing_cnt_b_p1"	address="0x5" permission="r" description="TOB packet missing count for P1"/>
   <node id="tob_packet_missing_cnt_b_p2"	address="0x6" permission="r" description="TOB packet missing count for P2"/>
   <node id="tob_packet_missing_cnt_b_p3"	address="0x7" permission="r" description="TOB packet missing count for P3"/>
   <node id="debug_packet_created_cnt_b_p0"	address="0x8" permission="r" description="Debug packet created count for P0"/>
   <node id="debug_packet_created_cnt_b_p1"	address="0x9" permission="r" description="Debug packet created count for P1"/>
   <node id="debug_packet_created_cnt_b_p2"	address="0xA" permission="r" description="Debug packet created count for P2"/>
   <node id="debug_packet_created_cnt_b_p3"	address="0xB" permission="r" description="Debug packet created count for P3"/>
  </node>

  <node id="spy_ram_control_reg"	address="0x8000" fwinfo="endpoint;width=1" description="Control Registers for Spy RAMs" >
   <node id="reset_write_address"	address="0x0" permission="rw" description="Reset Write Address Pointer for each spy RAM" >
    <node id="tob_mgt_spy"	mask="0x0000000F"  description="TOB MGT P3 downto P0" />
    <node id="raw_mgt_spy"	mask="0x000000F0"  description="Raw MGT P3 downto P0" />
    <node id="aurora_spy"	mask="0x00000300"  description="Aurora channel 1 downto 0" />
    <node id="rst_err_cntrs"	mask="0x00000400"  description="Reset All Memory Error Counters" />
    <node id="packet_err_cntrs_rst"	mask="0x00000800"  description="Reset All Packet Error Counters" />
   </node>
   <node id="wraparound_enable"	address="0x1" permission="rw" description="Enable wraparound of Write Address Pointer for each spy RAM" >
    <node id="tob_mgt_spy"	mask="0x0000000F"  description="TOB MGT P3 downto P0" />
    <node id="raw_mgt_spy"	mask="0x000000F0"  description="Raw MGT P3 downto P0" />
    <node id="aurora_spy"	mask="0x00000300"  description="Aurora channel 1 downto 0" />
   </node>
  </node>

 <node id="tob_mgt_p0_spy" address="0x10000"  mode="block" size="0x800"  description="Processor 0 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_mgt_p1_spy" address="0x20000"  mode="block" size="0x800"  description="Processor 1 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_mgt_p2_spy" address="0x30000"  mode="block" size="0x800"  description="Processor 2 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_mgt_p3_spy" address="0x40000"  mode="block" size="0x800"  description="Processor 3 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p0_spy" address="0x50000"  mode="block" size="0x800"  description="Processor 0 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p1_spy" address="0x60000"  mode="block" size="0x800"  description="Processor 1 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p2_spy" address="0x70000"  mode="block" size="0x800"  description="Processor 2 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p3_spy" address="0x80000"  mode="block" size="0x800"  description="Processor 3 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="aurora_channel0_spy" address="0x90000"  mode="block" size="0x2000"  description="Aurora Channel 0 Spy RAM" fwinfo="endpoint;width=13" permission="rw"/>
 <node id="aurora_channel1_spy" address="0xA0000"  mode="block" size="0x2000"  description="Aurora Channel 1 Spy RAM" fwinfo="endpoint;width=13" permission="rw"/>

</node>
