## Repository info - Merge request number: 293 - Branch name: feature-modify-busy-assertion ## MR Description add ILA to monitor double word detection. ## Changelog - Fix L1ID distribution - add 35 bit ILA for MGT capture ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 546a001 | 1.3.3 | | Constraints | 161bce0e | 1.3.3 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | ede539a | 6.19.9 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** TOB_rdout_lib | 03a3911 | 1.3.3 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | ddc0595 | 1.3.3 | | Constraints | 161bce0e | 1.3.3 | | IPbus XML | 6da16cc | 1.3.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | ede539a | 6.19.9 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 42b38ce | 1.3.3 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | ec7a448 | 1.3.3 | | Constraints | ec7a448f | 1.3.3 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | ede539a | 6.19.9 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** TOB_rdout_lib | 03a3911 | 1.3.3 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 546a001 | 1.3.3 | | Constraints | 161bce0e | 1.3.3 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | ede539a | 6.19.9 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** TOB_rdout_lib | 03a3911 | 1.3.3 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 546a001 | 1.3.3 | | Constraints | 161bce0e | 1.3.3 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | ede539a | 6.19.9 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** TOB_rdout_lib | 03a3911 | 1.3.3 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.025374 | | TNS: | 0.000000 | | WHS: | 0.035378 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.004552 | | TNS: | 0.000000 | | WHS: | 0.050998 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.003340 | | TNS: | 0.000000 | | WHS: | 0.016345 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.010441 | | TNS: | 0.000000 | | WHS: | 0.020237 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.039632 | | TNS: | 0.000000 | | WHS: | 0.018184 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182112 | 0 | 346400 | 52.57 | | Slice Registers | 255324 | 0 | 692800 | 36.85 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191340 | 0 | 346400 | 55.24 | | Slice Registers | 282358 | 0 | 692800 | 40.76 | | Block RAM Tile | 739 | 0 | 1180 | 62.63 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 22940 | 0 | 204000 | 11.25 | | Slice Registers | 32804 | 0 | 408000 | 8.04 | | Block RAM Tile | 318 | 0 | 750 | 42.40 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 378 | 0 | 600 | 63.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 30975 | 0 | 204000 | 15.18 | | Slice Registers | 51601 | 0 | 408000 | 12.65 | | Block RAM Tile | 359.5 | 0 | 750 | 47.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 346 | 334 | 600 | 57.67 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186220 | 0 | 346400 | 53.76 | | Slice Registers | 266896 | 0 | 692800 | 38.52 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194293 | 0 | 346400 | 56.09 | | Slice Registers | 293831 | 0 | 692800 | 42.41 | | Block RAM Tile | 750 | 0 | 1180 | 63.56 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182088 | 0 | 346400 | 52.57 | | Slice Registers | 255291 | 0 | 692800 | 36.85 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191452 | 0 | 346400 | 55.27 | | Slice Registers | 282578 | 0 | 692800 | 40.79 | | Block RAM Tile | 739 | 0 | 1180 | 62.63 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186150 | 0 | 346400 | 53.74 | | Slice Registers | 266884 | 0 | 692800 | 38.52 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194682 | 0 | 346400 | 56.20 | | Slice Registers | 295553 | 0 | 692800 | 42.66 | | Block RAM Tile | 750 | 0 | 1180 | 63.56 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 |