## Repository info - Merge request number: 294 - Branch name: feature/new_control_fpga_registers ## MR Description MINOR_VERSION: major overhaul of Control FPGA registers ## Changelog - Implement prescaled Input Data readout - increase TTC FIFO depth to be consistent with TOB FIFO depth... - fix corrective trailer length - fix corrective trailer length ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 43a1b82 | 1.4.0 | | Constraints | 161bce0e | 1.3.3 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | fcc3e88 | 6.48.0 | | **Lib:** TOB_rdout_lib | 32b3bd4 | 1.4.0 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 43a1b82 | 1.4.0 | | Constraints | 9478ee15 | 1.4.0 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | fcc3e88 | 6.48.0 | | **Lib:** TOB_rdout_lib | 32b3bd4 | 1.4.0 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 93cc57b | 1.4.0 | | Constraints | 93cc57bf | 1.4.0 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | fcc3e88 | 6.48.0 | | **Lib:** TOB_rdout_lib | 32b3bd4 | 1.4.0 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 17d0c64 | 1.4.0 | | Constraints | a09d51da | 1.4.0 | | IPbus XML | 4bedca7 | 1.4.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | fcc3e88 | 6.48.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 17d0c64 | 1.4.0 | ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 43a1b82 | 1.4.0 | | Constraints | 161bce0e | 1.3.3 | | IPbus XML | 546a001 | 1.3.3 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | fcc3e88 | 6.48.0 | | **Lib:** algolib | 546a001 | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** TOB_rdout_lib | 32b3bd4 | 1.4.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.070401 | | TNS: | 0.000000 | | WHS: | 0.012037 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.029688 | | TNS: | 0.000000 | | WHS: | 0.023033 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.067348 | | TNS: | 0.000000 | | WHS: | 0.015785 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.083851 | | TNS: | 0.000000 | | WHS: | 0.051879 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.056625 | | TNS: | 0.000000 | | WHS: | 0.015349 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186185 | 0 | 346400 | 53.75 | | Slice Registers | 267020 | 0 | 692800 | 38.54 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194643 | 0 | 346400 | 56.19 | | Slice Registers | 295782 | 0 | 692800 | 42.69 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182115 | 0 | 346400 | 52.57 | | Slice Registers | 255425 | 0 | 692800 | 36.87 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 190896 | 0 | 346400 | 55.11 | | Slice Registers | 282912 | 0 | 692800 | 40.84 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186242 | 0 | 346400 | 53.77 | | Slice Registers | 267030 | 0 | 692800 | 38.54 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 195021 | 0 | 346400 | 56.30 | | Slice Registers | 295268 | 0 | 692800 | 42.62 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 28490 | 0 | 204000 | 13.97 | | Slice Registers | 47874 | 0 | 408000 | 11.73 | | Block RAM Tile | 322 | 0 | 750 | 42.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 378 | 0 | 600 | 63.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 36503 | 0 | 204000 | 17.89 | | Slice Registers | 66718 | 0 | 408000 | 16.35 | | Block RAM Tile | 363.5 | 0 | 750 | 48.47 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 346 | 334 | 600 | 57.67 | ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182149 | 0 | 346400 | 52.58 | | Slice Registers | 255464 | 0 | 692800 | 36.87 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191277 | 0 | 346400 | 55.22 | | Slice Registers | 283288 | 0 | 692800 | 40.89 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 |