## Repository info - Merge request number: 297 - Branch name: minor_version/2023v2 ## MR Description Implement BUSY and xoff assert_count registers and more robust periodic register updates, rearrange Control FPGA ILAs Proper CDC for packet count in Processor R/O output FIFOs ## Changelog - use Hog2023.1-2 - adapt xmls to include new nopise thresholds - Change Input stage to include 6 thresholds per layer ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | b9225df | 1.5.0 | | Constraints | b9225dff | 1.5.0 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 057eae3 | 1.5.0 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | b22c249 | 1.5.0 | | Constraints | 9478ee15 | 1.4.0 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 057eae3 | 1.5.0 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 04c7977 | 1.5.0 | | Constraints | 04c79778 | 1.5.0 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 057eae3 | 1.5.0 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 2d7eb41 | 1.5.0 | | Constraints | a09d51da | 1.4.0 | | IPbus XML | 035a149 | 1.5.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** infrastructure_lib | 2d7eb41 | 1.5.0 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 04c7977 | 1.5.0 | | Constraints | 04c79778 | 1.5.0 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 057eae3 | 1.5.0 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.076838 | | TNS: | 0.000000 | | WHS: | 0.009029 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.005856 | | TNS: | 0.000000 | | WHS: | 0.006304 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.025892 | | TNS: | 0.000000 | | WHS: | 0.026972 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.069103 | | TNS: | 0.000000 | | WHS: | 0.053222 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.008406 | | TNS: | 0.000000 | | WHS: | 0.010965 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182073 | 0 | 346400 | 52.56 | | Slice Registers | 256456 | 0 | 692800 | 37.02 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191790 | 0 | 346400 | 55.37 | | Slice Registers | 283671 | 0 | 692800 | 40.95 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182079 | 0 | 346400 | 52.56 | | Slice Registers | 256456 | 0 | 692800 | 37.02 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 190926 | 0 | 346400 | 55.12 | | Slice Registers | 283579 | 0 | 692800 | 40.93 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186106 | 0 | 346400 | 53.73 | | Slice Registers | 268016 | 0 | 692800 | 38.69 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 195132 | 0 | 346400 | 56.33 | | Slice Registers | 295564 | 0 | 692800 | 42.66 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 29964 | 0 | 204000 | 14.69 | | Slice Registers | 50886 | 0 | 408000 | 12.47 | | Block RAM Tile | 322 | 0 | 750 | 42.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 378 | 0 | 600 | 63.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 37933 | 0 | 204000 | 18.59 | | Slice Registers | 69426 | 0 | 408000 | 17.02 | | Block RAM Tile | 361.5 | 0 | 750 | 48.20 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 346 | 334 | 600 | 57.67 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186175 | 0 | 346400 | 53.75 | | Slice Registers | 268028 | 0 | 692800 | 38.69 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 195395 | 0 | 346400 | 56.41 | | Slice Registers | 295547 | 0 | 692800 | 42.66 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 |