*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2560.676 ; gain = 0.000 ; free physical = 81575 ; free virtual = 167065 INFO: [Netlist 29-17] Analyzing 6739 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3519.926 ; gain = 669.066 ; free physical = 80774 ; free virtual = 166263 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3543.930 ; gain = 0.000 ; free physical = 80866 ; free virtual = 166356 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:12 ; elapsed = 00:01:10 . Memory (MB): peak = 3543.930 ; gain = 1023.922 ; free physical = 80866 ; free virtual = 166356 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3551.934 ; gain = 8.000 ; free physical = 80859 ; free virtual = 166349 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1ee2623fa Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3551.934 ; gain = 0.000 ; free physical = 80741 ; free virtual = 166231 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3760.684 ; gain = 0.000 ; free physical = 80521 ; free virtual = 166036 Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3760.684 ; gain = 0.000 ; free physical = 80519 ; free virtual = 166034 Phase 1 Generate And Synthesize Debug Cores | Checksum: ebf58605 Time (s): cpu = 00:01:57 ; elapsed = 00:02:35 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80519 ; free virtual = 166034 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 232c99e70 Time (s): cpu = 00:02:04 ; elapsed = 00:02:43 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80614 ; free virtual = 166130 INFO: [Opt 31-389] Phase Retarget created 118 cells and removed 356 cells INFO: [Opt 31-1021] In phase Retarget, 434 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 20a8d0fbf Time (s): cpu = 00:02:05 ; elapsed = 00:02:44 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80615 ; free virtual = 166130 INFO: [Opt 31-389] Phase Constant propagation created 175 cells and removed 625 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 1c42e30b5 Time (s): cpu = 00:02:08 ; elapsed = 00:02:47 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80612 ; free virtual = 166127 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 747 cells INFO: [Opt 31-1021] In phase Sweep, 4682 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 216c0cf8c Time (s): cpu = 00:02:10 ; elapsed = 00:02:48 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80613 ; free virtual = 166129 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 206171fac Time (s): cpu = 00:02:10 ; elapsed = 00:02:49 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80614 ; free virtual = 166129 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 1b42b2fd6 Time (s): cpu = 00:02:10 ; elapsed = 00:02:49 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80614 ; free virtual = 166129 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 118 | 356 | 434 | | Constant propagation | 175 | 625 | 141 | | Sweep | 2 | 747 | 4682 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.21 . Memory (MB): peak = 3760.684 ; gain = 0.000 ; free physical = 80614 ; free virtual = 166129 Ending Logic Optimization Task | Checksum: 1d4a6aadd Time (s): cpu = 00:02:13 ; elapsed = 00:02:52 . Memory (MB): peak = 3760.684 ; gain = 42.785 ; free physical = 80614 ; free virtual = 166129 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 19e813e90 Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4794.582 ; gain = 0.000 ; free physical = 80404 ; free virtual = 165921 Ending Power Optimization Task | Checksum: 19e813e90 Time (s): cpu = 00:01:12 ; elapsed = 00:01:06 . Memory (MB): peak = 4794.582 ; gain = 1033.898 ; free physical = 80511 ; free virtual = 166028 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1b6613537 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 4794.582 ; gain = 0.000 ; free physical = 80476 ; free virtual = 165993 Ending Final Cleanup Task | Checksum: 1b6613537 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 4794.582 ; gain = 0.000 ; free physical = 80476 ; free virtual = 165993 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4794.582 ; gain = 0.000 ; free physical = 80476 ; free virtual = 165993 Ending Netlist Obfuscation Task | Checksum: 1b6613537 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4794.582 ; gain = 0.000 ; free physical = 80476 ; free virtual = 165993 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:02 ; elapsed = 00:04:37 . Memory (MB): peak = 4794.582 ; gain = 1250.652 ; free physical = 80479 ; free virtual = 165996 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4794.582 ; gain = 0.000 ; free physical = 80299 ; free virtual = 165875 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 4794.586 ; gain = 0.004 ; free physical = 80331 ; free virtual = 165875 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80210 ; free virtual = 165754 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80207 ; free virtual = 165751 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10a555929 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80207 ; free virtual = 165751 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80207 ; free virtual = 165751 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8b3b1397 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80254 ; free virtual = 165798 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 14b7ef487 Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80114 ; free virtual = 165658 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 14b7ef487 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80114 ; free virtual = 165658 Phase 1 Placer Initialization | Checksum: 14b7ef487 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80109 ; free virtual = 165653 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 18e812d5e Time (s): cpu = 00:00:59 ; elapsed = 00:00:59 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80053 ; free virtual = 165597 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 103a046e7 Time (s): cpu = 00:01:06 ; elapsed = 00:01:07 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80052 ; free virtual = 165596 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 91 LUTNM shape to break, 2490 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 80, two critical 11, total 91, new lutff created 8 INFO: [Physopt 32-775] End 1 Pass. Optimized 995 nets or cells. Created 91 new cells, deleted 904 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 11 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 47 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 58 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 58 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.35 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80033 ; free virtual = 165581 INFO: [Physopt 32-76] Pass 1. Identified 13 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 7 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 13 nets. Created 67 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 67 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80033 ; free virtual = 165581 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-46] Identified 78 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80033 ; free virtual = 165581 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 16 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 5 nets or cells. Created 5 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80034 ; free virtual = 165582 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80037 ; free virtual = 165584 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 91 | 904 | 995 | 0 | 1 | 00:00:02 | | Very High Fanout | 58 | 0 | 2 | 0 | 1 | 00:00:03 | | Fanout | 67 | 0 | 13 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 5 | 0 | 5 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 221 | 904 | 1015 | 0 | 10 | 00:00:07 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1e2323b6d Time (s): cpu = 00:02:58 ; elapsed = 00:03:02 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80036 ; free virtual = 165584 Phase 2.3 Global Placement Core | Checksum: 1dee94e53 Time (s): cpu = 00:03:03 ; elapsed = 00:03:06 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80025 ; free virtual = 165573 Phase 2 Global Placement | Checksum: 1dee94e53 Time (s): cpu = 00:03:03 ; elapsed = 00:03:07 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80068 ; free virtual = 165616 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1b3b37b7d Time (s): cpu = 00:03:12 ; elapsed = 00:03:16 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80062 ; free virtual = 165610 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 273c65eeb Time (s): cpu = 00:03:30 ; elapsed = 00:03:34 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80048 ; free virtual = 165596 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1bdc6043a Time (s): cpu = 00:03:32 ; elapsed = 00:03:35 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80048 ; free virtual = 165595 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1ad5c14ef Time (s): cpu = 00:03:32 ; elapsed = 00:03:36 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80047 ; free virtual = 165595 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 2598d9cb4 Time (s): cpu = 00:03:54 ; elapsed = 00:03:58 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80041 ; free virtual = 165589 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: 17725287d Time (s): cpu = 00:04:30 ; elapsed = 00:04:34 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79939 ; free virtual = 165487 Phase 3.6 Small Shape Detail Placement | Checksum: 17725287d Time (s): cpu = 00:04:31 ; elapsed = 00:04:35 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79967 ; free virtual = 165514 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 20e5f1fd7 Time (s): cpu = 00:04:36 ; elapsed = 00:04:40 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79972 ; free virtual = 165520 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1251f3e2e Time (s): cpu = 00:04:37 ; elapsed = 00:04:41 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79972 ; free virtual = 165520 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 206023342 Time (s): cpu = 00:05:23 ; elapsed = 00:05:28 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79943 ; free virtual = 165490 Phase 3 Detail Placement | Checksum: 206023342 Time (s): cpu = 00:05:24 ; elapsed = 00:05:29 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79943 ; free virtual = 165490 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1dc18f484 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.630 | TNS=-414.691 | Phase 1 Physical Synthesis Initialization | Checksum: 23cded72c Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79914 ; free virtual = 165462 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 2155b821a Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79912 ; free virtual = 165460 Phase 4.1.1.1 BUFG Insertion | Checksum: 1dc18f484 Time (s): cpu = 00:06:11 ; elapsed = 00:06:16 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79915 ; free virtual = 165463 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.173. For the most accurate timing information please run report_timing. Time (s): cpu = 00:09:28 ; elapsed = 00:09:33 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79917 ; free virtual = 165465 Phase 4.1 Post Commit Optimization | Checksum: e64849b9 Time (s): cpu = 00:09:28 ; elapsed = 00:09:34 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79917 ; free virtual = 165465 Post Placement Optimization Initialization | Checksum: 15bcbec6d Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.366 | TNS=-123.244 | Phase 1 Physical Synthesis Initialization | Checksum: 1fd476a5b Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79921 ; free virtual = 165469 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1d4a5e6d4 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79920 ; free virtual = 165468 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.028. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 159bfe52e Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.028 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1d73a4185 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79924 ; free virtual = 165472 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1f8a7086b Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79922 ; free virtual = 165471 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.033. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 17813acb7 Time (s): cpu = 00:17:45 ; elapsed = 00:17:51 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79930 ; free virtual = 165478 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 1x1| 2x2| |___________|___________________|___________________| | West| 1x1| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 17813acb7 Time (s): cpu = 00:17:46 ; elapsed = 00:17:52 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79931 ; free virtual = 165479 Phase 4.3 Placer Reporting | Checksum: 17813acb7 Time (s): cpu = 00:17:47 ; elapsed = 00:17:53 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79931 ; free virtual = 165479 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79931 ; free virtual = 165479 Time (s): cpu = 00:17:47 ; elapsed = 00:17:53 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79931 ; free virtual = 165479 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 127f069d0 Time (s): cpu = 00:17:48 ; elapsed = 00:17:54 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79930 ; free virtual = 165479 Ending Placer Task | Checksum: 10bef551c Time (s): cpu = 00:17:48 ; elapsed = 00:17:54 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79931 ; free virtual = 165479 INFO: [Common 17-83] Releasing license: Implementation 198 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:17:55 ; elapsed = 00:18:01 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 80012 ; free virtual = 165560 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79825 ; free virtual = 165542 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79958 ; free virtual = 165544 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.48 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79932 ; free virtual = 165517 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.66 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79954 ; free virtual = 165541 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 211 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79915 ; free virtual = 165503 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79725 ; free virtual = 165481 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:40 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79858 ; free virtual = 165483 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: afe4408b ConstDB: 0 ShapeSum: 5c0b1491 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 992bb154 Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79569 ; free virtual = 165194 Post Restoration Checksum: NetGraph: 385bbbb1 NumContArr: 60cff5a3 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 992bb154 Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79599 ; free virtual = 165224 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 992bb154 Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79586 ; free virtual = 165211 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 992bb154 Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79586 ; free virtual = 165211 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 134b3106a Time (s): cpu = 00:01:42 ; elapsed = 00:01:43 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79556 ; free virtual = 165180 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.016 | TNS=0.000 | WHS=-2.845 | THS=-4932.408| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1c8eb4fb1 Time (s): cpu = 00:02:15 ; elapsed = 00:02:16 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79545 ; free virtual = 165169 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.016 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1347ba92f Time (s): cpu = 00:02:15 ; elapsed = 00:02:16 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79543 ; free virtual = 165167 Phase 2 Router Initialization | Checksum: 128bdbee3 Time (s): cpu = 00:02:16 ; elapsed = 00:02:17 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79543 ; free virtual = 165167 Router Utilization Summary Global Vertical Routing Utilization = 2.59626e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 101661 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 101659 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 128bdbee3 Time (s): cpu = 00:02:17 ; elapsed = 00:02:18 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79540 ; free virtual = 165165 Phase 3 Initial Routing | Checksum: 143810f07 Time (s): cpu = 00:04:36 ; elapsed = 00:04:38 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79526 ; free virtual = 165151 INFO: [Route 35-580] Design has 30 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/FSM_sequential_current_state_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[1]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 9283 Number of Nodes with overlaps = 986 Number of Nodes with overlaps = 267 Number of Nodes with overlaps = 101 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.039 | TNS=-0.490 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 18af548c9 Time (s): cpu = 00:06:23 ; elapsed = 00:06:26 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79519 ; free virtual = 165144 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1138 Number of Nodes with overlaps = 207 Number of Nodes with overlaps = 105 Number of Nodes with overlaps = 29 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.000 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 23851299c Time (s): cpu = 00:07:03 ; elapsed = 00:07:07 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79518 ; free virtual = 165143 Phase 4 Rip-up And Reroute | Checksum: 23851299c Time (s): cpu = 00:07:03 ; elapsed = 00:07:07 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79518 ; free virtual = 165143 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 23851299c Time (s): cpu = 00:07:03 ; elapsed = 00:07:08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79518 ; free virtual = 165143 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 23851299c Time (s): cpu = 00:07:04 ; elapsed = 00:07:08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79518 ; free virtual = 165143 Phase 5 Delay and Skew Optimization | Checksum: 23851299c Time (s): cpu = 00:07:04 ; elapsed = 00:07:08 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79518 ; free virtual = 165143 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1fbef8a16 Time (s): cpu = 00:07:17 ; elapsed = 00:07:21 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79521 ; free virtual = 165145 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.063 | TNS=0.000 | WHS=-1.493 | THS=-30.786| Phase 6.1 Hold Fix Iter | Checksum: 19fc919c8 Time (s): cpu = 00:07:18 ; elapsed = 00:07:22 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79520 ; free virtual = 165144 Phase 6 Post Hold Fix | Checksum: 255d89a23 Time (s): cpu = 00:07:18 ; elapsed = 00:07:22 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79519 ; free virtual = 165144 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 255b42a74 Time (s): cpu = 00:07:35 ; elapsed = 00:07:39 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79522 ; free virtual = 165147 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.063 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 255b42a74 Time (s): cpu = 00:07:35 ; elapsed = 00:07:39 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79522 ; free virtual = 165147 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.27632 % Global Horizontal Routing Utilization = 10.2406 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 255b42a74 Time (s): cpu = 00:07:36 ; elapsed = 00:07:40 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79522 ; free virtual = 165146 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 255b42a74 Time (s): cpu = 00:07:36 ; elapsed = 00:07:41 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79519 ; free virtual = 165144 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 2584da110 Time (s): cpu = 00:07:45 ; elapsed = 00:07:49 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79514 ; free virtual = 165138 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.063 | TNS=0.000 | WHS=0.052 | THS=0.000 | Phase 11 Post Router Timing | Checksum: 26d5288cd Time (s): cpu = 00:08:27 ; elapsed = 00:08:31 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79432 ; free virtual = 165057 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 1 | 0.063 | 0.000 | -1.493 | - | Pass | 00:07:02 | x | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:08:27 ; elapsed = 00:08:31 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79647 ; free virtual = 165271 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 231 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:08:47 ; elapsed = 00:08:52 . Memory (MB): peak = 4794.586 ; gain = 0.000 ; free physical = 79647 ; free virtual = 165271 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.2-hog7080975 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value 7080975 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.2-hog7080975 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.5.2-hog7080975... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.