## efex_processor.2 Synthesis Utilization report
                                                                                     
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |   
| ---    |         ---  |        --- |         ---  |             ---  |             
| Slice  LUTs*     |    186146   |   0         |    346400        |    53.74     |   
| Slice  Registers |    268028   |   0         |    692800        |    38.69     |   
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03
| DSPs   |         0    |        0   |         2880 |             0.00 |             
| Bonded IOB       |    500      |   0         |    600           |    83.33     |   
                                                                                     
## efex_processor.2 Implementation Utilization report
                                                                                      
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         ---  |             ---  |              
| Slice  LUTs      |    195058   |   0         |    346400        |    56.31     |    
| Slice  Registers |    295977   |   0         |    692800        |    42.72     |    
| Block  RAM       Tile |        751 |         0    |             1180 |         63.64
| DSPs   |         120  |        0   |         2880 |             4.17 |              
| Bonded IOB       |    448      |   448       |    600           |    74.67     |