## Repository info - Merge request number: 301 - Branch name: feature/readout_update ## MR Description update TOB readout to ensure the trigger slice TOB/XTOB BCN value is used in the TOB Readout Packet Header. This is achieved by adding the slice_trigger value to the first TOB/XTOB BCN value ## Changelog ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e2034d7 | 1.5.3 | | Constraints | 04c79778 | 1.5.0 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | e2034d7 | 1.5.3 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e58176a | 1.5.3 | | Constraints | e58176a5 | 1.5.3 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | e2034d7 | 1.5.3 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e58176a | 1.5.3 | | Constraints | e58176a5 | 1.5.3 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | e2034d7 | 1.5.3 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e2034d7 | 1.5.3 | | Constraints | 9478ee15 | 1.4.0 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | e2034d7 | 1.5.3 | | **Lib:** algolib | a04cc2c | 1.5.0 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.078319 | | TNS: | 0.000000 | | WHS: | 0.025899 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.033920 | | TNS: | 0.000000 | | WHS: | 0.007789 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.000000 | | TNS: | 0.000000 | | WHS: | 0.009777 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.033767 | | TNS: | 0.000000 | | WHS: | 0.012073 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186146 | 0 | 346400 | 53.74 | | Slice Registers | 268028 | 0 | 692800 | 38.69 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 195058 | 0 | 346400 | 56.31 | | Slice Registers | 295977 | 0 | 692800 | 42.72 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186080 | 0 | 346400 | 53.72 | | Slice Registers | 268017 | 0 | 692800 | 38.69 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194907 | 0 | 346400 | 56.27 | | Slice Registers | 295714 | 0 | 692800 | 42.68 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182335 | 0 | 346400 | 52.64 | | Slice Registers | 256451 | 0 | 692800 | 37.02 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 192676 | 0 | 346400 | 55.62 | | Slice Registers | 284298 | 0 | 692800 | 41.04 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182332 | 0 | 346400 | 52.64 | | Slice Registers | 256444 | 0 | 692800 | 37.02 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191583 | 0 | 346400 | 55.31 | | Slice Registers | 283820 | 0 | 692800 | 40.97 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 |