*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2563.672 ; gain = 0.000 ; free physical = 67368 ; free virtual = 154400 INFO: [Netlist 29-17] Analyzing 6739 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3520.953 ; gain = 670.066 ; free physical = 66542 ; free virtual = 153538 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3543.957 ; gain = 0.000 ; free physical = 66601 ; free virtual = 153584 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:14 ; elapsed = 00:01:12 . Memory (MB): peak = 3543.957 ; gain = 1022.887 ; free physical = 66608 ; free virtual = 153590 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3551.961 ; gain = 8.000 ; free physical = 66615 ; free virtual = 153574 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 21be71219 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3551.961 ; gain = 0.000 ; free physical = 66494 ; free virtual = 153448 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3760.711 ; gain = 0.000 ; free physical = 66169 ; free virtual = 152905 Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3760.711 ; gain = 0.000 ; free physical = 66167 ; free virtual = 152903 Phase 1 Generate And Synthesize Debug Cores | Checksum: 15535555f Time (s): cpu = 00:02:01 ; elapsed = 00:02:39 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66167 ; free virtual = 152903 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 13c0ca975 Time (s): cpu = 00:02:08 ; elapsed = 00:02:47 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66264 ; free virtual = 152994 INFO: [Opt 31-389] Phase Retarget created 118 cells and removed 356 cells INFO: [Opt 31-1021] In phase Retarget, 434 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: e4c85f11 Time (s): cpu = 00:02:09 ; elapsed = 00:02:48 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66265 ; free virtual = 152993 INFO: [Opt 31-389] Phase Constant propagation created 175 cells and removed 625 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 12f06f18a Time (s): cpu = 00:02:12 ; elapsed = 00:02:51 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66256 ; free virtual = 152979 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 747 cells INFO: [Opt 31-1021] In phase Sweep, 4682 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 10d65d446 Time (s): cpu = 00:02:14 ; elapsed = 00:02:53 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66147 ; free virtual = 152947 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: e9f38ac3 Time (s): cpu = 00:02:14 ; elapsed = 00:02:53 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66129 ; free virtual = 152947 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 117ea0b4a Time (s): cpu = 00:02:15 ; elapsed = 00:02:53 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 66105 ; free virtual = 152952 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 118 | 356 | 434 | | Constant propagation | 175 | 625 | 141 | | Sweep | 2 | 747 | 4682 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3760.711 ; gain = 0.000 ; free physical = 65978 ; free virtual = 152937 Ending Logic Optimization Task | Checksum: 137e3632d Time (s): cpu = 00:02:18 ; elapsed = 00:02:56 . Memory (MB): peak = 3760.711 ; gain = 42.785 ; free physical = 65978 ; free virtual = 152937 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 174ac5e6b Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.008 ; gain = 0.000 ; free physical = 64770 ; free virtual = 152145 Ending Power Optimization Task | Checksum: 174ac5e6b Time (s): cpu = 00:01:13 ; elapsed = 00:01:07 . Memory (MB): peak = 4795.008 ; gain = 1034.297 ; free physical = 64864 ; free virtual = 152248 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 16e097147 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 4795.008 ; gain = 0.000 ; free physical = 64458 ; free virtual = 151900 Ending Final Cleanup Task | Checksum: 16e097147 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 4795.008 ; gain = 0.000 ; free physical = 64448 ; free virtual = 151890 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.008 ; gain = 0.000 ; free physical = 64446 ; free virtual = 151888 Ending Netlist Obfuscation Task | Checksum: 16e097147 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.008 ; gain = 0.000 ; free physical = 64440 ; free virtual = 151882 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:08 ; elapsed = 00:04:43 . Memory (MB): peak = 4795.008 ; gain = 1251.051 ; free physical = 64444 ; free virtual = 151886 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4795.008 ; gain = 0.000 ; free physical = 63533 ; free virtual = 151294 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:40 . Memory (MB): peak = 4795.012 ; gain = 0.004 ; free physical = 63531 ; free virtual = 151322 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62935 ; free virtual = 150744 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62861 ; free virtual = 150693 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: adab2514 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62862 ; free virtual = 150694 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62864 ; free virtual = 150696 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 820bd8c6 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62715 ; free virtual = 150689 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: a38ac50a Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62298 ; free virtual = 150288 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: a38ac50a Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62333 ; free virtual = 150323 Phase 1 Placer Initialization | Checksum: a38ac50a Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62325 ; free virtual = 150315 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 115f91a27 Time (s): cpu = 00:01:02 ; elapsed = 00:01:02 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62281 ; free virtual = 150250 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 61cad46a Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62286 ; free virtual = 150265 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 56 LUTNM shape to break, 2439 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 44, two critical 12, total 56, new lutff created 4 INFO: [Physopt 32-775] End 1 Pass. Optimized 955 nets or cells. Created 56 new cells, deleted 899 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 10 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 50 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 60 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 60 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62323 ; free virtual = 150229 INFO: [Physopt 32-76] Pass 1. Identified 11 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-232] Optimized 9 nets. Created 45 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 45 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62333 ; free virtual = 150235 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.hub2_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver GOLDEN_IF.hub2_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2 could not be replicated INFO: [Physopt 32-46] Identified 134 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[3]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[8]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[11]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[0]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-232] Optimized 11 nets. Created 11 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 11 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62337 ; free virtual = 150238 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 50 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_14. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 14 nets or cells. Created 14 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62319 ; free virtual = 150217 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62334 ; free virtual = 150231 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 56 | 899 | 955 | 0 | 1 | 00:00:02 | | Very High Fanout | 60 | 0 | 2 | 0 | 1 | 00:00:03 | | Fanout | 45 | 0 | 9 | 0 | 1 | 00:00:01 | | Critical Cell | 11 | 0 | 11 | 0 | 1 | 00:00:01 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 14 | 0 | 14 | 0 | 1 | 00:00:02 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 186 | 899 | 991 | 0 | 10 | 00:00:09 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: f31d6707 Time (s): cpu = 00:03:12 ; elapsed = 00:03:15 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62385 ; free virtual = 150206 Phase 2.3 Global Placement Core | Checksum: db233725 Time (s): cpu = 00:03:17 ; elapsed = 00:03:21 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62368 ; free virtual = 150184 Phase 2 Global Placement | Checksum: db233725 Time (s): cpu = 00:03:17 ; elapsed = 00:03:21 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62386 ; free virtual = 150201 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: adb420b6 Time (s): cpu = 00:03:27 ; elapsed = 00:03:30 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62380 ; free virtual = 150185 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22b51f2b Time (s): cpu = 00:03:46 ; elapsed = 00:03:50 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62399 ; free virtual = 150202 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: da443329 Time (s): cpu = 00:03:48 ; elapsed = 00:03:52 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62412 ; free virtual = 150207 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: e9489d18 Time (s): cpu = 00:03:48 ; elapsed = 00:03:52 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62412 ; free virtual = 150208 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 114e438b8 Time (s): cpu = 00:04:10 ; elapsed = 00:04:15 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62443 ; free virtual = 150138 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 80bac741 Time (s): cpu = 00:04:48 ; elapsed = 00:04:53 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62156 ; free virtual = 150006 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 14156ff34 Time (s): cpu = 00:04:53 ; elapsed = 00:04:57 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62154 ; free virtual = 149999 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1245af883 Time (s): cpu = 00:04:54 ; elapsed = 00:04:58 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 62140 ; free virtual = 149987 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: f32393ff Time (s): cpu = 00:05:38 ; elapsed = 00:05:42 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61812 ; free virtual = 149823 Phase 3 Detail Placement | Checksum: f32393ff Time (s): cpu = 00:05:38 ; elapsed = 00:05:43 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61841 ; free virtual = 149852 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: d0eb809c Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.615 | TNS=-115.364 | Phase 1 Physical Synthesis Initialization | Checksum: 16a5ac429 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61603 ; free virtual = 149797 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 17c2bcf5b Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61570 ; free virtual = 149764 Phase 4.1.1.1 BUFG Insertion | Checksum: d0eb809c Time (s): cpu = 00:06:26 ; elapsed = 00:06:31 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61559 ; free virtual = 149753 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.015. For the most accurate timing information please run report_timing. Time (s): cpu = 00:09:51 ; elapsed = 00:09:57 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 63243 ; free virtual = 151352 Phase 4.1 Post Commit Optimization | Checksum: 185aab851 Time (s): cpu = 00:09:52 ; elapsed = 00:09:57 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 63245 ; free virtual = 151354 Post Placement Optimization Initialization | Checksum: 176918a15 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.524 | TNS=-80.080 | Phase 1 Physical Synthesis Initialization | Checksum: 17f95d18d Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64474 ; free virtual = 153313 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 20c96cb70 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64457 ; free virtual = 153298 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.176. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1ac3adeec Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.176 | TNS=-0.736 | Phase 1 Physical Synthesis Initialization | Checksum: 19a17d662 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 71480 ; free virtual = 157327 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 227be1b72 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 71413 ; free virtual = 157260 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.172. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: ab1fddd9 Time (s): cpu = 00:18:16 ; elapsed = 00:18:22 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64443 ; free virtual = 150290 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 2x2| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: ab1fddd9 Time (s): cpu = 00:18:17 ; elapsed = 00:18:23 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64458 ; free virtual = 150306 Phase 4.3 Placer Reporting | Checksum: ab1fddd9 Time (s): cpu = 00:18:18 ; elapsed = 00:18:24 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64552 ; free virtual = 150400 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64527 ; free virtual = 150374 Time (s): cpu = 00:18:18 ; elapsed = 00:18:24 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64526 ; free virtual = 150374 Phase 4 Post Placement Optimization and Clean-Up | Checksum: a72c24f4 Time (s): cpu = 00:18:19 ; elapsed = 00:18:25 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64484 ; free virtual = 150332 Ending Placer Task | Checksum: 9b661d6e Time (s): cpu = 00:18:19 ; elapsed = 00:18:25 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64599 ; free virtual = 150446 INFO: [Common 17-83] Releasing license: Implementation 281 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:18:26 ; elapsed = 00:18:32 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 64674 ; free virtual = 150522 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61237 ; free virtual = 147252 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:38 ; elapsed = 00:00:42 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61407 ; free virtual = 147292 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.47 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61286 ; free virtual = 147171 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.68 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61221 ; free virtual = 147108 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 61366 ; free virtual = 147253 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.172 | TNS=-0.660 | Phase 1 Physical Synthesis Initialization | Checksum: 1ca3bdf43 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60488 ; free virtual = 146375 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.172 | TNS=-0.660 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 1ca3bdf43 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60377 ; free virtual = 146264 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.172 | TNS=-0.660 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[4]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[4] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.172 | TNS=-0.487 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[51]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[51] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[51]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.064 | TNS=-0.315 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[43]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[43] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[43]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.064 | TNS=-0.251 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[56]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[56] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[56]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.064 | TNS=-0.186 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[57]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[57] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[57]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.122 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[30]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[30] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[30]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.104 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[39]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[39] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[39]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.087 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[42]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[42] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[42]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.070 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[43]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[43] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[43]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.052 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[44]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[44] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[44]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.035 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[45]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[45] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[45]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.017 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[49]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[49] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[49]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.002 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.002 | TNS=0.000 | Phase 3 Critical Path Optimization | Checksum: 1ca3bdf43 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60321 ; free virtual = 146208 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.002 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.002 | TNS=0.000 | Phase 4 Critical Path Optimization | Checksum: 1ca3bdf43 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60321 ; free virtual = 146208 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60323 ; free virtual = 146210 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.002 | TNS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.174 | 0.660 | 0 | 0 | 12 | 0 | 2 | 00:00:03 | | Total | 0.174 | 0.660 | 0 | 0 | 12 | 0 | 3 | 00:00:03 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60322 ; free virtual = 146209 Ending Physical Synthesis Task | Checksum: 2182860ab Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60309 ; free virtual = 146196 INFO: [Common 17-83] Releasing license: Implementation 338 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60374 ; free virtual = 146261 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60890 ; free virtual = 146962 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 60675 ; free virtual = 146618 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 7e124bc8 ConstDB: 0 ShapeSum: af470048 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1d8245733 Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 58198 ; free virtual = 144161 Post Restoration Checksum: NetGraph: da7d8130 NumContArr: fda6d603 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 1d8245733 Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 58210 ; free virtual = 144173 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 1d8245733 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 58183 ; free virtual = 144146 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 1d8245733 Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 58180 ; free virtual = 144143 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 2588527c8 Time (s): cpu = 00:01:47 ; elapsed = 00:01:48 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57581 ; free virtual = 143555 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.050 | TNS=-0.136 | WHS=-2.813 | THS=-5424.074| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 23d5f676c Time (s): cpu = 00:02:20 ; elapsed = 00:02:21 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57725 ; free virtual = 143700 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.050 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 264fe9e95 Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57679 ; free virtual = 143654 Phase 2 Router Initialization | Checksum: 237e07f58 Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57660 ; free virtual = 143635 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 101646 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 101644 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 237e07f58 Time (s): cpu = 00:02:22 ; elapsed = 00:02:24 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57622 ; free virtual = 143597 Phase 3 Initial Routing | Checksum: 10d61a43e Time (s): cpu = 00:04:24 ; elapsed = 00:04:26 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 58915 ; free virtual = 144858 INFO: [Route 35-580] Design has 24 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/delay_count_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Reg_enable_reg/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/FSM_sequential_current_state_reg[1]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 8338 Number of Nodes with overlaps = 816 Number of Nodes with overlaps = 220 Number of Nodes with overlaps = 70 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.172 | TNS=-13.416| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1918421c9 Time (s): cpu = 00:06:10 ; elapsed = 00:06:14 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 54062 ; free virtual = 140005 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 579 Number of Nodes with overlaps = 113 Number of Nodes with overlaps = 42 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.047 | TNS=-0.111 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 742807e6 Time (s): cpu = 00:06:38 ; elapsed = 00:06:42 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 52723 ; free virtual = 138666 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 993 Number of Nodes with overlaps = 183 Number of Nodes with overlaps = 110 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.034 | TNS=-0.275 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1706cd933 Time (s): cpu = 00:07:26 ; elapsed = 00:07:31 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 54750 ; free virtual = 140693 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 687 Number of Nodes with overlaps = 105 Number of Nodes with overlaps = 67 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.022 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 1c2cad880 Time (s): cpu = 00:07:52 ; elapsed = 00:07:58 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 53668 ; free virtual = 139611 Phase 4 Rip-up And Reroute | Checksum: 1c2cad880 Time (s): cpu = 00:07:52 ; elapsed = 00:07:58 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 53662 ; free virtual = 139605 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1c2cad880 Time (s): cpu = 00:07:53 ; elapsed = 00:07:59 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 53652 ; free virtual = 139595 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1c2cad880 Time (s): cpu = 00:07:53 ; elapsed = 00:07:59 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 53648 ; free virtual = 139592 Phase 5 Delay and Skew Optimization | Checksum: 1c2cad880 Time (s): cpu = 00:07:53 ; elapsed = 00:07:59 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 53644 ; free virtual = 139587 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 116d5cf8a Time (s): cpu = 00:08:06 ; elapsed = 00:08:12 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 54089 ; free virtual = 140032 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.045 | TNS=0.000 | WHS=-0.951 | THS=-38.885| Phase 6.1 Hold Fix Iter | Checksum: fe80d83b Time (s): cpu = 00:08:07 ; elapsed = 00:08:13 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 54162 ; free virtual = 140105 Phase 6 Post Hold Fix | Checksum: a24f94ce Time (s): cpu = 00:08:08 ; elapsed = 00:08:14 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 54158 ; free virtual = 140101 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 11ee18a93 Time (s): cpu = 00:08:25 ; elapsed = 00:08:31 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 55774 ; free virtual = 141717 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.045 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 11ee18a93 Time (s): cpu = 00:08:25 ; elapsed = 00:08:31 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 55759 ; free virtual = 141702 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.20057 % Global Horizontal Routing Utilization = 10.2336 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 11ee18a93 Time (s): cpu = 00:08:26 ; elapsed = 00:08:32 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 55836 ; free virtual = 141779 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 11ee18a93 Time (s): cpu = 00:08:26 ; elapsed = 00:08:32 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 55832 ; free virtual = 141775 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 15a5024fe Time (s): cpu = 00:08:35 ; elapsed = 00:08:41 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 55687 ; free virtual = 141630 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.045 | TNS=0.000 | WHS=0.050 | THS=0.000 | Phase 11 Post Router Timing | Checksum: 19afdf2db Time (s): cpu = 00:09:18 ; elapsed = 00:09:24 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57680 ; free virtual = 143623 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 1 | 0.045 | 0.000 | -0.951 | - | Pass | 00:07:52 | x | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:09:18 ; elapsed = 00:09:24 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57900 ; free virtual = 143843 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 360 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:10:00 ; elapsed = 00:10:06 . Memory (MB): peak = 4795.012 ; gain = 0.000 ; free physical = 57901 ; free virtual = 143844 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.4-hog91ab74c INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value 91ab74c will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.4-hog91ab74c INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.5.4-hog91ab74c... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.