Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date         : Thu Apr 13 15:20:08 2023
| Host         : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command      : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx
| Design       : top_efex_control
| Device       : xc7vx330tffg1157-2
| Speed File   : -2
| Design State : Synthesized
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 3
+---------+----------+--------------------+------------+
| Rule    | Severity | Description        | Violations |
+---------+----------+--------------------+------------+
| REQP-45 | Warning  | must_use_ref_clock | 3          |
+---------+----------+--------------------+------------+

2. REPORT DETAILS
-----------------
REQP-45#1 Warning
must_use_ref_clock  
GTHE2_COMMON cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/common0_i/gthe2_common_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set QPLLREFCLKSEL[2:0] appropriately) must be used (unless this cell is just to set needed configuration).
Related violations: <none>

REQP-45#2 Warning
must_use_ref_clock  
GTHE2_COMMON cell GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/gt_common_support/gthe2_common_lane1_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set QPLLREFCLKSEL[2:0] appropriately) must be used (unless this cell is just to set needed configuration).
Related violations: <none>

REQP-45#3 Warning
must_use_ref_clock  
GTHE2_COMMON cell GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/gt_common_support/gthe2_common_lane1_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set QPLLREFCLKSEL[2:0] appropriately) must be used (unless this cell is just to set needed configuration).
Related violations: <none>


