Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Thu Apr 13 19:00:53 2023 | Host : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.4-v1.5.4-hog367983f/reports/hierarchical_utilization.txt | Design : top_efex_processor | Device : 7vx550tffg1927-2 | Design State : Routed ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------+----------------+----------------+-----------+--------------+----------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------+----------------+----------------+-----------+--------------+----------------+-------------+-----------+------------+ | top_efex_processor | (top) | 191833(55.38%) | 177507(51.24%) | 24(0.01%) | 14302(8.21%) | 283942(40.98%) | 714(60.51%) | 52(2.20%) | 120(4.17%) | | (top_efex_processor) | (top) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_PATH_IF.data_path_Module | data_path_block | 124815(36.03%) | 110795(31.98%) | 0(0.00%) | 14020(8.05%) | 203090(29.31%) | 8(0.68%) | 0(0.00%) | 120(4.17%) | | (DATA_PATH_IF.data_path_Module) | data_path_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Sorting_Module | IPBusTopSortingModule | 3246(0.94%) | 3233(0.93%) | 0(0.00%) | 13(0.01%) | 6819(0.98%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Sorting_Module) | IPBusTopSortingModule | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_Delay | GeneralDelay__parameterized8 | 34(0.01%) | 22(0.01%) | 0(0.00%) | 12(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_SORTING_REGISTERS | ipbus_ctrlreg_v__parameterized8 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_eg | TopSortingModule | 1584(0.46%) | 1583(0.46%) | 0(0.00%) | 1(0.01%) | 3341(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_eg) | TopSortingModule | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 290(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5711 | 221(0.06%) | 220(0.06%) | 0(0.00%) | 1(0.01%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5711 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5730 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5731 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5712 | 217(0.06%) | 217(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5728 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5729 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5713 | 217(0.06%) | 217(0.06%) | 0(0.00%) | 0(0.00%) | 437(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5713 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5726 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5727 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0_5714 | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0_5714 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5724 | 132(0.04%) | 132(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5725 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5715 | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5715 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5722 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5723 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5716 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5716 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5720 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5721 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5717 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 438(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5718 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5719 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_tau | TopSortingModule_5692 | 1584(0.46%) | 1584(0.46%) | 0(0.00%) | 0(0.00%) | 3335(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_tau) | TopSortingModule_5692 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 288(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter | 217(0.06%) | 217(0.06%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5709 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5710 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5693 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5693 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5707 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5708 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5694 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5694 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5705 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5706 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5703 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5704 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5695 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5695 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5701 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5702 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5696 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5696 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5699 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5700 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5697 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5697 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5698 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | algorithm_block | IPBusTopAlgoModule | 101856(29.40%) | 100347(28.97%) | 0(0.00%) | 1509(0.87%) | 158747(22.91%) | 8(0.68%) | 0(0.00%) | 120(4.17%) | | (algorithm_block) | IPBusTopAlgoModule | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_Delay_internal | GeneralDelay__parameterized6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_STAGE | AlgoInputStage | 5600(1.62%) | 5600(1.62%) | 0(0.00%) | 0(0.00%) | 19488(2.81%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (INPUT_STAGE) | AlgoInputStage | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 108(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].EnergyConverterH | EnergyConverter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1581 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1582 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1583 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1584 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1585 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1586 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1587 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1588 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1589 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1590 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].EnergyConverterH | EnergyConverter_1591 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1592 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1593 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1594 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1595 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1596 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1597 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1598 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1599 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1600 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1601 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].EnergyConverterH | EnergyConverter_1602 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1603 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1604 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1605 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1606 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1607 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1608 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1609 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1610 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1611 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1612 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].EnergyConverterH | EnergyConverter_1613 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1614 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1615 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1616 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1617 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1618 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1619 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1620 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1621 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1622 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1623 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].EnergyConverterH | EnergyConverter_1624 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1625 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1626 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1627 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1628 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1629 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1630 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1631 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1632 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1633 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1634 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].EnergyConverterH | EnergyConverter_1635 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1636 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1637 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1638 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1639 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1640 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1642 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1643 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1644 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1645 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].EnergyConverterH | EnergyConverter_1646 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1647 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1648 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1649 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1650 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1651 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1652 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1653 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1654 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1655 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1656 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].EnergyConverterH | EnergyConverter_1657 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1658 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1659 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1660 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1661 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1662 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1663 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1664 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1665 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1666 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1667 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].EnergyConverterH | EnergyConverter_1668 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1669 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1670 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1671 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1672 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1673 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1674 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1675 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1676 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1677 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1678 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].EnergyConverterH | EnergyConverter_1679 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1680 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1681 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1682 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1683 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1684 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1685 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1686 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1687 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1688 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1689 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].EnergyConverterH | EnergyConverter_1690 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1691 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1692 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1693 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1694 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1695 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1696 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1697 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1698 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1699 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1700 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].EnergyConverterH | EnergyConverter_1701 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1702 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1703 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1704 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1705 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1706 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1707 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1708 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1709 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1711 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].EnergyConverterH | EnergyConverter_1712 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1713 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1714 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1715 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1716 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1717 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1718 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1719 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1720 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1721 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1722 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].EnergyConverterH | EnergyConverter_1723 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1724 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1725 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1726 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1727 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1728 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1729 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1730 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1731 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1732 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1733 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].EnergyConverterH | EnergyConverter_1734 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1735 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1736 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1737 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1738 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1739 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1740 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1741 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1742 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1743 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1744 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].EnergyConverterH | EnergyConverter_1745 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1746 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1747 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1748 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1749 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1750 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1751 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1752 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1753 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1754 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1755 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].EnergyConverterH | EnergyConverter_1756 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1757 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1758 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1759 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1760 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1761 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1762 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1763 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1764 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1765 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1766 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].EnergyConverterH | EnergyConverter_1767 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1768 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1769 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1770 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1771 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1772 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1773 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1774 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1775 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1776 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1777 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].EnergyConverterH | EnergyConverter_1778 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1779 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1780 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1781 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1782 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1783 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1784 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1785 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1786 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1787 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1788 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].EnergyConverterH | EnergyConverter_1789 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1790 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1791 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1792 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1793 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1794 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1795 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1796 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1797 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1798 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1799 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].EnergyConverterH | EnergyConverter_1800 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1801 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1802 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1803 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1804 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1805 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1806 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1807 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1808 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1809 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1810 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].EnergyConverterH | EnergyConverter_1811 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1812 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1813 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1814 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1815 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1816 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1817 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1818 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1819 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1820 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1821 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].EnergyConverterH | EnergyConverter_1822 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1823 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1824 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1825 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1826 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1827 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1828 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1829 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1830 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1831 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1832 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].EnergyConverterH | EnergyConverter_1833 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1834 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1835 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1836 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1837 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1838 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1839 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1840 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1841 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1842 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1843 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].EnergyConverterH | EnergyConverter_1844 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1845 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1846 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1847 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1848 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1849 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1850 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1851 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1852 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1853 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1854 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].EnergyConverterH | EnergyConverter_1855 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1856 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1857 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1858 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1859 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1860 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1861 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1862 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1863 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1864 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1865 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].EnergyConverterH | EnergyConverter_1866 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1867 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1868 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1869 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1870 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1871 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1872 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1873 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1874 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1875 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1876 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].EnergyConverterH | EnergyConverter_1877 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1878 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1879 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1880 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1881 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1882 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1883 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1884 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1885 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1886 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1887 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].EnergyConverterH | EnergyConverter_1888 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1889 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1890 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1891 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1892 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1893 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1894 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1895 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1896 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1897 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1898 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].EnergyConverterH | EnergyConverter_1899 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1900 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1901 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1902 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1903 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1904 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1905 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1906 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1907 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1908 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1909 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].EnergyConverterH | EnergyConverter_1910 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1911 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1912 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1913 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1914 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1915 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1916 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1917 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1918 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1919 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1920 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].EnergyConverterH | EnergyConverter_1921 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1922 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1923 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1924 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1925 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1926 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1927 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1928 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1929 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1930 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1931 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].EnergyConverterH | EnergyConverter_1932 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1933 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1934 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1935 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1936 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1937 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1938 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1939 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1940 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1941 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1942 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].EnergyConverterH | EnergyConverter_1943 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1944 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1945 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1946 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1947 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1948 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1949 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1950 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1951 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1952 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1953 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].EnergyConverterH | EnergyConverter_1954 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1955 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1956 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1957 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1958 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1959 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1960 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1961 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1962 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1963 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1964 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].EnergyConverterH | EnergyConverter_1965 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1966 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1967 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1968 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1969 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1970 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1971 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1972 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1973 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1974 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1975 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].EnergyConverterH | EnergyConverter_1976 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1977 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1978 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1979 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1980 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1981 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1982 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1983 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1984 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1985 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1986 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].EnergyConverterH | EnergyConverter_1987 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1988 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1989 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1990 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1991 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1992 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1993 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1994 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1995 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1996 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1997 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].EnergyConverterH | EnergyConverter_1998 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1999 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2000 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2001 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2002 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2003 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2004 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2005 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2006 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2007 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2008 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].EnergyConverterH | EnergyConverter_2009 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2010 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2011 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2012 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2013 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2014 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2015 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2016 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2017 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2018 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2019 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].EnergyConverterH | EnergyConverter_2020 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2021 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2022 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2023 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2024 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2025 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2026 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2027 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2028 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2029 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2030 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].EnergyConverterH | EnergyConverter_2031 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2032 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2033 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2034 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2035 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2036 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2037 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2038 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2039 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2040 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2041 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].EnergyConverterH | EnergyConverter_2042 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2043 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2044 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2045 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2046 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2047 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2048 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2049 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2050 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2051 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2052 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].EnergyConverterH | EnergyConverter_2053 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2054 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2055 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2056 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2057 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2058 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2059 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2060 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2061 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2062 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2063 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].EnergyConverterH | EnergyConverter_2064 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2065 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2066 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2067 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2068 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2069 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2070 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2071 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2072 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2073 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2074 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].EnergyConverterH | EnergyConverter_2075 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2076 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2077 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2078 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2079 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2080 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2081 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2082 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2084 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2085 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].EnergyConverterH | EnergyConverter_2086 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2087 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2088 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2089 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2090 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2091 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2092 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2093 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2094 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2095 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2096 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].EnergyConverterH | EnergyConverter_2097 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2098 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2099 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2100 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2101 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2102 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2103 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2104 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2105 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2106 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2107 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].EnergyConverterH | EnergyConverter_2108 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2109 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2110 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2111 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2112 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2113 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2114 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2115 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2116 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2117 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2118 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].EnergyConverterH | EnergyConverter_2119 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2120 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2121 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2122 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2123 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2124 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2125 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2126 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2127 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2128 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2129 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].EnergyConverterH | EnergyConverter_2130 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2131 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2132 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2133 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2134 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2135 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2136 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2137 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2138 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2139 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2140 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].EnergyConverterH | EnergyConverter_2141 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2142 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2143 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2144 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2145 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2146 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2147 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2148 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2149 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2150 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2151 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].EnergyConverterH | EnergyConverter_2152 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2153 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2154 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2155 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2156 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2157 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2158 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2159 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2160 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2161 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2162 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].EnergyConverterH | EnergyConverter_2163 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2164 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2165 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2166 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2167 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2168 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2169 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2170 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2171 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2172 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2173 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].EnergyConverterH | EnergyConverter_2174 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2175 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2176 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2177 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2178 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2179 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2180 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2181 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2183 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2184 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].EnergyConverterH | EnergyConverter_2185 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2186 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2187 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2188 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2189 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2190 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2191 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2192 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2193 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2194 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2195 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].EnergyConverterH | EnergyConverter_2196 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2197 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2198 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2199 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2200 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2201 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2202 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2203 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2204 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2205 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2206 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].EnergyConverterH | EnergyConverter_2207 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2208 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2209 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2210 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2211 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2212 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2213 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2214 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2215 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2216 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2217 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].EnergyConverterH | EnergyConverter_2218 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2219 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2220 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2221 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2222 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2223 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2224 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2225 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2227 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2228 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].EnergyConverterH | EnergyConverter_2229 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2230 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2231 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2232 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2233 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2234 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2235 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2236 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2237 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2238 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2239 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_PARAMETER_RAM | AlgoParameterRAM_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (IPBUS_ALGO_PARAMETER_RAM) | AlgoParameterRAM_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_PARAMETER_RAM | AlgoParameterRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | AlgoParameterRAM_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | AlgoParameterRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized7 | 5541(1.60%) | 5541(1.60%) | 0(0.00%) | 0(0.00%) | 2059(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LOAD_GENERATOR | LoadGenerator | 120(0.03%) | 118(0.03%) | 0(0.00%) | 2(0.01%) | 121(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RATE_MONITOR | AlgoRateMonitor | 1923(0.56%) | 1922(0.55%) | 0(0.00%) | 1(0.01%) | 3215(0.46%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RATE_MONITOR) | AlgoRateMonitor | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized6 | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | NORMALISATION_CNT | counter | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_EG | counter_1485 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_TAU | counter_1486 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_EG | counter_1487 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_TAU | counter_1488 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_EG | counter_1489 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_TAU | counter_1490 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_EG | counter_1491 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_TAU | counter_1492 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_EG | counter_1493 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_TAU | counter_1494 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_EG | counter_1495 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_TAU | counter_1496 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_EG | counter_1497 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_TAU | counter_1498 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_EG | counter_1499 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_TAU | counter_1500 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_EG | counter_1501 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_TAU | counter_1502 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_EG | counter_1503 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_TAU | counter_1504 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_EG | counter_1505 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_TAU | counter_1506 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_EG | counter_1507 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_TAU | counter_1508 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_EG | counter_1509 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_TAU | counter_1510 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_EG | counter_1511 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_TAU | counter_1512 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_EG | counter_1513 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_TAU | counter_1514 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_EG | counter_1515 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_TAU | counter_1516 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_EG | counter_1517 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_TAU | counter_1518 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_EG | counter_1519 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_TAU | counter_1520 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_EG | counter_1521 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_TAU | counter_1522 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_EG | counter_1523 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_TAU | counter_1524 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_EG | counter_1525 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_TAU | counter_1526 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_EG | counter_1527 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_TAU | counter_1528 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_EG | counter_1529 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_TAU | counter_1530 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_EG | counter_1531 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_TAU | counter_1532 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_EG | counter_1533 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_TAU | counter_1534 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_EG | counter_1535 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_TAU | counter_1536 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_EG | counter_1537 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_TAU | counter_1538 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_EG | counter_1539 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_TAU | counter_1540 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_EG | counter_1541 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_TAU | counter_1542 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_EG | counter_1543 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_TAU | counter_1544 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_EG | counter_1545 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_TAU | counter_1546 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_EG | counter_1547 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_TAU | counter_1548 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_EG | counter_1549 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_TAU | counter_1550 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_EG | counter_1551 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_TAU | counter_1552 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_EG | counter_1553 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_TAU | counter_1554 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_EG | counter_1555 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_TAU | counter_1556 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_EG | counter_1557 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_TAU | counter_1558 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_EG | counter_1559 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_TAU | counter_1560 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_EG | counter_1561 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_TAU | counter_1562 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_EG | counter_1563 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_TAU | counter_1564 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_EG | counter_1565 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_TAU | counter_1566 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_EG | counter_1567 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_TAU | counter_1568 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_EG | counter_1569 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_TAU | counter_1570 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_EG | counter_1571 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_TAU | counter_1572 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_EG | counter_1573 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_TAU | counter_1574 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_EG | counter_1575 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_TAU | counter_1576 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_EG | counter_1577 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_TAU | counter_1578 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_EG | counter_1579 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_TAU | counter_1580 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOP_ALGO_MODULE | TopAlgoModule | 83755(24.18%) | 82253(23.75%) | 0(0.00%) | 1502(0.86%) | 126158(18.21%) | 0(0.00%) | 0(0.00%) | 120(4.17%) | | (TOP_ALGO_MODULE) | TopAlgoModule | 81494(23.53%) | 81494(23.53%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[0].AGLO_CORE_EG | AlgoCore_eg__xdcDup__1 | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7305(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[0].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__1 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5469 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_5470 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5471 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_5472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_5473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_5473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | 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stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_5661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_5662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_5663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_5665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_5666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 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Adder__sblockDup__1_5673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_5675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_5676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_5677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_5678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_5679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_5680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_5681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_5682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_5683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_5684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_5685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_5474 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_5474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5558 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_5475 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_5475 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5476 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 124(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5476 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5479 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5479 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_5480 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_5481 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5482 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[0].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__1 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6852(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[0].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__1 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5258 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_5259 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_5259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5440 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5260 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_5261 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_5262 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_5263 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_5264 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_5264 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_5265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_5265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_5266 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_5266 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_5268 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_5277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_5277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_5278 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_5279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[1].AGLO_CORE_EG | AlgoCore_eg__xdcDup__2 | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7307(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[1].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__2 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5035 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_5036 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5037 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_5038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_5039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_5039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_5174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_5175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_5176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_5177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_5178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_5179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_5180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_5181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_5182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_5185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_5186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_5193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_5194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_5195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_5196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_5197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_5198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_5199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_5200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_5201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_5202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_5203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_5204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_5205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_5206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_5207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_5209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_5210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_5211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_5213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_5214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_5215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_5217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_5218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_5219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_5220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_5221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_5222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_5228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_5229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_5230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_5231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_5232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_5233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_5234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_5235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_5237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_5238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_5240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_5241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_5242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_5243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_5244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_5245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_5247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_5248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_5249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_5250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_5251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_5252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_5253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_5254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_5255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_5256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_5257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_5040 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_5040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5124 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_5041 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_5041 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5042 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5042 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5045 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5045 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_5046 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_5047 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5048 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[1].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__2 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6866(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[1].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__2 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4824 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_4825 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_4825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5006 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4826 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_4827 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_4828 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_4829 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_4830 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_4830 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_4832 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_4832 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_4834 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_4844 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[2].AGLO_CORE_EG | AlgoCore_eg__xdcDup__3 | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7300(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[2].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__3 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4601 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_4602 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4603 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_4604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_4605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_4605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4716 | 0(0.00%) | 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0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_4606 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_4606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4690 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_4607 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_4607 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4608 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4608 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4611 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4611 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_4612 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_4613 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4614 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[2].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__3 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6857(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[2].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__3 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4390 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_4391 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_4391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4572 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_4595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_4596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_4597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_4598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_4600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4392 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_4393 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_4394 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_4395 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_4396 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_4396 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_4397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_4397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_4398 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_4398 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_4399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_4399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_4400 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_4409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_4409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_4410 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[3].AGLO_CORE_EG | AlgoCore_eg__xdcDup__4 | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7300(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[3].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__4 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4167 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_4168 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4169 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_4170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_4171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_4171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_4306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_4307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_4308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_4309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_4310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_4311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_4312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_4314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_4315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_4317 | 0(0.00%) | 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0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_4172 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_4172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4256 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_4173 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_4173 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4174 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4174 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4177 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4177 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_4178 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_4179 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4180 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[3].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__4 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6850(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[3].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__4 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3956 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_3957 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_3957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4138 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_4161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_4162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_4163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_4164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_4165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_4166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3958 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_3959 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_3960 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_3961 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_3962 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_3962 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_3963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_3963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_3964 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_3964 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_3965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_3965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_3966 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_3976 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[4].AGLO_CORE_EG | AlgoCore_eg__xdcDup__5 | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7300(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[4].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__5 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3733 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_3734 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3735 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_3736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_3737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_3737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_3907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_3908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_3909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_3910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_3912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_3913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_3915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_3916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_3917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_3918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_3920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_3921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_3922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_3925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_3926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_3927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_3928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_3929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_3930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_3931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_3932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_3933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_3934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_3935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_3738 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3822 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_3739 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_3739 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3740 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3740 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3743 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3743 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_3744 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_3745 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3746 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[4].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__5 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6850(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[4].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__5 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3522 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_3523 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_3523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3704 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3524 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_3525 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_3526 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_3527 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_3528 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_3528 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_3529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_3529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_3530 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_3530 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_3531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_3531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_3532 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_3542 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[5].AGLO_CORE_EG | AlgoCore_eg__xdcDup__6 | 123(0.04%) | 38(0.01%) | 0(0.00%) | 85(0.05%) | 7301(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[5].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__6 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3299 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_3300 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3301 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3438 | 0(0.00%) | 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0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_3304 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_3304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3388 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_3305 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_3305 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3306 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3306 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3309 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3309 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_3310 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_3311 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3312 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[5].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__6 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6850(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[5].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__6 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3088 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_3089 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3270 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3090 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_3091 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_3092 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_3093 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_3094 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_3094 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_3096 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_3096 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_3098 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_3108 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[6].AGLO_CORE_EG | AlgoCore_eg__xdcDup__7 | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7301(1.05%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[6].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__7 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_2865 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_2866 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_2867 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_2868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_2870 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2954 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1_2871 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 431(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1_2871 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_2872 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_2872 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_2875 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_2875 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_2876 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_2877 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_2878 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[6].AGLO_CORE_TAU | AlgoCore_tau__xdcDup__7 | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6850(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[6].AGLO_CORE_TAU) | AlgoCore_tau__xdcDup__7 | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_2654 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1_2655 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1_2655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2836 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_2850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_2856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_2859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_2864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_2656 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1_2657 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1_2658 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1_2659 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1_2660 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1_2660 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1_2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1_2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_2662 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_2662 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1_2664 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1_2674 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[7].AGLO_CORE_EG | AlgoCore_eg | 124(0.04%) | 38(0.01%) | 0(0.00%) | 86(0.05%) | 7320(1.06%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[7].AGLO_CORE_EG) | AlgoCore_eg | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_2439 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_2440 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__xdcDup__38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3594(0.52%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 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0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_2627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_2628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_2629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_2630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_2631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_2632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_2633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_2634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_2635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_2636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_2637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_2638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_2639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_2640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_2641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_2642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_2643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_2644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_2645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_2646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_2647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_2648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_2649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_2650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_2651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_2652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_2653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized0__sblockDup__1_2441 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized0__sblockDup__1_2441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2520 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized3__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 432(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized3__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_2442 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 123(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_2442 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[7].AGLO_CORE_TAU | AlgoCore_tau | 159(0.05%) | 57(0.02%) | 0(0.00%) | 102(0.06%) | 6850(0.99%) | 0(0.00%) | 0(0.00%) | 6(0.21%) | | (ALGO_GENERATION[7].AGLO_CORE_TAU) | AlgoCore_tau | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ENERGY_ADDER | MultiAdder__parameterized4__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 765(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (ENERGY_ADDER) | MultiAdder__parameterized4__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2410 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_2423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_2424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_2425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_2427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_2428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_2429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_2432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_2433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_2436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_2437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | tauInputMultiplexer__sblockDup__1 | 48(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.03%) | 3284(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Jet_MULTIPLIER | MultiMultiplier__xdcDup__39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].MULTIPLIER | Mult_HD416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].MULTIPLIER | Mult_HD420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].MULTIPLIER | Mult_HD424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | LITTLE_SEED_DELAY | GeneralDelay__parameterized4__sblockDup__1 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LITTLE_SEED_FINDER | LittleSeedFinder__sblockDup__1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_CORE | MultiAdder__parameterized1__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_CORE) | MultiAdder__parameterized1__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Frac_ENV | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Frac_ENV) | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_CORE | MultiAdder__parameterized1__sblockDup__1_2240 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_CORE) | MultiAdder__parameterized1__sblockDup__1_2240 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_Jet_ENV | MultiAdder__parameterized0__sblockDup__1_2241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_Jet_ENV) | MultiAdder__parameterized0__sblockDup__1_2241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized5__sblockDup__1 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[0].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[0].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[1].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[1].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[2].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[2].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[3].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[3].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[4].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[4].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[5].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[5].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[6].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[6].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[7].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[7].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SF_ADDER_FOR[8].SEED_FINDER_ADDER | MultiAdder__parameterized0__sblockDup__1_2250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 216(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SF_ADDER_FOR[8].SEED_FINDER_ADDER) | MultiAdder__parameterized0__sblockDup__1_2250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_DELAY | GeneralDelay__parameterized3__sblockDup__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_SHIFT_REGISTER | AlgoShiftRegister | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12725(1.84%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_eg | SerialSorter | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 481(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_eg) | SerialSorter | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1480 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1481 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1482 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1483 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1484 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_tau | SerialSorter_1391 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_tau) | SerialSorter_1391 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1475 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1476 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1477 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1478 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1479 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_eg | SerialSorter_1392 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_eg) | SerialSorter_1392 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1470 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1471 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1472 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1473 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1474 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_tau | SerialSorter_1393 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_tau) | SerialSorter_1393 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1465 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1466 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1467 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1468 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1469 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_eg | SerialSorter_1394 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_eg) | SerialSorter_1394 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1460 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1461 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1462 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1463 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1464 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_tau | SerialSorter_1395 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_tau) | SerialSorter_1395 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1455 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1456 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1457 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1458 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1459 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_eg | SerialSorter_1396 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_eg) | SerialSorter_1396 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1450 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1451 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1452 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1453 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1454 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_tau | SerialSorter_1397 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_tau) | SerialSorter_1397 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1445 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1446 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1447 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1448 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1449 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_eg | SerialSorter_1398 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_eg) | SerialSorter_1398 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1440 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1441 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1442 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1443 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1444 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_tau | SerialSorter_1399 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_tau) | SerialSorter_1399 | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1435 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1436 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1437 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1438 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1439 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_eg | SerialSorter_1400 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_eg) | SerialSorter_1400 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1430 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1431 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1432 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1433 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1434 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_tau | SerialSorter_1401 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_tau) | SerialSorter_1401 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1425 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1426 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1427 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1428 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1429 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_eg | SerialSorter_1402 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_eg) | SerialSorter_1402 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1420 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1421 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1422 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1423 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1424 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_tau | SerialSorter_1403 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_tau) | SerialSorter_1403 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1415 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1416 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1417 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1418 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1419 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_eg | SerialSorter_1404 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_eg) | SerialSorter_1404 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1410 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1411 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1412 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1413 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1414 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_tau | SerialSorter_1405 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_tau) | SerialSorter_1405 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1406 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1407 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1408 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1409 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_alignment_block | data_alignment | 19692(5.68%) | 7194(2.08%) | 0(0.00%) | 12498(7.17%) | 37512(5.41%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_alignment_block) | data_alignment | 180(0.05%) | 180(0.05%) | 0(0.00%) | 0(0.00%) | 848(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[0].bc_align_b | quad_bc_alignment | 117(0.03%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[0].bc_align_b) | quad_bc_alignment | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1387 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1388 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1389 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1390 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[10].bc_align_b | quad_bc_alignment_580 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[10].bc_align_b) | quad_bc_alignment_580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1380 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1381 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1382 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1383 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[12].bc_align_b | quad_bc_alignment_581 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[12].bc_align_b) | quad_bc_alignment_581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1372 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1373 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1374 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1375 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[13].bc_align_b | quad_bc_alignment_582 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[13].bc_align_b) | quad_bc_alignment_582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1364 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1365 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1366 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1367 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[14].bc_align_b | quad_bc_alignment_583 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[14].bc_align_b) | quad_bc_alignment_583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1356 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1357 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1358 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1359 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[15].bc_align_b | quad_bc_alignment_584 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[15].bc_align_b) | quad_bc_alignment_584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1348 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1349 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1350 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1351 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[1].bc_align_b | quad_bc_alignment_585 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[1].bc_align_b) | quad_bc_alignment_585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1340 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1341 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1342 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1343 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[2].bc_align_b | quad_bc_alignment_586 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[2].bc_align_b) | quad_bc_alignment_586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1332 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1333 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1334 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1335 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[3].bc_align_b | quad_bc_alignment_587 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[3].bc_align_b) | quad_bc_alignment_587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1324 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1325 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1326 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1327 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[4].bc_align_b | quad_bc_alignment_588 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[4].bc_align_b) | quad_bc_alignment_588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1316 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1317 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1318 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1319 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[5].bc_align_b | quad_bc_alignment_589 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[5].bc_align_b) | quad_bc_alignment_589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1308 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1309 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1310 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1311 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[6].bc_align_b | quad_bc_alignment_590 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[6].bc_align_b) | quad_bc_alignment_590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1300 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1301 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1302 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1303 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[7].bc_align_b | quad_bc_alignment_591 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[7].bc_align_b) | quad_bc_alignment_591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1292 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1293 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1294 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1295 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[8].bc_align_b | quad_bc_alignment_592 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[8].bc_align_b) | quad_bc_alignment_592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1284 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1285 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1286 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1287 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[9].bc_align_b | quad_bc_alignment_593 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[9].bc_align_b) | quad_bc_alignment_593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1276 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1277 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1278 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1279 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[0].bc_align_a | quad_bc_alignment_594 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[0].bc_align_a) | quad_bc_alignment_594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1268 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1269 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1270 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1271 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[10].bc_align_a | quad_bc_alignment_595 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[10].bc_align_a) | quad_bc_alignment_595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1261 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1262 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1263 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1264 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[12].bc_align_a | quad_bc_alignment_597 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[12].bc_align_a) | quad_bc_alignment_597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1249 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1250 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1251 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1252 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[13].bc_align_a | quad_bc_alignment_598 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[13].bc_align_a) | quad_bc_alignment_598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1241 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1242 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1243 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1244 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[14].bc_align_a | quad_bc_alignment_599 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[14].bc_align_a) | quad_bc_alignment_599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1233 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1234 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1235 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1236 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[15].bc_align_a | quad_bc_alignment_600 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[15].bc_align_a) | quad_bc_alignment_600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1225 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1226 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1227 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1228 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[1].bc_align_a | quad_bc_alignment_601 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[1].bc_align_a) | quad_bc_alignment_601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1217 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1218 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1219 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1220 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[2].bc_align_a | quad_bc_alignment_602 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[2].bc_align_a) | quad_bc_alignment_602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1209 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1210 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1211 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1212 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[3].bc_align_a | quad_bc_alignment_603 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[3].bc_align_a) | quad_bc_alignment_603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1201 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1202 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1203 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1204 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[4].bc_align_a | quad_bc_alignment_604 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[4].bc_align_a) | quad_bc_alignment_604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1193 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1194 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1195 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1196 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[5].bc_align_a | quad_bc_alignment_605 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[5].bc_align_a) | quad_bc_alignment_605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1185 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1186 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1187 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1188 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[6].bc_align_a | quad_bc_alignment_606 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[6].bc_align_a) | quad_bc_alignment_606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1177 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1178 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1179 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1180 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[7].bc_align_a | quad_bc_alignment_607 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[7].bc_align_a) | quad_bc_alignment_607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1169 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1170 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1171 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1172 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[8].bc_align_a | quad_bc_alignment_608 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[8].bc_align_a) | quad_bc_alignment_608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1161 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1162 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1163 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1164 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[9].bc_align_a | quad_bc_alignment_609 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[9].bc_align_a) | quad_bc_alignment_609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1154 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1155 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1156 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo | pseudo_orbit_gen | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo_b | pseudo_orbit_gen_610 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u0 | top_synch | 273(0.08%) | 24(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u0) | top_synch | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1145 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1146 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1147 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1148 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1148 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1149 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u1 | crc_checker | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u1) | crc_checker | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1143 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u0 | top_synch_611 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u0) | top_synch_611 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1137 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1138 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1139 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1140 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1141 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1141 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1142 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u1 | crc_checker_612 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u1) | crc_checker_612 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1136 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u0 | top_synch_613 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u0) | top_synch_613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1131 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1132 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1133 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1134 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1134 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1135 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u1 | crc_checker_614 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u1) | crc_checker_614 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1129 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u0 | top_synch_615 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u0) | top_synch_615 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1123 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1124 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1125 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1126 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1127 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1127 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1128 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u1 | crc_checker_616 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u1) | crc_checker_616 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1122 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u0 | top_synch_617 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u0) | top_synch_617 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1117 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1118 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1119 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1120 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1120 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1121 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u1 | crc_checker_618 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u1) | crc_checker_618 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1115 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u0 | top_synch_619 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u0) | top_synch_619 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1109 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1110 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1111 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1112 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1113 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1113 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1114 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u1 | crc_checker_620 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u1) | crc_checker_620 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1108 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u0 | top_synch_621 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u0) | top_synch_621 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1103 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1104 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1105 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1106 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1106 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1107 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u1 | crc_checker_622 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u1) | crc_checker_622 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1101 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u0 | top_synch_623 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u0) | top_synch_623 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1096 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1097 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1098 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1099 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1099 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1100 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u1 | crc_checker_624 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u1) | crc_checker_624 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1094 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u0 | top_synch_625 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u0) | top_synch_625 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1088 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1089 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1090 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1091 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1092 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1092 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1093 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u1 | crc_checker_626 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u1) | crc_checker_626 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1087 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u0 | top_synch_627 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u0) | top_synch_627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1081 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1082 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1083 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1084 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1085 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1085 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1086 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u1 | crc_checker_628 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u1) | crc_checker_628 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1080 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u0 | top_synch_629 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u0) | top_synch_629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1075 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1076 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1077 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1078 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1078 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1079 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u1 | crc_checker_630 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u1) | crc_checker_630 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1073 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u0 | top_synch_631 | 273(0.08%) | 24(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u0) | top_synch_631 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1067 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1068 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1069 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1070 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1071 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1071 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1072 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u1 | crc_checker_632 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u1) | crc_checker_632 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1066 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u0 | top_synch_633 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u0) | top_synch_633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1060 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1061 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1062 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1063 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1064 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1064 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1065 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u1 | crc_checker_634 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u1) | crc_checker_634 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1059 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u0 | top_synch_635 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u0) | top_synch_635 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1053 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1054 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1055 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1056 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1057 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1057 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1058 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u1 | crc_checker_636 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u1) | crc_checker_636 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1052 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u0 | top_synch_637 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u0) | top_synch_637 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1047 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1048 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1049 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1050 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1050 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1051 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u1 | crc_checker_638 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u1) | crc_checker_638 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1045 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u0 | top_synch_639 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u0) | top_synch_639 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1040 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1041 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1042 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1043 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1043 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1044 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u1 | crc_checker_640 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u1) | crc_checker_640 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1038 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u0 | top_synch_641 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u0) | top_synch_641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1032 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1033 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1034 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1035 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1036 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1036 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1037 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u1 | crc_checker_642 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u1) | crc_checker_642 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1031 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u0 | top_synch_643 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u0) | top_synch_643 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1025 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1026 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1027 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1028 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1029 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1029 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1030 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u1 | crc_checker_644 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u1) | crc_checker_644 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1024 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u0 | top_synch_645 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u0) | top_synch_645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1018 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1019 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1020 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1021 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1022 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1022 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1023 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u1 | crc_checker_646 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u1) | crc_checker_646 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1017 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u0 | top_synch_647 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u0) | top_synch_647 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1012 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1013 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1014 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1015 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1015 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1016 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u1 | crc_checker_648 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u1) | crc_checker_648 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1010 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u0 | top_synch_649 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u0) | top_synch_649 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1005 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1006 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1007 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1008 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1008 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1009 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u1 | crc_checker_650 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u1) | crc_checker_650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1003 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u0 | top_synch_651 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u0) | top_synch_651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_997 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_998 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_999 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1000 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1001 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1001 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1002 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u1 | crc_checker_652 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u1) | crc_checker_652 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_996 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u0 | top_synch_653 | 273(0.08%) | 24(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u0) | top_synch_653 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_991 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_992 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_993 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_994 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_994 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_995 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u1 | crc_checker_654 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u1) | crc_checker_654 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_989 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u0 | top_synch_655 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u0) | top_synch_655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_983 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_984 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_985 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_986 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_987 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_987 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_988 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u1 | crc_checker_656 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u1) | crc_checker_656 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_982 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u0 | top_synch_657 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u0) | top_synch_657 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_976 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_977 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_978 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_979 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_980 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_980 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_981 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u1 | crc_checker_658 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u1) | crc_checker_658 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_975 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u0 | top_synch_659 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u0) | top_synch_659 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_969 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_970 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_971 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_972 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_973 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_973 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_974 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u1 | crc_checker_660 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u1) | crc_checker_660 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_968 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u0 | top_synch_661 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u0) | top_synch_661 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_962 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_963 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_964 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_965 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_966 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_966 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_967 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u1 | crc_checker_662 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u1) | crc_checker_662 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_961 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u0 | top_synch_663 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u0) | top_synch_663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_955 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_956 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_957 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_958 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_959 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_959 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_960 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u1 | crc_checker_664 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u1) | crc_checker_664 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_954 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u0 | top_synch_665 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u0) | top_synch_665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_948 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_949 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_950 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_951 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_952 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_952 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_953 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u1 | crc_checker_666 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u1) | crc_checker_666 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_947 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u0 | top_synch_667 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u0) | top_synch_667 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_941 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_942 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_943 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_944 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_945 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_945 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_946 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u1 | crc_checker_668 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u1) | crc_checker_668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_940 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u0 | top_synch_669 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u0) | top_synch_669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_934 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_935 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_936 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_937 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_938 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_938 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_939 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u1 | crc_checker_670 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u1) | crc_checker_670 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_933 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u0 | top_synch_671 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u0) | top_synch_671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_927 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_928 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_929 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_930 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_931 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_931 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_932 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u1 | crc_checker_672 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u1) | crc_checker_672 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_926 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u0 | top_synch_673 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u0) | top_synch_673 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_921 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_922 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_923 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_924 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_924 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_925 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u1 | crc_checker_674 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u1) | crc_checker_674 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_919 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u0 | top_synch_675 | 273(0.08%) | 24(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u0) | top_synch_675 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_913 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_914 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_915 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_916 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_917 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_917 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_918 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u1 | crc_checker_676 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u1) | crc_checker_676 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_912 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[40].u0 | top_synch_677 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[40].u0) | top_synch_677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_907 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_908 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_909 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_910 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_910 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_911 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[40].u1 | crc_checker_678 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[40].u1) | crc_checker_678 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_905 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[41].u0 | top_synch_679 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[41].u0) | top_synch_679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_899 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_900 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_901 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_902 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_903 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_903 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_904 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[41].u1 | crc_checker_680 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[41].u1) | crc_checker_680 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_898 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[42].u0 | top_synch_681 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[42].u0) | top_synch_681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_893 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_894 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_895 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_896 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_896 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_897 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[42].u1 | crc_checker_682 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[42].u1) | crc_checker_682 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_891 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[43].u0 | top_synch_683 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[43].u0) | top_synch_683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_886 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_887 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_888 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_889 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_889 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_890 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[43].u1 | crc_checker_684 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[43].u1) | crc_checker_684 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_884 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u0 | top_synch_689 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u0) | top_synch_689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_875 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_876 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_877 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_878 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_878 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_879 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u1 | crc_checker_690 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u1) | crc_checker_690 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_873 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u0 | top_synch_691 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u0) | top_synch_691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_868 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_869 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_870 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_871 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_871 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_872 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u1 | crc_checker_692 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u1) | crc_checker_692 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_866 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u0 | top_synch_693 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u0) | top_synch_693 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_860 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_861 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_862 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_863 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_864 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_864 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_865 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u1 | crc_checker_694 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u1) | crc_checker_694 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_859 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u0 | top_synch_695 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u0) | top_synch_695 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_853 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_854 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_855 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_856 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_857 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_857 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_858 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u1 | crc_checker_696 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u1) | crc_checker_696 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_852 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u0 | top_synch_697 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u0) | top_synch_697 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_846 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_847 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_848 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_849 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_850 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_850 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_851 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u1 | crc_checker_698 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u1) | crc_checker_698 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_845 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u0 | top_synch_699 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u0) | top_synch_699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_839 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_840 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_841 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_842 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_843 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_843 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_844 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u1 | crc_checker_700 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u1) | crc_checker_700 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_838 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u0 | top_synch_701 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u0) | top_synch_701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_832 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_833 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_834 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_835 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_836 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_836 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_837 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u1 | crc_checker_702 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u1) | crc_checker_702 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_831 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u0 | top_synch_703 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u0) | top_synch_703 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_826 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_827 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_828 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_829 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_829 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_830 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u1 | crc_checker_704 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u1) | crc_checker_704 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_824 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u0 | top_synch_705 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u0) | top_synch_705 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_819 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_820 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_821 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_822 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_822 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_823 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u1 | crc_checker_706 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u1) | crc_checker_706 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_817 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u0 | top_synch_707 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u0) | top_synch_707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_812 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_813 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_814 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_815 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_815 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_816 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u1 | crc_checker_708 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u1) | crc_checker_708 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_810 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u0 | top_synch_709 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u0) | top_synch_709 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_805 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_806 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_807 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_808 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_808 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_809 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u1 | crc_checker_710 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u1) | crc_checker_710 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_803 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u0 | top_synch_711 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u0) | top_synch_711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_797 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_798 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_799 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_800 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_801 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_801 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_802 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u1 | crc_checker_712 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u1) | crc_checker_712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_796 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u0 | top_synch_713 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u0) | top_synch_713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_790 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_791 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_792 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_793 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_794 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_794 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_795 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u1 | crc_checker_714 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u1) | crc_checker_714 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_789 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u0 | top_synch_715 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u0) | top_synch_715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_784 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_785 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_786 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_787 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_787 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_788 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u1 | crc_checker_716 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u1) | crc_checker_716 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_782 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u0 | top_synch_717 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u0) | top_synch_717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_777 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_778 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_779 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_780 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_780 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_781 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u1 | crc_checker_718 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u1) | crc_checker_718 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_775 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u0 | top_synch_719 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u0) | top_synch_719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_769 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_770 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_771 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_772 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_773 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_773 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_774 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u1 | crc_checker_720 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u1) | crc_checker_720 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_768 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u0 | top_synch_721 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u0) | top_synch_721 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_762 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_763 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_764 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_765 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_766 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_766 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_767 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u1 | crc_checker_722 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u1) | crc_checker_722 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_761 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u0 | top_synch_723 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u0) | top_synch_723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_756 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_757 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_758 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_759 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_759 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_760 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u1 | crc_checker_724 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u1) | crc_checker_724 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_754 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u0 | top_synch_725 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u0) | top_synch_725 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_748 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_749 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_750 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_751 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_752 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_752 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_753 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u1 | crc_checker_726 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u1) | crc_checker_726 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_747 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u0 | top_synch_727 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u0) | top_synch_727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_742 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_743 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_744 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_745 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_745 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_746 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u1 | crc_checker_728 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u1) | crc_checker_728 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_740 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u0 | top_synch_729 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u0) | top_synch_729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_735 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_736 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_737 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_738 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_738 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_739 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u1 | crc_checker_730 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u1) | crc_checker_730 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_733 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u0 | top_synch_731 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u0) | top_synch_731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u1 | crc_checker_732 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u1) | crc_checker_732 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bcn_cntr | local_bcn_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_TX_RX | MGT_4_quad_gen | 9991(2.88%) | 9991(2.88%) | 0(0.00%) | 0(0.00%) | 17936(2.59%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__1 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__1 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__1 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_578 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD611 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD612 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD612 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD613 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD613 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD615 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD616 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD616 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD617 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD619 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD620 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD624 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD624 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD625 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD626 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD627 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD630 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD631 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD633 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD635 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD636 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD637 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD637 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD638 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD644 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD644 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD646 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD647 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD647 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD648 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD650 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD655 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD655 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD656 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD662 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD662 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD664 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD665 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD665 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD666 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD668 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD673 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD673 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD674 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD680 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD680 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD682 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD683 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD683 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD684 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD686 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD687 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD691 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD691 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD692 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD698 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD702 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[10].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__8 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__8 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__8 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_575 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1807 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1808 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1808 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1809 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1809 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1812 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1812 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1813 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1815 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1816 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1820 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1820 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1822 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1823 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1824 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1826 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1829 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1830 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1831 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1832 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1833 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1833 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1834 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1836 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1840 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1840 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1842 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1843 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1843 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1844 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1846 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1847 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1851 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1851 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1852 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1854 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1858 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1858 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1860 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1861 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1861 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1862 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1864 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1865 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1869 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1869 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1870 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1872 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1876 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1876 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1878 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1879 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1879 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1880 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1882 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1883 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1887 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1887 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1888 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1890 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1894 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1895 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1896 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1897 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1898 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[11].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__9 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__9 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__9 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__9 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_572 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1899 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1900 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1900 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1901 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1904 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1904 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1907 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1908 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1912 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1912 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1913 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1914 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1915 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1916 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1917 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1918 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1921 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1923 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1924 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1925 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1925 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1926 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1928 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1932 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1932 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1934 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1935 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1935 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1936 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1938 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1939 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1943 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1943 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1944 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1946 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1950 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1950 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1952 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1953 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1953 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1954 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1956 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1957 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1961 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1961 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1962 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1964 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1968 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1968 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1970 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1971 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1971 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1972 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1974 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1979 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1979 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1980 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1982 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1986 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1987 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1988 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1989 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1990 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[12].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__10 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__10 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__10 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__10 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_569 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD703 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD704 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD704 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD705 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD708 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD708 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD709 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD711 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD716 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD716 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD718 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD719 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD721 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD722 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD725 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD728 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD729 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD729 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD730 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD736 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD736 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD738 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD739 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD739 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD740 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD742 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD743 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD747 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD747 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD748 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD754 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD754 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD756 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD757 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD757 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD758 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD760 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD761 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD765 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD765 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD766 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD768 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD772 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD772 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD774 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD775 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD775 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD776 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD778 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD783 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD783 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD784 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD786 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD790 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD792 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD794 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[13].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__11 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__11 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__11 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__11 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_566 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD795 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD796 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD796 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD797 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD797 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD799 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD800 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD800 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD801 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD803 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD808 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD808 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD809 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD810 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD811 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD812 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD814 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD815 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD816 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD817 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD820 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD821 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD821 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD822 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD824 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD828 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD828 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD830 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD831 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD831 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD832 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD834 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD835 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD839 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD839 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD840 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD842 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD846 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD846 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD848 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD849 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD849 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD850 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD852 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD853 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD857 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD857 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD858 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD860 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD864 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD864 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD866 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD867 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD867 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD868 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD870 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD871 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD875 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD875 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD876 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD882 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD883 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD886 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[14].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__12 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__12 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__12 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__12 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_563 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD887 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD888 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD888 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD889 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD889 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD891 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD892 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD892 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD893 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD895 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD896 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD900 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD900 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD901 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD902 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD903 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD904 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD906 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD907 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD908 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD909 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD911 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD912 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD913 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD913 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD914 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD916 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD920 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD920 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD922 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD923 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD923 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD924 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD926 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD927 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD931 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD931 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD932 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD934 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD938 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD938 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD940 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD941 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD941 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD942 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD944 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD945 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD949 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD949 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD950 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD952 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD956 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD956 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD958 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD959 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD959 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD960 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD962 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD963 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD967 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD967 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD968 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD974 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD976 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD977 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD978 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[16].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__13 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__13 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__13 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__13 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_560 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD979 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD980 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD980 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD981 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD981 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD983 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD984 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD984 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD985 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD987 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD988 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD992 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD992 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD993 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD994 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD995 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD996 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD997 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD998 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD999 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1000 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1002 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1004 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1005 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1005 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1006 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1008 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1012 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1012 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1014 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1015 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1015 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1016 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1018 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1023 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1023 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1024 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1026 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1030 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1030 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1032 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1033 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1033 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1034 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1036 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1037 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1041 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1041 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1042 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1044 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1048 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1048 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1050 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1051 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1051 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1052 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1054 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1055 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1059 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1059 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1060 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1062 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1066 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1067 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1068 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1069 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1070 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[17].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__14 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__14 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__14 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__14 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_557 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1071 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1072 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1072 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1073 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1073 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1076 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1076 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1077 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1079 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1084 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1084 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1085 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1086 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1087 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1088 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1089 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1090 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1092 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1093 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1096 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1097 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1097 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1098 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1100 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1104 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1104 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1107 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1107 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1108 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1110 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1111 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1115 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1115 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1116 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1118 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1122 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1122 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1124 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1125 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1125 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1126 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1128 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1133 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1133 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1134 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1140 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1140 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1142 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1143 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1143 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1144 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1146 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1151 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1151 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1152 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1158 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1160 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1162 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[18].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__15 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__15 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__15 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__15 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_554 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1163 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1164 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1164 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1165 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1167 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1168 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1168 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1169 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1171 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1176 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1176 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1177 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1178 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1179 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1180 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1182 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1185 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1186 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1187 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1188 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1189 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1189 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1190 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1196 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1196 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1198 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1199 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1199 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1200 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1202 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1203 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1207 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1207 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1208 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1214 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1214 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1216 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1217 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1217 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1218 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1220 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1225 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1225 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1226 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1232 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1232 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1234 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1235 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1235 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1236 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1238 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1243 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1243 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1244 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1250 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1251 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1252 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1253 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1254 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[19].mgt_1quad_Rx_Tx | mgt_selection_wrapper | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_551 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[1].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__2 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__2 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__2 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__2 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_548 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1255 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1256 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1256 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1257 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1257 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1259 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1260 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1260 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1261 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1263 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1264 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1268 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1268 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1270 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1271 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1274 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1276 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1277 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1278 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1279 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1280 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1281 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1281 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1282 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1288 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1288 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1290 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1291 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1291 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1292 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1294 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1295 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1299 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1299 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1300 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1302 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1306 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1306 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1308 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1309 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1309 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1310 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1312 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1313 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1317 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1317 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1318 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1324 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1324 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1326 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1327 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1327 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1328 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1330 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1335 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1335 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1336 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1342 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1344 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1346 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[5].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__3 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__3 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__3 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_545 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1347 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1348 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1348 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1349 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1349 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1351 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1352 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1352 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1353 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1355 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1356 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1360 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1360 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1361 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1362 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1363 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1366 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1368 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1372 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1373 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1373 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1374 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1376 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1380 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1380 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1382 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1383 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1383 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1384 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1386 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1387 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1391 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1391 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1392 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1394 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1398 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1398 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1400 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1401 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1401 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1402 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1404 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1409 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1409 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1410 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1412 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1416 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1416 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1418 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1419 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1419 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1420 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1422 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1427 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1427 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1428 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1434 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1435 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1436 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1437 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1438 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[6].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__4 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__4 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__4 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__4 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_542 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1439 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1440 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1440 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1441 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1441 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1443 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1444 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1444 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1445 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1447 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1448 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1452 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1452 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1454 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1455 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1456 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1457 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1458 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1460 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1461 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1463 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1464 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1465 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1465 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1466 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1472 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1472 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1474 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1475 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1475 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1476 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1478 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1479 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1483 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1483 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1484 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1490 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1490 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1492 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1493 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1493 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1494 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1496 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1497 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1501 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1501 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1502 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1504 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1508 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1508 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1510 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1511 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1511 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1512 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1514 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1515 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1519 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1519 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1520 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1522 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1526 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1530 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[7].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__5 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__5 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__5 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__5 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_539 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1531 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1532 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1532 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1533 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1533 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1535 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1536 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1536 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1537 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1539 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1540 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1544 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1544 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1546 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1547 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1548 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1549 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1550 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1551 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1553 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1554 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1556 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1557 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1557 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1558 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1560 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1564 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1564 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1566 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1567 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1567 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1568 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1570 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1571 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1575 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1575 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1576 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1578 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1582 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1582 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1584 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1585 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1585 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1586 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1588 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1589 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1593 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1593 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1594 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1596 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1600 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1600 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1602 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1603 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1603 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1604 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1606 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1607 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1611 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1611 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1612 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1614 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1618 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1619 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1620 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1621 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1622 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[8].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__6 | 621(0.18%) | 621(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__6 | 621(0.18%) | 621(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__6 | 621(0.18%) | 621(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_536 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1623 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1624 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1624 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1625 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1625 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1628 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1628 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1629 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1631 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1636 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1636 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1637 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1638 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1639 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1642 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1643 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1644 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1645 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1647 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1648 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1649 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1649 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1650 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1652 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1656 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1656 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1658 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1659 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1659 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1660 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1662 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1667 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1667 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1668 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1674 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1674 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1676 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1677 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1677 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1678 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1680 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1685 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1685 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1686 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1688 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1692 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1692 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1694 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1695 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1695 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1696 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1698 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1703 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1703 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1704 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1710 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1714 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[9].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__7 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__7 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__7 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1715 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1716 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1716 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1717 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1720 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1720 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1721 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1723 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1728 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1728 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1730 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1731 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1733 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1734 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1737 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1740 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1741 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1741 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1742 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1748 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1748 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1750 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1751 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1751 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1752 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1754 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1759 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1759 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1760 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1762 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1766 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1766 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1768 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1769 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1769 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1770 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1772 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1777 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1777 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1778 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1784 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1784 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1786 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1787 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1787 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1788 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1790 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1795 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1795 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1796 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1802 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1803 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1806 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_ipb | mgt_slaves | 35619(10.28%) | 35619(10.28%) | 0(0.00%) | 0(0.00%) | 8589(1.24%) | 512(43.39%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[0].quad | mgt_quad_slaves__xdcDup__1 | 3531(1.02%) | 3531(1.02%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[0].quad) | mgt_quad_slaves__xdcDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__1 | 867(0.25%) | 867(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_530 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_531 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_532 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_533 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__1 | 824(0.24%) | 824(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__1 | 816(0.24%) | 816(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_534 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__2 | 867(0.25%) | 867(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_525 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_526 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_527 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_528 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__2 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__2 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_529 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__3 | 872(0.25%) | 872(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_520 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_521 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_522 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_523 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__3 | 831(0.24%) | 831(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__3 | 823(0.24%) | 823(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_524 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__4 | 879(0.25%) | 879(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_515 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_516 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_517 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_518 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__4 | 831(0.24%) | 831(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__4 | 823(0.24%) | 823(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_519 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_508 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_510 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_512 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_513 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[10].quad | mgt_quad_slaves__xdcDup__8 | 2475(0.71%) | 2475(0.71%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[10].quad) | mgt_quad_slaves__xdcDup__8 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__41 | 577(0.17%) | 577(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_503 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_504 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_505 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_506 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__41 | 536(0.15%) | 536(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__41 | 528(0.15%) | 528(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_507 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__42 | 634(0.18%) | 634(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_498 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_499 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_500 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_501 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__42 | 593(0.17%) | 593(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__42 | 585(0.17%) | 585(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_502 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__43 | 645(0.19%) | 645(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_493 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_494 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_495 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_496 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__43 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__43 | 596(0.17%) | 596(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_497 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__44 | 596(0.17%) | 596(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_488 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_489 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_490 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_491 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__44 | 548(0.16%) | 548(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__44 | 540(0.16%) | 540(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_492 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_481 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_483 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_485 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_487 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[11].quad | mgt_quad_slaves__xdcDup__9 | 2465(0.71%) | 2465(0.71%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[11].quad) | mgt_quad_slaves__xdcDup__9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__45 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_476 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_477 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_478 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_479 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__45 | 564(0.16%) | 564(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__45 | 556(0.16%) | 556(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_480 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__46 | 637(0.18%) | 637(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_471 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_472 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_473 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_474 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__46 | 596(0.17%) | 596(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__46 | 588(0.17%) | 588(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_475 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__47 | 594(0.17%) | 594(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_466 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_467 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_468 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_469 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__47 | 553(0.16%) | 553(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__47 | 545(0.16%) | 545(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_470 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__48 | 584(0.17%) | 584(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_461 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_462 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_463 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_464 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__48 | 536(0.15%) | 536(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__48 | 528(0.15%) | 528(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_465 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_454 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_456 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_460 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[12].quad | mgt_quad_slaves__xdcDup__10 | 3022(0.87%) | 3022(0.87%) | 0(0.00%) | 0(0.00%) | 554(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[12].quad) | mgt_quad_slaves__xdcDup__10 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__49 | 545(0.16%) | 545(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_449 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_450 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_451 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_452 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__49 | 504(0.15%) | 504(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__49 | 496(0.14%) | 496(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_453 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__50 | 643(0.19%) | 643(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_444 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_445 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_446 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_447 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__50 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__50 | 594(0.17%) | 594(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_448 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__51 | 915(0.26%) | 915(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_439 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_440 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_441 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_442 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__51 | 874(0.25%) | 874(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__51 | 866(0.25%) | 866(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_443 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__52 | 874(0.25%) | 874(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_434 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_435 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_436 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_437 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__52 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__52 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_438 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_427 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_429 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_431 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[13].quad | mgt_quad_slaves__xdcDup__11 | 3541(1.02%) | 3541(1.02%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[13].quad) | mgt_quad_slaves__xdcDup__11 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__53 | 870(0.25%) | 870(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_422 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_423 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_424 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_425 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__53 | 829(0.24%) | 829(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__53 | 821(0.24%) | 821(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_426 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__54 | 866(0.25%) | 866(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_417 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_418 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_419 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_420 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__54 | 825(0.24%) | 825(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__54 | 817(0.24%) | 817(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_421 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__55 | 879(0.25%) | 879(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_412 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_413 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_414 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_415 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__55 | 838(0.24%) | 838(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__55 | 830(0.24%) | 830(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_416 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__56 | 878(0.25%) | 878(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_407 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_408 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_409 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_410 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__56 | 830(0.24%) | 830(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__56 | 822(0.24%) | 822(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_411 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_400 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_402 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_404 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[14].quad | mgt_quad_slaves__xdcDup__12 | 3552(1.03%) | 3552(1.03%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[14].quad) | mgt_quad_slaves__xdcDup__12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__57 | 874(0.25%) | 874(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_395 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_396 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_397 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_398 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__57 | 833(0.24%) | 833(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__57 | 825(0.24%) | 825(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_399 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__58 | 869(0.25%) | 869(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_390 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_391 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_392 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_393 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__58 | 828(0.24%) | 828(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__58 | 820(0.24%) | 820(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_394 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__59 | 882(0.25%) | 882(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_385 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_386 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_387 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_388 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__59 | 841(0.24%) | 841(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__59 | 833(0.24%) | 833(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_389 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__60 | 881(0.25%) | 881(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_380 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_381 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_382 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_383 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__60 | 832(0.24%) | 832(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__60 | 824(0.24%) | 824(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_384 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_373 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_375 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_377 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_378 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_379 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[16].quad | mgt_quad_slaves__xdcDup__13 | 991(0.29%) | 991(0.29%) | 0(0.00%) | 0(0.00%) | 534(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[16].quad) | mgt_quad_slaves__xdcDup__13 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__65 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_368 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_369 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_370 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_371 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__65 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__65 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_372 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__66 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_363 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_364 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_365 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_366 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__66 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__66 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_367 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__67 | 486(0.14%) | 486(0.14%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_358 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_359 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_360 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_361 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__67 | 444(0.13%) | 444(0.13%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__67 | 436(0.13%) | 436(0.13%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_362 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__68 | 339(0.10%) | 339(0.10%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_353 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_354 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_355 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_356 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__68 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__68 | 290(0.08%) | 290(0.08%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_357 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_346 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_348 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_351 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_352 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[17].quad | mgt_quad_slaves__xdcDup__14 | 926(0.27%) | 926(0.27%) | 0(0.00%) | 0(0.00%) | 534(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[17].quad) | mgt_quad_slaves__xdcDup__14 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__69 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_341 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_342 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_343 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_344 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__69 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__69 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_345 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__70 | 342(0.10%) | 342(0.10%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_336 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_337 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_338 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_339 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__70 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__70 | 293(0.08%) | 293(0.08%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_340 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__71 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_331 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_332 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_333 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_334 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__71 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__71 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_335 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__72 | 402(0.12%) | 402(0.12%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_326 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_327 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_328 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_329 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__72 | 361(0.10%) | 361(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__72 | 353(0.10%) | 353(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_330 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_319 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_321 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_324 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[18].quad | mgt_quad_slaves__xdcDup__15 | 1036(0.30%) | 1036(0.30%) | 0(0.00%) | 0(0.00%) | 538(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[18].quad) | mgt_quad_slaves__xdcDup__15 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__73 | 454(0.13%) | 454(0.13%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_314 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_315 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_316 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_317 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__73 | 413(0.12%) | 413(0.12%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__73 | 404(0.12%) | 404(0.12%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_318 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__74 | 390(0.11%) | 390(0.11%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_309 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_310 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_311 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_312 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__74 | 349(0.10%) | 349(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__74 | 341(0.10%) | 341(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_313 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__75 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_304 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_305 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_306 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_307 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__75 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__75 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_308 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__76 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_299 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_300 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_301 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_302 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__76 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__76 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_303 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_292 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_294 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_296 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[19].quad | mgt_quad_slaves | 313(0.09%) | 313(0.09%) | 0(0.00%) | 0(0.00%) | 526(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[19].quad) | mgt_quad_slaves | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__77 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_287 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_288 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_289 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_290 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__77 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__77 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_291 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__78 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_282 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_283 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_284 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_285 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__78 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__78 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_286 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__79 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_277 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_278 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_279 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_280 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__79 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__79 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_281 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_272 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_273 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_274 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_275 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_276 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_265 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_268 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[1].quad | mgt_quad_slaves__xdcDup__2 | 3484(1.01%) | 3484(1.01%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[1].quad) | mgt_quad_slaves__xdcDup__2 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__5 | 861(0.25%) | 861(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_260 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_261 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_262 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_263 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__5 | 820(0.24%) | 820(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__5 | 812(0.23%) | 812(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_264 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__6 | 838(0.24%) | 838(0.24%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_255 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_256 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_257 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_258 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__6 | 797(0.23%) | 797(0.23%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__6 | 789(0.23%) | 789(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_259 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__7 | 872(0.25%) | 872(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_250 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_251 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_252 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_253 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__7 | 831(0.24%) | 831(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__7 | 823(0.24%) | 823(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_254 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__8 | 866(0.25%) | 866(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_245 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_246 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_247 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_248 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__8 | 824(0.24%) | 824(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__8 | 816(0.24%) | 816(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_249 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_238 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_240 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_244 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[5].quad | mgt_quad_slaves__xdcDup__3 | 3047(0.88%) | 3047(0.88%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[5].quad) | mgt_quad_slaves__xdcDup__3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__21 | 934(0.27%) | 934(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_233 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_234 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_235 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_236 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__21 | 892(0.26%) | 892(0.26%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__21 | 883(0.25%) | 883(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_237 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__22 | 878(0.25%) | 878(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_228 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_229 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_230 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_231 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__22 | 836(0.24%) | 836(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__22 | 827(0.24%) | 827(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_232 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__23 | 569(0.16%) | 569(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_223 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_224 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_225 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_226 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__23 | 527(0.15%) | 527(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__23 | 519(0.15%) | 519(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_227 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__24 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_218 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_219 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_220 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_221 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__24 | 569(0.16%) | 569(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__24 | 560(0.16%) | 560(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_222 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_211 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_213 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_215 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_216 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[6].quad | mgt_quad_slaves__xdcDup__4 | 2630(0.76%) | 2630(0.76%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[6].quad) | mgt_quad_slaves__xdcDup__4 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__25 | 729(0.21%) | 729(0.21%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_206 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_207 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_208 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_209 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__25 | 686(0.20%) | 686(0.20%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__25 | 678(0.20%) | 678(0.20%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_210 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__26 | 634(0.18%) | 634(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_201 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_202 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_203 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_204 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__26 | 593(0.17%) | 593(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__26 | 585(0.17%) | 585(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_205 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__27 | 648(0.19%) | 648(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_196 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_197 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_198 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_199 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__27 | 607(0.18%) | 607(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__27 | 599(0.17%) | 599(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_200 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__28 | 574(0.17%) | 574(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_191 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_192 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_193 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_194 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__28 | 525(0.15%) | 525(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__28 | 516(0.15%) | 516(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_195 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_184 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_186 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_189 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_190 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[7].quad | mgt_quad_slaves__xdcDup__5 | 2628(0.76%) | 2628(0.76%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[7].quad) | mgt_quad_slaves__xdcDup__5 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__29 | 702(0.20%) | 702(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_179 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_180 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_181 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_182 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__29 | 661(0.19%) | 661(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__29 | 653(0.19%) | 653(0.19%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_183 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__30 | 700(0.20%) | 700(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_174 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_175 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_176 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_177 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__30 | 659(0.19%) | 659(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__30 | 651(0.19%) | 651(0.19%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_178 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__31 | 600(0.17%) | 600(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_169 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_170 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_171 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_172 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__31 | 559(0.16%) | 559(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__31 | 551(0.16%) | 551(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_173 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__32 | 600(0.17%) | 600(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_164 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_165 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_166 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_167 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__32 | 552(0.16%) | 552(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__32 | 544(0.16%) | 544(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_168 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_157 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_159 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_162 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[8].quad | mgt_quad_slaves__xdcDup__6 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 395(0.06%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[8].quad) | mgt_quad_slaves__xdcDup__6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__33 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_153 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_154 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_155 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__33 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_156 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__34 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_149 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_150 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_151 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__34 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__34 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_152 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__35 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_145 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_146 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_147 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__35 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__35 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_148 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__36 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_141 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_142 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_143 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__36 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_144 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_136 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_139 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[9].quad | mgt_quad_slaves__xdcDup__7 | 1991(0.57%) | 1991(0.57%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[9].quad) | mgt_quad_slaves__xdcDup__7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__37 | 574(0.17%) | 574(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_129 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_130 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_131 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_132 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__37 | 533(0.15%) | 533(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__37 | 525(0.15%) | 525(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_133 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__38 | 725(0.21%) | 725(0.21%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_124 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_125 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_126 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_127 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__38 | 684(0.20%) | 684(0.20%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__38 | 676(0.20%) | 676(0.20%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_128 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__39 | 587(0.17%) | 587(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_119 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_120 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_121 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_122 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__39 | 546(0.16%) | 546(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__39 | 538(0.16%) | 538(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_123 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__40 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_116 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_117 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_118 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__40 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__40 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_110 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_112 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READOUT_IF.Readout_block | Readout_logic_top | 14486(4.18%) | 14224(4.11%) | 0(0.00%) | 262(0.15%) | 49552(7.15%) | 174(14.75%) | 52(2.20%) | 0(0.00%) | | (READOUT_IF.Readout_block) | Readout_logic_top | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_ECR_debug_counter | cntr_generic | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_L1A_debug_counter | cntr_generic_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOBs_readout | TOBs_rdout | 5876(1.70%) | 5616(1.62%) | 0(0.00%) | 260(0.15%) | 13924(2.01%) | 114(9.66%) | 2(0.08%) | 0(0.00%) | | (U0_TOBs_readout) | TOBs_rdout | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 159(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_FIFO_BCN_L1A | FIFO_47b_512_HD3730 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_5_HD3731 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_5_synth_HD3732 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top_HD3733 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo_HD3734 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs_HD3735 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs_HD3735 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray_HD3736 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2_HD3737 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic_HD3738 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as_HD3739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as_HD3740 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as_HD3740 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1_HD3741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2_HD3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr_HD3744 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic_HD3745 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as_HD3746 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as_HD3747 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as_HD3747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_HD3748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0_HD3749 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr_HD3750 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory_HD3751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_4_HD3752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_4_synth_HD3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top_HD3754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr_HD3755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width_HD3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper_HD3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo_HD3758 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo_HD3758 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst_HD3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single_HD3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2_HD3761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1_HD3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_TOB_SPY_mem | ipbus_dpram__1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U14_stop_tob_wr | fsm_TOB_double_word | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_gen_sync_280 | gen_sync_280M_87 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOBs_eg_sorting | XTOBs_sorting__xdcDup__1 | 634(0.18%) | 629(0.18%) | 0(0.00%) | 5(0.01%) | 4032(0.58%) | 48(4.07%) | 0(0.00%) | 0(0.00%) | | (U2_XTOBs_eg_sorting) | XTOBs_sorting__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1407(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit_99 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_182b_512_HD3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_182b_512_HD4265 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4266 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4267 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4268 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4269 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4270 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4270 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4271 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4272 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4273 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4274 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4274 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4278 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4279 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_182b_512_wr_dc_as_HD4281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4282 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4282 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4285 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4297 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4297 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_182b_512_HD3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_182b_512_HD4302 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4303 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4304 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4305 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4306 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4307 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4307 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4308 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4309 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4310 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4311 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4311 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4312 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4315 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4316 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4319 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4319 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4321 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4322 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4334 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4334 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_182b_512_HD3925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_182b_512_HD4339 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4340 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4341 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4342 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4343 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4344 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4344 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4345 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4346 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4347 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4348 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4348 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4352 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4353 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4356 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4356 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4359 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4371 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4371 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_182b_512_HD3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_182b_512_HD4376 | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 165(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4377 | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 165(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4378 | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 165(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4379 | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 165(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4380 | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 165(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4381 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4381 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4382 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4383 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4384 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4386 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_182b_512_rd_handshaking_flags_HD4388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4389 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4390 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_182b_512_wr_pf_as_HD4391 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4393 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4393 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4395 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4396 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4408 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4408 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_182b_512_HD3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_182b_512_HD4413 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4414 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4415 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4416 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4417 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4418 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4418 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4419 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4420 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4421 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4422 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4422 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4426 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4427 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4430 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4430 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4433 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4445 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4445 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_182b_512_HD3958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_182b_512_HD4450 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4451 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4452 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4453 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4454 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4455 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4455 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4456 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4457 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4458 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4459 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4459 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4460 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4463 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4464 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4467 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4467 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4469 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4470 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4482 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4482 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_182b_512_HD3969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_182b_512_HD4487 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4488 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4489 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4490 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4491 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4492 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4492 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4493 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4494 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4495 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4497 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4500 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4501 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4507 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4519 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4519 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_182b_512_HD3980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_182b_512_HD4524 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4525 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4526 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4527 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4528 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4529 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4529 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4530 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4531 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4532 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4533 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4533 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4534 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4537 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4538 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4541 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4541 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4544 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4556 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4556 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO_107 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO_107 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b_109 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_BCN_Delay | GeneralDelay_108 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOBs_tau_sorting | XTOBs_sorting | 637(0.18%) | 632(0.18%) | 0(0.00%) | 5(0.01%) | 3882(0.56%) | 48(4.07%) | 0(0.00%) | 0(0.00%) | | (U3_XTOBs_tau_sorting) | XTOBs_sorting | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1402(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 153(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_182b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_182b_512 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_182b_512_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_92 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 149(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_182b_512_HD3826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_182b_512_HD4006 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4007 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4008 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4009 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4010 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4011 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4011 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4012 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4013 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4014 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4015 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4015 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4019 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4020 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4023 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4023 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4025 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4026 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4038 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4038 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_93 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_182b_512_HD3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_182b_512_HD4043 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4044 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4045 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4046 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4047 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4048 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4048 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4049 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4050 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4051 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4052 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4052 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4053 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4056 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4057 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4060 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4060 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4062 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4063 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4075 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4075 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_182b_512_HD3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_182b_512_HD4080 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4081 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4082 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4083 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4084 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4085 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4085 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4086 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4087 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4088 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4089 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4089 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4090 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4093 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4094 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_182b_512_wr_pf_as_HD4095 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4097 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4097 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4099 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4100 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4112 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4112 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 149(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_182b_512_HD3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_182b_512_HD4117 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4118 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4119 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4120 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4121 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4122 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4122 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4123 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4124 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4125 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4127 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4130 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4131 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4134 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4134 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4137 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4149 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4149 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 149(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_182b_512_HD3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_182b_512_HD4154 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4155 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4156 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4157 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4158 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4159 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4159 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4160 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4161 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4162 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4163 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4163 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4164 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4167 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4168 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4171 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4171 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4173 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4174 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4186 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4186 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 146(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_182b_512_HD3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_182b_512_HD4191 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4192 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4193 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4194 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4195 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4196 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4196 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4197 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4198 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4199 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4200 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4200 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4201 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4204 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4205 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4208 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4208 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4211 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4223 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4223 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 149(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_182b_512_HD3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_182b_512_blk_mem_gen_v8_4_4_HD3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_182b_512_blk_mem_gen_v8_4_4_synth_HD3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_182b_512_blk_mem_gen_top_HD3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_182b_512_blk_mem_gen_generic_cstr_HD3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_182b_512_blk_mem_gen_prim_width_HD3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper_HD3898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized0_HD3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_182b_512_blk_mem_gen_prim_width__parameterized1_HD3901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_182b_512_HD4228 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_182b_512_fifo_generator_v13_2_5_HD4229 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_182b_512_fifo_generator_v13_2_5_synth_HD4230 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_182b_512_fifo_generator_top_HD4231 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_182b_512_fifo_generator_ramfifo_HD4232 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 154(0.02%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_182b_512_clk_x_pntrs_HD4233 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_182b_512_clk_x_pntrs_HD4233 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray_HD4234 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_182b_512_xpm_cdc_gray__2_HD4235 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_182b_512_rd_logic_HD4236 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_182b_512_rd_status_flags_as_HD4237 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_182b_512_rd_status_flags_as_HD4237 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_182b_512_compare_1_HD4238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_2_HD4239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_182b_512_rd_bin_cntr_HD4241 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_182b_512_wr_logic_HD4242 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_182b_512_wr_status_flags_as_HD4245 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_182b_512_wr_status_flags_as_HD4245 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_182b_512_compare_HD4246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_182b_512_compare_0_HD4247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_182b_512_wr_bin_cntr_HD4248 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_182b_512_memory_HD4249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_182b_512_blk_mem_gen_v8_4_4_HD4250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_182b_512_blk_mem_gen_v8_4_4_synth_HD4251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_182b_512_blk_mem_gen_top_HD4252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_182b_512_blk_mem_gen_generic_cstr_HD4253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_182b_512_blk_mem_gen_prim_width_HD4254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper_HD4255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized0_HD4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_182b_512_blk_mem_gen_prim_width__parameterized1_HD4258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_182b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_182b_512_reset_blk_ramfifo_HD4260 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_182b_512_reset_blk_ramfifo_HD4260 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst_HD4261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_182b_512_xpm_cdc_single_HD4262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_182b_512_xpm_cdc_single__2_HD4263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_182b_512_xpm_cdc_async_rst__1_HD4264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_BCN_Delay | GeneralDelay | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_rd_mux_fsm | fsm_TOBs_to_muxPISO | 3127(0.90%) | 3127(0.90%) | 0(0.00%) | 0(0.00%) | 3170(0.46%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U6_rd_mux_fsm) | fsm_TOBs_to_muxPISO | 3109(0.90%) | 3109(0.90%) | 0(0.00%) | 0(0.00%) | 3144(0.45%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_TOB_payld_length | cntr_generic__parameterized2_90 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_eg_cntr | cntr_generic__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_tau_cntr | cntr_generic__parameterized1_91 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO | FIFO_33b_8192_HD3764 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_5_HD3765 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_5_synth_HD3766 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top_HD3767 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo_HD3768 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs_HD3769 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs_HD3769 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray_HD3770 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2_HD3771 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic_HD3772 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as_HD3773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as_HD3774 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as_HD3774 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2_HD3775 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3_HD3776 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr_HD3778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic_HD3779 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as_HD3780 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as_HD3782 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as_HD3782 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_HD3783 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1_HD3784 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr_HD3785 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory_HD3786 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_4_HD3787 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_4_synth_HD3788 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top_HD3789 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr_HD3790 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec_HD3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0_HD3792 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0_HD3793 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width_HD3794 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper_HD3795 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0_HD3796 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0_HD3797 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1_HD3798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1_HD3799 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2_HD3800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2_HD3801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3_HD3802 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3_HD3803 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4_HD3804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4_HD3805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5_HD3806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5_HD3807 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6_HD3808 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6_HD3809 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo_HD3810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_ila_TOB_LO_FIFO | ila_ipbus_fabric_rd_wr | 1129(0.33%) | 880(0.25%) | 0(0.00%) | 249(0.14%) | 2049(0.30%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | (U7_ila_TOB_LO_FIFO) | ila_ipbus_fabric_rd_wr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila | 1129(0.33%) | 880(0.25%) | 0(0.00%) | 249(0.14%) | 2049(0.30%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | (U0) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_core | 1128(0.33%) | 879(0.25%) | 0(0.00%) | 249(0.14%) | 2043(0.29%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | (ila_core_inst) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_core | 76(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.04%) | 193(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | valid.cstr | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[8].ram.r | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_ipbus_fabric_rd_wr_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_ctrl_legacy | 82(0.02%) | 35(0.01%) | 0(0.00%) | 47(0.03%) | 126(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_ctrl_legacy | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut6__parameterized0 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut7_71 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_addrgen | 67(0.02%) | 30(0.01%) | 0(0.00%) | 37(0.02%) | 120(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_sample_counter | 35(0.01%) | 22(0.01%) | 0(0.00%) | 13(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_sample_counter | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut4_78 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut5_79 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut6_80 | 5(0.01%) | 3(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match_nodelay_81 | 10(0.01%) | 1(0.01%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA_nodelay_82 | 10(0.01%) | 1(0.01%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA_nodelay_82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized2_83 | 10(0.01%) | 1(0.01%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized2_83 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized1_84 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized2_85 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_cfglut5_72 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA_nodelay_74 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized2_75 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized2_75 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized1_76 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized2_77 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match_nodelay_73 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_register | 741(0.21%) | 740(0.21%) | 0(0.00%) | 1(0.01%) | 1181(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_register | 116(0.03%) | 115(0.03%) | 0(0.00%) | 1(0.01%) | 161(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[1].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized0 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[2].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized1 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[3].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized2 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[4].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized3 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[5].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized4 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[6].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized5 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[7].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized6 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[8].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized7 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[9].mu_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized8 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized9 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_xsdbs | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 213(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized44 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_69 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized45 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized46 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_67 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized47 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_66 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized48 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized49 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl__parameterized1_64 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized29 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_63 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized30 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl__parameterized0 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized31 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stat_62 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl__parameterized1_61 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized51 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_60 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized53 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_59 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized54 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_58 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl_57 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized57 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stat_56 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized59 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stat_55 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stat_70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stat_54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_p2s__parameterized10 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stream | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_ctl | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stream__parameterized0 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_ipbus_fabric_rd_wr_xsdbs_v1_0_2_reg_stat | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_reset_ctrl | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_reset_ctrl | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_rising_edge_detection | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_async_edge_xfer | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_async_edge_xfer_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_async_edge_xfer_51 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_async_edge_xfer_52 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_rising_edge_detection_53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_trigger | 132(0.04%) | 9(0.01%) | 0(0.00%) | 123(0.07%) | 333(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_trigger | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match | 10(0.01%) | 1(0.01%) | 0(0.00%) | 9(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_48 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_49 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_ipbus_fabric_rd_wr_ila_v6_2_11_ila_trig_match | 122(0.04%) | 8(0.01%) | 0(0.00%) | 114(0.07%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0_41 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0_41 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0_42 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0_42 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_43 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_44 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_45 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_46 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[1].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0_0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[1].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0_34 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0_35 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0_35 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_38 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_39 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_40 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[2].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[2].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_32 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[3].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[3].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_29 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_29 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_30 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[4].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_2 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[4].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_25 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_26 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[5].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0_3 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[5].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0_18 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0_19 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0_19 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_20 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_21 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_22 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[6].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0_4 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[6].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized0_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 73(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_14 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_15 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice_16 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[7].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_5 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[7].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_11 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_12 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_12 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_13 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[8].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_6 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[8].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_8 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_9 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1_9 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0_10 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[9].U_M | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_7 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[9].U_M) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_match__parameterized1_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_allx_typeA__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_ipbus_fabric_rd_wr_ltlib_v1_0_0_generic_memrd | 85(0.02%) | 83(0.02%) | 0(0.00%) | 2(0.01%) | 176(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_TOB_Link_output_FIFO_FSM | FIFO_to_MGT_TOB_FSM | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_clk_closs_pulse | clk_closs_pulse_fsm_88 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_frame_counter | cntr_up_dn_generic_89 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_real_time_40m_counter | cntr_generic_7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_tob_double_word_counter | cntr_generic_8 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_readout | RAW_data_rdout | 8269(2.39%) | 8267(2.39%) | 0(0.00%) | 2(0.01%) | 34472(4.98%) | 60(5.08%) | 50(2.12%) | 0(0.00%) | | (U1_RAW_readout) | RAW_data_rdout | 81(0.02%) | 80(0.02%) | 0(0.00%) | 1(0.01%) | 15101(2.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U1_gen_sync_280 | gen_sync_280M | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U2_PISO_RAW | PISO_RAW_data | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U3_DPRAM_RAW_Data | DPR_36b_1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U4_FIFO_RAW_Data | FIFO_36b_512 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[10].U2_PISO_RAW | PISO_RAW_data_39 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U4_FIFO_RAW_Data | FIFO_36b_512_HD4993 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD4994 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD4995 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4996 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4997 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4998 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5002 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5002 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5005 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5006 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5007 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5008 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5008 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5010 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5012 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[11].U2_PISO_RAW | PISO_RAW_data_40 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U4_FIFO_RAW_Data | FIFO_36b_512_HD5021 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5022 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5023 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5024 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5025 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5026 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5030 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5030 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5032 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5033 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5034 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5035 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5036 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5036 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5038 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5040 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[12].U2_PISO_RAW | PISO_RAW_data_41 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U4_FIFO_RAW_Data | FIFO_36b_512_HD5049 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5050 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5051 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5052 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5053 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5054 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5058 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5058 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5060 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5061 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5062 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5063 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5064 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5064 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5066 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5067 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5068 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[13].U2_PISO_RAW | PISO_RAW_data_42 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U4_FIFO_RAW_Data | FIFO_36b_512_HD5077 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5078 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5079 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5080 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5081 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5082 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5086 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5086 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5088 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5089 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5090 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5091 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5092 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5092 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5096 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[14].U2_PISO_RAW | PISO_RAW_data_43 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U4_FIFO_RAW_Data | FIFO_36b_512_HD5105 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5106 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5107 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5108 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5109 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5110 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5114 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5114 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5117 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5118 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5119 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5120 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5120 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5123 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5124 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[15].U2_PISO_RAW | PISO_RAW_data_44 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U4_FIFO_RAW_Data | FIFO_36b_512_HD5133 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5134 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5135 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5136 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5137 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5138 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5142 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5142 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5145 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5146 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5147 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5148 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5148 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5152 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[16].U2_PISO_RAW | PISO_RAW_data_45 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U4_FIFO_RAW_Data | FIFO_36b_512_HD5161 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5162 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5163 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5164 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5165 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5166 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5170 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5170 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5173 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5174 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5175 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5176 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5176 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5178 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5179 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5180 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[17].U2_PISO_RAW | PISO_RAW_data_46 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U4_FIFO_RAW_Data | FIFO_36b_512_HD5189 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5190 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5191 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5192 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5193 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5194 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5198 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5198 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5201 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5202 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5203 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5204 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5204 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5208 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[18].U2_PISO_RAW | PISO_RAW_data_47 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U4_FIFO_RAW_Data | FIFO_36b_512_HD5217 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5218 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5219 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5220 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5221 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5222 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5226 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5226 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5229 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5230 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5231 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5232 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5232 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5236 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[19].U2_PISO_RAW | PISO_RAW_data_48 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U4_FIFO_RAW_Data | FIFO_36b_512_HD5245 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5246 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5247 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5248 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5249 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5250 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5254 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5254 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5256 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5257 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5258 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5259 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5260 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5260 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5264 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[1].U2_PISO_RAW | PISO_RAW_data_49 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U4_FIFO_RAW_Data | FIFO_36b_512_HD5273 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5274 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5275 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5276 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5277 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5278 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5282 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5282 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5285 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5286 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5287 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5288 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5288 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5290 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5291 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5292 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[20].U2_PISO_RAW | PISO_RAW_data_50 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U4_FIFO_RAW_Data | FIFO_36b_512_HD5301 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5302 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5303 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5304 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5305 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5306 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5308 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5309 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5310 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5310 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5312 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5313 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5314 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5315 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5316 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5316 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5319 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5320 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[21].U2_PISO_RAW | PISO_RAW_data_51 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U4_FIFO_RAW_Data | FIFO_36b_512_HD5329 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5330 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5331 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5332 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5333 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5334 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5338 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5338 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5340 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5341 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5342 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5343 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5344 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5344 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5347 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5348 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[22].U2_PISO_RAW | PISO_RAW_data_52 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U4_FIFO_RAW_Data | FIFO_36b_512_HD5357 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5358 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5359 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5360 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5361 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5362 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5366 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5366 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5368 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5369 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5370 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5371 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5372 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5372 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5374 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5375 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5376 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[23].U2_PISO_RAW | PISO_RAW_data_53 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U4_FIFO_RAW_Data | FIFO_36b_512_HD5385 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5386 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5387 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5388 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5389 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5390 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5394 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5394 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5396 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5397 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5398 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5399 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5400 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5400 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5403 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5404 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[24].U2_PISO_RAW | PISO_RAW_data_54 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U4_FIFO_RAW_Data | FIFO_36b_512_HD5413 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5414 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5415 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5416 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5417 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5418 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5422 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5422 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5425 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5426 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5427 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5428 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5428 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5431 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5432 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[25].U2_PISO_RAW | PISO_RAW_data_55 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U4_FIFO_RAW_Data | FIFO_36b_512_HD5441 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5442 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5443 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5444 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5445 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5446 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5450 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5450 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5452 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5453 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5454 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5455 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5456 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5456 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5460 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[26].U2_PISO_RAW | PISO_RAW_data_56 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U4_FIFO_RAW_Data | FIFO_36b_512_HD5469 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5470 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5471 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5472 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5473 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5474 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5478 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5478 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5480 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5481 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5482 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5483 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5484 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5484 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5487 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5488 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[27].U2_PISO_RAW | PISO_RAW_data_57 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U4_FIFO_RAW_Data | FIFO_36b_512_HD5497 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5498 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5499 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5500 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5501 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5502 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5506 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5506 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5508 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5509 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5510 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5511 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5512 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5512 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5515 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5516 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[28].U2_PISO_RAW | PISO_RAW_data_58 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U4_FIFO_RAW_Data | FIFO_36b_512_HD5525 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5526 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5527 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5528 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5529 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5530 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5534 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5534 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5536 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5537 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5538 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5539 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5540 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5540 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5544 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[29].U2_PISO_RAW | PISO_RAW_data_59 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U4_FIFO_RAW_Data | FIFO_36b_512_HD5553 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5554 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5555 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5556 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5557 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5558 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5562 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5562 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5565 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5566 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5567 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5568 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5568 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5571 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5572 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[2].U2_PISO_RAW | PISO_RAW_data_60 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U4_FIFO_RAW_Data | FIFO_36b_512_HD5581 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5582 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5583 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5584 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5585 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5586 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5590 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5590 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5593 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5594 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5595 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5596 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5596 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5599 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5600 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[30].U2_PISO_RAW | PISO_RAW_data_61 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U4_FIFO_RAW_Data | FIFO_36b_512_HD5609 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5610 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5611 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5612 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5613 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5614 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5618 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5618 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5620 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5621 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5622 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5623 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5624 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5624 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5628 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[31].U2_PISO_RAW | PISO_RAW_data_62 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U4_FIFO_RAW_Data | FIFO_36b_512_HD5637 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5638 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5639 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5640 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5641 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5642 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5646 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5646 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5649 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5650 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5651 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5652 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5652 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5656 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[32].U2_PISO_RAW | PISO_RAW_data_63 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U4_FIFO_RAW_Data | FIFO_36b_512_HD5665 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5666 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5667 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5668 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5669 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5670 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5674 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5674 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5677 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5678 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5679 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5680 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5680 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5684 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[33].U2_PISO_RAW | PISO_RAW_data_64 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U4_FIFO_RAW_Data | FIFO_36b_512_HD5693 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5694 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5695 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5696 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5697 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5698 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5702 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5705 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5706 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5707 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5708 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5708 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5712 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[34].U2_PISO_RAW | PISO_RAW_data_65 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U4_FIFO_RAW_Data | FIFO_36b_512_HD5721 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5722 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5723 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5724 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5725 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5726 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5730 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5730 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5733 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5734 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5735 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5736 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5736 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5740 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[35].U2_PISO_RAW | PISO_RAW_data_66 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U4_FIFO_RAW_Data | FIFO_36b_512_HD5749 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5750 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5751 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5752 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5753 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5754 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5758 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5758 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5760 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5761 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5762 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5763 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5764 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5764 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5767 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5768 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[36].U2_PISO_RAW | PISO_RAW_data_67 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U4_FIFO_RAW_Data | FIFO_36b_512_HD5777 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5778 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5779 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5780 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5781 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5782 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5786 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5786 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5789 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5790 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5791 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5792 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5792 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5794 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5795 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5796 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[37].U2_PISO_RAW | PISO_RAW_data_68 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U4_FIFO_RAW_Data | FIFO_36b_512_HD5805 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5806 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5807 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5808 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5809 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5810 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5814 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5814 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5816 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5817 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5818 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5819 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5820 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5820 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5822 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5823 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5824 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[38].U2_PISO_RAW | PISO_RAW_data_69 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U4_FIFO_RAW_Data | FIFO_36b_512_HD5833 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5834 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5835 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5836 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5837 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5838 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5842 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5842 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5845 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5846 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5847 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5848 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5848 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5851 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5852 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[39].U2_PISO_RAW | PISO_RAW_data_70 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U4_FIFO_RAW_Data | FIFO_36b_512_HD5861 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5862 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5863 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5864 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5865 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5866 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5870 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5870 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5872 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5873 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5874 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5875 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5876 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5876 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5879 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5880 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[3].U2_PISO_RAW | PISO_RAW_data_71 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U4_FIFO_RAW_Data | FIFO_36b_512_HD5889 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5890 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5891 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5892 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5893 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5894 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5898 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5898 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5900 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5901 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5902 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5903 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5904 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5904 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5907 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5908 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[40].U2_PISO_RAW | PISO_RAW_data_72 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U4_FIFO_RAW_Data | FIFO_36b_512_HD5917 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5918 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5919 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5920 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5921 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5922 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5926 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5926 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5928 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5929 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5930 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5931 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5932 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5932 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5934 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5935 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5936 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[41].U2_PISO_RAW | PISO_RAW_data_73 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U4_FIFO_RAW_Data | FIFO_36b_512_HD5945 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5946 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5947 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5948 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5949 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5950 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5954 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5954 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5956 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5957 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5958 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5959 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5960 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5960 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5962 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5963 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5964 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[42].U2_PISO_RAW | PISO_RAW_data_74 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U4_FIFO_RAW_Data | FIFO_36b_512_HD5973 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5974 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5975 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5976 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5977 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5978 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5982 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5982 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5984 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5985 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5986 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5987 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5988 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5988 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5991 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5992 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[43].U2_PISO_RAW | PISO_RAW_data_75 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U4_FIFO_RAW_Data | FIFO_36b_512_HD6001 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6002 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6003 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6004 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6005 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6006 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6010 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6010 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6012 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6013 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6014 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6015 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6016 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6016 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6018 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6020 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[44].U2_PISO_RAW | PISO_RAW_data_76 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U4_FIFO_RAW_Data | FIFO_36b_512_HD6029 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6030 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6031 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6032 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6033 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6034 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6038 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6038 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6040 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6041 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6042 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6043 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6044 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6044 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6047 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6048 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[45].U2_PISO_RAW | PISO_RAW_data_77 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U4_FIFO_RAW_Data | FIFO_36b_512_HD6057 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6058 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6059 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6060 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6061 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6062 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6066 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6066 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6068 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6069 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6070 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6071 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6072 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6072 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6076 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[46].U2_PISO_RAW | PISO_RAW_data_78 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U4_FIFO_RAW_Data | FIFO_36b_512_HD6085 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6086 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6087 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6088 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6089 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6090 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6094 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6094 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6097 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6098 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6099 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6100 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6100 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6104 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[47].U2_PISO_RAW | PISO_RAW_data_79 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U4_FIFO_RAW_Data | FIFO_36b_512_HD6113 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6114 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6115 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6116 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6117 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6118 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6122 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6122 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6124 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6125 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6126 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6127 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6128 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6128 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6132 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[48].U2_PISO_RAW | PISO_RAW_data_80 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U4_FIFO_RAW_Data | FIFO_36b_512_HD6141 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6142 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6143 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6144 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6145 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6146 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6150 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6150 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6153 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6154 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6155 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6156 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6156 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6160 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[4].U2_PISO_RAW | PISO_RAW_data_81 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U4_FIFO_RAW_Data | FIFO_36b_512_HD6169 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6170 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6171 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6172 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6173 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6174 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6178 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6178 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6180 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6181 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6182 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6183 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6184 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6184 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6186 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6187 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6188 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[5].U2_PISO_RAW | PISO_RAW_data_82 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U4_FIFO_RAW_Data | FIFO_36b_512_HD6197 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6198 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6199 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6200 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6201 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6202 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6206 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6206 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6209 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6210 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6211 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6212 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6212 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6215 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6216 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[6].U2_PISO_RAW | PISO_RAW_data_83 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U4_FIFO_RAW_Data | FIFO_36b_512_HD6225 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6226 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6227 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6228 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6229 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6230 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6234 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6234 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6237 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6238 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6239 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6240 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6240 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6244 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[7].U2_PISO_RAW | PISO_RAW_data_84 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U4_FIFO_RAW_Data | FIFO_36b_512_HD6253 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6254 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6255 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6256 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6257 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6258 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6262 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6262 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6264 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6265 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6266 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6267 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6268 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6268 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6272 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[8].U2_PISO_RAW | PISO_RAW_data_85 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U4_FIFO_RAW_Data | FIFO_36b_512_HD6281 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6282 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6283 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6284 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6285 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6286 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6290 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6290 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6293 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6294 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6295 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6296 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6296 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6299 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6300 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[9].U2_PISO_RAW | PISO_RAW_data_86 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U4_FIFO_RAW_Data | FIFO_36b_512_HD6309 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6310 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6311 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6312 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6313 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6314 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6318 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6318 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6321 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6322 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6323 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6324 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6324 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6326 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6327 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6328 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U10_RAW_frame_counter | cntr_up_dn_generic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U10_clk_closs_pulse | clk_closs_pulse_fsm | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_RAW_SPY_mem | ipbus_dpram | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_FIFO_link_err | FIFO_54b_512 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_54b_512_fifo_generator_v13_2_5 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_54b_512_fifo_generator_v13_2_5_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_54b_512_fifo_generator_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbi.bi | FIFO_54b_512_fifo_generator_v13_2_5_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | FIFO_54b_512_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | FIFO_54b_512_builtin_top_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | FIFO_54b_512_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | FIFO_54b_512_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U5_RAW_fsm | fsm_RAW_data_wr_to_DPR | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U5_RAW_fsm) | fsm_RAW_data_wr_to_DPR | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_10b | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_link_err | link_errors_ORed | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5b_gen_full_flag | RAW_fifo_full_flag_gen | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_FIFO_BCN_L1A | FIFO_47b_512 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_5 | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_5_synth | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo | 100(0.03%) | 100(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_47b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_rd_RAW_mux_fsm | fsm_RAW_to_muxPISO | 805(0.23%) | 805(0.23%) | 0(0.00%) | 0(0.00%) | 2086(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U7_rd_RAW_mux_fsm) | fsm_RAW_to_muxPISO | 778(0.22%) | 778(0.22%) | 0(0.00%) | 0(0.00%) | 2074(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_raw_payld_length | cntr_generic__parameterized2 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_RAW_Link_output_FIFO | FIFO_33b_8192 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_5 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_5_synth | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 68(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_4 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_4_synth | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_RAW_Link_output_FIFO_FSM | FIFO_to_MGT_RAW_FSM | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_rdout_ipb_slave | readout_ipb_slave | 314(0.09%) | 314(0.09%) | 0(0.00%) | 0(0.00%) | 961(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U4_rdout_ipb_slave) | readout_ipb_slave | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_Test_Cntl_Reg | ipbus_ctrlreg_v__parameterized2_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_pulsed_register | ipbus_ctrlreg_v__parameterized2_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_top_level_counters | ipbus_ctrlreg_v__parameterized4 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_slave | slave_TOB_readout | 135(0.04%) | 135(0.04%) | 0(0.00%) | 0(0.00%) | 544(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U11_LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_22 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_23 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U18_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_25 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOB_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_EG_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_27 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_TAU_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_SLICES_TO_RD | ipbus_ctrlreg_v__parameterized2_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_trigger_slice | ipbus_ctrlreg_v__parameterized2_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_TOB_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_TOB_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_32 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_EG_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_TAU_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_36 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_EG_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_TAU_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_38 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_RAW_slave | slave_RAW_readout | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U15_RAW_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_11 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_RAW_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_15 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_Link_output_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_19 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9A_RAW_FIFO_FULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_20 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9B_RAW_FIFO_FULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_21 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | proc_FPGAs | 5967(1.72%) | 5948(1.72%) | 0(0.00%) | 19(0.01%) | 2669(0.39%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_node_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | ipbus_ctrl | 5955(1.72%) | 5936(1.71%) | 0(0.00%) | 19(0.01%) | 2616(0.38%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (U_2) | ipbus_ctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 4440(1.28%) | 4440(1.28%) | 0(0.00%) | 0(0.00%) | 376(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 190(0.05%) | 190(0.05%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 4262(1.23%) | 4262(1.23%) | 0(0.00%) | 0(0.00%) | 241(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 1513(0.44%) | 1494(0.43%) | 0(0.00%) | 19(0.01%) | 2240(0.32%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 194(0.06%) | 193(0.06%) | 0(0.00%) | 1(0.01%) | 224(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 179(0.05%) | 179(0.05%) | 0(0.00%) | 0(0.00%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 108(0.03%) | 92(0.03%) | 0(0.00%) | 16(0.01%) | 353(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 143(0.04%) | 143(0.04%) | 0(0.00%) | 0(0.00%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 235(0.07%) | 235(0.07%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_5 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_resources | clk_resources | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_resources) | clk_resources | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Inputclk40M | ClockWizard | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | ClockWizard_ClockWizard_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk40_gen | clk_wiz_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_1_clk_wiz_1_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 20(0.01%) | 19(0.01%) | 0(0.00%) | 1(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 4(0.01%) | 3(0.01%) | 0(0.00%) | 1(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_hub | dbg_hub | 455(0.13%) | 431(0.12%) | 24(0.01%) | 0(0.00%) | 741(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_hub) | dbg_hub | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dbg_hub_xsdbm_v3_0_0_xsdbm | 455(0.13%) | 431(0.12%) | 24(0.01%) | 0(0.00%) | 741(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BSCANID.u_xsdbm_id | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 455(0.13%) | 431(0.12%) | 24(0.01%) | 0(0.00%) | 741(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BSCANID.u_xsdbm_id) | dbg_hub_xsdbm_v3_0_0_xsdbm_id | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.UUT_MASTER | dbg_hub_xsdbm_v3_0_0_icon2xsdb | 278(0.08%) | 254(0.07%) | 24(0.01%) | 0(0.00%) | 554(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_ICON_INTERFACE | dbg_hub_xsdbm_v3_0_0_if | 163(0.05%) | 139(0.04%) | 24(0.01%) | 0(0.00%) | 450(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_ICON_INTERFACE) | dbg_hub_xsdbm_v3_0_0_if | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD1 | dbg_hub_xsdbm_v3_0_0_ctl_reg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD2 | dbg_hub_xsdbm_v3_0_0_stat_reg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD3 | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD4 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized0 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD5 | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_RD | dbg_hub_xsdbm_v3_0_0_rdreg | 67(0.02%) | 55(0.02%) | 12(0.01%) | 0(0.00%) | 134(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_RD) | dbg_hub_xsdbm_v3_0_0_rdreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_FIFO | dbg_hub_xsdbm_v3_0_0_rdfifo | 65(0.02%) | 53(0.02%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_RD_FIFO) | dbg_hub_xsdbm_v3_0_0_rdfifo | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst) | dbg_hub_fifo_generator_v13_1_4__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo__parameterized0 | 47(0.01%) | 35(0.01%) | 12(0.01%) | 0(0.00%) | 114(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs_7 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs_7 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | dbg_hub_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr_18 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as_14 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory__parameterized0 | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | dbg_hub_memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem_13 | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo_8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_WR | dbg_hub_xsdbm_v3_0_0_wrreg | 46(0.01%) | 34(0.01%) | 12(0.01%) | 0(0.00%) | 110(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_WR) | dbg_hub_xsdbm_v3_0_0_wrreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WR_FIFO | dbg_hub_xsdbm_v3_0_0_wrfifo | 44(0.01%) | 32(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_WR_FIFO) | dbg_hub_xsdbm_v3_0_0_wrfifo | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst | dbg_hub_fifo_generator_v13_1_4 | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst) | dbg_hub_fifo_generator_v13_1_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_4_synth | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo | 42(0.01%) | 30(0.01%) | 12(0.01%) | 0(0.00%) | 90(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem | 12(0.01%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_CTL | dbg_hub_xsdbm_v3_0_0_ctl_reg__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_STAT | dbg_hub_xsdbm_v3_0_0_stat_reg__parameterized0_0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STATIC_STATUS | dbg_hub_xsdbm_v3_0_0_if_static_status | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_ADDRESS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_addr_ctl | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BURST_WD_LEN_CONTROLLER | dbg_hub_xsdbm_v3_0_0_burst_wdlen_ctl | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_CONTROLLER | dbg_hub_xsdbm_v3_0_0_bus_ctl | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_CONTROLLER) | dbg_hub_xsdbm_v3_0_0_bus_ctl | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_ABORT_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg__parameterized0 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_REQ_FLAG | dbg_hub_xsdbm_v3_0_0_bus_ctl_flg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TIMER | dbg_hub_xsdbm_v3_0_0_bus_ctl_cnt | 52(0.02%) | 52(0.02%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_MSTR2SL_PORT_IFACE | dbg_hub_xsdbm_v3_0_0_bus_mstr2sl_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.U_ICON | dbg_hub_xsdbm_v3_0_0_icon | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CORE_XSDB.U_ICON) | dbg_hub_xsdbm_v3_0_0_icon | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD | dbg_hub_xsdbm_v3_0_0_cmd_decode | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STAT | dbg_hub_xsdbm_v3_0_0_stat | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SYNC | dbg_hub_xsdbm_v3_0_0_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_inst | dbg_hub_ltlib_v1_0_0_bscan | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_switch | dbg_hub_xsdbm_v3_0_0_bscan_switch | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 125(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | slaves | 559(0.16%) | 559(0.16%) | 0(0.00%) | 0(0.00%) | 1289(0.19%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | bcmuxvalue_sync | ipbus_ctrlreg_v__parameterized2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 425(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig__0 | ipbus_ctrlreg_v__parameterized2_0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32 | 273(0.08%) | 273(0.08%) | 0(0.00%) | 0(0.00%) | 304(0.04%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bc_delay | ipbus_ctrlreg_v__parameterized1_1 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bus_delay | ipbus_ctrlreg_v__parameterized1_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_synch | ipbus_ctrlreg_v__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_orbit_length | ipbus_ctrlreg_v__parameterized2_4 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 367(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 366(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------+----------------+----------------+-----------+--------------+----------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining