## Repository info - Merge request number: 302 - Branch name: feature/raw_readout_update ## MR Description Fixes to Readout CDC packet counting logic to ensure no mismatch between actual FIFO state and packet counters Update to Algo threshold test so that channel can be disabled even when saturated ## Changelog - force clk_closs_pulse_fsm to be single tick - modify test for over threshold to '<=' ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | abc93c3 | 1.5.4 | | Constraints | abc93c3f | 1.5.4 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 15b3e39 | 1.5.4 | | **Lib:** algolib | eb44a0f | 1.5.4 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 91ab74c | 1.5.4 | | Constraints | a09d51da | 1.4.0 | | IPbus XML | 035a149 | 1.5.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** infrastructure_lib | 7080975 | 1.5.2 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 367983f | 1.5.4 | | Constraints | 367983f9 | 1.5.4 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 15b3e39 | 1.5.4 | | **Lib:** algolib | eb44a0f | 1.5.4 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 91ab74c | 1.5.4 | | Constraints | e58176a5 | 1.5.3 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 15b3e39 | 1.5.4 | | **Lib:** algolib | eb44a0f | 1.5.4 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | abc93c3 | 1.5.4 | | Constraints | abc93c3f | 1.5.4 | | IPbus XML | b17d984 | 1.5.0 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 15b3e39 | 1.5.4 | | **Lib:** algolib | eb44a0f | 1.5.4 | | **Lib:** infrastructure_lib | 5dde7ec | 1.3.3 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | 5dde7ec | 1.3.3 | ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.056679 | | TNS: | 0.000000 | | WHS: | 0.027927 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.044558 | | TNS: | 0.000000 | | WHS: | 0.050456 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.024970 | | TNS: | 0.000000 | | WHS: | 0.014221 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.095957 | | TNS: | 0.000000 | | WHS: | 0.026197 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.022584 | | TNS: | 0.000000 | | WHS: | 0.015464 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186207 | 0 | 346400 | 53.75 | | Slice Registers | 268033 | 0 | 692800 | 38.69 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 195436 | 0 | 346400 | 56.42 | | Slice Registers | 295230 | 0 | 692800 | 42.61 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 30035 | 0 | 204000 | 14.72 | | Slice Registers | 50891 | 0 | 408000 | 12.47 | | Block RAM Tile | 322 | 0 | 750 | 42.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 378 | 0 | 600 | 63.00 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 38029 | 0 | 204000 | 18.64 | | Slice Registers | 69450 | 0 | 408000 | 17.02 | | Block RAM Tile | 361.5 | 0 | 750 | 48.20 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 346 | 334 | 600 | 57.67 | ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182387 | 0 | 346400 | 52.65 | | Slice Registers | 256448 | 0 | 692800 | 37.02 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191833 | 0 | 346400 | 55.38 | | Slice Registers | 283942 | 0 | 692800 | 40.98 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186131 | 0 | 346400 | 53.73 | | Slice Registers | 268021 | 0 | 692800 | 38.69 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194648 | 0 | 346400 | 56.19 | | Slice Registers | 295300 | 0 | 692800 | 42.62 | | Block RAM Tile | 751 | 0 | 1180 | 63.64 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182360 | 0 | 346400 | 52.64 | | Slice Registers | 256421 | 0 | 692800 | 37.01 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191364 | 0 | 346400 | 55.24 | | Slice Registers | 283911 | 0 | 692800 | 40.98 | | Block RAM Tile | 740 | 0 | 1180 | 62.71 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 |