*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2521.078 ; gain = 0.000 ; free physical = 76630 ; free virtual = 161847 INFO: [Netlist 29-17] Analyzing 330 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3139.262 ; gain = 562.164 ; free physical = 73849 ; free virtual = 159068 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3139.262 ; gain = 0.000 ; free physical = 73703 ; free virtual = 158922 INFO: [Project 1-111] Unisim Transformation Summary: A total of 49 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 17 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 3139.262 ; gain = 618.195 ; free physical = 73702 ; free virtual = 158922 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.86 . Memory (MB): peak = 3147.266 ; gain = 8.000 ; free physical = 73669 ; free virtual = 158889 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1b6790953 Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.63 . Memory (MB): peak = 3147.266 ; gain = 0.000 ; free physical = 73529 ; free virtual = 158749 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 2 inverter(s) to 3 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: e72929f3 Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73420 ; free virtual = 158639 INFO: [Opt 31-389] Phase Retarget created 44 cells and removed 344 cells INFO: [Opt 31-1021] In phase Retarget, 161 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 134719925 Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.99 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73426 ; free virtual = 158645 INFO: [Opt 31-389] Phase Constant propagation created 153 cells and removed 437 cells INFO: [Opt 31-1021] In phase Constant propagation, 154 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 122487d02 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73426 ; free virtual = 158645 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 233 cells INFO: [Opt 31-1021] In phase Sweep, 282 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 4 BUFG optimization | Checksum: f61827f2 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73410 ; free virtual = 158630 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: f61827f2 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73409 ; free virtual = 158628 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 952ac8bb Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73404 ; free virtual = 158623 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 155 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 44 | 344 | 161 | | Constant propagation | 153 | 437 | 154 | | Sweep | 2 | 233 | 282 | | BUFG optimization | 0 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 155 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3285.266 ; gain = 0.000 ; free physical = 73384 ; free virtual = 158604 Ending Logic Optimization Task | Checksum: 59bca88b Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3285.266 ; gain = 1.004 ; free physical = 73384 ; free virtual = 158604 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 23 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 46 Ending PowerOpt Patch Enables Task | Checksum: 9e9a01a9 Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73388 ; free virtual = 158624 Ending Power Optimization Task | Checksum: 9e9a01a9 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3616.316 ; gain = 331.051 ; free physical = 73393 ; free virtual = 158630 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: c7b44874 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73339 ; free virtual = 158564 Ending Final Cleanup Task | Checksum: c7b44874 Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73339 ; free virtual = 158565 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73340 ; free virtual = 158565 Ending Netlist Obfuscation Task | Checksum: c7b44874 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73340 ; free virtual = 158565 INFO: [Common 17-83] Releasing license: Implementation 51 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3616.316 ; gain = 477.055 ; free physical = 73340 ; free virtual = 158566 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73319 ; free virtual = 158553 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73147 ; free virtual = 158377 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 91586bc2 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73152 ; free virtual = 158382 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73152 ; free virtual = 158382 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 97f6ace3 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73187 ; free virtual = 158416 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 140380897 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73218 ; free virtual = 158451 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 140380897 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73218 ; free virtual = 158451 Phase 1 Placer Initialization | Checksum: 140380897 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73223 ; free virtual = 158456 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 102461a6d Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73185 ; free virtual = 158418 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 12df77771 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73164 ; free virtual = 158396 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 497 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 215 nets or cells. Created 0 new cell, deleted 215 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73256 ; free virtual = 158498 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 215 | 215 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 215 | 215 | 0 | 3 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 15f2b1355 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73215 ; free virtual = 158468 Phase 2.3 Global Placement Core | Checksum: de68037d Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73202 ; free virtual = 158466 Phase 2 Global Placement | Checksum: de68037d Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73207 ; free virtual = 158471 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: e025b6bd Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73208 ; free virtual = 158475 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: dea885be Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73203 ; free virtual = 158470 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: da43cdeb Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73220 ; free virtual = 158470 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 14e84f6ca Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 73221 ; free virtual = 158471 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1755de0ce Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72817 ; free virtual = 158067 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: a1e9546b Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72721 ; free virtual = 157970 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: ae4508fb Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72719 ; free virtual = 157968 Phase 3 Detail Placement | Checksum: ae4508fb Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72718 ; free virtual = 157967 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 182829092 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.891 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1b5285bf9 Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72678 ; free virtual = 157928 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 10b9c61ea Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72677 ; free virtual = 157927 Phase 4.1.1.1 BUFG Insertion | Checksum: 182829092 Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72677 ; free virtual = 157926 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.891. For the most accurate timing information please run report_timing. Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72676 ; free virtual = 157926 Phase 4.1 Post Commit Optimization | Checksum: 1b871b6d4 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72676 ; free virtual = 157925 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1b871b6d4 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72681 ; free virtual = 157931 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1b871b6d4 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72681 ; free virtual = 157930 Phase 4.3 Placer Reporting | Checksum: 1b871b6d4 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72680 ; free virtual = 157930 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72680 ; free virtual = 157930 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72680 ; free virtual = 157930 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 116f182f2 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72680 ; free virtual = 157929 Ending Placer Task | Checksum: 33c05156 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72679 ; free virtual = 157928 INFO: [Common 17-83] Releasing license: Implementation 84 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72710 ; free virtual = 157960 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.62 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72563 ; free virtual = 157829 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72477 ; free virtual = 157730 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72490 ; free virtual = 157744 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 96 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.62 . Memory (MB): peak = 3616.316 ; gain = 0.000 ; free physical = 72369 ; free virtual = 157640 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 3b6114b ConstDB: 0 ShapeSum: 300a400b RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 137b99658 Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 3729.422 ; gain = 113.105 ; free physical = 71442 ; free virtual = 156700 Post Restoration Checksum: NetGraph: ae44011f NumContArr: 89759539 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 137b99658 Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 3729.422 ; gain = 113.105 ; free physical = 71444 ; free virtual = 156702 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 137b99658 Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3733.422 ; gain = 117.105 ; free physical = 71436 ; free virtual = 156694 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 137b99658 Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3733.422 ; gain = 117.105 ; free physical = 71436 ; free virtual = 156694 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1122f21f9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71419 ; free virtual = 156677 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=-0.274 | THS=-297.375| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: fdd008e8 Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71517 ; free virtual = 156775 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 11a3061ef Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71516 ; free virtual = 156774 Phase 2 Router Initialization | Checksum: 5ee3ea2e Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71510 ; free virtual = 156768 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 9927 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 9925 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 5ee3ea2e Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71545 ; free virtual = 156803 Phase 3 Initial Routing | Checksum: 17cfe6553 Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71483 ; free virtual = 156741 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 795 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 16786f434 Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71599 ; free virtual = 156857 Phase 4 Rip-up And Reroute | Checksum: 16786f434 Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71594 ; free virtual = 156852 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 16786f434 Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71605 ; free virtual = 156863 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 16786f434 Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71594 ; free virtual = 156852 Phase 5 Delay and Skew Optimization | Checksum: 16786f434 Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71600 ; free virtual = 156858 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: e2d3daaf Time (s): cpu = 00:01:13 ; elapsed = 00:01:14 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71602 ; free virtual = 156860 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.060 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: b9750d41 Time (s): cpu = 00:01:13 ; elapsed = 00:01:14 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71604 ; free virtual = 156862 Phase 6 Post Hold Fix | Checksum: b9750d41 Time (s): cpu = 00:01:13 ; elapsed = 00:01:14 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71607 ; free virtual = 156865 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.555054 % Global Horizontal Routing Utilization = 0.607455 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1942c7979 Time (s): cpu = 00:01:14 ; elapsed = 00:01:15 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71603 ; free virtual = 156861 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1942c7979 Time (s): cpu = 00:01:14 ; elapsed = 00:01:15 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71600 ; free virtual = 156858 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 22495e467 Time (s): cpu = 00:01:14 ; elapsed = 00:01:16 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71591 ; free virtual = 156849 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.060 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 22495e467 Time (s): cpu = 00:01:15 ; elapsed = 00:01:16 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71596 ; free virtual = 156854 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:01:15 ; elapsed = 00:01:16 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71619 ; free virtual = 156877 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 111 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 3801.633 ; gain = 185.316 ; free physical = 71625 ; free virtual = 156883 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.5-hog527b417 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_golden_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] The git SHA value 527b417 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.5-hog527b417 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_control-v1.5.5-hog527b417... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.