*** Running vivado with args -log top_efex_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_efex_control.tcl WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.5.6-hog9532924... INFO: [Hog:Msg-0] Opening project efex_control... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'. INFO: [Hog:Msg-0] Checking efex_control list files... INFO: [Hog:Msg-0] Retrieved Vivado project files... INFO: [Hog:Msg-0] Design List Files matches project. Nothing to do. INFO: [Hog:Msg-0] Simulation List Files matches project. Nothing to do. INFO: [Hog:Msg-0] /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top//efex_control/hog.conf matches project. Nothing to do WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top//efex_control/sim.conf not found. Skipping properties check INFO: [Hog:Msg-0] Design List files and hog.conf match project. All ok! INFO: [Hog:Msg-0] Simulation list files match project. All ok! INFO: [Hog:Msg-0] Simulation config files match project. All ok! INFO: [Hog:Msg-0] All done. INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Git describe for 9532924 is: v1.5.6-hog9532924 INFO: [Hog:Msg-0] Found last SHA for efex_control: 9532924 INFO: [Hog:Msg-0] The commit in which project efex_control was last modified is 9532924, that is 32 commits older than current commit 9663925. INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing placeholders with xml version 01050000... INFO: [Hog:CopyXMLsFromListFile-0] 15 lines read from ./Top//efex_control/list/xml.lst INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/L1CaloEfex.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_backplane.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_backplane_busy_status.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_common_id_version.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_fifo_status.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_merger_status.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_mgt_status.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_mux_status.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_infrastructure.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_mgt_channel.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_mgt_quad.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_mgt.xml to /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] 13 file/s copied WARNING: [Hog:CopyXMLsFromListFile-0] Address map generation failed for L1CaloEfex.xml: child process exited abnormally INFO: [Hog:CopyXMLsFromListFile-0] efex_cntrl_backplane.xml and /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_backplane.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of efex_cntrl_backplane_busy_status.xml as no VHDL file was specified. WARNING: [Hog:CopyXMLsFromListFile-0] VHDL address map file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_common_id_version.vhd not found. INFO: [Hog:CopyXMLsFromListFile-0] efex_cntrl_data_path.xml and /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_data_path.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of efex_cntrl_data_path_fifo_status.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of efex_cntrl_data_path_merger_status.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of efex_cntrl_data_path_mgt_status.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of efex_cntrl_data_path_mux_status.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] efex_cntrl_infrastructure.xml and /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_infrastructure.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_cntrl_mgt_channel.xml and /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_mgt_channel.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_cntrl_mgt_quad.xml and /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_mgt_quad.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_cntrl_mgt.xml and /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_cntrl_mgt.vhd match. INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:WriteGenerics-0] Passing parameters/generics to project /efex_control's top module... INFO: [Hog:WriteGenerics-0] Setting parameters/generics... INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/versions.txt... ------------------------- PRE SYNTHESIS ------------------------- 08/06/2023 at 12:08:38 Firmware date and time: 05062023, 00141325 Global SHA: 9532924, VER: 1.5.6 Constraints SHA: 00FB8DC1, VER: 1.5.6 IPbus XML SHA: 035A149, VER: 1.5.0 Top SHA: D88FAA0, VER: 0.15.0 Hog SHA: 7DD4817, VER: 6.48.5 --- Libraries --- infrastructure_lib SHA: 9532924, VER: 1.5.6 ipbus_lib SHA: D6F4F62, VER: 1.0.0 ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with Hog2023.1-4 in .gitlab-ci.yml. INFO: [Hog:Msg-0] All done. Command: synth_design -top top_efex_control -part xc7vx330tffg1157-2 -retiming Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 16158 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2612.773 ; gain = 3.664 ; free physical = 74677 ; free virtual = 161751 --------------------------------------------------------------------------------- WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:67] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:68] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:65] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:50] INFO: [Synth 8-638] synthesizing module 'top_efex_control' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:182] Parameter FLAVOUR bound to: 0 - type: integer Parameter GLOBAL_DATE bound to: 32'b00000101000001100010000000100011 Parameter GLOBAL_TIME bound to: 32'b00000000000101000001001100100101 Parameter GLOBAL_SHA bound to: 32'b00001001010100110010100100100100 Parameter GLOBAL_VER bound to: 32'b00000001000001010000000000000110 Parameter XML_SHA bound to: 32'b00000000001101011010000101001001 Parameter XML_VER bound to: 32'b00000001000001010000000000000000 Parameter TOP_SHA bound to: 32'b00001101100010001111101010100000 Parameter TOP_VER bound to: 32'b00000000000011110000000000000000 Parameter HOG_SHA bound to: 32'b00000111110111010100100000010111 Parameter HOG_VER bound to: 32'b00000110001100000000000000000101 Parameter CON_SHA bound to: 32'b00000000111110111000110111000001 Parameter CON_VER bound to: 32'b00000001000001010000000000000110 Parameter INFRASTRUCTURE_LIB_VER bound to: 32'b00000001000001010000000000000110 Parameter INFRASTRUCTURE_LIB_SHA bound to: 32'b00001001010100110010100100100100 Parameter IPBUS_LIB_SHA bound to: 32'b00001101011011110100111101100010 Parameter IPBUS_LIB_VER bound to: 32'b00000001000000000000000000000000 Parameter N_PROCESSORFPGA bound to: 4 - type: integer Parameter GOLDEN bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 5 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (1#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'common_id_registers' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (1#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (2#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:107] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:109] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (2#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:121] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:123] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:135] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:149] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:151] INFO: [Synth 8-256] done synthesizing module 'common_id_registers' (3#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'top_udp_config_FPGA' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:68] Parameter IPBUSBUFWIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'interface_proc_fpga' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/interface_proc_fpga_struct.vhd:47] Parameter IPBUFWIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'UDP_hub_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_fifo.vhd:35] Parameter BUFWIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'UDP_hub_fifo' (4#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_fifo.vhd:35] INFO: [Synth 8-638] synthesizing module 'UDP_hub_if' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_if.vhd:36] INFO: [Synth 8-256] done synthesizing module 'UDP_hub_if' (5#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_if.vhd:36] INFO: [Synth 8-256] done synthesizing module 'interface_proc_fpga' (6#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/interface_proc_fpga_struct.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b1 Parameter N_OOB bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:89] WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'udp_ipam_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:60] Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'udp_ipam_block' (7#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:60] INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (8#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (9#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_ipam' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_ipam' (10#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (11#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (12#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (13#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (14#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (15#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (16#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (17#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (18#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (19#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (20#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (21#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (22#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (22#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (23#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:83] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (24#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (24#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] Parameter INTERNAL_ONLY bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (25#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (26#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (27#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (28#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (29#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (30#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (31#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor' (32#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (33#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:260] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:261] INFO: [Synth 8-638] synthesizing module 'mac_arbiter' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_eth/firmware/hdl/mac_arbiter.vhd:61] Parameter NSRC bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'mac_arbiter' (34#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_eth/firmware/hdl/mac_arbiter.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_hub_rarp' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_rarp.vhd:24] INFO: [Synth 8-256] done synthesizing module 'udp_hub_rarp' (35#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_rarp.vhd:24] INFO: [Synth 8-638] synthesizing module 'unique_address' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/unique_address.vhd:22] INFO: [Synth 8-256] done synthesizing module 'unique_address' (36#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/unique_address.vhd:22] INFO: [Synth 8-256] done synthesizing module 'top_udp_config_FPGA' (37#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:68] INFO: [Synth 8-638] synthesizing module 'interconnect' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'parity_checker' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-256] done synthesizing module 'parity_checker' (38#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-638] synthesizing module 'parity_gen' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] Parameter width bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'parity_gen' (39#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] INFO: [Synth 8-256] done synthesizing module 'interconnect' (40#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFGDS' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:51] INFO: [Synth 8-113] binding component instance 'bufg200' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:57] INFO: [Synth 8-113] binding component instance 'bufg125' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:62] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:69] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 1.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_DIVIDE bound to: 5 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm' to cell 'MMCME2_BASE' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:76] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:58] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (41#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (42#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] INFO: [Synth 8-638] synthesizing module 'eth_7s_gmii' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:45] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-113] binding component instance 'idelayctrl0' to cell 'IDELAYCTRL' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:116] INFO: [Synth 8-3491] module 'temac_gbe_v9_0' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/temac_gbe_v9_0_stub.vhdl:5' bound to instance 'emac0' of component 'temac_gbe_v9_0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:124] INFO: [Synth 8-638] synthesizing module 'temac_gbe_v9_0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/temac_gbe_v9_0_stub.vhdl:47] INFO: [Synth 8-3491] module 'mac_fifo_axi4' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mac_fifo_axi4_stub.vhdl:5' bound to instance 'fifo' of component 'mac_fifo_axi4' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:168] INFO: [Synth 8-638] synthesizing module 'mac_fifo_axi4' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mac_fifo_axi4_stub.vhdl:24] INFO: [Synth 8-256] done synthesizing module 'eth_7s_gmii' (43#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:45] INFO: [Synth 8-638] synthesizing module 'infrastructure_slaves_cntrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd:69] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 7 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (43#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (43#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_xadc_drp' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] Parameter NUMREG bound to: 19 - type: integer Parameter reg48 bound to: 16'b0100111100000001 Parameter reg49 bound to: 16'b0000010100001111 INFO: [Synth 8-638] synthesizing module 'xadc_eFEX' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] Parameter reg48 bound to: 16'b0100111100000001 Parameter reg49 bound to: 16'b0000010100001111 INFO: [Synth 8-113] binding component instance 'U_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:141] Parameter INIT_40 bound to: 16'b1001000000000000 Parameter INIT_41 bound to: 16'b0010111011110000 Parameter INIT_42 bound to: 16'b0000010000000000 Parameter INIT_43 bound to: 16'b0010111011110000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000001 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0100111100000001 Parameter INIT_49 bound to: 16'b0000010100001111 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101100110011001 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1101110111011101 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101000100010001 Parameter INIT_56 bound to: 16'b1001000111101011 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:147] INFO: [Synth 8-256] done synthesizing module 'xadc_eFEX' (44#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] INFO: [Synth 8-256] done synthesizing module 'ipbus_xadc_drp' (45#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 0 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'd' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized2' (45#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd:157] INFO: [Synth 8-638] synthesizing module 'ipbus_i2c_master_arb' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/i2c_arbitration.vhd:24] Parameter addr_width bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 2 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch' (46#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_i2c_master' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd:25] Parameter addr_width bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'i2c_master_top' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:111] Parameter ARST_LVL bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:258] INFO: [Synth 8-3491] module 'i2c_master_byte_ctrl' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:80' bound to instance 'byte_controller' of component 'i2c_master_byte_ctrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:283] INFO: [Synth 8-638] synthesizing module 'i2c_master_byte_ctrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:106] INFO: [Synth 8-256] done synthesizing module 'i2c_master_byte_ctrl' (47#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:106] INFO: [Synth 8-3491] module 'i2c_master_bit_ctrl' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:122' bound to instance 'bit_controller' of component 'i2c_master_bit_ctrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:303] INFO: [Synth 8-638] synthesizing module 'i2c_master_bit_ctrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:146] INFO: [Synth 8-256] done synthesizing module 'i2c_master_bit_ctrl' (48#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:146] INFO: [Synth 8-3491] module 'i2c_master_registers' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:81' bound to instance 'registers' of component 'i2c_master_registers' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:322] INFO: [Synth 8-638] synthesizing module 'i2c_master_registers' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:101] INFO: [Synth 8-256] done synthesizing module 'i2c_master_registers' (49#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:101] INFO: [Synth 8-256] done synthesizing module 'i2c_master_top' (50#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:111] INFO: [Synth 8-256] done synthesizing module 'ipbus_i2c_master' (51#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd:25] INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] Parameter TIMER_WIDTH bound to: 20 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog' (52#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] INFO: [Synth 8-256] done synthesizing module 'ipbus_i2c_master_arb' (53#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/i2c_arbitration.vhd:24] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] Parameter BYTE_SPI bound to: 0 - type: bool Parameter ADDR_WIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized0' (53#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized3' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 4 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized3' (53#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash' (54#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized0' (54#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'command_sync' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-256] done synthesizing module 'command_sync' (55#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-638] synthesizing module 'spi32_8_control' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter BYTE_SPI bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'spi32_8_control' (56#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] INFO: [Synth 8-638] synthesizing module 'clock_pulse' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'clock_pulse' (57#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32' (58#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] Parameter BYTE_SPI bound to: 1 - type: bool Parameter ADDR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized1' (58#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized1' (58#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized2' (58#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'spi32_8_control__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter BYTE_SPI bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'spi32_8_control__parameterized0' (58#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32__parameterized0' (58#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_ram' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ram' (59#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] INFO: [Synth 8-256] done synthesizing module 'infrastructure_slaves_cntrl' (60#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd:69] INFO: [Synth 8-638] synthesizing module 'pll_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/pll_selector.vhd:22] INFO: [Synth 8-256] done synthesizing module 'pll_selector' (61#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/pll_selector.vhd:22] INFO: [Synth 8-638] synthesizing module 'startup' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-113] binding component instance 'STARTUPE2_inst' to cell 'STARTUPE2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:34] INFO: [Synth 8-256] done synthesizing module 'startup' (62#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] INFO: [Synth 8-638] synthesizing module 'self_configure' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/self_configure.vhd:36] INFO: [Synth 8-638] synthesizing module 'reconfig' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:37] Parameter DEVICE_ID bound to: 32'b00000011011001010001000010010011 Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-113] binding component instance 'ICAPE2_inst' to cell 'ICAPE2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:70] INFO: [Synth 8-256] done synthesizing module 'reconfig' (63#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:37] INFO: [Synth 8-256] done synthesizing module 'self_configure' (64#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/self_configure.vhd:36] INFO: [Synth 8-3491] module 'clk_ttc' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/clk_ttc_stub.vhdl:5' bound to instance 'ttc_clk' of component 'clk_ttc' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:900] INFO: [Synth 8-638] synthesizing module 'clk_ttc' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/clk_ttc_stub.vhdl:17] INFO: [Synth 8-638] synthesizing module 'nreset_pll' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_pll.vhd:27] INFO: [Synth 8-638] synthesizing module 'nreset_gen' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_gen.vhd:31] INFO: [Synth 8-256] done synthesizing module 'nreset_gen' (65#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_gen.vhd:31] INFO: [Synth 8-256] done synthesizing module 'nreset_pll' (66#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_pll.vhd:27] INFO: [Synth 8-638] synthesizing module 'top_mgt_cfpga' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:90] Parameter NProcessorFPGA bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'MGT_quad_gen' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd:89] Parameter num_quad_tx_rx bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt_tx_rx_6g4_wrapper' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_wrapper.vhd:221] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_support' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:420] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1434] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:111] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'ibufds_instq1_clk0' to cell 'IBUFDS_GTE2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:182] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg0_i' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:196] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg1_i' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:204] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' (67#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:111] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4_common' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:70' bound to instance 'common0_i' of component 'MGT_TX_RX_6G4_common' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1473] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_common' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:92] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0000100000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-113] binding component instance 'gthe2_common_i' to cell 'GTHE2_COMMON' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:164] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_common' (68#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:92] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4_common_reset' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'MGT_TX_RX_6G4_common_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1493] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_common_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_common_reset' (69#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:91] INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/MGT_TX_RX_6G4_stub.vhdl:5' bound to instance 'MGT_TX_RX_6G4_init_i' of component 'MGT_TX_RX_6G4' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1506] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/MGT_TX_RX_6G4_stub.vhdl:245] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_support' (70#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:420] INFO: [Synth 8-256] done synthesizing module 'mgt_tx_rx_6g4_wrapper' (71#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_wrapper.vhd:221] INFO: [Synth 8-256] done synthesizing module 'MGT_quad_gen' (72#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd:89] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_gen' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:61] Parameter num_quad_tx_rx bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_wrapper' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:207] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_support' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:410] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1370] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:111] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'ibufds_instq1_clk1' to cell 'IBUFDS_GTE2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:182] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg0_i' to cell 'BUFH' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:196] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg1_i' to cell 'BUFH' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:204] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' (73#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:111] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga_common' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:70' bound to instance 'common0_i' of component 'mgt11g2_tx_rx_cfpga_common' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1409] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_common' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:97] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000001011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-113] binding component instance 'gthe2_common_i' to cell 'GTHE2_COMMON' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:169] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_common' (74#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:97] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga_common_reset' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'mgt11g2_tx_rx_cfpga_common_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1434] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_common_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_common_reset' (75#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:91] INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt11g2_tx_rx_cfpga_stub.vhdl:5' bound to instance 'mgt11g2_tx_rx_cfpga_init_i' of component 'mgt11g2_tx_rx_cfpga' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1448] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt11g2_tx_rx_cfpga_stub.vhdl:232] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_support' (76#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:410] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_wrapper' (77#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:207] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_gen' (78#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:61] INFO: [Synth 8-256] done synthesizing module 'top_mgt_cfpga' (79#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:90] WARNING: [Synth 8-614] signal 'reg_temp0' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1047] WARNING: [Synth 8-614] signal 'reg_temp1' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1047] INFO: [Synth 8-638] synthesizing module 'top_cntrl_synch' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/top_ctrl_synch.vhd:54] INFO: [Synth 8-638] synthesizing module 'd_type' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/d_type.vhd:24] INFO: [Synth 8-256] done synthesizing module 'd_type' (80#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/d_type.vhd:24] INFO: [Synth 8-638] synthesizing module 'tac_sm' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:37] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:70] INFO: [Synth 8-256] done synthesizing module 'tac_sm' (81#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:37] INFO: [Synth 8-638] synthesizing module 'first_stage_synch' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:52] INFO: [Synth 8-638] synthesizing module 'SRL16E_cntrl' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:31] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] INFO: [Synth 8-256] done synthesizing module 'SRL16E_cntrl' (82#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:31] INFO: [Synth 8-256] done synthesizing module 'first_stage_synch' (83#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:52] INFO: [Synth 8-638] synthesizing module 'ctrl_synch_latch' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ctrl_synch_latch.vhd:26] INFO: [Synth 8-256] done synthesizing module 'ctrl_synch_latch' (84#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ctrl_synch_latch.vhd:26] INFO: [Synth 8-256] done synthesizing module 'top_cntrl_synch' (85#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/top_ctrl_synch.vhd:54] INFO: [Synth 8-638] synthesizing module 'cntrl_crc_checker' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/cntrl_crc_checker.vhd:34] INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd:18] Parameter REVERSE_BIT_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (86#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd:18] INFO: [Synth 8-638] synthesizing module 'ttc_crc_sm' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_crc_sm.vhd:43] INFO: [Synth 8-256] done synthesizing module 'ttc_crc_sm' (87#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_crc_sm.vhd:43] INFO: [Synth 8-256] done synthesizing module 'cntrl_crc_checker' (88#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/cntrl_crc_checker.vhd:34] INFO: [Synth 8-3491] module 'ila_1' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_1_stub.vhdl:5' bound to instance 'crc_ila_hub1' of component 'ila_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1100] INFO: [Synth 8-638] synthesizing module 'ila_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_1_stub.vhdl:13] INFO: [Synth 8-3491] module 'ila_0' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_0_stub.vhdl:5' bound to instance 'combined_ttc_ila' of component 'ila_0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1329] INFO: [Synth 8-638] synthesizing module 'ila_0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_0_stub.vhdl:13] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1359] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1373] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'ttc_parity' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd:23] Parameter SEED bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'ttc_parity' (89#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd:23] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-638] synthesizing module 'backplane_registers' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:58] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 28 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (89#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized4' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 2 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized4' (89#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized5' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 6 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized5' (89#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:148] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:155] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:167] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:168] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:167] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:168] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized6' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 4 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized6' (89#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:195] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:200] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:195] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:200] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] INFO: [Synth 8-638] synthesizing module 'cntr_generic' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 32 - type: integer Parameter WRAPAROUND bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic' (90#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'backplane_registers' (91#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:58] INFO: [Synth 8-638] synthesizing module 'mgt_cntrl_slaves' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_cntrl_slaves.vhd:61] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized3' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 3 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized3' (91#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'cntrl_mgt_quad_slaves' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized4' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 8 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized4' (91#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'led_stretch' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/led_stretch.vhd:23] INFO: [Synth 8-256] done synthesizing module 'led_stretch' (92#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/led_stretch.vhd:23] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:147] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:160] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:187] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:188] INFO: [Synth 8-638] synthesizing module 'gt_information' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:67] Parameter addr_width bound to: 3 - type: integer WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:111] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:112] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:124] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:125] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:138] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:150] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:151] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:163] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:164] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:176] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:177] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:189] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:190] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:202] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:203] INFO: [Synth 8-638] synthesizing module 'counter' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] Parameter DEPTH bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'counter' (93#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] INFO: [Synth 8-256] done synthesizing module 'gt_information' (94#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:67] INFO: [Synth 8-256] done synthesizing module 'cntrl_mgt_quad_slaves' (95#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-638] synthesizing module 'cntrl_mgt_quad_slaves__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:147] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:160] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:187] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:188] INFO: [Synth 8-256] done synthesizing module 'cntrl_mgt_quad_slaves__parameterized0' (95#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-638] synthesizing module 'cntrl_mgt_quad_slaves__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:147] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:160] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:187] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:188] INFO: [Synth 8-256] done synthesizing module 'cntrl_mgt_quad_slaves__parameterized1' (95#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-256] done synthesizing module 'mgt_cntrl_slaves' (96#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_cntrl_slaves.vhd:61] INFO: [Synth 8-638] synthesizing module 'packet_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:99] Parameter NProcessorFPGA bound to: 4 - type: integer Parameter TOB_FIFO_ADDR_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_ADDR_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_ADDR_WIDTH bound to: 13 - type: integer Parameter TOB_SPY_ADDR_WIDTH bound to: 11 - type: integer Parameter RAW_SPY_ADDR_WIDTH bound to: 11 - type: integer Parameter MERGER_SPY_ADDR_WIDTH bound to: 10 - type: integer Parameter AURORA_SPY_ADDR_WIDTH bound to: 12 - type: integer Parameter MAX_BUILT_PACKET_WIDTH bound to: 9 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:637] INFO: [Synth 8-638] synthesizing module 'mgt_buffer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b00 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b00 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver' (97#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt_axi_fifo_stub.vhdl:5' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] INFO: [Synth 8-638] synthesizing module 'mgt_axi_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt_axi_fifo_stub.vhdl:26] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram' (98#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62] INFO: [Synth 8-3491] module 'ila_1' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_1_stub.vhdl:5' bound to instance 'mgt_ila' of component 'ila_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer' (99#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:675] INFO: [Synth 8-638] synthesizing module 'fifo_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:37] INFO: [Synth 8-256] done synthesizing module 'fifo_selector' (100#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:37] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:693] INFO: [Synth 8-638] synthesizing module 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_ram_fifo' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:16' bound to instance 'data_ram_fifo' of component 'packet_ram_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:94] INFO: [Synth 8-638] synthesizing module 'packet_ram_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_ram_fifo' (101#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-3491] module 'packet_fifo' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo.vhd:14' bound to instance 'data_fifo' of component 'packet_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:116] INFO: [Synth 8-638] synthesizing module 'packet_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo.vhd:48] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_fifo' (102#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo.vhd:48] INFO: [Synth 8-256] done synthesizing module 'packet_fifo_block' (103#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:718] INFO: [Synth 8-638] synthesizing module 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:26] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-256] done synthesizing module 'fwft_register' (104#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:26] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:737] INFO: [Synth 8-638] synthesizing module 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:25] INFO: [Synth 8-256] done synthesizing module 'packet_fifo_reset_block' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:25] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:747] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:772] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:791] Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:637] INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b11 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b11 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver__parameterized1' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt_axi_fifo_stub.vhdl:5' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-3491] module 'ila_1' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_1_stub.vhdl:5' bound to instance 'mgt_ila' of component 'ila_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized1' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:675] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:693] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:718] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:737] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:747] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:772] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:791] Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:637] INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized3' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b01 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver__parameterized3' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b01 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver__parameterized3' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt_axi_fifo_stub.vhdl:5' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-3491] module 'ila_1' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_1_stub.vhdl:5' bound to instance 'mgt_ila' of component 'ila_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized3' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:675] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:693] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:718] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:737] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:747] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:772] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:791] Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:637] INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized5' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b10 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver__parameterized5' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b10 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver__parameterized5' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/mgt_axi_fifo_stub.vhdl:5' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-3491] module 'ila_1' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/ila_1_stub.vhdl:5' bound to instance 'mgt_ila' of component 'ila_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized5' (105#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:675] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:693] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:718] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:737] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:747] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:772] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:791] Parameter DELAY_DEPTH bound to: 63 - type: integer INFO: [Synth 8-3491] module 'ttc_fifo_block' declared at '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:15' bound to instance 'ttc_fifos' of component 'ttc_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:803] INFO: [Synth 8-638] synthesizing module 'ttc_fifo_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:42] Parameter DELAY_DEPTH bound to: 63 - type: integer Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (106#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:78184' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'fifo_40M_160M' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/fifo_40M_160M_stub.vhdl:20] INFO: [Synth 8-256] done synthesizing module 'ttc_fifo_block' (107#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:42] Parameter DATA_FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'efex_tob_merger' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_merger.vhd:48] Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'efex_tob_processer' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_processor.vhd:52] Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter NSRC bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_merger' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter NSRC bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_merger' (108#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'efex_tob_processer' (109#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_processor.vhd:52] Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_merger__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_merger__parameterized1' (109#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter NSRC bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_mux' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter NSRC bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_mux' (110#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'efex_tob_merger' (111#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_merger.vhd:48] Parameter RAM_ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'tob_merger_spy' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/tob_merger_spy.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 10 - type: integer Parameter IPBUS_ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'fifo_spy' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] Parameter IPBUS_ADDR_WIDTH bound to: 10 - type: integer Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram64' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram64' (112#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] INFO: [Synth 8-256] done synthesizing module 'fifo_spy' (113#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] INFO: [Synth 8-256] done synthesizing module 'tob_merger_spy' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/tob_merger_spy.vhd:43] Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter RAM_ADDR_WIDTH bound to: 10 - type: integer Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_fifo_block__parameterized2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 11 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_ram_fifo__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_ram_fifo__parameterized1' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_fifo_block__parameterized2' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized7' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b00 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized7' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_ram_fifo__parameterized3' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_ram_fifo__parameterized3' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized9' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b11 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized9' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized11' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b01 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized11' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized13' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b10 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized13' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_mux__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_mux__parameterized1' (114#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter NSRC bound to: 6 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_builder' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_builder.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-638] synthesizing module 'CRC20' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-256] done synthesizing module 'CRC20' (115#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'CRC20__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'CRC20__parameterized1' (115#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] INFO: [Synth 8-256] done synthesizing module 'efex_packet_builder' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_builder.vhd:31] Parameter IPBUS_ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-638] synthesizing module 'fifo_spy__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] Parameter IPBUS_ADDR_WIDTH bound to: 12 - type: integer Parameter ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram64__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] Parameter ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram64__parameterized1' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] INFO: [Synth 8-256] done synthesizing module 'fifo_spy__parameterized1' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] Parameter DATA_WIDTH bound to: 65 - type: integer Parameter IPBUS_ADDR_WIDTH bound to: 12 - type: integer Parameter TOB_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_status_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_status_block.vhd:176] Parameter TOB_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'rdout_ipb_slave' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:185] Parameter TOB_FIFO_MAX_ADDR_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_MAX_ADDR_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_MAX_ADDR_WIDTH bound to: 13 - type: integer Parameter PACKET_MAX_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized5' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 62 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized5' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized7' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 7 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized7' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] INFO: [Common 17-14] Message 'Synth 8-6778' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized8' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 9 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized8' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized9' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 3 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized9' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized10' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 12 - type: integer Parameter N_STAT bound to: 0 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'd' ignored [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized10' (116#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-256] done synthesizing module 'rdout_ipb_slave' (117#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:185] INFO: [Synth 8-638] synthesizing module 'rdout_err_cnt' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_err_cnt.vhd:91] INFO: [Synth 8-256] done synthesizing module 'rdout_err_cnt' (118#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_err_cnt.vhd:91] INFO: [Synth 8-638] synthesizing module 'rdout_monitor' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_monitor.vhd:100] INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 35 - type: integer Parameter WRAPAROUND bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized0' (118#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'rdout_monitor' (119#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_monitor.vhd:100] INFO: [Synth 8-638] synthesizing module 'packet_tide_mark_block' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_tide_mark_block.vhd:33] Parameter NChannels bound to: 46 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_tide_mark_block' (120#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_tide_mark_block.vhd:33] INFO: [Synth 8-256] done synthesizing module 'packet_status_block' (121#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_status_block.vhd:176] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'packet_block' (122#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:99] INFO: [Synth 8-638] synthesizing module 'axi_stream_fifo' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/axi_stream_fifo_stub.vhdl:28] INFO: [Synth 8-638] synthesizing module 'ufc_controller' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/ufc_controller.vhd:36] Parameter TX_DATA_WIDTH bound to: 64 - type: integer Parameter GAP_WIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'ufc_controller' (123#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/ufc_controller.vhd:36] INFO: [Synth 8-638] synthesizing module 'aurora_hub2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_hub2.vhd:73] INFO: [Synth 8-638] synthesizing module 'aurora_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'aurora_reset' (124#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'aurora_wrapper_hub2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_wrapper_hub2.vhd:50] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_support' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:221] INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:33137] Parameter CLKCM_CFG bound to: TRUE - type: string Parameter CLKRCV_TRST bound to: TRUE - type: string Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (125#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:33137] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_CLOCK_MODULE' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_clock_module.vhd:86] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (126#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_CLOCK_MODULE' (127#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_clock_module.vhd:86] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support_reset_logic.vhd:81] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_cdc_sync_exdes' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd:153] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_cdc_sync_exdes' (128#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd:153] INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_SUPPORT_RESET_LOGIC' (129#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support_reset_logic.vhd:81] WARNING: [Synth 8-5640] Port 'gt_qpllclk_quad4_i' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt_qpllrefclk_quad4_i' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_gtrefclk0_common_in' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qplllock_out' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qplllockdetclk_in' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qpllrefclklost_out' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qpllreset_in' is missing in component declaration [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_gt_common_wrapper' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_gt_common_wrapper.vhd:93] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_gt_common_wrapper' (130#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_gt_common_wrapper.vhd:93] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-13322-efex-heavyduty-vm0.cern.ch/realtime/efex_aurora_hub2_stub.vhdl:131] INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_support' (131#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:221] INFO: [Synth 8-256] done synthesizing module 'aurora_wrapper_hub2' (132#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_wrapper_hub2.vhd:50] INFO: [Synth 8-256] done synthesizing module 'aurora_hub2' (133#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_hub2.vhd:73] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.mgt_slaves'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1509] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.synch_hub2_combined_ttc'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1150] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.synch_ttc_combined'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1057] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.MGT_TX_RX'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:994] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.crc_checker_hub2'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1168] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.crc_checker_hub1'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1075] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.top_aurora_hub1'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1783] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.hub1_ufc_block'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1679] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.top_aurora_hub2'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1829] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.hub2_ufc_block'. This will prevent further optimization [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1718] INFO: [Synth 8-256] done synthesizing module 'top_efex_control' (134#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:182] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2897.660 ; gain = 288.551 ; free physical = 74383 ; free virtual = 161465 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.531 ; gain = 303.422 ; free physical = 74193 ; free virtual = 161275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2912.531 ; gain = 303.422 ; free physical = 74193 ; free virtual = 161275 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2919.469 ; gain = 0.000 ; free physical = 74385 ; free virtual = 161665 INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.combined_ttc_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.combined_ttc_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel1_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel1_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel2_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel2_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.crc_ila_hub1' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.crc_ila_hub1' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4/MGT_TX_RX_6G4_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4/MGT_TX_RX_6G4_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc] for cell 'ttc_clk' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc] for cell 'ttc_clk' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4/mac_fifo_axi4_in_context.xdc] for cell 'eth/fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4/mac_fifo_axi4_in_context.xdc] for cell 'eth/fifo' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc] for cell 'eth/emac0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc] for cell 'eth/emac0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3128.879 ; gain = 0.000 ; free physical = 73576 ; free virtual = 160680 INFO: [Project 1-111] Unisim Transformation Summary: A total of 19 instances were transformed. IBUFGDS => IBUFDS: 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 16 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3128.879 ; gain = 0.000 ; free physical = 73492 ; free virtual = 160596 WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.crc_ila_hub1' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.hub1_axi_stream_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.hub2_axi_stream_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.output_channel1_ila' at clock pin 'clk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.output_channel2_ila' at clock pin 'clk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'eth/fifo' at clock pin 's_aclk' is different from the actual clock period '8.000', this can lead to different synthesis results. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 3147.719 ; gain = 538.609 ; free physical = 73131 ; free virtual = 160236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx330tffg1157-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 3147.719 ; gain = 538.609 ; free physical = 73131 ; free virtual = 160235 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for clk_40_n. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk_40_n. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for clk_40_p. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk_40_p. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_clk. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_clk. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_dv. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_dv. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_er. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_er. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[0]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[0]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[1]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[1]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[2]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[2]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[3]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[3]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[4]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[4]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[5]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[5]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[6]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[6]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[7]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[7]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for gmii_gtx_clk. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_gtx_clk. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for gmii_tx_en. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_tx_en. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for gmii_tx_er. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_tx_er. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[0]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[0]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[1]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[1]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[2]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[2]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[3]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[3]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[4]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[4]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[5]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[5]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[6]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[6]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[7]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[7]. (constraint file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 48). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.top_aurora_hub1 /aurora_core/aurora_module_i/efex_aurora_hub2_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.top_aurora_hub2 /aurora_core/aurora_module_i/efex_aurora_hub2_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.combined_ttc_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.output_channel1_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.output_channel2_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.hub1_axi_stream_fifo . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.hub2_axi_stream_fifo . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.crc_ila_hub1 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[0].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[1].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[2].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[3].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[0].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[1].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[2].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[3].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[0].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[1].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[2].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[3].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /ttc_fifos/ttc_fifo_A. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /ttc_fifos/ttc_fifo_B. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /ttc_fifos/ttc_fifo_delay. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.MGT_TX_RX /MGT_TX_RX_11G2/\MGT_GEN[0].mgt_1quad_Rx_Tx /mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.MGT_TX_RX /MGT_TX_RX_11G2/\MGT_GEN[1].mgt_1quad_Rx_Tx /mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.MGT_TX_RX /MGT_TX_RX_6G4/\MGT_GEN[0].mgt_quad_Rx_Tx /min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for ttc_clk. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for eth/fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for eth/emac0. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 3147.719 ; gain = 538.609 ; free physical = 73103 ; free virtual = 160208 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'xadc_eFEX' INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_byte_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_bit_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'command_sync' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'NEXT_STATE_reg' in module 'reconfig' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'nreset_gen' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'tac_sm' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'ttc_crc_sm' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver__parameterized3' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver__parameterized5' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'efex_packet_merger' INFO: [Synth 8-802] inferred FSM for state register 'state_sig_reg' in module 'efex_tob_processer' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'efex_packet_merger__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'state_sig_reg' in module 'efex_tob_merger' INFO: [Synth 8-802] inferred FSM for state register 'state_machine.next_state_reg' in module 'efex_packet_builder' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init_read | 00000000000000000000000000000000000000001 | 000000 read_waitdrdy | 00000000000000000000000000000000000000010 | 000001 write_waitdrdy | 00000000000000000000000000000000000000100 | 000010 read_reg00 | 00000000000000000000000000000000000001000 | 000011 reg00_waitdrdy | 00000000000000000000000000000000000010000 | 000100 read_reg01 | 00000000000000000000000000000000000100000 | 000101 reg01_waitdrdy | 00000000000000000000000000000000001000000 | 000110 read_reg02 | 00000000000000000000000000000000010000000 | 000111 reg02_waitdrdy | 00000000000000000000000000000000100000000 | 001000 read_reg03 | 00000000000000000000000000000001000000000 | 001001 reg03_waitdrdy | 00000000000000000000000000000010000000000 | 001010 read_reg06 | 00000000000000000000000000000100000000000 | 001011 reg06_waitdrdy | 00000000000000000000000000001000000000000 | 001100 read_reg10 | 00000000000000000000000000010000000000000 | 001101 reg10_waitdrdy | 00000000000000000000000000100000000000000 | 001110 read_reg11 | 00000000000000000000000001000000000000000 | 001111 reg11_waitdrdy | 00000000000000000000000010000000000000000 | 010000 read_reg12 | 00000000000000000000000100000000000000000 | 010001 reg12_waitdrdy | 00000000000000000000001000000000000000000 | 010010 read_reg13 | 00000000000000000000010000000000000000000 | 010011 reg13_waitdrdy | 00000000000000000000100000000000000000000 | 010100 read_reg14 | 00000000000000000001000000000000000000000 | 010101 reg14_waitdrdy | 00000000000000000010000000000000000000000 | 010110 read_reg15 | 00000000000000000100000000000000000000000 | 010111 reg15_waitdrdy | 00000000000000001000000000000000000000000 | 011000 read_reg20 | 00000000000000010000000000000000000000000 | 011001 reg20_waitdrdy | 00000000000000100000000000000000000000000 | 011010 read_reg21 | 00000000000001000000000000000000000000000 | 011011 reg21_waitdrdy | 00000000000010000000000000000000000000000 | 011100 read_reg22 | 00000000000100000000000000000000000000000 | 011101 reg22_waitdrdy | 00000000001000000000000000000000000000000 | 011110 read_reg23 | 00000000010000000000000000000000000000000 | 011111 reg23_waitdrdy | 00000000100000000000000000000000000000000 | 100000 read_reg24 | 00000001000000000000000000000000000000000 | 100001 reg24_waitdrdy | 00000010000000000000000000000000000000000 | 100010 read_reg25 | 00000100000000000000000000000000000000000 | 100011 reg25_waitdrdy | 00001000000000000000000000000000000000000 | 100100 read_reg26 | 00010000000000000000000000000000000000000 | 100101 reg26_waitdrdy | 00100000000000000000000000000000000000000 | 100110 read_reg27 | 01000000000000000000000000000000000000000 | 100111 reg27_waitdrdy | 10000000000000000000000000000000000000000 | 101000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'xadc_eFEX' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 000 | 00000 st_start | 001 | 00001 st_read | 010 | 00010 st_write | 011 | 00100 st_ack | 100 | 01000 st_stop | 101 | 10000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_byte_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000 | 00000000000000000 start_a | 00001 | 00000000000000001 start_b | 00010 | 00000000000000010 start_c | 00011 | 00000000000000100 start_d | 00100 | 00000000000001000 start_e | 00101 | 00000000000010000 stop_a | 00110 | 00000000000100000 stop_b | 00111 | 00000000001000000 stop_c | 01000 | 00000000010000000 stop_d | 01001 | 00000000100000000 wr_a | 01010 | 00010000000000000 wr_b | 01011 | 00100000000000000 wr_c | 01100 | 01000000000000000 wr_d | 01101 | 10000000000000000 rd_a | 01110 | 00000001000000000 rd_b | 01111 | 00000010000000000 rd_c | 10000 | 00000100000000000 rd_d | 10001 | 00001000000000000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_bit_ctrl' INFO: [Synth 8-3971] The signal "ipbus_dpram_flash:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized0:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0001 | 00 request | 0010 | 01 done | 0100 | 10 iSTATE | 1000 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'one-hot' in module 'command_sync' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control' INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized1:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized2:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 data_00 | 0001 | 0001 data_01 | 0010 | 0010 data_02 | 0011 | 0011 data_03 | 0100 | 0100 data_04 | 0101 | 0101 data_05 | 0110 | 0110 data_06 | 0111 | 0111 data_07 | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'NEXT_STATE_reg' using encoding 'sequential' in module 'reconfig' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s0 | 00 | 00 s1 | 01 | 01 s2 | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'nreset_gen' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 wt_rstdone | 01 | 01 wt_comma | 10 | 10 wt_ttc_redge | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'tac_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000001 | 000 st0 | 000010 | 001 st1 | 000100 | 010 st2 | 001000 | 011 st3 | 010000 | 100 st4 | 100000 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'one-hot' in module 'ttc_crc_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver' INFO: [Synth 8-3971] The signal "ipbus_dpram:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver__parameterized3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver__parameterized5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 * searching | 0010 | 01 pause | 0100 | 10 active | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'efex_packet_merger' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000000000001 | 0000 * prepare_l1id | 000000000010 | 0001 parse_l1id | 000000000100 | 0010 check_l1id | 000000001000 | 0011 start_debug_merger | 000000010000 | 0100 send_debug_header | 000000100000 | 0101 send_debug | 000001000000 | 0110 wait_fifo | 000010000000 | 0111 send_status | 000100000000 | 1000 skip_payload_header | 001000000000 | 1001 send_payload | 010000000000 | 1010 end_event | 100000000000 | 1011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_sig_reg' using encoding 'one-hot' in module 'efex_tob_processer' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0100 | 00 * searching | 0001 | 01 pause | 1000 | 10 active | 0010 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'efex_packet_merger__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000 | 000 * wait_fifos | 001 | 001 start_event | 010 | 010 prepare_tobs | 011 | 011 start_merger | 100 | 100 merge_tobs | 101 | 101 ifg | 110 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_sig_reg' using encoding 'sequential' in module 'efex_tob_merger' INFO: [Synth 8-3971] The signal "ipbus_dpram64:/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram64:/ram_th_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00000000001 | 0000 * capture_l1id | 00000000010 | 0001 do_hdr_crc | 00000000100 | 0010 wait_hdr_crc | 00000001000 | 0011 send_l1id | 00000010000 | 0100 send_payload | 00000100000 | 0101 build_trailer | 00001000000 | 0110 do_trailer_crc | 00010000000 | 0111 wait_trailer_crc | 00100000000 | 1000 send_trailer | 01000000000 | 1001 wait_end | 10000000000 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_machine.next_state_reg' using encoding 'one-hot' in module 'efex_packet_builder' INFO: [Synth 8-3971] The signal "ipbus_dpram64__parameterized1:/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram64__parameterized1:/ram_th_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:00 ; elapsed = 00:01:07 . Memory (MB): peak = 3147.723 ; gain = 538.613 ; free physical = 72255 ; free virtual = 159377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 31 Bit Adders := 3 2 Input 24 Bit Adders := 1 2 Input 19 Bit Adders := 2 2 Input 16 Bit Adders := 5 2 Input 14 Bit Adders := 16 3 Input 13 Bit Adders := 16 2 Input 13 Bit Adders := 35 2 Input 12 Bit Adders := 11 2 Input 11 Bit Adders := 10 2 Input 10 Bit Adders := 18 2 Input 9 Bit Adders := 37 3 Input 8 Bit Adders := 8 2 Input 8 Bit Adders := 19 2 Input 7 Bit Adders := 5 3 Input 7 Bit Adders := 8 2 Input 6 Bit Adders := 14 2 Input 5 Bit Adders := 22 2 Input 4 Bit Adders := 94 3 Input 4 Bit Adders := 20 2 Input 3 Bit Adders := 16 2 Input 2 Bit Adders := 3 +---XORs : 2 Input 20 Bit XORs := 296 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 2 Input 9 Bit XORs := 274 2 Input 1 Bit XORs := 48 13 Input 1 Bit XORs := 1 21 Input 1 Bit XORs := 3 3 Input 1 Bit XORs := 10 9 Input 1 Bit XORs := 8 4 Input 1 Bit XORs := 6 15 Input 1 Bit XORs := 2 10 Input 1 Bit XORs := 4 19 Input 1 Bit XORs := 2 14 Input 1 Bit XORs := 2 12 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 2 +---Registers : 136 Bit Registers := 1 129 Bit Registers := 8 128 Bit Registers := 6 120 Bit Registers := 1 112 Bit Registers := 2 76 Bit Registers := 1 65 Bit Registers := 98 64 Bit Registers := 110 48 Bit Registers := 7 45 Bit Registers := 2 44 Bit Registers := 1 42 Bit Registers := 1 40 Bit Registers := 1 38 Bit Registers := 1 36 Bit Registers := 2 34 Bit Registers := 1 33 Bit Registers := 8 32 Bit Registers := 558 31 Bit Registers := 3 28 Bit Registers := 6 24 Bit Registers := 8 20 Bit Registers := 7 19 Bit Registers := 2 17 Bit Registers := 2 16 Bit Registers := 230 14 Bit Registers := 34 13 Bit Registers := 87 12 Bit Registers := 39 11 Bit Registers := 26 10 Bit Registers := 55 9 Bit Registers := 69 8 Bit Registers := 132 7 Bit Registers := 9 6 Bit Registers := 28 5 Bit Registers := 33 4 Bit Registers := 108 3 Bit Registers := 81 2 Bit Registers := 123 1 Bit Registers := 1863 +---RAMs : 520K Bit (8192 X 65 bit) RAMs := 16 256K Bit (8192 X 32 bit) RAMs := 1 128K Bit (4096 X 32 bit) RAMs := 4 64K Bit (2048 X 32 bit) RAMs := 8 64K Bit (8192 X 8 bit) RAMs := 4 32K Bit (1024 X 32 bit) RAMs := 5 32K Bit (4096 X 8 bit) RAMs := 1 4K Bit (128 X 32 bit) RAMs := 2 1K Bit (16 X 65 bit) RAMs := 20 640 Bit (64 X 10 bit) RAMs := 4 512 Bit (16 X 32 bit) RAMs := 2 +---Muxes : 2 Input 136 Bit Muxes := 1 2 Input 129 Bit Muxes := 4 2 Input 128 Bit Muxes := 7 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 3 Input 112 Bit Muxes := 1 2 Input 112 Bit Muxes := 15 4 Input 112 Bit Muxes := 3 3 Input 76 Bit Muxes := 1 2 Input 65 Bit Muxes := 82 2 Input 64 Bit Muxes := 74 9 Input 64 Bit Muxes := 2 2 Input 48 Bit Muxes := 9 13 Input 48 Bit Muxes := 1 5 Input 48 Bit Muxes := 1 3 Input 42 Bit Muxes := 1 41 Input 41 Bit Muxes := 1 2 Input 41 Bit Muxes := 21 5 Input 40 Bit Muxes := 1 3 Input 38 Bit Muxes := 1 2 Input 36 Bit Muxes := 1 3 Input 36 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 32 Bit Muxes := 169 4 Input 32 Bit Muxes := 36 7 Input 32 Bit Muxes := 8 9 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 6 6 Input 32 Bit Muxes := 3 2 Input 31 Bit Muxes := 6 2 Input 24 Bit Muxes := 5 5 Input 24 Bit Muxes := 1 2 Input 20 Bit Muxes := 260 2 Input 19 Bit Muxes := 2 2 Input 17 Bit Muxes := 6 2 Input 16 Bit Muxes := 39 7 Input 16 Bit Muxes := 1 4 Input 16 Bit Muxes := 3 8 Input 16 Bit Muxes := 1 5 Input 16 Bit Muxes := 1 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 18 Input 16 Bit Muxes := 4 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 80 2 Input 13 Bit Muxes := 47 4 Input 13 Bit Muxes := 2 8 Input 13 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 93 9 Input 12 Bit Muxes := 8 12 Input 12 Bit Muxes := 8 2 Input 11 Bit Muxes := 16 11 Input 11 Bit Muxes := 2 2 Input 10 Bit Muxes := 52 4 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 293 3 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 156 5 Input 8 Bit Muxes := 23 6 Input 8 Bit Muxes := 2 4 Input 8 Bit Muxes := 2 13 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 1 3 Input 8 Bit Muxes := 1 41 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 20 7 Input 7 Bit Muxes := 1 63 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 116 6 Input 6 Bit Muxes := 7 3 Input 6 Bit Muxes := 3 4 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 40 29 Input 5 Bit Muxes := 1 24 Input 5 Bit Muxes := 1 6 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 5 Input 5 Bit Muxes := 1 9 Input 4 Bit Muxes := 24 13 Input 4 Bit Muxes := 8 2 Input 4 Bit Muxes := 324 4 Input 4 Bit Muxes := 60 7 Input 4 Bit Muxes := 2 3 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 2 15 Input 4 Bit Muxes := 1 5 Input 4 Bit Muxes := 3 2 Input 3 Bit Muxes := 163 4 Input 3 Bit Muxes := 49 7 Input 3 Bit Muxes := 5 6 Input 3 Bit Muxes := 3 5 Input 3 Bit Muxes := 3 15 Input 3 Bit Muxes := 1 8 Input 3 Bit Muxes := 4 2 Input 2 Bit Muxes := 56 3 Input 2 Bit Muxes := 17 4 Input 2 Bit Muxes := 9 41 Input 2 Bit Muxes := 2 17 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1615 3 Input 1 Bit Muxes := 44 7 Input 1 Bit Muxes := 57 9 Input 1 Bit Muxes := 82 4 Input 1 Bit Muxes := 88 6 Input 1 Bit Muxes := 80 12 Input 1 Bit Muxes := 10 8 Input 1 Bit Muxes := 11 11 Input 1 Bit Muxes := 14 5 Input 1 Bit Muxes := 9 41 Input 1 Bit Muxes := 23 18 Input 1 Bit Muxes := 7 13 Input 1 Bit Muxes := 9 16 Input 1 Bit Muxes := 9 17 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 1120 (col length:140) BRAMs: 1500 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3971] The signal "\GOLDEN_IF.readout_packet_blocki_10 /\TOB_sources[1].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "\GOLDEN_IF.readout_packet_blocki_11 /\TOB_sources[2].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\packet_tide_mark_block/tide_mark_procs[45]._tide_mark_block.tide_mark_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\packet_tide_mark_block/tide_mark_procs[44]._tide_mark_block.tide_mark_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[1][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[0][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[1][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[0][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[1][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[0][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[1][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[0][15] ) INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] WARNING: [Synth 8-7129] Port readout_delay[31] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[30] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[29] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[28] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[27] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[26] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[25] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[24] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[23] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[22] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[21] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[20] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[19] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[18] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[17] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[16] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[15] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[14] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[13] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[12] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[11] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[10] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[9] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port readout_delay[8] in module ttc_fifo_block is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ipb in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][31] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][30] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][29] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][28] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][27] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][26] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][25] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][24] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][23] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][22] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][21] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][20] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][19] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][18] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][17] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][16] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][15] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][14] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][13] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][12] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][11] in module mgt_buffer__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ipb in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][31] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][30] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][29] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][28] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][27] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][26] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][25] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][24] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][23] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][22] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][21] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][20] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][19] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][18] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][17] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][16] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][15] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][14] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][13] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][12] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][11] in module tob_merger_spy is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ipb in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][31] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][30] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][29] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][28] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][27] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][26] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][25] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][24] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][23] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][22] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][21] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][20] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][19] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][18] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][17] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][16] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][15] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][14] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][13] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][12] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][11] in module tob_merger_spy__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ipb in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][31] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][30] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][29] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][28] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][27] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][26] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][25] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][24] in module mgt_buffer__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipb_in[ipb_addr][23] in module mgt_buffer__parameterized9 is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3971] The signal "\TOB_sources[0].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_B/debug_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_B/debug_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_A/debug_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_A/debug_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "\TOB_sources[3].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[0]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[29]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[1]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[2]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[2]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[3]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[3]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[4]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[4]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[5]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[5]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[6]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[6]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[7]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[7]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[20]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[20]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[21]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[21]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[22]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[22]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[23]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[23]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[24]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[24]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[25]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[25]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[26]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[26]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[27]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[27]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[28]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[28]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[30]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[30]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tob_merge_B/\TOB_Header_block.header_reg[31] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (tob_spy_A/\debug_spy/fifo_tready_i_reg ) INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'ttc_fifos/ttc_veto_block_clk40.stretch_reg[15]' (FDS) to 'ttc_fifos/ttc_veto_clk40_reg' INFO: [Synth 8-3333] propagating constant 1 across sequential element (tob_spy_B/\debug_spy/fifo_tready_i_reg ) INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[0].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[0].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3886] merging instance 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]' (FDE) to 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[2]' (FDE) to 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' (FDE) to 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[0].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[3].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3886] merging instance 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[0]' (FDE) to 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' (FDE) to 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[3].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[0]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[29]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[1]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[2]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[2]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[3]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[3]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[4]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[4]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[5]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[5]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[6]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[6]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[7]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[7]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[20]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[20]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[21]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[21]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[22]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[22]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[23]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[23]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[24]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[24]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[25]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[25]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[26]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[26]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[27]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[27]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[28]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[28]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[30]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[30]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tob_merge_A/\TOB_Header_block.header_reg[31] ) INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bulk_sources[1].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3886] merging instance 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[0]' (FDE) to 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]' INFO: [Synth 8-3886] merging instance 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[2]' (FDE) to 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bulk_sources[1].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (TOB_sources[0].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[1].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[2].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[3].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_merger/FSM_onehot_state_reg[2]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[0].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_sources[1].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_sources[2].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_sources[3].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_merger/FSM_onehot_state_reg[2]) is unused and will be removed from module efex_tob_merger. INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Synth 8-3971] The signal "\Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bulk_sources[3].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bulk_sources[3].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3917] design packet_block__GCB4 has port ipbus_built_fifo_rbus_array[0][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design packet_block__GCB4 has port ipbus_built_fifo_rbus_array[1][ipb_err] driven by constant 0 INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg to conserve power WARNING: [Synth 8-6014] Unused sequential element spi_dpram_out/ram_reg was removed. INFO: [Synth 8-3971] The signal "\infrastructure_control/spi_pll/spi_dpram_in/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power WARNING: [Synth 8-6014] Unused sequential element spi_dpram_out/ram_reg was removed. INFO: [Synth 8-3971] The signal "\infrastructure_control/spi_flash/spi_dpram_in/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power WARNING: [Synth 8-3332] Sequential element (synch/FSM_onehot_sequencer_reg[3]) is unused and will be removed from module ipbus_spi32. WARNING: [Synth 8-3332] Sequential element (synch/FSM_onehot_sequencer_reg[3]) is unused and will be removed from module ipbus_spi32__parameterized0. INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-5544] ROM "buf_to_load_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status_buffer/\header_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.IPAM_block /\dhcp_discover._dhcp_block.data_buffer_reg[7] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_5/udp_if /IPADDR/\dhcp_offer._MAC_IP_addr_rx_dhcp.pkt_mask_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.IPAM_block /\ipam_end_addr_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ARP /\arp_end_addr_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /payload/\do_cksum.payload_len_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\bigendian.unreliable_data_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.reliable_data_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\ipbus_pkt.pkt_data_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.unreliable_data_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\primary_mode._ping.pkt_data_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /tx_main/\default_mode._udp_build_data.pay_len_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /tx_main/\default_mode._udp_build_data.pay_len_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ping /\int_data_ping_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ping /\int_data_ping_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\resend.pkt_data_reg[3] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_5/udp_if /status_buffer/\header_reg[125] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status_buffer/\header_reg[127] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ping /\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ARP /\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status/\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status/\addr_to_set_reg[6] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_5/udp_if /\primary_mode.IPAM_block /\ipam_req_block.req_end_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_7/parse_address.ip_addr_int_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /tx_main/\state_machine.addr_to_set_int_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_7/mac_addr_reg[37] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_7/mac_addr_reg[39] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /payload/\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /payload/\addr_to_set_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/trans/sm/err_d_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\f5_ipbus_access_led_block.reset_counter_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\l1a_stretch_block.reset_counter_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\ipbus_pkt.pkt_data_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.unreliable_data_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\primary_mode._ping.pkt_data_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\resend.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\ipbus_pkt.pkt_data_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.unreliable_data_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\primary_mode._ping.pkt_data_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.unreliable_data_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:03:33 ; elapsed = 00:04:18 . Memory (MB): peak = 3151.637 ; gain = 542.527 ; free physical = 66062 ; free virtual = 154547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |\TOB_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[0].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[0].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[0].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[1].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[1].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_B | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_B | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\TOB_sources[1].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_A | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_A | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\TOB_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_10 /\TOB_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_11 /\TOB_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | Bulk_sources[3].raw_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[0].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[2].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |ipbus_dpram_flash: | ram_reg | 16 x 32(READ_FIRST) | W | R | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_pll | spi_dpram_in/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |top_efex_control__GCB2 | infrastructure_control/RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | |\U_0/U_5/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |\TOB_sources[0].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[0].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[0].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[1].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Bulk_sources[3].raw_fifo_A/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[3].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control__GCB4 | U_0/U_0/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB4 | U_0/U_1/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB4 | U_0/U_2/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB4 | U_0/U_3/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:43 ; elapsed = 00:04:29 . Memory (MB): peak = 3151.637 ; gain = 542.527 ; free physical = 65583 ; free virtual = 154454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:04:06 ; elapsed = 00:04:52 . Memory (MB): peak = 3155.715 ; gain = 546.605 ; free physical = 65474 ; free virtual = 154620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |\TOB_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[0].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[0].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[0].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[1].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[1].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_B | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_B | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\TOB_sources[1].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_A | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_A | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\TOB_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_10 /\TOB_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_11 /\TOB_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | Bulk_sources[3].raw_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[0].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[2].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |ipbus_dpram_flash: | ram_reg | 16 x 32(READ_FIRST) | W | R | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_pll | spi_dpram_in/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |top_efex_control__GCB2 | infrastructure_control/RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | |\U_0/U_5/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Distributed RAM: Final Mapping Report +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |\TOB_sources[0].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[0].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[0].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[1].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Bulk_sources[3].raw_fifo_A/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[3].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control__GCB4 | U_0/U_0/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB4 | U_0/U_1/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB4 | U_0/U_2/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB4 | U_0/U_3/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-5816] Retiming module `clocks_7s_extphy__GC0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `clocks_7s_extphy__GC0' done INFO: [Synth 8-5816] Retiming module `rdout_err_cnt` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `rdout_err_cnt' done INFO: [Synth 8-5816] Retiming module `packet_status_block__GB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_status_block__GB2' done INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized1' done INFO: [Synth 8-5816] Retiming module `packet_block__GCB1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_block__GCB1' done INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized3` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized3' done INFO: [Synth 8-5816] Retiming module `packet_block__GCB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_block__GCB2' done INFO: [Synth 8-5816] Retiming module `packet_block__GCB4` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_block__GCB4' done INFO: [Synth 8-5816] Retiming module `top_cntrl_synch__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_cntrl_synch__1' done INFO: [Synth 8-5816] Retiming module `ufc_controller__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ufc_controller__1' done INFO: [Synth 8-5816] Retiming module `ufc_controller` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ufc_controller' done INFO: [Synth 8-5816] Retiming module `aurora_hub2__xdcDup__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `aurora_hub2__xdcDup__1' done INFO: [Synth 8-5816] Retiming module `aurora_hub2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `aurora_hub2' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB1' done INFO: [Synth 8-5816] Retiming module `top_mgt_cfpga` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_mgt_cfpga' done INFO: [Synth 8-5816] Retiming module `ipbus_spi32` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ipbus_spi32' done INFO: [Synth 8-5816] Retiming module `ipbus_spi32__parameterized0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ipbus_spi32__parameterized0' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB2' done INFO: [Synth 8-5816] Retiming module `mgt_cntrl_slaves` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `mgt_cntrl_slaves' done INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker__1' done INFO: [Synth 8-5816] Retiming module `top_cntrl_synch` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_cntrl_synch' done INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB3` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB3' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_10/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_10/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_11/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_11/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_13/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_pll/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/RAM/reg_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-5816] Retiming module `packet_status_block__GB0_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_status_block__GB0_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-5816] Retiming module `packet_status_block__GB1_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_status_block__GB1_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-5816] Retiming module `mgt_buffer` Numbers of forward move = 0, and backward move = 2 Retimed registers names: GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 INFO: [Synth 8-5816] Retiming module `mgt_buffer' done INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized5` Numbers of forward move = 0, and backward move = 3 Retimed registers names: GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__1 GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized5' done WARNING: [Synth 8-3332] Sequential element (MGT_receiver/Trailer_checker.write_block_reg_bret) is unused and will be removed from module mgt_buffer__parameterized5. WARNING: [Synth 8-3332] Sequential element (MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret) is unused and will be removed from module mgt_buffer__parameterized5. INFO: [Synth 8-5816] Retiming module `packet_block__GCB0_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_block__GCB0_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_9/GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-5816] Retiming module `packet_block__GCB3_tempName` Numbers of forward move = 0, and backward move = 9 Retimed registers names: GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__4 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__1 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__3 GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__4 INFO: [Synth 8-5816] Retiming module `packet_block__GCB3_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_blocki_12/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB0_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB0_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB4_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB4_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_4/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:05:16 ; elapsed = 00:06:12 . Memory (MB): peak = 3167.641 ; gain = 558.531 ; free physical = 65340 ; free virtual = 154268 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_pll/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:05:36 ; elapsed = 00:06:32 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65243 ; free virtual = 154187 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:05:36 ; elapsed = 00:06:33 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65262 ; free virtual = 154206 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:05:51 ; elapsed = 00:06:48 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65136 ; free virtual = 154070 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:05:52 ; elapsed = 00:06:48 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65134 ; free virtual = 154069 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:05:54 ; elapsed = 00:06:51 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65110 ; free virtual = 154045 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:05:54 ; elapsed = 00:06:51 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65101 ; free virtual = 154036 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-----------------+-------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-----------------+-------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top_cntrl_synch | temp2_reg | 3 | 2 | NO | NO | YES | 2 | 0 | |top_efex_control | GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/in_data_reg_reg[0] | 3 | 256 | NO | NO | YES | 256 | 0 | |top_efex_control | master_rx1_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | master_rx2_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | master_rx3_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | master_rx4_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |top_efex_control | U_0/U_5/udp_if/resend/resend_pkt_id_block.pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[33] | 6 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._arp.pkt_mask_reg[29] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_mask_reg[41] | 4 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[18] | 5 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._ping.pkt_mask_reg[35] | 23 | 1 | YES | NO | YES | 0 | 1 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[37] | 23 | 1 | YES | NO | YES | 0 | 1 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._arp.pkt_mask_reg[41] | 12 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._arp.pkt_mask_reg[19] | 8 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_mask_reg[75] | 12 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_mask_reg[60] | 8 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_mask_reg[51] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_mask_reg[30] | 25 | 1 | YES | NO | YES | 0 | 1 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._ping.pkt_mask_reg[11] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[71] | 5 | 4 | YES | NO | YES | 4 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[59] | 4 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._arp.pkt_data_reg[111] | 10 | 4 | YES | NO | YES | 4 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._arp.pkt_data_reg[90] | 4 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode._arp.pkt_data_reg[72] | 5 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_data_reg[135] | 11 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_data_reg[129] | 5 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_data_reg[123] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_data_reg[106] | 4 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer._dhcp.pkt_data_reg[100] | 7 | 1 | YES | NO | YES | 1 | 0 | +-----------------+-------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Retiming Report: +--------------------+----+ |Retiming summary: | | +--------------------+----+ |Forward Retiming | 0 | |Backward Retiming | 14 | |New registers added | 67 | |Registers deleted | 10 | +--------------------+----+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------------+----------+ | |BlackBox name |Instances | +------+--------------------+----------+ |1 |efex_aurora_hub2 | 2| |2 |ila_0 | 3| |3 |axi_stream_fifo | 2| |4 |mgt11g2_tx_rx_cfpga | 2| |5 |MGT_TX_RX_6G4 | 1| |6 |ila_1 | 5| |7 |clk_ttc | 1| |8 |mgt_axi_fifo | 8| |9 |fifo_40M_160M | 3| |10 |temac_gbe_v9_0 | 1| |11 |mac_fifo_axi4 | 1| +------+--------------------+----------+ Report Cell Usage: +------+-----------------------------+------+ | |Cell |Count | +------+-----------------------------+------+ |1 |MGT_TX_RX_6G4_bbox | 1| |2 |axi_stream_fifo_bbox | 2| |4 |clk_ttc_bbox | 1| |5 |efex_aurora_hub2_bbox | 1| |6 |efex_aurora_hub2_bbox_42_ | 1| |7 |fifo_40M_160M_bbox | 3| |10 |ila_0_bbox | 3| |13 |ila_1_bbox | 5| |18 |mac_fifo_axi4_bbox | 1| |19 |mgt11g2_tx_rx_cfpga_bbox | 1| |20 |mgt11g2_tx_rx_cfpga_bbox_20_ | 1| |21 |mgt_axi_fifo_bbox | 8| |29 |temac_gbe_v9_0_bbox | 1| |30 |BUFG | 13| |31 |BUFH | 4| |32 |CARRY4 | 3390| |33 |GTHE2_COMMON | 7| |34 |IBUFDS_GTE2 | 5| |35 |ICAPE2 | 1| |36 |IDELAYCTRL | 1| |37 |LUT1 | 725| |38 |LUT2 | 2647| |39 |LUT3 | 2745| |40 |LUT4 | 5627| |41 |LUT5 | 5623| |42 |LUT6 | 12366| |43 |MMCME2_BASE | 1| |44 |MUXF7 | 588| |45 |MUXF8 | 5| |46 |RAM16X1D | 1300| |47 |RAM64X1D | 40| |48 |RAMB18E1 | 16| |49 |RAMB36E1 | 314| |59 |SRL16 | 1| |60 |SRL16E | 398| |61 |SRLC32E | 191| |62 |STARTUPE2 | 1| |63 |XADC | 1| |64 |FDCE | 152| |65 |FDPE | 46| |66 |FDRE | 49472| |67 |FDSE | 1245| |68 |IBUF | 114| |69 |IBUFGDS | 1| |70 |IOBUF | 1| |71 |OBUF | 243| |72 |OBUFDS | 16| +------+-----------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:05:55 ; elapsed = 00:06:52 . Memory (MB): peak = 3196.121 ; gain = 587.012 ; free physical = 65108 ; free virtual = 154043 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 118 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:05:44 ; elapsed = 00:06:36 . Memory (MB): peak = 3200.027 ; gain = 355.730 ; free physical = 66564 ; free virtual = 155499 Synthesis Optimization Complete : Time (s): cpu = 00:06:00 ; elapsed = 00:06:54 . Memory (MB): peak = 3200.027 ; gain = 590.918 ; free physical = 66576 ; free virtual = 155498 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3200.027 ; gain = 0.000 ; free physical = 66485 ; free virtual = 155407 INFO: [Netlist 29-17] Analyzing 5675 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3318.680 ; gain = 0.000 ; free physical = 66488 ; free virtual = 155405 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1360 instances were transformed. IBUFGDS => IBUFDS: 1 instance IOBUF => IOBUF (IBUF, OBUFT): 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 40 instances SRL16 => SRL16E: 1 instance INFO: [Common 17-83] Releasing license: Synthesis 1227 Infos, 291 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:06:34 ; elapsed = 00:07:31 . Memory (MB): peak = 3318.680 ; gain = 709.570 ; free physical = 66717 ; free virtual = 155635 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/top_efex_control.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3318.688 ; gain = 0.008 ; free physical = 66799 ; free virtual = 155705 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_synth.rpt -pb top_efex_control_utilization_synth.pb source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-synthesis.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.5.6-hog9532924 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.5.6-hog9532924... INFO: [Hog:Msg-0] Copying synthesised IP MGT_TX_RX_6G4 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: MGT_TX_RX_6G4.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP axi_stream_fifo to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: axi_stream_fifo.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP clk_ttc to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: clk_ttc.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP efex_aurora_hub2 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: efex_aurora_hub2.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP fifo_40M_160M to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: fifo_40M_160M.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP ila_0 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: ila_0.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP ila_1 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: ila_1.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP mac_fifo_axi4 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: mac_fifo_axi4.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP mgt11g2_tx_rx_cfpga to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: mgt11g2_tx_rx_cfpga.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP mgt_axi_fifo to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: mgt_axi_fifo.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP temac_gbe_v9_0 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: temac_gbe_v9_0.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] All done. INFO: [Common 17-206] Exiting Vivado at Thu Jun 8 12:16:53 2023...