<!-- Top level of data path structure  -->
<!-- version: 1.5.0     sha: 035A149 -->

<node id="efex_cntrl_data_path" fwinfo="endpoint;width=16">

  <node id="control" address="0x0" fwinfo="endpoint;width=3" description="Control registers for status counters and spy RAMs" >
   <node id="readout_delay" address="0x0" permission="rw" description="Control register for readout delay" >
    <node description="Number of BC*32 to delay readout after L1A"	id="number_srl32" mask="0xf" />
   </node>
   <node id="counter_control" address="0x1" permission="rw" description="Control register for status counter update and reset" >
    <node description="Pulsed counter update on assert"	id="pulse_update" mask="0x1" />
    <node description="Prescaled counter update on BCR"	id="prescale_update" mask="0x2" />
    <node description="Continuous counter update"		id="force_update" mask="0x4" />
    <node description="Reset All Error Counters"		id="err_cntr_rst" mask="0x10" />
    <node description="Reset All Status Counters"		id="status_cntr_rst" mask="0x20" />
    <node description="Reset All XOff/BUSY Counters"	id="xoff_cntr_rst" mask="0x40" />
    <node description="Prescale factor"					id="prescale_factor" mask="0xffffff00" />
   </node>
   <node id="spy_ram_reset_write_address"	address="0x2" permission="rw" description="Reset Write Address Pointer for each spy RAM" >
    <node id="tob_mgt_spy"	mask="0x0000000F"  description="TOB MGT P3 downto P0" />
    <node id="raw_mgt_spy"	mask="0x000000F0"  description="Raw MGT P3 downto P0" />
    <node id="aurora_spy"	mask="0x00000300"  description="Aurora channel 1 downto 0" />
    <node id="tob_merger_debug_spy"	mask="0x00000C00"  description="Merger B downto A" />
   </node>
   <node id="spy_ram_wraparound_enable"	address="0x3" permission="rw" description="Enable wraparound of Write Address Pointer for each spy RAM" >
    <node id="tob_mgt_spy"	mask="0x0000000F"  description="TOB MGT P3 downto P0" />
    <node id="raw_mgt_spy"	mask="0x000000F0"  description="Raw MGT P3 downto P0" />
    <node id="aurora_spy"	mask="0x00000300"  description="Aurora channel 1 downto 0" />
    <node id="tob_merger_debug_spy"	mask="0x00000C00"  description="Merger B downto A" />
   </node>
   <node id="fifo_bc_count"	address="0x4" permission="r" description="Reference BC counter for FIFO BUSY and xoff status" />
  </node>

  <node id="fifo_control" address="0x20" description="FIFO threshold registers"  fwinfo="endpoint;width=4">
   <node id="tob_fifo_prog_full_thresh_assert"	address="0x0" permission="rw" description="tob_fifo_fill_level BUSY assertion threshold"/>
   <node id="tob_fifo_prog_full_thresh_negate"	address="0x1" permission="rw" description="tob_fifo_fill_level BUSY negation threshold"/>
   <node id="raw_fifo_prog_full_thresh_assert"	address="0x2" permission="rw" description="raw_fifo_fill_level BUSY assertion threshold"/>
   <node id="raw_fifo_prog_full_thresh_negate"	address="0x3" permission="rw" description="raw_fifo_fill_level BUSY negation threshold"/>
   <node id="tob_fifo_xoff_thresh_assert"		address="0x4" permission="rw" description="tob_fifo_fill_level XOFF assertion threshold"/>
   <node id="tob_fifo_xoff_thresh_negate"		address="0x5" permission="rw" description="tob_fifo_fill_level XOFF negation threshold"/>
   <node id="raw_fifo_xoff_thresh_assert"		address="0x6" permission="rw" description="raw_fifo_fill_level XOFF assertion threshold"/>
   <node id="raw_fifo_xoff_thresh_negate"		address="0x7" permission="rw" description="raw_fifo_fill_level XOFF negation threshold"/>
   <node id="merged_fifo_xoff_thresh_assert"	address="0x8" permission="rw" description="merged_tob_fifo_fill_level XOFF assertion threshold"/>
   <node id="merged_fifo_xoff_thresh_negate"	address="0x9" permission="rw" description="merged_tob_fifo_fill_level XOFF negation threshold"/>
   <node id="dbg_fifo_xoff_thresh_assert"		address="0xA" permission="rw" description="debug_fifo_fill_level XOFF assertion threshold"/>
   <node id="dbg_fifo_xoff_thresh_negate"		address="0xB" permission="rw" description="debug_fifo_fill_level XOFF negation threshold"/>
  </node>

  <node id="tob_mgt_status" address="0x80" description="TOB MGT status block">
   <node id="p0" address="0x0"  description="Processor 0" module="file://efex_cntrl_data_path_mgt_status.xml"/>
   <node id="p1" address="0x10" description="Processor 1" module="file://efex_cntrl_data_path_mgt_status.xml"/>
   <node id="p2" address="0x20" description="Processor 2" module="file://efex_cntrl_data_path_mgt_status.xml"/>
   <node id="p3" address="0x30" description="Processor 3" module="file://efex_cntrl_data_path_mgt_status.xml"/>
  </node>

  <node id="raw_mgt_status" address="0xC0" description="Raw MGT status block">
   <node id="p0" address="0x0"  description="Processor 0" module="file://efex_cntrl_data_path_mgt_status.xml"/>
   <node id="p1" address="0x10" description="Processor 1" module="file://efex_cntrl_data_path_mgt_status.xml"/>
   <node id="p2" address="0x20" description="Processor 2" module="file://efex_cntrl_data_path_mgt_status.xml"/>
   <node id="p3" address="0x30" description="Processor 3" module="file://efex_cntrl_data_path_mgt_status.xml"/>
  </node>

  <node id="tob_fifo_status_a" address="0x100" description="TOB FIFO status block A">
   <node id="p0" address="0x0"  description="Processor 0" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p1" address="0x10" description="Processor 1" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p2" address="0x20" description="Processor 2" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p3" address="0x30" description="Processor 3" module="file://efex_cntrl_data_path_fifo_status.xml"/>
  </node>

  <node id="tob_fifo_status_b" address="0x140" description="TOB FIFO status block B">
   <node id="p0" address="0x0"  description="Processor 0" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p1" address="0x10" description="Processor 1" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p2" address="0x20" description="Processor 2" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p3" address="0x30" description="Processor 3" module="file://efex_cntrl_data_path_fifo_status.xml"/>
  </node>

  <node id="raw_fifo_status" address="0x180" description="Raw FIFO status block">
   <node id="p0" address="0x0"  description="Processor 0" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p1" address="0x10" description="Processor 1" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p2" address="0x20" description="Processor 2" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="p3" address="0x30" description="Processor 3" module="file://efex_cntrl_data_path_fifo_status.xml"/>
  </node>

  <node id="tob_merger_status_a" address="0x1C0" description="TOB merger status block A">
   <node id="merger" address="0x0" description="Merger status" fwinfo="endpoint;width=1">
    <node id="l1a_count" address="0x0" description="Number of L1A processed" permission="r"/>
    <node id="last_l1id" address="0x1" description="Last L1ID processed" permission="r"/>
   </node>
   <node id="p0" address="0x4" description="Processor 0" module="file://efex_cntrl_data_path_merger_status.xml"/>
   <node id="p1" address="0x8" description="Processor 1" module="file://efex_cntrl_data_path_merger_status.xml"/>
   <node id="p2" address="0xC" description="Processor 2" module="file://efex_cntrl_data_path_merger_status.xml"/>
   <node id="p3" address="0x10" description="Processor 3" module="file://efex_cntrl_data_path_merger_status.xml"/>
  </node>

  <node id="tob_merger_status_b" address="0x1E0" description="TOB merger status block B">
   <node id="merger" address="0x0" description="Merger status" fwinfo="endpoint;width=1">
    <node id="l1a_count" address="0x0" description="Number of L1A processed" permission="r"/>
    <node id="last_l1id" address="0x1" description="Last L1ID processed" permission="r"/>
   </node>
   <node id="p0" address="0x4" description="Processor 0" module="file://efex_cntrl_data_path_merger_status.xml"/>
   <node id="p1" address="0x8" description="Processor 1" module="file://efex_cntrl_data_path_merger_status.xml"/>
   <node id="p2" address="0xC" description="Processor 2" module="file://efex_cntrl_data_path_merger_status.xml"/>
   <node id="p3" address="0x10" description="Processor 3" module="file://efex_cntrl_data_path_merger_status.xml"/>
  </node>

  <node id="merged_fifo_status_a" address="0x200" description="Merged FIFO status block A">
   <node id="tob"	address="0x0"	description="TOB packets" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="debug"	address="0x10"	description="Debug packets" module="file://efex_cntrl_data_path_fifo_status.xml"/>
  </node>

  <node id="merged_fifo_status_b" address="0x220" description="Merged FIFO status block B">
   <node id="tob"	address="0x0"	description="TOB packets" module="file://efex_cntrl_data_path_fifo_status.xml"/>
   <node id="debug"	address="0x10"	description="Debug packets" module="file://efex_cntrl_data_path_fifo_status.xml"/>
  </node>

  <node id="mux_status_a" address="0x240" description="MUX status block A">
   <node id="mux_active" permission="r"   address="0x0" description="BC per orbit that MUX is active" fwinfo="endpoint;width=0">
    <node id="tidemark" 	  mask="0xffff0000" description="Peak level" />
    <node id="value"  mask="0xffff" description="Last Orbit" />
   </node>
   <node id="tob"	address="0x4" description="TOB packets" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="debug"	address="0x8" description="Debug packets" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_0" address="0xC" description="Raw Processor 0" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_1" address="0x10" description="Raw Processor 1" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_2" address="0x14" description="Raw Processor 2" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_3" address="0x18" description="Raw Processor 3" module="file://efex_cntrl_data_path_mux_status.xml"/>
  </node>

  <node id="mux_status_b" address="0x280" description="MUX status block B">
   <node id="mux_active" permission="r"   address="0x0" description="BC per orbit that MUX is active" fwinfo="endpoint;width=0">
    <node id="tidemark" 	  mask="0xffff0000" description="Peak level" />
    <node id="value"  mask="0xffff" description="Last Orbit" />
   </node>
   <node id="tob"	address="0x4" description="TOB packets" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="debug"	address="0x8" description="Debug packets" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_0" address="0xC" description="Raw Processor 0" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_1" address="0x10" description="Raw Processor 1" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_2" address="0x14" description="Raw Processor 2" module="file://efex_cntrl_data_path_mux_status.xml"/>
   <node id="raw_3" address="0x18" description="Raw Processor 3" module="file://efex_cntrl_data_path_mux_status.xml"/>
  </node>

 <node id="tob_mgt_p0_spy" address="0x10000"  mode="block" size="0x800"  description="Processor 0 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_mgt_p1_spy" address="0x20000"  mode="block" size="0x800"  description="Processor 1 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_mgt_p2_spy" address="0x30000"  mode="block" size="0x800"  description="Processor 2 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_mgt_p3_spy" address="0x40000"  mode="block" size="0x800"  description="Processor 3 TOB MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p0_spy" address="0x50000"  mode="block" size="0x800"  description="Processor 0 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p1_spy" address="0x60000"  mode="block" size="0x800"  description="Processor 1 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p2_spy" address="0x70000"  mode="block" size="0x800"  description="Processor 2 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="raw_mgt_p3_spy" address="0x80000"  mode="block" size="0x800"  description="Processor 3 Raw MGT Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="aurora_channel0_spy" address="0x90000"  mode="block" size="0x2000"  description="Aurora Channel 0 Spy RAM" fwinfo="endpoint;width=13" permission="rw"/>
 <node id="aurora_channel1_spy" address="0xA0000"  mode="block" size="0x2000"  description="Aurora Channel 1 Spy RAM" fwinfo="endpoint;width=13" permission="rw"/>
 <node id="tob_merger_a_spy" address="0xB0000"  mode="block" size="0x800"  description="TOB Merger A Debug Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>
 <node id="tob_merger_b_spy" address="0xC0000"  mode="block" size="0x800"  description="TOB Merger B Debug Spy RAM" fwinfo="endpoint;width=11" permission="rw"/>

</node>
