## Repository info - Merge request number: 306 - Branch name: fix_busy_flag_2nd ## MR Description Implement BUSY flag Bring in BDT branch (disabled by default) Bug fix in Terminator packet logic in efex_tob_processor No longer reset readout logic on Aurora link resets Add add parity bit and BCN to TTC distribution from Control FPGA ## Changelog - no longer reset readout logic on Aurora link resets ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 9663925 | 1.5.6 | | Constraints | 96639250 | 1.5.6 | | IPbus XML | 36d50f0 | 1.5.6 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 36d50f0 | 1.5.6 | | **Lib:** algolib | 966b35f | 1.5.6 | | **Lib:** infrastructure_lib | 9d51af7 | 1.5.6 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e9b43d6 | 1.5.6 | | Constraints | 9d51af7e | 1.5.6 | | IPbus XML | 36d50f0 | 1.5.6 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 36d50f0 | 1.5.6 | | **Lib:** algolib | 966b35f | 1.5.6 | | **Lib:** infrastructure_lib | 9d51af7 | 1.5.6 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e9b43d6 | 1.5.6 | | Constraints | 00fb8dc1 | 1.5.6 | | IPbus XML | 36d50f0 | 1.5.6 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 36d50f0 | 1.5.6 | | **Lib:** algolib | 966b35f | 1.5.6 | | **Lib:** infrastructure_lib | 9d51af7 | 1.5.6 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | e9b43d6 | 1.5.6 | | Constraints | 00fb8dc1 | 1.5.6 | | IPbus XML | 36d50f0 | 1.5.6 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 36d50f0 | 1.5.6 | | **Lib:** algolib | 966b35f | 1.5.6 | | **Lib:** infrastructure_lib | 9d51af7 | 1.5.6 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 9532924 | 1.5.6 | | Constraints | 00fb8dc1 | 1.5.6 | | IPbus XML | 035a149 | 1.5.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** infrastructure_lib | 9532924 | 1.5.6 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.049477 | | TNS: | 0.000000 | | WHS: | 0.015037 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.041718 | | TNS: | 0.000000 | | WHS: | 0.004680 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.015027 | | TNS: | 0.000000 | | WHS: | 0.018686 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.002214 | | TNS: | 0.000000 | | WHS: | 0.029175 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.042199 | | TNS: | 0.000000 | | WHS: | 0.050509 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182419 | 0 | 346400 | 52.66 | | Slice Registers | 256619 | 0 | 692800 | 37.04 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 190780 | 0 | 346400 | 55.08 | | Slice Registers | 281599 | 0 | 692800 | 40.65 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186258 | 0 | 346400 | 53.77 | | Slice Registers | 268194 | 0 | 692800 | 38.71 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 193787 | 0 | 346400 | 55.94 | | Slice Registers | 292774 | 0 | 692800 | 42.26 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182424 | 0 | 346400 | 52.66 | | Slice Registers | 256618 | 0 | 692800 | 37.04 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 502 | 0 | 600 | 83.67 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 189992 | 0 | 346400 | 54.85 | | Slice Registers | 280853 | 0 | 692800 | 40.54 | | Block RAM Tile | 731.5 | 0 | 1180 | 61.99 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 252 | 250 | 600 | 42.00 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186203 | 0 | 346400 | 53.75 | | Slice Registers | 268183 | 0 | 692800 | 38.71 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 500 | 0 | 600 | 83.33 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194221 | 0 | 346400 | 56.07 | | Slice Registers | 292693 | 0 | 692800 | 42.25 | | Block RAM Tile | 742.5 | 0 | 1180 | 62.92 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 448 | 448 | 600 | 74.67 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 30051 | 0 | 204000 | 14.73 | | Slice Registers | 50915 | 0 | 408000 | 12.48 | | Block RAM Tile | 322 | 0 | 750 | 42.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 382 | 0 | 600 | 63.67 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 37999 | 0 | 204000 | 18.63 | | Slice Registers | 69470 | 0 | 408000 | 17.03 | | Block RAM Tile | 361.5 | 0 | 750 | 48.20 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 350 | 338 | 600 | 58.33 |