*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2562.672 ; gain = 0.000 ; free physical = 67348 ; free virtual = 153464 INFO: [Netlist 29-17] Analyzing 6745 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3521.922 ; gain = 669.066 ; free physical = 66460 ; free virtual = 152543 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3545.926 ; gain = 0.000 ; free physical = 66626 ; free virtual = 152701 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:14 ; elapsed = 00:01:11 . Memory (MB): peak = 3545.926 ; gain = 1024.855 ; free physical = 66625 ; free virtual = 152696 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3553.930 ; gain = 8.000 ; free physical = 66579 ; free virtual = 152640 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 13e73d6ef Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3553.930 ; gain = 0.000 ; free physical = 66451 ; free virtual = 152497 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3764.680 ; gain = 0.000 ; free physical = 66130 ; free virtual = 151962 Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3764.680 ; gain = 0.000 ; free physical = 66135 ; free virtual = 151967 Phase 1 Generate And Synthesize Debug Cores | Checksum: 22a489b5f Time (s): cpu = 00:02:00 ; elapsed = 00:02:39 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66135 ; free virtual = 151967 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: f887b5bf Time (s): cpu = 00:02:08 ; elapsed = 00:02:47 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66227 ; free virtual = 152047 INFO: [Opt 31-389] Phase Retarget created 117 cells and removed 355 cells INFO: [Opt 31-1021] In phase Retarget, 438 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 1d2d1b750 Time (s): cpu = 00:02:09 ; elapsed = 00:02:48 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66216 ; free virtual = 152037 INFO: [Opt 31-389] Phase Constant propagation created 175 cells and removed 625 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 145e3f1c6 Time (s): cpu = 00:02:12 ; elapsed = 00:02:51 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66211 ; free virtual = 152031 INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 746 cells INFO: [Opt 31-1021] In phase Sweep, 4690 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 172b24038 Time (s): cpu = 00:02:14 ; elapsed = 00:02:53 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66217 ; free virtual = 152028 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1ab43aee3 Time (s): cpu = 00:02:14 ; elapsed = 00:02:53 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66217 ; free virtual = 152028 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 1782d965f Time (s): cpu = 00:02:15 ; elapsed = 00:02:53 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66217 ; free virtual = 152028 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 117 | 355 | 438 | | Constant propagation | 175 | 625 | 141 | | Sweep | 2 | 746 | 4690 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3764.680 ; gain = 0.000 ; free physical = 66199 ; free virtual = 152007 Ending Logic Optimization Task | Checksum: e2a13ae2 Time (s): cpu = 00:02:18 ; elapsed = 00:02:56 . Memory (MB): peak = 3764.680 ; gain = 43.785 ; free physical = 66199 ; free virtual = 152007 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 10d972b71 Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.719 ; gain = 0.000 ; free physical = 64800 ; free virtual = 151283 Ending Power Optimization Task | Checksum: 10d972b71 Time (s): cpu = 00:01:14 ; elapsed = 00:01:08 . Memory (MB): peak = 4795.719 ; gain = 1031.039 ; free physical = 64900 ; free virtual = 151383 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 201c0fd2f Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 4795.719 ; gain = 0.000 ; free physical = 64657 ; free virtual = 151151 Ending Final Cleanup Task | Checksum: 201c0fd2f Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 4795.719 ; gain = 0.000 ; free physical = 64651 ; free virtual = 151145 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.719 ; gain = 0.000 ; free physical = 64651 ; free virtual = 151145 Ending Netlist Obfuscation Task | Checksum: 201c0fd2f Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.719 ; gain = 0.000 ; free physical = 64651 ; free virtual = 151145 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:10 ; elapsed = 00:04:44 . Memory (MB): peak = 4795.719 ; gain = 1249.793 ; free physical = 64652 ; free virtual = 151145 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4795.719 ; gain = 0.000 ; free physical = 63939 ; free virtual = 150661 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 4795.723 ; gain = 0.004 ; free physical = 63921 ; free virtual = 150619 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63085 ; free virtual = 149980 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62939 ; free virtual = 149856 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 138c8d936 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62939 ; free virtual = 149856 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62938 ; free virtual = 149855 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a4a1826f Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62531 ; free virtual = 149575 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: ec82380a Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62265 ; free virtual = 149296 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: ec82380a Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62252 ; free virtual = 149286 Phase 1 Placer Initialization | Checksum: ec82380a Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62235 ; free virtual = 149277 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 10f2a8dda Time (s): cpu = 00:01:02 ; elapsed = 00:01:02 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62228 ; free virtual = 149271 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1a1563ac7 Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62217 ; free virtual = 149266 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 66 LUTNM shape to break, 2324 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 53, two critical 13, total 66, new lutff created 7 INFO: [Physopt 32-775] End 1 Pass. Optimized 954 nets or cells. Created 66 new cells, deleted 888 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 11 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 45 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 56 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 56 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62196 ; free virtual = 149251 INFO: [Physopt 32-76] Pass 1. Identified 14 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 7 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 7 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 12 nets. Created 64 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 64 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62249 ; free virtual = 149299 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-46] Identified 90 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[3]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[9]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[2]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[6]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[0]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/read_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-232] Optimized 14 nets. Created 14 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 14 nets or cells. Created 14 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62217 ; free virtual = 149267 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 18 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 11 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62242 ; free virtual = 149292 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62207 ; free virtual = 149257 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 66 | 888 | 954 | 0 | 1 | 00:00:02 | | Very High Fanout | 56 | 0 | 2 | 0 | 1 | 00:00:03 | | Fanout | 64 | 0 | 12 | 0 | 1 | 00:00:01 | | Critical Cell | 14 | 0 | 14 | 0 | 1 | 00:00:01 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 11 | 0 | 11 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 211 | 888 | 993 | 0 | 10 | 00:00:08 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 196029d8b Time (s): cpu = 00:03:14 ; elapsed = 00:03:17 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62276 ; free virtual = 149242 Phase 2.3 Global Placement Core | Checksum: 12871f90a Time (s): cpu = 00:03:19 ; elapsed = 00:03:22 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62282 ; free virtual = 149253 Phase 2 Global Placement | Checksum: 12871f90a Time (s): cpu = 00:03:19 ; elapsed = 00:03:23 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62314 ; free virtual = 149286 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 160406830 Time (s): cpu = 00:03:29 ; elapsed = 00:03:32 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62342 ; free virtual = 149304 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12414396e Time (s): cpu = 00:03:48 ; elapsed = 00:03:52 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62357 ; free virtual = 149234 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: e413f487 Time (s): cpu = 00:03:50 ; elapsed = 00:03:53 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62344 ; free virtual = 149221 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 19641ae7f Time (s): cpu = 00:03:50 ; elapsed = 00:03:54 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62331 ; free virtual = 149195 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 147379330 Time (s): cpu = 00:04:14 ; elapsed = 00:04:18 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62396 ; free virtual = 149177 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: 1b3789376 Time (s): cpu = 00:04:49 ; elapsed = 00:04:54 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62060 ; free virtual = 148980 Phase 3.6 Small Shape Detail Placement | Checksum: 1b3789376 Time (s): cpu = 00:04:50 ; elapsed = 00:04:55 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62078 ; free virtual = 148999 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1afad2f00 Time (s): cpu = 00:04:55 ; elapsed = 00:05:00 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62066 ; free virtual = 148983 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: f63ec38d Time (s): cpu = 00:04:56 ; elapsed = 00:05:01 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62034 ; free virtual = 148945 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 168a4aae4 Time (s): cpu = 00:05:45 ; elapsed = 00:05:50 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62069 ; free virtual = 148953 Phase 3 Detail Placement | Checksum: 168a4aae4 Time (s): cpu = 00:05:45 ; elapsed = 00:05:51 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62066 ; free virtual = 148950 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 17d96a97c Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.580 | TNS=-109.857 | Phase 1 Physical Synthesis Initialization | Checksum: 1a04c4977 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61576 ; free virtual = 148836 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/rst_xoff_cntr_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 13db67132 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61570 ; free virtual = 148833 Phase 4.1.1.1 BUFG Insertion | Checksum: 17d96a97c Time (s): cpu = 00:06:34 ; elapsed = 00:06:39 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61577 ; free virtual = 148840 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.069. For the most accurate timing information please run report_timing. Time (s): cpu = 00:09:37 ; elapsed = 00:09:42 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61839 ; free virtual = 149058 Phase 4.1 Post Commit Optimization | Checksum: c39a479e Time (s): cpu = 00:09:37 ; elapsed = 00:09:43 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61838 ; free virtual = 149057 Post Placement Optimization Initialization | Checksum: 154554a7f Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.681 | TNS=-193.754 | Phase 1 Physical Synthesis Initialization | Checksum: 1401aec69 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63808 ; free virtual = 151639 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/reg_reg[1][5]_13[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 174a66f43 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63800 ; free virtual = 151633 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.114. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1fb037581 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.114 | TNS=-5.679 | Phase 1 Physical Synthesis Initialization | Checksum: 1c6e61edb Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 72932 ; free virtual = 157840 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/reg_reg[1][5]_13[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1948967d3 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 72692 ; free virtual = 157601 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.114. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 15c08b066 Time (s): cpu = 00:17:37 ; elapsed = 00:17:43 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66286 ; free virtual = 151195 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 2x2| 4x4| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 1x1| 4x4| |___________|___________________|___________________| | West| 2x2| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 15c08b066 Time (s): cpu = 00:17:38 ; elapsed = 00:17:44 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66283 ; free virtual = 151192 Phase 4.3 Placer Reporting | Checksum: 15c08b066 Time (s): cpu = 00:17:38 ; elapsed = 00:17:45 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66282 ; free virtual = 151191 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66268 ; free virtual = 151177 Time (s): cpu = 00:17:38 ; elapsed = 00:17:45 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66268 ; free virtual = 151177 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ee7b3156 Time (s): cpu = 00:17:39 ; elapsed = 00:17:45 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66201 ; free virtual = 151110 Ending Placer Task | Checksum: 1969837f6 Time (s): cpu = 00:17:39 ; elapsed = 00:17:45 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66094 ; free virtual = 151003 INFO: [Common 17-83] Releasing license: Implementation 217 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:17:46 ; elapsed = 00:17:53 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66247 ; free virtual = 151156 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66098 ; free virtual = 151186 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66230 ; free virtual = 151176 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.47 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 66164 ; free virtual = 151111 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.66 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 65834 ; free virtual = 150783 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 62474 ; free virtual = 147423 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.114 | TNS=-5.679 | Phase 1 Physical Synthesis Initialization | Checksum: 19633ce44 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 59733 ; free virtual = 144682 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.114 | TNS=-5.679 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 19633ce44 Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 59769 ; free virtual = 144718 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.114 | TNS=-5.679 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data[15]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data_reg[15] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data[15]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.114 | TNS=-5.565 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data[16]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data_reg[16] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data[16]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[3]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.dout_valid_i_2__15 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data[64]_i_1__14_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/prefetched_data[64]_i_1__14_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.092 | TNS=-3.348 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[11]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[11] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[11]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.069 | TNS=-3.256 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_fifo/fifo_proc.last_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_fifo/last3_out. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.046 | TNS=-3.187 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[31]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[31] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[31]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_1. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__2 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[64]_i_1__9_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[64]_i_1__9_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.042 | TNS=-1.781 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_packet_merged_bus_reg[3]_0[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_merger/TOB_packet_merged_bus[1]_i_2_n_0. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_merger/TOB_packet_merged_bus[1]_i_2 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_merger/TOB_packet_merged_bus[1]_i_2_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.039 | TNS=-1.738 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/in_ready_sig_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_sources[2].tob_processer/register_process.dout_valid_reg. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_sources[2].tob_processer/in_ready_sig_i_2__3 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/in_ready_sig_i_1__3_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/in_ready_sig_i_1__3_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_sources[2].tob_processer/register_process.dout_valid_reg. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.037 | TNS=-1.699 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[26]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[26] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[26]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.037 | TNS=-1.661 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[28]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.037 | TNS=-1.624 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[36]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[36] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[36]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.037 | TNS=-1.587 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[47]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[47] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[47]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.037 | TNS=-1.549 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[6]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[6] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.037 | TNS=-1.512 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[7]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[7] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.474 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[39]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[39] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[39]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.444 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[42]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[42] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[42]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.414 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[43]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[43] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[43]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.384 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[48]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[48] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[48]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.354 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[53]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[53] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[53]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.324 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[55]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[55] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[55]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.294 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[7]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[7] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.264 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[9]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg[9] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[1].Packet_Builder_register/prefetched_data_reg_n_0_[9]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.234 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[28]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.229 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[29]. Did not re-place instance GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[29] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[29]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/Fatal__0. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data[63]_i_3__4 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/Fatal__0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.163 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/data_fifo_data[16]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_4_ENARDEN_cooolgate_en_sig_111. Re-placed instance GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_4_ENARDEN_cooolgate_en_gate_210 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_4_ENARDEN_cooolgate_en_sig_111. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.130 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.130 | Phase 3 Critical Path Optimization | Checksum: 19633ce44 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60787 ; free virtual = 145736 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.130 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[4]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[4] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.097 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[52]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[52] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[52]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.065 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[54]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[54] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[54]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.032 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[56]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[56] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[56]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.000 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[57]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[57] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[57]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.968 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[58]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[58] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[58]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.935 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[63]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data_reg[63] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_B/prefetched_data[63]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.903 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_B/middle_data[18]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_B/middle_data_reg[18] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_B/middle_data[18]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[5]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.dout_valid_i_2__16 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_B/middle_data[64]_i_1__18_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_B/middle_data[64]_i_1__18_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.030 | TNS=-0.735 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/out_data_reg[63]_0[22]. Did not re-place instance GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/out_data_reg[22] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/out_data_reg[63]_0[22]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/Fatal__0. Did not re-place instance GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/fifo_proc.Fatal_i_2__8 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/out_data[63]_i_1__10_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/out_data[63]_i_1__10_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_fifo/Fatal__0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-0.705 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[28]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.024 | TNS=-0.676 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_fifo/out_data_reg[63]_0[32]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/local_reset_reg_31. Re-placed instance GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/out_data[32]_i_2__2 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/local_reset_reg_31. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.022 | TNS=-0.672 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/out_data_reg[63]_0[63]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.last_i_3__6_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.last_i_3__6 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.last_i_3__6_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Tail[2]_i_1__6_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Tail[2]_i_2__4 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Tail[2]_i_1__6_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.021 | TNS=-0.649 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/Q[1]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/src_reg[1] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/Q[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/active017_out__1. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/round_robin[3]_i_3__1 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/active017_out__1. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_5_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_5 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_5_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_6_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_6 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_6_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.020 | TNS=-0.628 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data[1]_i_1__1_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.608 | INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_fifo/out_data[32]_i_1__11_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.588 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[21]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data_reg[21] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.571 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[57]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data_reg[57] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[57]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.015 | TNS=-0.554 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[36]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data_reg[36] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[36]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.015 | TNS=-0.538 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[53]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data_reg[53] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[53]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.015 | TNS=-0.523 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[55]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data_reg[55] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_A/middle_data[55]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.015 | TNS=-0.507 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.015 | TNS=-0.507 | Phase 4 Critical Path Optimization | Checksum: 19633ce44 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61378 ; free virtual = 146327 Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61381 ; free virtual = 146330 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.015 | TNS=-0.507 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.099 | 5.172 | 0 | 0 | 44 | 0 | 2 | 00:00:09 | | Total | 0.099 | 5.172 | 0 | 0 | 44 | 0 | 3 | 00:00:09 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61384 ; free virtual = 146333 Ending Physical Synthesis Task | Checksum: 185bc7534 Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61440 ; free virtual = 146389 INFO: [Common 17-83] Releasing license: Implementation 401 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 61451 ; free virtual = 146400 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60810 ; free virtual = 145934 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60808 ; free virtual = 145795 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 519e0e18 ConstDB: 0 ShapeSum: 71d09af4 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: a450bbc4 Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63439 ; free virtual = 148425 Post Restoration Checksum: NetGraph: 10d01067 NumContArr: 9380ab5d Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: a450bbc4 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63401 ; free virtual = 148388 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: a450bbc4 Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63397 ; free virtual = 148383 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: a450bbc4 Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 63392 ; free virtual = 148378 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: ff7582d5 Time (s): cpu = 00:01:47 ; elapsed = 00:01:48 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60911 ; free virtual = 145897 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.062 | TNS=-0.172 | WHS=-2.776 | THS=-4557.808| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1538f31e8 Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60388 ; free virtual = 145375 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.062 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 147b45b95 Time (s): cpu = 00:02:22 ; elapsed = 00:02:23 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60375 ; free virtual = 145361 Phase 2 Router Initialization | Checksum: bd6cfd66 Time (s): cpu = 00:02:22 ; elapsed = 00:02:23 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60370 ; free virtual = 145357 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 101790 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 101788 Number of Partially Routed Nets = 2 Number of Node Overlaps = 1 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: bd6cfd66 Time (s): cpu = 00:02:23 ; elapsed = 00:02:24 . Memory (MB): peak = 4795.723 ; gain = 0.000 ; free physical = 60382 ; free virtual = 145368 Phase 3 Initial Routing | Checksum: 14ea83bae Time (s): cpu = 00:04:48 ; elapsed = 00:04:50 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 54877 ; free virtual = 139864 INFO: [Route 35-580] Design has 26 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/FSM_sequential_current_state_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[1]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[0]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 8553 Number of Nodes with overlaps = 872 Number of Nodes with overlaps = 239 Number of Nodes with overlaps = 94 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.175 | TNS=-9.872 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1c4f2eebe Time (s): cpu = 00:06:50 ; elapsed = 00:06:54 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59606 ; free virtual = 144593 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 534 Number of Nodes with overlaps = 131 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.248 | TNS=-13.131| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 155ec20c2 Time (s): cpu = 00:07:12 ; elapsed = 00:07:16 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59367 ; free virtual = 144355 Phase 4 Rip-up And Reroute | Checksum: 155ec20c2 Time (s): cpu = 00:07:12 ; elapsed = 00:07:17 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59367 ; free virtual = 144355 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1a379373d Time (s): cpu = 00:07:24 ; elapsed = 00:07:28 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58764 ; free virtual = 143751 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.088 | TNS=-2.733 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 21982cf9e Time (s): cpu = 00:07:26 ; elapsed = 00:07:30 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58633 ; free virtual = 143620 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 21982cf9e Time (s): cpu = 00:07:26 ; elapsed = 00:07:30 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58646 ; free virtual = 143633 Phase 5 Delay and Skew Optimization | Checksum: 21982cf9e Time (s): cpu = 00:07:27 ; elapsed = 00:07:31 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58668 ; free virtual = 143655 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 187a00509 Time (s): cpu = 00:07:40 ; elapsed = 00:07:44 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58900 ; free virtual = 143887 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.078 | TNS=-2.421 | WHS=-1.432 | THS=-89.200| Phase 6.1 Hold Fix Iter | Checksum: 1ef411e2b Time (s): cpu = 00:07:41 ; elapsed = 00:07:45 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58852 ; free virtual = 143839 Phase 6 Post Hold Fix | Checksum: 19bc165f1 Time (s): cpu = 00:07:41 ; elapsed = 00:07:46 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 58824 ; free virtual = 143811 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 23a0d2ad0 Time (s): cpu = 00:07:58 ; elapsed = 00:08:03 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59211 ; free virtual = 144199 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.078 | TNS=-2.421 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 23a0d2ad0 Time (s): cpu = 00:07:59 ; elapsed = 00:08:03 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59190 ; free virtual = 144178 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.37245 % Global Horizontal Routing Utilization = 10.1103 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 81.0811%, No Congested Regions. South Dir 1x1 Area, Max Cong = 77.4775%, No Congested Regions. East Dir 1x1 Area, Max Cong = 89.7059%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X47Y145 -> INT_R_X47Y145 INT_R_X45Y143 -> INT_R_X45Y143 INT_R_X47Y143 -> INT_R_X47Y143 INT_L_X48Y138 -> INT_L_X48Y138 INT_L_X46Y136 -> INT_L_X46Y136 West Dir 1x1 Area, Max Cong = 83.8235%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 8 Route finalize | Checksum: 23a0d2ad0 Time (s): cpu = 00:08:00 ; elapsed = 00:08:04 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59155 ; free virtual = 144143 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 23a0d2ad0 Time (s): cpu = 00:08:00 ; elapsed = 00:08:04 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59151 ; free virtual = 144139 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 177a2fe6d Time (s): cpu = 00:08:09 ; elapsed = 00:08:13 . Memory (MB): peak = 4803.719 ; gain = 7.996 ; free physical = 59146 ; free virtual = 144134 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4803.719 ; gain = 0.000 ; free physical = 59019 ; free virtual = 144007 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.011. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 1b4db746a Time (s): cpu = 00:01:52 ; elapsed = 00:01:52 . Memory (MB): peak = 4898.336 ; gain = 94.617 ; free physical = 57440 ; free virtual = 142428 Phase 11 Incr Placement Change | Checksum: 177a2fe6d Time (s): cpu = 00:10:03 ; elapsed = 00:10:08 . Memory (MB): peak = 4900.410 ; gain = 104.688 ; free physical = 57439 ; free virtual = 142427 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: 953f3c7a Time (s): cpu = 00:10:17 ; elapsed = 00:10:22 . Memory (MB): peak = 4900.410 ; gain = 104.688 ; free physical = 57402 ; free virtual = 142390 Post Restoration Checksum: NetGraph: c8c13f53 NumContArr: 444b673e Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: 10d0ca691 Time (s): cpu = 00:10:21 ; elapsed = 00:10:26 . Memory (MB): peak = 4900.410 ; gain = 104.688 ; free physical = 57370 ; free virtual = 142358 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: 10d0ca691 Time (s): cpu = 00:10:22 ; elapsed = 00:10:27 . Memory (MB): peak = 4900.410 ; gain = 104.688 ; free physical = 57376 ; free virtual = 142364 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: 74c43c15 Time (s): cpu = 00:10:23 ; elapsed = 00:10:28 . Memory (MB): peak = 4900.410 ; gain = 104.688 ; free physical = 57376 ; free virtual = 142364 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: df0247a9 Time (s): cpu = 00:11:19 ; elapsed = 00:11:25 . Memory (MB): peak = 4949.410 ; gain = 153.688 ; free physical = 57319 ; free virtual = 142307 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.037 | TNS=-0.731 | WHS=-2.776 | THS=-4546.793| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 125c48655 Time (s): cpu = 00:11:52 ; elapsed = 00:11:58 . Memory (MB): peak = 4949.410 ; gain = 153.688 ; free physical = 57308 ; free virtual = 142296 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.037 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: b1b25901 Time (s): cpu = 00:11:53 ; elapsed = 00:11:58 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57306 ; free virtual = 142294 Phase 13 Router Initialization | Checksum: 17e79bf24 Time (s): cpu = 00:11:54 ; elapsed = 00:11:59 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57307 ; free virtual = 142295 Router Utilization Summary Global Vertical Routing Utilization = 8.36183 % Global Horizontal Routing Utilization = 10.0992 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 330 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 135 Number of Partially Routed Nets = 195 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14.1 Global Routing Phase 14.1 Global Routing | Checksum: 17e79bf24 Time (s): cpu = 00:11:55 ; elapsed = 00:12:00 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57322 ; free virtual = 142310 Phase 14 Initial Routing | Checksum: 260e8ff8f Time (s): cpu = 00:11:57 ; elapsed = 00:12:03 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57301 ; free virtual = 142290 INFO: [Route 35-580] Design has 55 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/FSM_sequential_current_state_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[3]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[2]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[1]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 168 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 61 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.095 | TNS=-1.324 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: 1f211d3a8 Time (s): cpu = 00:12:46 ; elapsed = 00:12:52 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57300 ; free virtual = 142288 Phase 15.2 Global Iteration 1 Number of Nodes with overlaps = 1867 Number of Nodes with overlaps = 334 Number of Nodes with overlaps = 176 Number of Nodes with overlaps = 81 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.072 | TNS=-0.630 | WHS=N/A | THS=N/A | Phase 15.2 Global Iteration 1 | Checksum: 12a680aad Time (s): cpu = 00:13:25 ; elapsed = 00:13:32 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57299 ; free virtual = 142288 Phase 15.3 Global Iteration 2 Number of Nodes with overlaps = 1243 Number of Nodes with overlaps = 309 Number of Nodes with overlaps = 108 Number of Nodes with overlaps = 54 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.206 | TNS=-13.783| WHS=N/A | THS=N/A | Phase 15.3 Global Iteration 2 | Checksum: 1ac53cbf2 Time (s): cpu = 00:14:08 ; elapsed = 00:14:16 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57297 ; free virtual = 142285 Phase 15 Rip-up And Reroute | Checksum: 1ac53cbf2 Time (s): cpu = 00:14:08 ; elapsed = 00:14:16 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57297 ; free virtual = 142285 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 1a80b3295 Time (s): cpu = 00:14:19 ; elapsed = 00:14:27 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57297 ; free virtual = 142286 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.015 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 16.1 Delay CleanUp | Checksum: 2185ab082 Time (s): cpu = 00:14:20 ; elapsed = 00:14:28 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57299 ; free virtual = 142287 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: 2185ab082 Time (s): cpu = 00:14:20 ; elapsed = 00:14:28 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57299 ; free virtual = 142287 Phase 16 Delay and Skew Optimization | Checksum: 2185ab082 Time (s): cpu = 00:14:20 ; elapsed = 00:14:28 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57299 ; free virtual = 142287 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 2517efa58 Time (s): cpu = 00:14:34 ; elapsed = 00:14:41 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57307 ; free virtual = 142295 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.015 | TNS=0.000 | WHS=-0.104 | THS=-2.981 | Phase 17.1 Hold Fix Iter | Checksum: 207ae1f84 Time (s): cpu = 00:14:34 ; elapsed = 00:14:42 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57306 ; free virtual = 142294 Phase 17 Post Hold Fix | Checksum: 1e0858e94 Time (s): cpu = 00:14:34 ; elapsed = 00:14:42 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57328 ; free virtual = 142316 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 1dbab122f Time (s): cpu = 00:14:51 ; elapsed = 00:14:59 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57309 ; free virtual = 142297 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.015 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 1dbab122f Time (s): cpu = 00:14:51 ; elapsed = 00:14:59 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57309 ; free virtual = 142297 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.4084 % Global Horizontal Routing Utilization = 10.1505 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 1dbab122f Time (s): cpu = 00:14:52 ; elapsed = 00:15:00 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57321 ; free virtual = 142309 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 1dbab122f Time (s): cpu = 00:14:53 ; elapsed = 00:15:01 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57298 ; free virtual = 142286 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: f6b14af6 Time (s): cpu = 00:15:01 ; elapsed = 00:15:09 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57196 ; free virtual = 142316 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.017 | TNS=0.000 | WHS=0.057 | THS=0.000 | Phase 22 Post Router Timing | Checksum: 1811d67ea Time (s): cpu = 00:15:44 ; elapsed = 00:15:52 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 56997 ; free virtual = 142286 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+--------+--------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 1 | -0.078 | -2.421 | -1.432 | - | Pass | 00:07:24 | | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 2 | 0.015 | 0.000 | -0.104 | - | Pass | 00:04:44 | x | +------+--------+--------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:15:45 ; elapsed = 00:15:53 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57230 ; free virtual = 142520 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 434 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:16:27 ; elapsed = 00:16:35 . Memory (MB): peak = 4965.410 ; gain = 169.688 ; free physical = 57230 ; free virtual = 142520 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.0-hogf6704a2 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value f6704a2 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.0-hogf6704a2 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.6.0-hogf6704a2... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.