*** Running vivado with args -log top_efex_processor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_efex_processor.tcl WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace source /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:Msg-0] Project efex_golden_processor.1 has flavour = 1, the generic variable FLAVOUR will be set to 1 INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1 clean. INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_processor.1-v1.6.0-hog7d3a917... INFO: [Hog:Msg-0] Opening project efex_golden_processor.1... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'. INFO: [Hog:Msg-0] Checking efex_golden_processor.1 list files... INFO: [Hog:Msg-0] Retrieved Vivado project files... INFO: [Hog:Msg-0] Design List Files matches project. Nothing to do. INFO: [Hog:Msg-0] Simulation List Files matches project. Nothing to do. INFO: [Hog:Msg-0] /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1/hog.conf matches project. Nothing to do WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1/sim.conf not found. Skipping properties check INFO: [Hog:Msg-0] Design List files and hog.conf match project. All ok! INFO: [Hog:Msg-0] Simulation list files match project. All ok! INFO: [Hog:Msg-0] Simulation config files match project. All ok! INFO: [Hog:Msg-0] All done. INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Git describe for 7d3a917 is: v1.6.0-hog7d3a917 INFO: [Hog:Msg-0] Found last SHA for efex_golden_processor.1: 7d3a917 INFO: [Hog:Msg-0] The commit in which project efex_golden_processor.1 was last modified is 7d3a917, that is 5 commits older than current commit D6802F0. INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml and replacing placeholders with xml version 01050006... INFO: [Hog:CopyXMLsFromListFile-0] 17 lines read from ./Top/golden/efex_golden_processor.1/list/xml.lst INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/L1CaloEfexProcessor.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_common_id_version.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_infrastructure.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_mgt_channel.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_mgt_quad.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_mgt_top.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_lib_version.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Algorithm/xml/efex_algorithm.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Algorithm/xml/efex_sorting.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Algorithm/xml/efex_merging.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Readout/xml/efex_readout.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Readout/xml/efex_raw_readout.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Readout/xml/efex_tob_readout.xml to /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] 13 file/s copied INFO: [Hog:CopyXMLsFromListFile-0] L1CaloEfexProcessor.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_L1CaloEfexProcessor.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_common_id_version.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_common_id_version.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_infrastructure.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_infrastructure.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_mgt_channel.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_mgt_channel.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_mgt_quad.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_mgt_quad.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_mgt_top.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_mgt_top.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_lib_version.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/address_table/ipbus_decode_efex_lib_version.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_algorithm.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Algorithm/address_table/ipbus_decode_efex_algorithm.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_sorting.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Algorithm/address_table/ipbus_decode_efex_sorting.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_merging.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Algorithm/address_table/ipbus_decode_efex_merging.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_readout.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Readout/address_table/ipbus_decode_efex_readout.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_raw_readout.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Readout/address_table/ipbus_decode_efex_raw_readout.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] efex_tob_readout.xml and /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Readout/address_table/ipbus_decode_efex_tob_readout.vhd match. INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:WriteGenerics-0] Passing parameters/generics to project golden/efex_golden_processor.1's top module... INFO: [Hog:WriteGenerics-0] Setting parameters/generics... INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/versions.txt... ------------------------- PRE SYNTHESIS ------------------------- 18/06/2023 at 03:23:50 Firmware date and time: 16062023, 00171421 Project flavour: 1 Global SHA: 7d3a917, VER: 1.6.0 Constraints SHA: F68521EE, VER: 1.3.3 IPbus XML SHA: 36D50F0, VER: 1.5.6 Top SHA: 9D86591, VER: 0.17.0 Hog SHA: 7DD4817, VER: 6.48.5 --- Libraries --- TOB_rdout_lib SHA: 36D50F0, VER: 1.5.6 algolib SHA: 966B35F, VER: 1.5.6 infrastructure_lib SHA: 7D3A917, VER: 1.6.0 ipbus_lib SHA: D6F4F62, VER: 1.0.0 ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with Hog2023.1-4 in .gitlab-ci.yml. INFO: [Hog:Msg-0] Sourcing user pre-synthesis file ./Top/golden/efex_golden_processor.1/pre-synthesis.tcl INFO: [Hog:Msg-0] Generics set for Golden FPGA INFO: [Hog:Msg-0] All done. Command: synth_design -top top_efex_processor -part xc7vx550tffg1927-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 15104 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2610.758 ; gain = 90.684 ; free physical = 5592 ; free virtual = 86839 --------------------------------------------------------------------------------- WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:65] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:50] INFO: [Synth 8-638] synthesizing module 'top_efex_processor' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:199] Parameter FLAVOUR bound to: 1 - type: integer Parameter GLOBAL_DATE bound to: 32'b00010110000001100010000000100011 Parameter GLOBAL_TIME bound to: 32'b00000000000101110001010000100001 Parameter GLOBAL_SHA bound to: 32'b00000111110100111010100100010111 Parameter GLOBAL_VER bound to: 32'b00000001000001100000000000000000 Parameter TOP_SHA bound to: 32'b00001001110110000110010110010001 Parameter TOP_VER bound to: 32'b00000000000100010000000000000000 Parameter CON_SHA bound to: 32'b11110110100001010010000111101110 Parameter CON_VER bound to: 32'b00000001000000110000000000000011 Parameter XML_SHA bound to: 32'b00000011011011010101000011110000 Parameter XML_VER bound to: 32'b00000001000001010000000000000110 Parameter HOG_SHA bound to: 32'b00000111110111010100100000010111 Parameter HOG_VER bound to: 32'b00000110001100000000000000000101 Parameter ALGOLIB_SHA bound to: 32'b00001001011001101011001101011111 Parameter ALGOLIB_VER bound to: 32'b00000001000001010000000000000110 Parameter INFRASTRUCTURE_LIB_SHA bound to: 32'b00000111110100111010100100010111 Parameter INFRASTRUCTURE_LIB_VER bound to: 32'b00000001000001100000000000000000 Parameter TOB_RDOUT_LIB_SHA bound to: 32'b00000011011011010101000011110000 Parameter TOB_RDOUT_LIB_VER bound to: 32'b00000001000001010000000000000110 Parameter IPBUS_LIB_SHA bound to: 32'b00001101011011110100111101100010 Parameter IPBUS_LIB_VER bound to: 32'b00000001000000000000000000000000 Parameter READOUT_ENABLED bound to: 0 - type: bool Parameter INPUT_RAM_ENABLED bound to: 0 - type: bool Parameter OUTPUT_RAMS_ENABLED bound to: 0 - type: bool Parameter SORT_IN_RAM_ENABLED bound to: 0 - type: bool Parameter SORT_OUT_RAM_ENABLED bound to: 0 - type: bool Parameter MGT_ENABLED bound to: 0 - type: bool Parameter MERGE_ENABLED bound to: 0 - type: bool Parameter DATA_PATH_ENABLED bound to: 0 - type: bool Parameter TAU_BDT_ENABLED bound to: 0 - type: bool Parameter ENCODING_MODE bound to: 2 - type: integer Parameter EFEX_POSITION bound to: 0 - type: integer Parameter n_channels bound to: 64 - type: integer INFO: [Synth 8-113] binding component instance 'reset_bufg' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:612] INFO: [Synth 8-638] synthesizing module 'proc_FPGAs' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/Process_FPGA_IPbus.vhd:74] Parameter IPBUSPORT bound to: 16'b1100001101010010 INFO: [Synth 8-638] synthesizing module 'UDP_node_if' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_node_if.vhd:35] INFO: [Synth 8-256] done synthesizing module 'UDP_node_if' (1#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_node_if.vhd:35] INFO: [Synth 8-638] synthesizing module 'interconnect' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'parity_checker' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-256] done synthesizing module 'parity_checker' (2#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-638] synthesizing module 'parity_gen' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] Parameter width bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'parity_gen' (3#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] INFO: [Synth 8-256] done synthesizing module 'interconnect' (4#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b1 Parameter DHCP_RARP bound to: 1'b0 Parameter N_OOB bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:89] WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b1 Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_ipam' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_ipam' (5#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (6#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (7#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (8#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (9#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (10#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (11#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] Parameter SECONDARYPORT bound to: 1'b1 Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (12#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (13#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (14#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (15#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (16#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (17#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (17#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (18#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:83] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (19#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (19#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] Parameter INTERNAL_ONLY bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (20#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (21#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (22#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (23#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (24#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (25#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (26#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor' (27#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (28#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] INFO: [Synth 8-256] done synthesizing module 'proc_FPGAs' (29#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/Process_FPGA_IPbus.vhd:74] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 8 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (30#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'common_id_registers' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (30#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (31#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:107] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:109] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (31#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:121] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:123] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:135] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:149] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:151] INFO: [Synth 8-256] done synthesizing module 'common_id_registers' (32#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'lib_registers' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:41] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 7 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (32#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:72] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:73] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:85] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:86] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:98] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:99] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:111] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:112] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:124] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:125] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:138] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:150] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:151] INFO: [Synth 8-256] done synthesizing module 'lib_registers' (33#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:41] INFO: [Synth 8-638] synthesizing module 'slaves' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:69] Parameter FPGA_FLAVOUR bound to: 1 - type: integer Parameter reg48 bound to: 16'b0100011100000001 Parameter reg49 bound to: 16'b0000000000000000 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 10 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (33#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (33#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized2' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 0 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'd' ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized2' (33#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:133] INFO: [Synth 8-638] synthesizing module 'ipbus_xadc_drp' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] Parameter NUMREG bound to: 19 - type: integer Parameter reg48 bound to: 16'b0100011100000001 Parameter reg49 bound to: 16'b0000000000000000 INFO: [Synth 8-638] synthesizing module 'xadc_eFEX' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] Parameter reg48 bound to: 16'b0100011100000001 Parameter reg49 bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'U_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:141] Parameter INIT_40 bound to: 16'b1001000000000000 Parameter INIT_41 bound to: 16'b0010111011110000 Parameter INIT_42 bound to: 16'b0000010000000000 Parameter INIT_43 bound to: 16'b0010111011110000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000001 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0100011100000001 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101100110011001 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1101110111011101 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101000100010001 Parameter INIT_56 bound to: 16'b1001000111101011 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:147] INFO: [Synth 8-256] done synthesizing module 'xadc_eFEX' (34#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] INFO: [Synth 8-256] done synthesizing module 'ipbus_xadc_drp' (35#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:166] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:181] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:197] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] Parameter BYTE_SPI bound to: 1 - type: bool Parameter ADDR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch' (36#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized3' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 4 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized3' (36#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] Parameter TIMER_WIDTH bound to: 20 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog' (37#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash' (38#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized0' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized0' (38#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'command_sync' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-256] done synthesizing module 'command_sync' (39#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-638] synthesizing module 'spi32_8_control' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter BYTE_SPI bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'spi32_8_control' (40#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] INFO: [Synth 8-638] synthesizing module 'clock_pulse' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'clock_pulse' (41#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32' (42#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_ram' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ram' (43#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] INFO: [Synth 8-256] done synthesizing module 'slaves' (44#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:69] INFO: [Synth 8-638] synthesizing module 'startup' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-113] binding component instance 'STARTUPE2_inst' to cell 'STARTUPE2' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:34] INFO: [Synth 8-256] done synthesizing module 'startup' (45#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] INFO: [Synth 8-638] synthesizing module 'self_configure' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/self_configure.vhd:36] INFO: [Synth 8-638] synthesizing module 'reconfig' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:37] Parameter DEVICE_ID bound to: 32'b00000011011001010001000010010011 Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-113] binding component instance 'ICAPE2_inst' to cell 'ICAPE2' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:70] INFO: [Synth 8-256] done synthesizing module 'reconfig' (46#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:37] INFO: [Synth 8-256] done synthesizing module 'self_configure' (47#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/self_configure.vhd:36] INFO: [Synth 8-638] synthesizing module 'clk_resources' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:67] INFO: [Synth 8-3491] module 'ClockWizard' declared at '/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/.Xil/Vivado-14428-efex-heavyduty-vm0.cern.ch/realtime/ClockWizard_stub.vhdl:5' bound to instance 'Inputclk40M' of component 'ClockWizard' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:117] INFO: [Synth 8-638] synthesizing module 'ClockWizard' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/.Xil/Vivado-14428-efex-heavyduty-vm0.cern.ch/realtime/ClockWizard_stub.vhdl:19] INFO: [Synth 8-3491] module 'clk_wiz_1' declared at '/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/.Xil/Vivado-14428-efex-heavyduty-vm0.cern.ch/realtime/clk_wiz_1_stub.vhdl:5' bound to instance 'clk40_gen' of component 'clk_wiz_1' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:133] INFO: [Synth 8-638] synthesizing module 'clk_wiz_1' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/.Xil/Vivado-14428-efex-heavyduty-vm0.cern.ch/realtime/clk_wiz_1_stub.vhdl:15] INFO: [Synth 8-3491] module 'clocks_7s_extphy' declared at '/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:23' bound to instance 'clocks' of component 'clocks_7s_extphy' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:148] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFGDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:51] INFO: [Synth 8-113] binding component instance 'bufg200' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:57] INFO: [Synth 8-113] binding component instance 'bufg125' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:62] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:69] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 1.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_DIVIDE bound to: 5 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm' to cell 'MMCME2_BASE' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:76] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:58] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (48#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (49#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] INFO: [Synth 8-256] done synthesizing module 'clk_resources' (50#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:67] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:906] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:906] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:906] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:906] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:995] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:1002] WARNING: [Synth 8-6026] Ignoring keep related attribute (keep/mark_debug/dont_touch) applied on memory [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:348] INFO: [Synth 8-256] done synthesizing module 'top_efex_processor' (51#1) [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:199] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2721.699 ; gain = 201.625 ; free physical = 6341 ; free virtual = 87590 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2733.570 ; gain = 213.496 ; free physical = 6363 ; free virtual = 87612 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2733.570 ; gain = 213.496 ; free physical = 6363 ; free virtual = 87612 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2741.508 ; gain = 0.000 ; free physical = 6346 ; free virtual = 87595 INFO: [Netlist 29-17] Analyzing 75 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1/clk_wiz_1_in_context.xdc] for cell 'clock_resources/clk40_gen' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1/clk_wiz_1_in_context.xdc] for cell 'clock_resources/clk40_gen' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc] for cell 'clock_resources/Inputclk40M' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc] for cell 'clock_resources/Inputclk40M' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.293 ; gain = 0.000 ; free physical = 6249 ; free virtual = 87498 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3 instances were transformed. IBUFGDS => IBUFDS: 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2841.293 ; gain = 0.000 ; free physical = 6249 ; free virtual = 87497 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6330 ; free virtual = 87579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6330 ; free virtual = 87579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for ttc_clk_n. (constraint file /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc, line 6). Applied set_property CLOCK_BUFFER_TYPE = NONE for ttc_clk_n. (constraint file /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc, line 7). Applied set_property IO_BUFFER_TYPE = NONE for ttc_clk_p. (constraint file /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc, line 8). Applied set_property CLOCK_BUFFER_TYPE = NONE for ttc_clk_p. (constraint file /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc, line 9). Applied set_property KEEP_HIERARCHY = SOFT for clock_resources/clk40_gen. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for clock_resources/Inputclk40M. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6327 ; free virtual = 87576 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'xadc_eFEX' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'command_sync' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control' INFO: [Synth 8-802] inferred FSM for state register 'NEXT_STATE_reg' in module 'reconfig' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init_read | 00000000000000000000000000000000000000001 | 000000 read_waitdrdy | 00000000000000000000000000000000000000010 | 000001 write_waitdrdy | 00000000000000000000000000000000000000100 | 000010 read_reg00 | 00000000000000000000000000000000000001000 | 000011 reg00_waitdrdy | 00000000000000000000000000000000000010000 | 000100 read_reg01 | 00000000000000000000000000000000000100000 | 000101 reg01_waitdrdy | 00000000000000000000000000000000001000000 | 000110 read_reg02 | 00000000000000000000000000000000010000000 | 000111 reg02_waitdrdy | 00000000000000000000000000000000100000000 | 001000 read_reg03 | 00000000000000000000000000000001000000000 | 001001 reg03_waitdrdy | 00000000000000000000000000000010000000000 | 001010 read_reg06 | 00000000000000000000000000000100000000000 | 001011 reg06_waitdrdy | 00000000000000000000000000001000000000000 | 001100 read_reg10 | 00000000000000000000000000010000000000000 | 001101 reg10_waitdrdy | 00000000000000000000000000100000000000000 | 001110 read_reg11 | 00000000000000000000000001000000000000000 | 001111 reg11_waitdrdy | 00000000000000000000000010000000000000000 | 010000 read_reg12 | 00000000000000000000000100000000000000000 | 010001 reg12_waitdrdy | 00000000000000000000001000000000000000000 | 010010 read_reg13 | 00000000000000000000010000000000000000000 | 010011 reg13_waitdrdy | 00000000000000000000100000000000000000000 | 010100 read_reg14 | 00000000000000000001000000000000000000000 | 010101 reg14_waitdrdy | 00000000000000000010000000000000000000000 | 010110 read_reg15 | 00000000000000000100000000000000000000000 | 010111 reg15_waitdrdy | 00000000000000001000000000000000000000000 | 011000 read_reg20 | 00000000000000010000000000000000000000000 | 011001 reg20_waitdrdy | 00000000000000100000000000000000000000000 | 011010 read_reg21 | 00000000000001000000000000000000000000000 | 011011 reg21_waitdrdy | 00000000000010000000000000000000000000000 | 011100 read_reg22 | 00000000000100000000000000000000000000000 | 011101 reg22_waitdrdy | 00000000001000000000000000000000000000000 | 011110 read_reg23 | 00000000010000000000000000000000000000000 | 011111 reg23_waitdrdy | 00000000100000000000000000000000000000000 | 100000 read_reg24 | 00000001000000000000000000000000000000000 | 100001 reg24_waitdrdy | 00000010000000000000000000000000000000000 | 100010 read_reg25 | 00000100000000000000000000000000000000000 | 100011 reg25_waitdrdy | 00001000000000000000000000000000000000000 | 100100 read_reg26 | 00010000000000000000000000000000000000000 | 100101 reg26_waitdrdy | 00100000000000000000000000000000000000000 | 100110 read_reg27 | 01000000000000000000000000000000000000000 | 100111 reg27_waitdrdy | 10000000000000000000000000000000000000000 | 101000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'xadc_eFEX' INFO: [Synth 8-3971] The signal "ipbus_dpram_flash:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized0:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0001 | 00 request | 0010 | 01 done | 0100 | 10 iSTATE | 1000 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'one-hot' in module 'command_sync' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 data_00 | 0001 | 0001 data_01 | 0010 | 0010 data_02 | 0011 | 0011 data_03 | 0100 | 0100 data_04 | 0101 | 0101 data_05 | 0110 | 0110 data_06 | 0111 | 0111 data_07 | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'NEXT_STATE_reg' using encoding 'sequential' in module 'reconfig' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6342 ; free virtual = 87593 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 16 Bit Adders := 2 2 Input 13 Bit Adders := 2 2 Input 9 Bit Adders := 4 2 Input 8 Bit Adders := 5 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 5 2 Input 2 Bit Adders := 2 +---XORs : 9 Input 1 Bit XORs := 1 2 Input 1 Bit XORs := 11 +---Registers : 128 Bit Registers := 7 120 Bit Registers := 1 80 Bit Registers := 1 48 Bit Registers := 3 45 Bit Registers := 2 42 Bit Registers := 1 38 Bit Registers := 1 34 Bit Registers := 1 33 Bit Registers := 2 32 Bit Registers := 34 31 Bit Registers := 1 24 Bit Registers := 1 22 Bit Registers := 1 20 Bit Registers := 1 16 Bit Registers := 57 13 Bit Registers := 18 12 Bit Registers := 1 10 Bit Registers := 4 9 Bit Registers := 10 8 Bit Registers := 23 7 Bit Registers := 5 6 Bit Registers := 2 5 Bit Registers := 3 4 Bit Registers := 14 3 Bit Registers := 9 2 Bit Registers := 14 1 Bit Registers := 207 +---RAMs : 256K Bit (8192 X 32 bit) RAMs := 1 64K Bit (8192 X 8 bit) RAMs := 4 32K Bit (4096 X 8 bit) RAMs := 1 32K Bit (1024 X 32 bit) RAMs := 1 4K Bit (128 X 32 bit) RAMs := 2 +---Muxes : 2 Input 128 Bit Muxes := 8 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 80 Bit Muxes := 11 2 Input 48 Bit Muxes := 2 5 Input 48 Bit Muxes := 1 41 Input 41 Bit Muxes := 1 2 Input 41 Bit Muxes := 21 3 Input 38 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 33 Bit Muxes := 2 2 Input 32 Bit Muxes := 42 4 Input 32 Bit Muxes := 7 6 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 2 9 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 2 2 Input 24 Bit Muxes := 1 3 Input 22 Bit Muxes := 1 2 Input 16 Bit Muxes := 28 4 Input 16 Bit Muxes := 2 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 18 Input 16 Bit Muxes := 4 2 Input 13 Bit Muxes := 23 8 Input 13 Bit Muxes := 1 4 Input 13 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 4 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 12 2 Input 8 Bit Muxes := 39 13 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 4 6 Input 8 Bit Muxes := 2 4 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 1 3 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 12 7 Input 7 Bit Muxes := 1 41 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 9 4 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 6 Input 6 Bit Muxes := 2 2 Input 5 Bit Muxes := 4 5 Input 5 Bit Muxes := 1 4 Input 4 Bit Muxes := 2 2 Input 4 Bit Muxes := 13 5 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 2 8 Input 3 Bit Muxes := 4 4 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 5 5 Input 3 Bit Muxes := 3 6 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 11 17 Input 2 Bit Muxes := 2 41 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 253 9 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 15 11 Input 1 Bit Muxes := 2 12 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 9 8 Input 1 Bit Muxes := 9 6 Input 1 Bit Muxes := 8 5 Input 1 Bit Muxes := 3 7 Input 1 Bit Muxes := 8 16 Input 1 Bit Muxes := 9 17 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 8 41 Input 1 Bit Muxes := 23 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3971] The signal "slaves/spi_flash/spi_dpram_in/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6314 ; free virtual = 87575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +------------------------------+-----------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------------------------+-----------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |U_1/\U_2/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slaves/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slaves/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |slaves | RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | +------------------------------+-----------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:53 ; elapsed = 00:00:59 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6204 ; free virtual = 87465 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:54 ; elapsed = 00:01:00 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6200 ; free virtual = 87461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +------------------------------+-----------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------------------------+-----------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |U_1/\U_2/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slaves/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slaves/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |slaves | RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | +------------------------------+-----------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance slaves/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance slaves/RAM/reg_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:01:03 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6194 ; free virtual = 87455 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_eg_TOB_inferred:in0[0] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin sorted_tau_TOB_inferred:in0[0] to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:00 ; elapsed = 00:01:07 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6180 ; free virtual = 87441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:00 ; elapsed = 00:01:07 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6180 ; free virtual = 87441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:01 ; elapsed = 00:01:07 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6137 ; free virtual = 87398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:01 ; elapsed = 00:01:07 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6132 ; free virtual = 87393 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:01 ; elapsed = 00:01:08 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6174 ; free virtual = 87435 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:01 ; elapsed = 00:01:08 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6174 ; free virtual = 87435 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-------------------+------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-------------------+------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top_efex_processor | U_1/U_2/udp_if/IPADDR/rarp_reply._MAC_IP_addr_rx_rarp.pkt_mask_reg[41] | 32 | 1 | YES | NO | YES | 0 | 1 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |top_efex_processor | U_1/U_2/udp_if/resend/resend_pkt_id_block.pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[33] | 6 | 2 | YES | NO | YES | 2 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/rarp_reply._rarp.pkt_mask_reg[21] | 6 | 3 | YES | NO | YES | 3 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[18] | 5 | 1 | YES | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[11] | 8 | 1 | YES | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[37] | 23 | 1 | YES | NO | YES | 0 | 1 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[13] | 12 | 1 | YES | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[71] | 5 | 4 | YES | NO | YES | 4 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[59] | 4 | 1 | YES | NO | YES | 1 | 0 | +-------------------+------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------+----------+ | |BlackBox name |Instances | +------+--------------+----------+ |1 |ClockWizard | 1| |2 |clk_wiz_1 | 1| +------+--------------+----------+ Report Cell Usage: +------+-----------------+------+ | |Cell |Count | +------+-----------------+------+ |1 |ClockWizard_bbox | 1| |2 |clk_wiz_1_bbox | 1| |3 |BUFG | 7| |4 |CARRY4 | 115| |5 |ICAPE2 | 1| |6 |LUT1 | 128| |7 |LUT2 | 268| |8 |LUT3 | 445| |9 |LUT4 | 506| |10 |LUT5 | 577| |11 |LUT6 | 1264| |12 |MMCME2_BASE | 1| |13 |MUXF7 | 6| |14 |MUXF8 | 3| |15 |RAMB36E1 | 20| |20 |SRL16 | 1| |21 |SRL16E | 13| |22 |SRLC32E | 6| |23 |STARTUPE2 | 1| |24 |XADC | 1| |25 |FDCE | 42| |26 |FDPE | 1| |27 |FDRE | 3418| |28 |FDSE | 183| |29 |IBUF | 23| |30 |IBUFDS | 4| |31 |IBUFGDS | 1| |32 |OBUF | 14| +------+-----------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:01 ; elapsed = 00:01:08 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6174 ; free virtual = 87435 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 64 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:55 ; elapsed = 00:01:01 . Memory (MB): peak = 2841.293 ; gain = 213.496 ; free physical = 6224 ; free virtual = 87484 Synthesis Optimization Complete : Time (s): cpu = 00:01:01 ; elapsed = 00:01:08 . Memory (MB): peak = 2841.293 ; gain = 321.219 ; free physical = 6224 ; free virtual = 87484 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2841.293 ; gain = 0.000 ; free physical = 6234 ; free virtual = 87495 INFO: [Netlist 29-17] Analyzing 153 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[0].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[0].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[1].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[1].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[2].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[2].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[3].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[3].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2995.078 ; gain = 0.000 ; free physical = 6187 ; free virtual = 87448 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3 instances were transformed. IBUFGDS => IBUFDS: 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance SRL16 => SRL16E: 1 instance INFO: [Common 17-83] Releasing license: Synthesis 327 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:22 ; elapsed = 00:01:25 . Memory (MB): peak = 2995.078 ; gain = 475.215 ; free physical = 6334 ; free virtual = 87595 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/synth_1/top_efex_processor.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_synth.rpt -pb top_efex_processor_utilization_synth.pb source /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-synthesis.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_processor.1... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.0-hog7d3a917 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/3/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_processor.1-v1.6.0-hog7d3a917... INFO: [Hog:Msg-0] Copying synthesised IP ClockWizard to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: ClockWizard.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] Copying synthesised IP clk_wiz_1 to /eos/user/e/efex/www/firmware/eFEX/ip... INFO: [Hog:HandleIP-0] IP remote directory path, on EOS, is set to: /eos/user/e/efex/www/firmware/eFEX/ip INFO: [Hog:HandleIP-0] Preparing to push IP: clk_wiz_1.xci... INFO: [Hog:HandleIP-0] IP already in the EOS repository, will not copy... INFO: [Hog:Msg-0] All done. INFO: [Common 17-206] Exiting Vivado at Sun Jun 18 03:25:34 2023...