Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Wed Jun 21 14:50:04 2023 | Host : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_control-v1.6.1-hog65796e1/reports/hierarchical_utilization.txt | Design : top_efex_control | Device : 7vx330tffg1157-2 | Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-------------+-------------+-----------+-----------+-------------+-----------+----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-------------+-------------+-----------+-----------+-------------+-----------+----------+------------+ | top_efex_control | (top) | 5002(2.45%) | 4830(2.37%) | 96(0.14%) | 76(0.11%) | 5899(1.45%) | 22(2.93%) | 1(0.07%) | 0(0.00%) | | (top_efex_control) | (top) | 104(0.05%) | 80(0.04%) | 0(0.00%) | 24(0.03%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | top_udp_config_FPGA | 3341(1.64%) | 3222(1.58%) | 80(0.11%) | 39(0.06%) | 3587(0.88%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | U_0 | interface_proc_fpga | 95(0.05%) | 75(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_22 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_23 | 87(0.04%) | 67(0.03%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interface_proc_fpga_14 | 99(0.05%) | 79(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_20 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_21 | 94(0.05%) | 74(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | interface_proc_fpga_15 | 103(0.05%) | 83(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_18 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_19 | 98(0.05%) | 78(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_3 | interface_proc_fpga_16 | 94(0.05%) | 74(0.04%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo | 87(0.04%) | 67(0.03%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_4 | mac_arbiter | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_5 | ipbus_ctrl | 2817(1.38%) | 2778(1.36%) | 0(0.00%) | 39(0.06%) | 3230(0.79%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | (U_5) | ipbus_ctrl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 636(0.31%) | 636(0.31%) | 0(0.00%) | 0(0.00%) | 313(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cfg__0 | transactor_cfg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 153(0.08%) | 153(0.08%) | 0(0.00%) | 0(0.00%) | 135(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 491(0.24%) | 491(0.24%) | 0(0.00%) | 0(0.00%) | 176(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 2179(1.07%) | 2140(1.05%) | 0(0.00%) | 39(0.06%) | 2917(0.71%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 240(0.12%) | 240(0.12%) | 0(0.00%) | 0(0.00%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 185(0.09%) | 185(0.09%) | 0(0.00%) | 0(0.00%) | 196(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ARP | udp_build_arp | 95(0.05%) | 95(0.05%) | 0(0.00%) | 0(0.00%) | 135(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.IPAM_block | udp_ipam_block | 272(0.13%) | 272(0.13%) | 0(0.00%) | 0(0.00%) | 168(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ping | udp_build_ping | 113(0.06%) | 113(0.06%) | 0(0.00%) | 0(0.00%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 257(0.13%) | 220(0.11%) | 0(0.00%) | 37(0.05%) | 517(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 139(0.07%) | 139(0.07%) | 0(0.00%) | 0(0.00%) | 172(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 232(0.11%) | 232(0.11%) | 0(0.00%) | 0(0.00%) | 433(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_17 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 216(0.11%) | 216(0.11%) | 0(0.00%) | 0(0.00%) | 222(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 102(0.05%) | 102(0.05%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.06%) | 130(0.06%) | 0(0.00%) | 0(0.00%) | 264(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_6 | udp_hub_rarp | 85(0.04%) | 85(0.04%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_7 | unique_address | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_12 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_13 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | interconnect_0 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_2) | interconnect_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_10 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_11 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_3 | interconnect_1 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_3) | interconnect_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_8 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_9 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_4 | interconnect_2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_4) | interconnect_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 48(0.02%) | 47(0.02%) | 0(0.00%) | 1(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 33(0.02%) | 32(0.02%) | 0(0.00%) | 1(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eth | eth_7s_gmii | 583(0.29%) | 555(0.27%) | 16(0.02%) | 12(0.02%) | 793(0.19%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (eth) | eth_7s_gmii | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | emac0 | temac_gbe_v9_0 | 530(0.26%) | 505(0.25%) | 16(0.02%) | 9(0.01%) | 679(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | temac_gbe_v9_0_temac_gbe_v9_0_block | 530(0.26%) | 505(0.25%) | 16(0.02%) | 9(0.01%) | 679(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_interface | temac_gbe_v9_0_temac_gbe_v9_0_gmii_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | temac_gbe_v9_0_core | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17 | 530(0.26%) | 505(0.25%) | 16(0.02%) | 9(0.01%) | 679(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (temac_gbe_v9_0_core) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_filter_top | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_addr_filter_wrap | 43(0.02%) | 26(0.01%) | 16(0.02%) | 1(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | address_filter_inst | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_addr_filter | 43(0.02%) | 26(0.01%) | 16(0.02%) | 1(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (address_filter_inst) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_addr_filter | 42(0.02%) | 25(0.01%) | 16(0.02%) | 1(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resync_promiscuous_mode | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | flow | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_control | 123(0.06%) | 123(0.06%) | 0(0.00%) | 0(0.00%) | 156(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (flow) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_control | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pfc_tx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_pfc_tx_cntl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx_cntl | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_pause | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx_sync_req | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_enable | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_enable | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_cntl | 53(0.03%) | 53(0.03%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_pause | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_pause | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_pause) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_pause | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_good_rx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_block_6 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_rx_gen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_gmii_mii_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_tx_gen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_gmii_mii_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_avb_tx_axi_intf.tx_axi_shim | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx_axi_intf | 80(0.04%) | 80(0.04%) | 0(0.00%) | 0(0.00%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_axi_shim | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx_axi_intf | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxgen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx | 155(0.08%) | 147(0.07%) | 0(0.00%) | 8(0.01%) | 181(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rxgen) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_rx | 26(0.01%) | 18(0.01%) | 0(0.00%) | 8(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FCS_CHECK | temac_gbe_v9_0_CRC32_8 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_CHECKER | temac_gbe_v9_0_PARAM_CHECK | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_DECODER | temac_gbe_v9_0_DECODE_FRAME | 42(0.02%) | 42(0.02%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX_SM | temac_gbe_v9_0_STATE_MACHINES | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_axi_rx_rstn_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_rx_rst_mgmt_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_tx_rst_mgmt_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_axi_rstn_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_sync_reset__parameterized0_4 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txgen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txgen) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_17_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TX_SM1 | temac_gbe_v9_0_TX_STATE_MACH | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 126(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TX_SM1) | temac_gbe_v9_0_TX_STATE_MACH | 74(0.04%) | 74(0.04%) | 0(0.00%) | 0(0.00%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CRCGEN | temac_gbe_v9_0_CRC32_8__1 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo | mac_fifo_axi4 | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | U0 | mac_fifo_axi4_fifo_generator_v13_2_5 | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | mac_fifo_axi4_fifo_generator_v13_2_5_synth | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mac_fifo_axi4_fifo_generator_top | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | grf.rf | mac_fifo_axi4_fifo_generator_ramfifo | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mac_fifo_axi4_clk_x_pntrs | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mac_fifo_axi4_clk_x_pntrs | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mac_fifo_axi4_xpm_cdc_gray | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mac_fifo_axi4_xpm_cdc_gray__2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mac_fifo_axi4_rd_logic | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mac_fifo_axi4_rd_fwft | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mac_fifo_axi4_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mac_fifo_axi4_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mac_fifo_axi4_wr_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mac_fifo_axi4_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mac_fifo_axi4_wr_bin_cntr | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mac_fifo_axi4_memory | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 18(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mac_fifo_axi4_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mac_fifo_axi4_blk_mem_gen_v8_4_4 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | mac_fifo_axi4_blk_mem_gen_v8_4_4_synth | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mac_fifo_axi4_blk_mem_gen_top | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | valid.cstr | mac_fifo_axi4_blk_mem_gen_generic_cstr | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | mac_fifo_axi4_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (ramloop[0].ram.r) | mac_fifo_axi4_blk_mem_gen_prim_width | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mac_fifo_axi4_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | rstblk | mac_fifo_axi4_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mac_fifo_axi4_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mac_fifo_axi4_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mac_fifo_axi4_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mac_fifo_axi4_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mac_fifo_axi4_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | infrastructure_control | infrastructure_slaves_cntrl | 824(0.40%) | 824(0.40%) | 0(0.00%) | 0(0.00%) | 1258(0.31%) | 5(0.67%) | 0(0.00%) | 0(0.00%) | | (infrastructure_control) | infrastructure_slaves_cntrl | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | i2c_0 | ipbus_i2c_master_arb | 207(0.10%) | 207(0.10%) | 0(0.00%) | 0(0.00%) | 221(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 86(0.04%) | 86(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | i2c_arp | ipbus_i2c_master | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | i2c | i2c_master_top | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (i2c) | i2c_master_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bit_controller | i2c_master_bit_ctrl | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | byte_controller | i2c_master_byte_ctrl | 34(0.02%) | 34(0.02%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | registers | i2c_master_registers | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig | ipbus_ctrlreg_v__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32__parameterized0 | 273(0.13%) | 273(0.13%) | 0(0.00%) | 0(0.00%) | 304(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog_3 | 131(0.06%) | 131(0.06%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized2 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control__parameterized0 | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_pll | ipbus_spi32 | 262(0.13%) | 262(0.13%) | 0(0.00%) | 0(0.00%) | 299(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (spi_pll) | ipbus_spi32 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog_4 | 131(0.06%) | 131(0.06%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3_6 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync_7 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 54(0.03%) | 54(0.03%) | 0(0.00%) | 0(0.00%) | 367(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 54(0.03%) | 54(0.03%) | 0(0.00%) | 0(0.00%) | 366(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pll_sel | pll_selector | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_pll | nreset_pll | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reset_pll) | nreset_pll | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen | nreset_gen | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_clk | clk_ttc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_ttc_clk_ttc_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +---------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-------------+-------------+-----------+-----------+-------------+-----------+----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining