*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2562.672 ; gain = 0.000 ; free physical = 61905 ; free virtual = 71432 INFO: [Netlist 29-17] Analyzing 6745 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 3521.922 ; gain = 669.066 ; free physical = 61091 ; free virtual = 70569 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3545.926 ; gain = 0.000 ; free physical = 61153 ; free virtual = 70627 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:10 ; elapsed = 00:01:08 . Memory (MB): peak = 3545.926 ; gain = 1024.855 ; free physical = 61163 ; free virtual = 70637 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3553.930 ; gain = 8.000 ; free physical = 61166 ; free virtual = 70622 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 20bd7f85d Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3553.930 ; gain = 0.000 ; free physical = 61000 ; free virtual = 70447 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3763.680 ; gain = 0.000 ; free physical = 60681 ; free virtual = 69895 Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3763.680 ; gain = 0.000 ; free physical = 60679 ; free virtual = 69893 Phase 1 Generate And Synthesize Debug Cores | Checksum: 14a328236 Time (s): cpu = 00:01:55 ; elapsed = 00:02:33 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60687 ; free virtual = 69901 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 167b9ed34 Time (s): cpu = 00:02:02 ; elapsed = 00:02:40 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60786 ; free virtual = 69985 INFO: [Opt 31-389] Phase Retarget created 117 cells and removed 356 cells INFO: [Opt 31-1021] In phase Retarget, 438 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 1be477a77 Time (s): cpu = 00:02:03 ; elapsed = 00:02:41 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60784 ; free virtual = 69981 INFO: [Opt 31-389] Phase Constant propagation created 174 cells and removed 624 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 2306748ed Time (s): cpu = 00:02:06 ; elapsed = 00:02:44 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60717 ; free virtual = 69914 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 746 cells INFO: [Opt 31-1021] In phase Sweep, 4690 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 17d356b6f Time (s): cpu = 00:02:08 ; elapsed = 00:02:46 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60774 ; free virtual = 69973 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1a2f05b4c Time (s): cpu = 00:02:08 ; elapsed = 00:02:46 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60779 ; free virtual = 69972 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 176d682c8 Time (s): cpu = 00:02:09 ; elapsed = 00:02:46 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60779 ; free virtual = 69972 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 117 | 356 | 438 | | Constant propagation | 174 | 624 | 141 | | Sweep | 6 | 746 | 4690 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3763.680 ; gain = 0.000 ; free physical = 60769 ; free virtual = 69959 Ending Logic Optimization Task | Checksum: bb55711c Time (s): cpu = 00:02:12 ; elapsed = 00:02:50 . Memory (MB): peak = 3763.680 ; gain = 43.785 ; free physical = 60768 ; free virtual = 69959 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 11073cc04 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4792.742 ; gain = 0.000 ; free physical = 59570 ; free virtual = 69214 Ending Power Optimization Task | Checksum: 11073cc04 Time (s): cpu = 00:01:07 ; elapsed = 00:01:02 . Memory (MB): peak = 4792.742 ; gain = 1029.062 ; free physical = 59672 ; free virtual = 69316 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1581f4563 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 4792.742 ; gain = 0.000 ; free physical = 59157 ; free virtual = 69053 Ending Final Cleanup Task | Checksum: 1581f4563 Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 4792.742 ; gain = 0.000 ; free physical = 59153 ; free virtual = 69050 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4792.742 ; gain = 0.000 ; free physical = 59153 ; free virtual = 69050 Ending Netlist Obfuscation Task | Checksum: 1581f4563 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4792.742 ; gain = 0.000 ; free physical = 59153 ; free virtual = 69050 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:03:55 ; elapsed = 00:04:29 . Memory (MB): peak = 4792.742 ; gain = 1246.816 ; free physical = 59153 ; free virtual = 69050 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4792.742 ; gain = 0.000 ; free physical = 58261 ; free virtual = 68385 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 4792.746 ; gain = 0.004 ; free physical = 58221 ; free virtual = 68320 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 57612 ; free virtual = 67890 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 57352 ; free virtual = 67630 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a8f583e9 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 57346 ; free virtual = 67623 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 57334 ; free virtual = 67612 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6555a7f0 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 57256 ; free virtual = 67710 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: dcbabea2 Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56870 ; free virtual = 67318 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: dcbabea2 Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56866 ; free virtual = 67315 Phase 1 Placer Initialization | Checksum: dcbabea2 Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56851 ; free virtual = 67299 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1433f9a67 Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56745 ; free virtual = 67181 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: ac3e6bc8 Time (s): cpu = 00:01:05 ; elapsed = 00:01:06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56752 ; free virtual = 67202 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 69 LUTNM shape to break, 2416 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 58, two critical 11, total 69, new lutff created 8 INFO: [Physopt 32-775] End 1 Pass. Optimized 983 nets or cells. Created 69 new cells, deleted 914 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 9 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 44 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 53 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 53 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.34 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56856 ; free virtual = 67232 INFO: [Physopt 32-76] Pass 1. Identified 12 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 7 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 11 nets. Created 58 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 58 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56796 ; free virtual = 67173 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-46] Identified 78 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[0]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-232] Optimized 2 nets. Created 2 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56850 ; free virtual = 67227 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 24 candidate cells for BRAM register optimization INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 12 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56860 ; free virtual = 67230 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56861 ; free virtual = 67233 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 69 | 914 | 983 | 0 | 1 | 00:00:02 | | Very High Fanout | 53 | 0 | 2 | 0 | 1 | 00:00:03 | | Fanout | 58 | 0 | 11 | 0 | 1 | 00:00:01 | | Critical Cell | 2 | 0 | 2 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 12 | 0 | 12 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 194 | 914 | 1010 | 0 | 10 | 00:00:07 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 18b9aeed6 Time (s): cpu = 00:02:58 ; elapsed = 00:03:01 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56859 ; free virtual = 67228 Phase 2.3 Global Placement Core | Checksum: 116b4d293 Time (s): cpu = 00:03:03 ; elapsed = 00:03:06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56866 ; free virtual = 67233 Phase 2 Global Placement | Checksum: 116b4d293 Time (s): cpu = 00:03:03 ; elapsed = 00:03:06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56890 ; free virtual = 67257 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1aaf32fe0 Time (s): cpu = 00:03:12 ; elapsed = 00:03:15 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56887 ; free virtual = 67251 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b8ceccb2 Time (s): cpu = 00:03:30 ; elapsed = 00:03:34 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56941 ; free virtual = 67213 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 26a076a3f Time (s): cpu = 00:03:32 ; elapsed = 00:03:36 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56922 ; free virtual = 67189 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 241d98b5c Time (s): cpu = 00:03:33 ; elapsed = 00:03:36 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56934 ; free virtual = 67201 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1a44873c1 Time (s): cpu = 00:03:55 ; elapsed = 00:03:59 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56972 ; free virtual = 67150 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: fb2442d4 Time (s): cpu = 00:04:29 ; elapsed = 00:04:34 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56599 ; free virtual = 66923 Phase 3.6 Small Shape Detail Placement | Checksum: fb2442d4 Time (s): cpu = 00:04:31 ; elapsed = 00:04:35 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56648 ; free virtual = 66977 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1284ffcfc Time (s): cpu = 00:04:35 ; elapsed = 00:04:39 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56656 ; free virtual = 66974 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 22f302e9e Time (s): cpu = 00:04:36 ; elapsed = 00:04:41 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56683 ; free virtual = 67010 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1706765a2 Time (s): cpu = 00:05:20 ; elapsed = 00:05:25 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56646 ; free virtual = 66935 Phase 3 Detail Placement | Checksum: 1706765a2 Time (s): cpu = 00:05:21 ; elapsed = 00:05:26 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56649 ; free virtual = 66934 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 26b0d5b12 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.551 | TNS=-155.672 | Phase 1 Physical Synthesis Initialization | Checksum: 2720721b0 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56239 ; free virtual = 66811 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/reg_reg[1][5]_13[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 203b0b1f8 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56144 ; free virtual = 66805 Phase 4.1.1.1 BUFG Insertion | Checksum: 26b0d5b12 Time (s): cpu = 00:06:07 ; elapsed = 00:06:12 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56148 ; free virtual = 66809 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.063. For the most accurate timing information please run report_timing. Time (s): cpu = 00:08:32 ; elapsed = 00:08:38 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56787 ; free virtual = 67408 Phase 4.1 Post Commit Optimization | Checksum: 166fc8aa4 Time (s): cpu = 00:08:33 ; elapsed = 00:08:38 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56792 ; free virtual = 67412 Post Placement Optimization Initialization | Checksum: 1aacbcf77 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.301 | TNS=-49.590 | Phase 1 Physical Synthesis Initialization | Checksum: 17a1a9d3c Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58413 ; free virtual = 69640 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/reg_reg[1][5]_13[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 23b5baad1 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58410 ; free virtual = 69638 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.148. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 17a785dd9 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-2.055 | Phase 1 Physical Synthesis Initialization | Checksum: 1d9ccca81 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 62702 ; free virtual = 72667 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/reg_reg[1][5]_13[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1ab560bee Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 62658 ; free virtual = 72622 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.148. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18b655a7b Time (s): cpu = 00:15:50 ; elapsed = 00:15:56 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65508 ; free virtual = 73811 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 2x2| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 18b655a7b Time (s): cpu = 00:15:51 ; elapsed = 00:15:57 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65483 ; free virtual = 73786 Phase 4.3 Placer Reporting | Checksum: 18b655a7b Time (s): cpu = 00:15:52 ; elapsed = 00:15:58 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65461 ; free virtual = 73763 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65460 ; free virtual = 73762 Time (s): cpu = 00:15:52 ; elapsed = 00:15:58 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65460 ; free virtual = 73762 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14574fb46 Time (s): cpu = 00:15:53 ; elapsed = 00:15:59 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65445 ; free virtual = 73747 Ending Placer Task | Checksum: cd92d245 Time (s): cpu = 00:15:53 ; elapsed = 00:15:59 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65408 ; free virtual = 73710 INFO: [Common 17-83] Releasing license: Implementation 210 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:15:59 ; elapsed = 00:16:06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 65472 ; free virtual = 73775 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 62486 ; free virtual = 70957 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 62378 ; free virtual = 70718 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.46 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 62259 ; free virtual = 70598 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.63 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 62169 ; free virtual = 70511 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed_1.rpt -pb top_efex_control_utilization_placed_1.pb Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 60767 ; free virtual = 69109 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-2.055 | Phase 1 Physical Synthesis Initialization | Checksum: bd6cf74c Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58973 ; free virtual = 67314 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-2.055 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: bd6cf74c Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58948 ; free virtual = 67290 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-2.055 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/in_ready_sig_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__1 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/in_ready_sig_i_1__8_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/in_ready_sig_i_1__8_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.106 | TNS=-2.027 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_B/in_ready_sig_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/register_process.dout_valid_reg. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/in_ready_sig_i_2__4 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/register_process.dout_valid_reg. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/tob_packet_ready_B_reg_bus[0]. Did not re-place instance GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/register_process.dout_valid_i_2 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/register_process.dout_valid_reg. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/in_ready_sig_i_2__4_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_sources[2].tob_processer/tob_packet_ready_B_reg_bus[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.921 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[35]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[35] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[35]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.898 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[36]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[36] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[36]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.875 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[3]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[3] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.033 | TNS=-1.852 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[50]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[50] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[50]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.829 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[11]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[11] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[11]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.798 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[13]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[13] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[13]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.766 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[14]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[14] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[14]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.735 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[34]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[34] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[34]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.030 | TNS=-1.703 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[21]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[21] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.673 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[15]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[15] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[15]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.643 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[17]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[17] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[17]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.614 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[19]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[19] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[19]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.585 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[64]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[64] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[64]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.555 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[42]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[42] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[42]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.527 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[43]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[43] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[43]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.498 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[51]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[51] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[51]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.470 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[52]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[52] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[52]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.027 | TNS=-1.442 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[29]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[29] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[29]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.027 | TNS=-1.414 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[31]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[31] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[31]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.027 | TNS=-1.387 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[35]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[35] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[35]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.027 | TNS=-1.359 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.027 | TNS=-1.359 | Phase 3 Critical Path Optimization | Checksum: bd6cf74c Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58900 ; free virtual = 67242 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.027 | TNS=-1.359 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[53]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[53] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[53]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.333 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[36]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[36] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[36]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.308 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[38]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[38] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[38]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.283 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[3]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[3] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.258 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[40]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[40] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[40]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.245 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[4]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[4] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.232 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[61]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[61] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[61]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.219 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[62]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[62] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[62]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.026 | TNS=-1.206 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[7]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[7] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.024 | TNS=-1.197 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[25]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[25] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[25]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.024 | TNS=-1.190 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[26]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[26] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[26]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.024 | TNS=-1.183 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[27]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[27] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[27]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.024 | TNS=-1.176 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[6]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[6] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.022 | TNS=-1.170 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[16]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[16] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[16]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.022 | TNS=-1.158 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[17]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[17] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[17]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.022 | TNS=-1.146 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[19]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[19] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[19]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.022 | TNS=-1.134 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[1]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[1] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__1 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.dout_valid_i_2__10_n_0. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.dout_valid_i_2__10 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.dout_valid_i_2__10_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.021 | TNS=-0.323 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_fifo/out_data_reg[63]_0[7]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_fifo/out_data[7]_i_1__11_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.020 | TNS=-0.301 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.output_channel2_ila/U0/ila_core_inst/xsdb_memory_read_inst/Q[5]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.output_channel2_ila/U0/ila_core_inst/xsdb_memory_read_inst/next_state__0[6]. Re-placed instance GOLDEN_IF.output_channel2_ila/U0/ila_core_inst/xsdb_memory_read_inst/current_state[6]_i_1 INFO: [Physopt 32-735] Processed net GOLDEN_IF.output_channel2_ila/U0/ila_core_inst/xsdb_memory_read_inst/next_state__0[6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.020 | TNS=-0.281 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[4].MUX_register_B/Q[18]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[4].MUX_register_B/out_data_reg[18] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[4].MUX_register_B/Q[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.020 | TNS=-0.261 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.020 | TNS=-0.261 | Phase 4 Critical Path Optimization | Checksum: bd6cf74c Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58738 ; free virtual = 67080 Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58730 ; free virtual = 67071 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.020 | TNS=-0.261 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.128 | 1.794 | 0 | 0 | 42 | 0 | 2 | 00:00:07 | | Total | 0.128 | 1.794 | 0 | 0 | 42 | 0 | 3 | 00:00:07 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58728 ; free virtual = 67070 Ending Physical Synthesis Task | Checksum: 14d1911f5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58730 ; free virtual = 67072 INFO: [Common 17-83] Releasing license: Implementation 370 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 58800 ; free virtual = 67141 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 55454 ; free virtual = 63961 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 55541 ; free virtual = 63921 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 1bb6509a ConstDB: 0 ShapeSum: 50fccfca RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 100e2e8cc Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53929 ; free virtual = 62309 Post Restoration Checksum: NetGraph: 8e171354 NumContArr: 72cbd578 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 100e2e8cc Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53974 ; free virtual = 62353 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 100e2e8cc Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53930 ; free virtual = 62310 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 100e2e8cc Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53944 ; free virtual = 62323 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1097b61ac Time (s): cpu = 00:01:41 ; elapsed = 00:01:42 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 55548 ; free virtual = 63947 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.024 | TNS=-0.101 | WHS=-2.796 | THS=-4965.078| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: c3081615 Time (s): cpu = 00:02:13 ; elapsed = 00:02:14 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53737 ; free virtual = 62136 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.024 | TNS=-0.001 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 124f299c6 Time (s): cpu = 00:02:14 ; elapsed = 00:02:15 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53732 ; free virtual = 62131 Phase 2 Router Initialization | Checksum: 11a7f0eb6 Time (s): cpu = 00:02:14 ; elapsed = 00:02:15 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53728 ; free virtual = 62127 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 101865 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 101863 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 11a7f0eb6 Time (s): cpu = 00:02:15 ; elapsed = 00:02:16 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53710 ; free virtual = 62109 Phase 3 Initial Routing | Checksum: 1c0a7b965 Time (s): cpu = 00:04:57 ; elapsed = 00:05:00 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 56472 ; free virtual = 64862 INFO: [Route 35-580] Design has 28 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/FSM_sequential_current_state_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[1]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 8255 Number of Nodes with overlaps = 738 Number of Nodes with overlaps = 193 Number of Nodes with overlaps = 63 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.214 | TNS=-6.540 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 14700e4a4 Time (s): cpu = 00:06:58 ; elapsed = 00:07:02 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 51346 ; free virtual = 59736 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1115 Number of Nodes with overlaps = 283 Number of Nodes with overlaps = 95 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.052 | TNS=-0.254 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 240a9a1e4 Time (s): cpu = 00:07:38 ; elapsed = 00:07:43 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 49088 ; free virtual = 57478 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 1116 Number of Nodes with overlaps = 210 Number of Nodes with overlaps = 112 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.048 | TNS=-0.452 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1bd3175a3 Time (s): cpu = 00:08:17 ; elapsed = 00:08:22 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 48697 ; free virtual = 57088 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 761 Number of Nodes with overlaps = 108 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.038 | TNS=-0.202 | WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 2311e39bc Time (s): cpu = 00:08:46 ; elapsed = 00:08:52 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 49769 ; free virtual = 58160 Phase 4.5 Global Iteration 4 Number of Nodes with overlaps = 554 Number of Nodes with overlaps = 72 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.033 | TNS=-0.297 | WHS=N/A | THS=N/A | Phase 4.5 Global Iteration 4 | Checksum: 21f33ab7f Time (s): cpu = 00:09:20 ; elapsed = 00:09:27 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 48168 ; free virtual = 56558 Phase 4.6 Global Iteration 5 Number of Nodes with overlaps = 417 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.084 | TNS=-0.927 | WHS=N/A | THS=N/A | Phase 4.6 Global Iteration 5 | Checksum: 220be3c90 Time (s): cpu = 00:09:39 ; elapsed = 00:09:46 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50406 ; free virtual = 58796 Phase 4 Rip-up And Reroute | Checksum: 220be3c90 Time (s): cpu = 00:09:39 ; elapsed = 00:09:46 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50385 ; free virtual = 58775 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 238d3f163 Time (s): cpu = 00:09:49 ; elapsed = 00:09:56 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 51603 ; free virtual = 59993 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.054 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 1d499ad84 Time (s): cpu = 00:09:50 ; elapsed = 00:09:57 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 52004 ; free virtual = 60395 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1d499ad84 Time (s): cpu = 00:09:50 ; elapsed = 00:09:57 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 52152 ; free virtual = 60543 Phase 5 Delay and Skew Optimization | Checksum: 1d499ad84 Time (s): cpu = 00:09:51 ; elapsed = 00:09:57 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 52111 ; free virtual = 60502 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1b4aed26b Time (s): cpu = 00:10:03 ; elapsed = 00:10:10 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 51368 ; free virtual = 59758 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.054 | TNS=0.000 | WHS=-1.110 | THS=-38.465| Phase 6.1 Hold Fix Iter | Checksum: 267696604 Time (s): cpu = 00:10:04 ; elapsed = 00:10:11 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 51324 ; free virtual = 59715 Phase 6 Post Hold Fix | Checksum: 1b419ba78 Time (s): cpu = 00:10:04 ; elapsed = 00:10:11 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 51318 ; free virtual = 59709 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1a42642a2 Time (s): cpu = 00:10:20 ; elapsed = 00:10:27 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50708 ; free virtual = 59098 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.054 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 1a42642a2 Time (s): cpu = 00:10:20 ; elapsed = 00:10:27 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50621 ; free virtual = 59012 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.20041 % Global Horizontal Routing Utilization = 9.72506 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 1a42642a2 Time (s): cpu = 00:10:21 ; elapsed = 00:10:28 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50541 ; free virtual = 58931 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1a42642a2 Time (s): cpu = 00:10:22 ; elapsed = 00:10:29 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50535 ; free virtual = 58925 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 10598b4fe Time (s): cpu = 00:10:30 ; elapsed = 00:10:37 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 50030 ; free virtual = 58421 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.054 | TNS=0.000 | WHS=0.055 | THS=0.000 | Phase 11 Post Router Timing | Checksum: 19c883285 Time (s): cpu = 00:11:09 ; elapsed = 00:11:16 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53163 ; free virtual = 61553 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 1 | 0.054 | 0.000 | -1.110 | - | Pass | 00:09:50 | x | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:11:09 ; elapsed = 00:11:16 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53364 ; free virtual = 61754 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 397 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:11:48 ; elapsed = 00:11:56 . Memory (MB): peak = 4792.746 ; gain = 0.000 ; free physical = 53364 ; free virtual = 61754 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.2-hog23ab5f1 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value 23ab5f1 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.2-hog23ab5f1 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.6.2-hog23ab5f1... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.