## efex_processor.2 Synthesis Utilization report
                                                                                     
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |   
| ---    |         ---  |        --- |         ---  |             ---  |             
| Slice  LUTs*     |    186507   |   0         |    346400        |    53.84     |   
| Slice  Registers |    268609   |   0         |    692800        |    38.77     |   
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03
| DSPs   |         0    |        0   |         2880 |             0.00 |             
| Bonded IOB       |    501      |   0         |    600           |    83.50     |   
                                                                                     
## efex_processor.2 Implementation Utilization report
                                                                                        
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         ---  |             ---  |              
| Slice  LUTs      |    194726   |     0         |    346400        |    56.21     |    
| Slice  Registers |    295499   |     0         |    692800        |    42.65     |    
| Block  RAM       Tile |        743.5 |         0    |             1180 |         63.01
| DSPs   |         120  |        0     |         2880 |             4.17 |              
| Bonded IOB       |    449      |     449       |    600           |    74.83     |