## Repository info - Merge request number: 311 - Branch name: feature/ttc_parity ## MR Description Add incoming TTC parity code to Processors ## Changelog - replace components with entities ## efex_processor.4 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 67508f9 | 1.6.2 | | Constraints | 61a0bb0f | 1.6.2 | | IPbus XML | 8f38057 | 1.6.2 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 8f38057 | 1.6.2 | | **Lib:** algolib | 4688372 | 1.6.2 | | **Lib:** infrastructure_lib | 67508f9 | 1.6.2 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_processor.2 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 5933dbb | 1.6.2 | | Constraints | 5933dbbb | 1.6.2 | | IPbus XML | 8f38057 | 1.6.2 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 8f38057 | 1.6.2 | | **Lib:** algolib | 4688372 | 1.6.2 | | **Lib:** infrastructure_lib | 67508f9 | 1.6.2 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_processor.1 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 67508f9 | 1.6.2 | | Constraints | ec59a208 | 1.6.2 | | IPbus XML | 8f38057 | 1.6.2 | | Top Directory | 6fb4826 | 0.14.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 8f38057 | 1.6.2 | | **Lib:** algolib | 4688372 | 1.6.2 | | **Lib:** infrastructure_lib | 67508f9 | 1.6.2 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_control Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 23ab5f1 | 1.6.2 | | Constraints | 23ab5f18 | 1.6.2 | | IPbus XML | 7d3a917 | 1.6.0 | | Top Directory | d88faa0 | 0.15.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** infrastructure_lib | 90d4ef1 | 1.6.2 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | ## efex_processor.3 Version Table | **File set** | **Commit SHA** | **Version** | | --- | --- | --- | | Global | 67508f9 | 1.6.2 | | Constraints | 00fb8dc1 | 1.5.6 | | IPbus XML | 8f38057 | 1.6.2 | | Top Directory | 544c0a0 | 0.8.0 | | Hog | 7dd4817 | 6.48.5 | | **Lib:** TOB_rdout_lib | 8f38057 | 1.6.2 | | **Lib:** algolib | 4688372 | 1.6.2 | | **Lib:** infrastructure_lib | 67508f9 | 1.6.2 | | **Lib:** ipbus_lib | d6f4f62 | 1.0.0 | | **Lib:** usr_ip | e9b43d6 | 1.5.6 | ## efex_processor.4 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.049318 | | TNS: | 0.000000 | | WHS: | 0.035194 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.2 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.036745 | | TNS: | 0.000000 | | WHS: | 0.049830 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.1 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.031307 | | TNS: | 0.000000 | | WHS: | 0.024048 | | THS: | 0.000000 | Time requirements are met. ## efex_control Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.053708 | | TNS: | 0.000000 | | WHS: | 0.055097 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.3 Timing summary | **Parameter** | **value (ns)** | | --- | --- | | WNS: | 0.028686 | | TNS: | 0.000000 | | WHS: | 0.028864 | | THS: | 0.000000 | Time requirements are met. ## efex_processor.4 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182670 | 0 | 346400 | 52.73 | | Slice Registers | 257039 | 0 | 692800 | 37.10 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 503 | 0 | 600 | 83.83 | ## efex_processor.4 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191612 | 0 | 346400 | 55.32 | | Slice Registers | 284183 | 0 | 692800 | 41.02 | | Block RAM Tile | 732.5 | 0 | 1180 | 62.08 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 253 | 251 | 600 | 42.17 | ## efex_processor.2 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186507 | 0 | 346400 | 53.84 | | Slice Registers | 268609 | 0 | 692800 | 38.77 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 501 | 0 | 600 | 83.50 | ## efex_processor.2 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 194726 | 0 | 346400 | 56.21 | | Slice Registers | 295499 | 0 | 692800 | 42.65 | | Block RAM Tile | 743.5 | 0 | 1180 | 63.01 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 449 | 449 | 600 | 74.83 | ## efex_processor.1 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 186439 | 0 | 346400 | 53.82 | | Slice Registers | 268589 | 0 | 692800 | 38.77 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 501 | 0 | 600 | 83.50 | ## efex_processor.1 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 195314 | 0 | 346400 | 56.38 | | Slice Registers | 295727 | 0 | 692800 | 42.69 | | Block RAM Tile | 743.5 | 0 | 1180 | 63.01 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 449 | 449 | 600 | 74.83 | ## efex_control Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 30210 | 0 | 204000 | 14.81 | | Slice Registers | 50931 | 0 | 408000 | 12.48 | | Block RAM Tile | 322 | 0 | 750 | 42.93 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 382 | 0 | 600 | 63.67 | ## efex_control Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 38186 | 0 | 204000 | 18.72 | | Slice Registers | 69485 | 0 | 408000 | 17.03 | | Block RAM Tile | 361.5 | 0 | 750 | 48.20 | DSPs | 0 | 0 | 1120 | 0.00 | | Bonded IOB | 350 | 338 | 600 | 58.33 | ## efex_processor.3 Synthesis Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs* | 182676 | 0 | 346400 | 52.74 | | Slice Registers | 257039 | 0 | 692800 | 37.10 | | Block RAM Tile | 24 | 0 | 1180 | 2.03 | DSPs | 0 | 0 | 2880 | 0.00 | | Bonded IOB | 503 | 0 | 600 | 83.83 | ## efex_processor.3 Implementation Utilization report | **Site Type** | **Used** | **Fixed** | **Available** | **Util%** | | --- | --- | --- | --- | --- | | Slice LUTs | 191615 | 0 | 346400 | 55.32 | | Slice Registers | 283834 | 0 | 692800 | 40.97 | | Block RAM Tile | 732.5 | 0 | 1180 | 62.08 | DSPs | 120 | 0 | 2880 | 4.17 | | Bonded IOB | 253 | 251 | 600 | 42.17 |