Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Mon Mar 18 18:43:13 2024 | Host : efex-heavyduty-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_processor.2-v1.6.4-8A425DB/reports/hierarchical_utilization.txt | Design : top_efex_processor | Device : 7vx550tffg1927-2 | Design State : Routed ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-------------------------------+-------------------------------------+-------------+-------------+----------+-----------+-------------+-----------+----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-------------------------------+-------------------------------------+-------------+-------------+----------+-----------+-------------+-----------+----------+------------+ | top_efex_processor | (top) | 2538(0.73%) | 2518(0.73%) | 0(0.00%) | 20(0.01%) | 3579(0.52%) | 20(1.69%) | 0(0.00%) | 0(0.00%) | | (top_efex_processor) | (top) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | proc_FPGAs | 2155(0.62%) | 2136(0.62%) | 0(0.00%) | 19(0.01%) | 2600(0.38%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_node_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | ipbus_ctrl | 2142(0.62%) | 2123(0.61%) | 0(0.00%) | 19(0.01%) | 2547(0.37%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (U_2) | ipbus_ctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 632(0.18%) | 632(0.18%) | 0(0.00%) | 0(0.00%) | 307(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 156(0.05%) | 156(0.05%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 487(0.14%) | 487(0.14%) | 0(0.00%) | 0(0.00%) | 172(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 1509(0.44%) | 1490(0.43%) | 0(0.00%) | 19(0.01%) | 2240(0.32%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 193(0.06%) | 192(0.06%) | 0(0.00%) | 1(0.01%) | 224(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 179(0.05%) | 179(0.05%) | 0(0.00%) | 0(0.00%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 106(0.03%) | 90(0.03%) | 0(0.00%) | 16(0.01%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 144(0.04%) | 144(0.04%) | 0(0.00%) | 0(0.00%) | 172(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 235(0.07%) | 235(0.07%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_5 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_resources | clk_resources | 9(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_resources) | clk_resources | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 8(0.01%) | 7(0.01%) | 0(0.00%) | 1(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 4(0.01%) | 3(0.01%) | 0(0.00%) | 1(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | slaves | 344(0.10%) | 344(0.10%) | 0(0.00%) | 0(0.00%) | 896(0.13%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | bcmuxvalue_sync | ipbus_ctrlreg_v__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig | ipbus_ctrlreg_v__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32 | 273(0.08%) | 273(0.08%) | 0(0.00%) | 0(0.00%) | 304(0.04%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bc_delay | ipbus_ctrlreg_v__parameterized1_1 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bus_delay | ipbus_ctrlreg_v__parameterized1_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_synch | ipbus_ctrlreg_v__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_orbit_length | ipbus_ctrlreg_v__parameterized2_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 367(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 366(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-------------------------------+-------------------------------------+-------------+-------------+----------+-----------+-------------+-----------+----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining