*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2504.066 ; gain = 0.000 ; free physical = 2202 ; free virtual = 6121 INFO: [Netlist 29-17] Analyzing 155 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[0].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[0].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[1].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[1].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[2].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[2].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[3].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[3].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3303.699 ; gain = 581.820 ; free physical = 1267 ; free virtual = 5185 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga3.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga3.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_only_fpga3.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_only_fpga3.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3303.699 ; gain = 0.000 ; free physical = 1261 ; free virtual = 5180 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 3303.699 ; gain = 799.844 ; free physical = 1261 ; free virtual = 5180 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3319.707 ; gain = 8.008 ; free physical = 1250 ; free virtual = 5169 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: f7d5a869 Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3329.613 ; gain = 9.906 ; free physical = 1243 ; free virtual = 5162 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1669b439e Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1027 ; free virtual = 4946 INFO: [Opt 31-389] Phase Retarget created 5 cells and removed 72 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 184585555 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.42 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1022 ; free virtual = 4941 INFO: [Opt 31-389] Phase Constant propagation created 2 cells and removed 49 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1aaab7e83 Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1015 ; free virtual = 4934 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells INFO: [Opt 31-1021] In phase Sweep, 92 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 4 BUFG optimization | Checksum: 1e6990808 Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.58 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1011 ; free virtual = 4930 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 1e6990808 Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.59 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1011 ; free virtual = 4930 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1d8d82bcc Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.61 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1011 ; free virtual = 4930 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 5 | 72 | 1 | | Constant propagation | 2 | 49 | 0 | | Sweep | 0 | 46 | 92 | | BUFG optimization | 0 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3494.582 ; gain = 0.000 ; free physical = 1011 ; free virtual = 4930 Ending Logic Optimization Task | Checksum: 1f9218af3 Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.75 . Memory (MB): peak = 3494.582 ; gain = 0.004 ; free physical = 1011 ; free virtual = 4930 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 20 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 40 Ending PowerOpt Patch Enables Task | Checksum: 2766ecd81 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1331 ; free virtual = 5250 Ending Power Optimization Task | Checksum: 2766ecd81 Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 3736.527 ; gain = 241.945 ; free physical = 1336 ; free virtual = 5255 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1852f663f Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.61 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1318 ; free virtual = 5237 Ending Final Cleanup Task | Checksum: 1852f663f Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1318 ; free virtual = 5237 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1318 ; free virtual = 5237 Ending Netlist Obfuscation Task | Checksum: 1852f663f Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1318 ; free virtual = 5237 INFO: [Common 17-83] Releasing license: Implementation 46 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3736.527 ; gain = 432.828 ; free physical = 1318 ; free virtual = 5237 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1300 ; free virtual = 5232 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.3/efex_golden_processor.3.runs/impl_1/top_efex_processor_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.3/efex_golden_processor.3.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1244 ; free virtual = 5165 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d8c1727a Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1244 ; free virtual = 5165 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1244 ; free virtual = 5165 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1c47b5120 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1255 ; free virtual = 5176 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 19404a166 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1254 ; free virtual = 5175 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 19404a166 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1254 ; free virtual = 5175 Phase 1 Placer Initialization | Checksum: 19404a166 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1247 ; free virtual = 5168 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 14063752e Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1231 ; free virtual = 5152 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fe955fb3 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1229 ; free virtual = 5150 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 157 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 72 nets or cells. Created 0 new cell, deleted 72 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1171 ; free virtual = 5092 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 72 | 72 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 72 | 72 | 0 | 3 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 2331d68f1 Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1167 ; free virtual = 5088 Phase 2.3 Global Placement Core | Checksum: 23e2d252c Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1155 ; free virtual = 5076 Phase 2 Global Placement | Checksum: 23e2d252c Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1163 ; free virtual = 5084 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 169daca1b Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1164 ; free virtual = 5085 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d8bb4084 Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1149 ; free virtual = 5070 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1f922c932 Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1145 ; free virtual = 5066 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 164bbcf98 Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1145 ; free virtual = 5066 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1f2f39ca8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1122 ; free virtual = 5043 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 2111eabda Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1121 ; free virtual = 5042 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1d93d3863 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1120 ; free virtual = 5041 Phase 3 Detail Placement | Checksum: 1d93d3863 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1120 ; free virtual = 5041 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 21e8bcc42 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.169 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 20c853c75 Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1138 ; free virtual = 5059 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 22f68e318 Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1138 ; free virtual = 5058 Phase 4.1.1.1 BUFG Insertion | Checksum: 21e8bcc42 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1138 ; free virtual = 5058 INFO: [Place 30-746] Post Placement Timing Summary WNS=2.169. For the most accurate timing information please run report_timing. Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1138 ; free virtual = 5059 Phase 4.1 Post Commit Optimization | Checksum: 256f41373 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1138 ; free virtual = 5059 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 256f41373 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1153 ; free virtual = 5074 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 256f41373 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1152 ; free virtual = 5073 Phase 4.3 Placer Reporting | Checksum: 256f41373 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1152 ; free virtual = 5073 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1152 ; free virtual = 5073 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1152 ; free virtual = 5073 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d0ee6dcf Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1151 ; free virtual = 5072 Ending Placer Task | Checksum: fcf549af Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1151 ; free virtual = 5072 INFO: [Common 17-83] Releasing license: Implementation 79 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1209 ; free virtual = 5130 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1183 ; free virtual = 5122 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.3/efex_golden_processor.3.runs/impl_1/top_efex_processor_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.42 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1152 ; free virtual = 5076 INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1191 ; free virtual = 5115 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 90 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3736.527 ; gain = 0.000 ; free physical = 1129 ; free virtual = 5071 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.3/efex_golden_processor.3.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: be748392 ConstDB: 0 ShapeSum: 3e80c61d RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: d215481d Time (s): cpu = 00:01:03 ; elapsed = 00:01:03 . Memory (MB): peak = 4062.887 ; gain = 326.359 ; free physical = 587 ; free virtual = 4513 Post Restoration Checksum: NetGraph: 7f06501d NumContArr: 530ef800 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: d215481d Time (s): cpu = 00:01:03 ; elapsed = 00:01:03 . Memory (MB): peak = 4062.887 ; gain = 326.359 ; free physical = 586 ; free virtual = 4513 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: d215481d Time (s): cpu = 00:01:03 ; elapsed = 00:01:04 . Memory (MB): peak = 4063.887 ; gain = 327.359 ; free physical = 572 ; free virtual = 4499 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: d215481d Time (s): cpu = 00:01:03 ; elapsed = 00:01:04 . Memory (MB): peak = 4063.887 ; gain = 327.359 ; free physical = 572 ; free virtual = 4498 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 19e516e2a Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4163.918 ; gain = 427.391 ; free physical = 632 ; free virtual = 4483 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.200 | TNS=0.000 | WHS=-0.354 | THS=-110.890| Phase 2 Router Initialization | Checksum: 1ead32960 Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4163.918 ; gain = 427.391 ; free physical = 663 ; free virtual = 4514 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 8.84712e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 5692 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 5691 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1ead32960 Time (s): cpu = 00:01:12 ; elapsed = 00:01:13 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 650 ; free virtual = 4356 Phase 3 Initial Routing | Checksum: 1cbfad964 Time (s): cpu = 00:01:16 ; elapsed = 00:01:16 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1047 ; free virtual = 4753 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 424 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.422 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 17a241df4 Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1042 ; free virtual = 4748 Phase 4 Rip-up And Reroute | Checksum: 17a241df4 Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1042 ; free virtual = 4748 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 17a241df4 Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1042 ; free virtual = 4748 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 17a241df4 Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1042 ; free virtual = 4748 Phase 5 Delay and Skew Optimization | Checksum: 17a241df4 Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1042 ; free virtual = 4748 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1b4b2d8e1 Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1038 ; free virtual = 4744 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.422 | TNS=0.000 | WHS=0.071 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1b4b2d8e1 Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1038 ; free virtual = 4744 Phase 6 Post Hold Fix | Checksum: 1b4b2d8e1 Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1038 ; free virtual = 4744 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.140392 % Global Horizontal Routing Utilization = 0.148091 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 17f2f8a87 Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1025 ; free virtual = 4731 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 17f2f8a87 Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1024 ; free virtual = 4730 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1413be9b9 Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1020 ; free virtual = 4726 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=2.422 | TNS=0.000 | WHS=0.071 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 1413be9b9 Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1024 ; free virtual = 4731 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1058 ; free virtual = 4764 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 104 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 4183.152 ; gain = 446.625 ; free physical = 1058 ; free virtual = 4764 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_processor.3... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.3 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.4-8A425DB INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_golden_processor.3 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.3 clean. INFO: [Hog:Msg-0] The git SHA value 8a425db will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_processor.3... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.3 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.4-8A425DB INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_processor.3-v1.6.4-8A425DB... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.