*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.dcp' for cell 'GLOBAL_MERGE.IO_DELAY_A1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.dcp' for cell 'GLOBAL_MERGE.IO_DELAY_BC_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM.dcp' for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_1/ALGO_OUTPUT_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_209b_512/DPR_209b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U4_T_TOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3421.023 ; gain = 28.988 ; free physical = 77476 ; free virtual = 81391 INFO: [Netlist 29-17] Analyzing 30118 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Chipscope 16-324] Core: READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity UUID: d422f308-f24a-5302-b8c8-8392916aaf97 Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] get_clocks: Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 5253.340 ; gain = 1074.512 ; free physical = 75852 ; free virtual = 79767 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] get_clocks: Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 5711.012 ; gain = 457.672 ; free physical = 75372 ; free virtual = 79287 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] create_generated_clock: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 5854.012 ; gain = 143.000 ; free physical = 75226 ; free virtual = 79141 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] create_generated_clock: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 6069.012 ; gain = 215.000 ; free physical = 75008 ; free virtual = 78924 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga1.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga1.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga1.xdc] get_pins: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7187.941 ; gain = 1110.930 ; free physical = 73952 ; free virtual = 77867 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga1.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga1.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga1.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga1.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga1.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1715] 4 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 7251.945 ; gain = 0.000 ; free physical = 75625 ; free virtual = 79540 INFO: [Project 1-111] Unisim Transformation Summary: A total of 114 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 48 instances OBUFDS => OBUFDS: 66 instances 32 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:05:36 ; elapsed = 00:05:26 . Memory (MB): peak = 7251.945 ; gain = 4747.086 ; free physical = 75625 ; free virtual = 79540 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 7267.953 ; gain = 8.004 ; free physical = 75619 ; free virtual = 79534 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1ba11fa19 Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74759 ; free virtual = 78675 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74329 ; free virtual = 78267 Netlist sorting complete. Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.43 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74330 ; free virtual = 78268 Phase 1 Generate And Synthesize Debug Cores | Checksum: 1d0a724f6 Time (s): cpu = 00:02:14 ; elapsed = 00:02:50 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74328 ; free virtual = 78267 Phase 2 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1abc181d0 Time (s): cpu = 00:02:41 ; elapsed = 00:03:18 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74890 ; free virtual = 78828 INFO: [Opt 31-389] Phase Retarget created 163 cells and removed 553 cells INFO: [Opt 31-1021] In phase Retarget, 289 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 1d1ec0653 Time (s): cpu = 00:02:45 ; elapsed = 00:03:22 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74890 ; free virtual = 78828 INFO: [Opt 31-389] Phase Constant propagation created 38 cells and removed 194 cells INFO: [Opt 31-1021] In phase Constant propagation, 205 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 276d2acaa Time (s): cpu = 00:03:00 ; elapsed = 00:03:37 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74901 ; free virtual = 78840 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3536 cells INFO: [Opt 31-1021] In phase Sweep, 1805 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 1d60a5fb3 Time (s): cpu = 00:03:08 ; elapsed = 00:03:45 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74901 ; free virtual = 78839 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1abc5089d Time (s): cpu = 00:03:10 ; elapsed = 00:03:47 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74901 ; free virtual = 78839 INFO: [Opt 31-389] Phase Shift Register Optimization created 64 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 2446e9b66 Time (s): cpu = 00:03:12 ; elapsed = 00:03:49 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74902 ; free virtual = 78840 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 359 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 163 | 553 | 289 | | Constant propagation | 38 | 194 | 205 | | Sweep | 0 | 3536 | 1805 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 64 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 359 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.97 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74910 ; free virtual = 78848 Ending Logic Optimization Task | Checksum: 21e655e1a Time (s): cpu = 00:03:26 ; elapsed = 00:04:03 . Memory (MB): peak = 7267.953 ; gain = 0.000 ; free physical = 74910 ; free virtual = 78848 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 800 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 98 newly gated: 189 Total Ports: 1600 Ending PowerOpt Patch Enables Task | Checksum: 268b7738f Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 10137.391 ; gain = 0.000 ; free physical = 73959 ; free virtual = 77899 Ending Power Optimization Task | Checksum: 268b7738f Time (s): cpu = 00:04:21 ; elapsed = 00:03:37 . Memory (MB): peak = 10137.391 ; gain = 2869.438 ; free physical = 74447 ; free virtual = 78388 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 16819fa49 Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 10137.391 ; gain = 0.000 ; free physical = 74087 ; free virtual = 78028 Ending Final Cleanup Task | Checksum: 16819fa49 Time (s): cpu = 00:01:02 ; elapsed = 00:01:04 . Memory (MB): peak = 10137.391 ; gain = 0.000 ; free physical = 74086 ; free virtual = 78026 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10137.391 ; gain = 0.000 ; free physical = 74087 ; free virtual = 78028 Ending Netlist Obfuscation Task | Checksum: 16819fa49 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10137.391 ; gain = 0.000 ; free physical = 74087 ; free virtual = 78028 INFO: [Common 17-83] Releasing license: Implementation 71 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:09:34 ; elapsed = 00:09:31 . Memory (MB): peak = 10137.391 ; gain = 2885.445 ; free physical = 74089 ; free virtual = 78029 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 10137.391 ; gain = 0.000 ; free physical = 72664 ; free virtual = 77018 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:09:50 ; elapsed = 00:10:10 . Memory (MB): peak = 10137.395 ; gain = 0.004 ; free physical = 72961 ; free virtual = 77032 INFO: [runtcl-4] Executing : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:49 ; elapsed = 00:01:51 . Memory (MB): peak = 10137.395 ; gain = 0.000 ; free physical = 72567 ; free virtual = 76636 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[10] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[9]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[11] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[10]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[12] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[11]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[13] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[12]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[1] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[0]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[2] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[1]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[3] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[2]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[4] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[3]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[5] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[4]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[6] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[5]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[7] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[6]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[8] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[7]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[9] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[8]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[10] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[9]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[11] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[10]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[12] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[11]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[13] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[12]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[7] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[6]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[8] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[7]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[9] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[8]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10137.395 ; gain = 0.000 ; free physical = 72559 ; free virtual = 76629 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12ae20c35 Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.16 . Memory (MB): peak = 10137.395 ; gain = 0.000 ; free physical = 72558 ; free virtual = 76628 Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 10137.395 ; gain = 0.000 ; free physical = 72558 ; free virtual = 76628 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ba3b48c1 Time (s): cpu = 00:19:16 ; elapsed = 00:26:13 . Memory (MB): peak = 34374.391 ; gain = 24236.996 ; free physical = 47031 ; free virtual = 51101 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 11e75892c Time (s): cpu = 00:21:01 ; elapsed = 00:28:00 . Memory (MB): peak = 35582.977 ; gain = 25445.582 ; free physical = 46570 ; free virtual = 50640 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 11e75892c Time (s): cpu = 00:21:03 ; elapsed = 00:28:01 . Memory (MB): peak = 35582.977 ; gain = 25445.582 ; free physical = 46575 ; free virtual = 50645 Phase 1 Placer Initialization | Checksum: 11e75892c Time (s): cpu = 00:21:04 ; elapsed = 00:28:03 . Memory (MB): peak = 35582.977 ; gain = 25445.582 ; free physical = 46560 ; free virtual = 50631 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1a32c08fc Time (s): cpu = 00:21:37 ; elapsed = 00:28:36 . Memory (MB): peak = 35582.977 ; gain = 25445.582 ; free physical = 46356 ; free virtual = 50427 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 21af22aec Time (s): cpu = 00:22:03 ; elapsed = 00:29:03 . Memory (MB): peak = 35582.977 ; gain = 25445.582 ; free physical = 46362 ; free virtual = 50432 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 67 LUTNM shape to break, 12733 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 38, two critical 29, total 67, new lutff created 12 INFO: [Physopt 32-775] End 1 Pass. Optimized 6068 nets or cells. Created 67 new cells, deleted 6001 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_hdr_BCN_in_i. Replicated 12 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/IN_Load. Replicated 79 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 69 times. INFO: [Physopt 32-232] Optimized 3 nets. Created 160 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 160 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46290 ; free virtual = 50361 INFO: [Physopt 32-76] Pass 1. Identified 18 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/enb. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1031[0]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1095[0]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1042[11]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1042[5]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1095[6]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1064[0]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1095[10]. Replicated 7 times. INFO: [Physopt 32-232] Optimized 18 nets. Created 144 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 18 nets or cells. Created 144 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46288 ; free virtual = 50359 INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/enb_array[1] could not be optimized because driver READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-46] Identified 20 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[8]. Replicated 4 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[7]. Replicated 3 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[0]. Replicated 2 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[2]. Replicated 4 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[1]. Replicated 3 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[5]. Replicated 3 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[3]. Replicated 3 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[6]. Replicated 3 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[9]. Replicated 4 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[4]. Replicated 4 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[6]_rep_n_0. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[4]_rep_n_0. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[9]_rep_n_0. Replicated 1 times. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[5]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[2]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[8]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[0]_rep_n_0 was not replicated. INFO: [Physopt 32-232] Optimized 13 nets. Created 36 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 36 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46288 ; free virtual = 50359 INFO: [Physopt 32-457] Pass 1. Identified 15 candidate cells for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 15 nets or cells. Created 120 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46288 ; free virtual = 50359 INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 35 nets or cells. Created 49 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46288 ; free virtual = 50358 INFO: [Physopt 32-527] Pass 1: Identified 4 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 20 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 116 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46287 ; free virtual = 50357 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 35603.102 ; gain = 0.000 ; free physical = 46305 ; free virtual = 50376 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 67 | 6001 | 6068 | 0 | 1 | 00:00:12 | | Very High Fanout | 160 | 0 | 3 | 0 | 1 | 00:00:12 | | Fanout | 144 | 0 | 18 | 0 | 1 | 00:00:06 | | Critical Cell | 36 | 0 | 13 | 0 | 1 | 00:00:01 | | DSP Register | 120 | 0 | 15 | 0 | 1 | 00:00:02 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 49 | 0 | 35 | 0 | 1 | 00:00:01 | | BRAM Register | 116 | 0 | 4 | 0 | 1 | 00:00:02 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 692 | 6001 | 6156 | 0 | 10 | 00:00:36 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1bfe2b895 Time (s): cpu = 00:28:52 ; elapsed = 00:36:02 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46308 ; free virtual = 50379 Phase 2.3 Global Placement Core | Checksum: 1aac69e83 Time (s): cpu = 00:29:09 ; elapsed = 00:36:19 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46285 ; free virtual = 50355 Phase 2 Global Placement | Checksum: 1aac69e83 Time (s): cpu = 00:29:09 ; elapsed = 00:36:20 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46448 ; free virtual = 50518 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21a50e885 Time (s): cpu = 00:29:43 ; elapsed = 00:36:54 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46428 ; free virtual = 50498 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1270d7bc7 Time (s): cpu = 00:30:55 ; elapsed = 00:38:07 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46315 ; free virtual = 50385 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 13f96ebec Time (s): cpu = 00:31:03 ; elapsed = 00:38:15 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46313 ; free virtual = 50383 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1804df5c8 Time (s): cpu = 00:31:05 ; elapsed = 00:38:16 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46313 ; free virtual = 50383 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 121481963 Time (s): cpu = 00:32:07 ; elapsed = 00:39:19 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46308 ; free virtual = 50378 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 134709e2b Time (s): cpu = 00:34:31 ; elapsed = 00:41:44 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46008 ; free virtual = 50078 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 122357cb0 Time (s): cpu = 00:34:50 ; elapsed = 00:42:03 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46027 ; free virtual = 50097 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 269b8688c Time (s): cpu = 00:34:56 ; elapsed = 00:42:09 . Memory (MB): peak = 35603.102 ; gain = 25465.707 ; free physical = 46027 ; free virtual = 50097 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 149c8833a Time (s): cpu = 00:36:52 ; elapsed = 00:44:06 . Memory (MB): peak = 35636.250 ; gain = 25498.855 ; free physical = 45991 ; free virtual = 50062 Phase 3 Detail Placement | Checksum: 149c8833a Time (s): cpu = 00:36:55 ; elapsed = 00:44:09 . Memory (MB): peak = 35636.250 ; gain = 25498.855 ; free physical = 45993 ; free virtual = 50064 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 15613fc99 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.344 | TNS=-10.612 | Phase 1 Physical Synthesis Initialization | Checksum: 1b87bfc3a Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 35746.715 ; gain = 42.465 ; free physical = 45468 ; free virtual = 49538 INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 5 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 5, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 23ce7b140 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 35768.719 ; gain = 64.469 ; free physical = 45460 ; free virtual = 49530 Phase 4.1.1.1 BUFG Insertion | Checksum: 15613fc99 Time (s): cpu = 00:39:53 ; elapsed = 00:47:09 . Memory (MB): peak = 35768.719 ; gain = 25631.324 ; free physical = 45480 ; free virtual = 49550 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.068. For the most accurate timing information please run report_timing. Time (s): cpu = 00:44:29 ; elapsed = 00:51:45 . Memory (MB): peak = 35836.719 ; gain = 25699.324 ; free physical = 45478 ; free virtual = 49549 Phase 4.1 Post Commit Optimization | Checksum: 24075746e Time (s): cpu = 00:44:32 ; elapsed = 00:51:48 . Memory (MB): peak = 35836.719 ; gain = 25699.324 ; free physical = 45476 ; free virtual = 49547 Post Placement Optimization Initialization | Checksum: 1724093f3 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.252 | TNS=-3.371 | Phase 1 Physical Synthesis Initialization | Checksum: 1e092bbcf Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 36056.992 ; gain = 0.000 ; free physical = 45533 ; free virtual = 49603 INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 5 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 5, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 230fd8905 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 36056.992 ; gain = 0.000 ; free physical = 45528 ; free virtual = 49598 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.238. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 197af98b1 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.238 | TNS=-0.238 | Phase 1 Physical Synthesis Initialization | Checksum: 1e6703cb9 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 36056.992 ; gain = 0.000 ; free physical = 45534 ; free virtual = 49604 INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 5 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 5, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 2508f0cd9 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 36056.992 ; gain = 0.000 ; free physical = 45528 ; free virtual = 49598 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.119. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: fe7e6850 Time (s): cpu = 00:58:17 ; elapsed = 01:05:35 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45540 ; free virtual = 49611 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 16x16| 8x8| |___________|___________________|___________________| | South| 16x16| 4x4| |___________|___________________|___________________| | East| 2x2| 4x4| |___________|___________________|___________________| | West| 16x16| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: fe7e6850 Time (s): cpu = 00:58:21 ; elapsed = 01:05:39 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45544 ; free virtual = 49614 Phase 4.3 Placer Reporting | Checksum: fe7e6850 Time (s): cpu = 00:58:24 ; elapsed = 01:05:42 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45544 ; free virtual = 49614 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 36056.992 ; gain = 0.000 ; free physical = 45551 ; free virtual = 49622 Time (s): cpu = 00:58:25 ; elapsed = 01:05:43 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45551 ; free virtual = 49622 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1162750ce Time (s): cpu = 00:58:27 ; elapsed = 01:05:45 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45552 ; free virtual = 49622 Ending Placer Task | Checksum: ee6c53c3 Time (s): cpu = 00:58:27 ; elapsed = 01:05:45 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45551 ; free virtual = 49622 INFO: [Common 17-83] Releasing license: Implementation 197 Infos, 50 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:59:09 ; elapsed = 01:06:28 . Memory (MB): peak = 36056.992 ; gain = 25919.598 ; free physical = 45892 ; free virtual = 49962 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 36056.992 ; gain = 0.000 ; free physical = 44918 ; free virtual = 49884 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:39 ; elapsed = 00:02:53 . Memory (MB): peak = 36056.996 ; gain = 0.004 ; free physical = 45669 ; free virtual = 49913 INFO: [runtcl-4] Executing : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:02 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45625 ; free virtual = 49869 INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45668 ; free virtual = 49912 INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45663 ; free virtual = 49910 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45542 ; free virtual = 49789 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.119 | TNS=-0.119 | Phase 1 Physical Synthesis Initialization | Checksum: 2551fda56 Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45376 ; free virtual = 49623 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.119 | TNS=-0.119 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 2551fda56 Time (s): cpu = 00:02:13 ; elapsed = 00:02:14 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45349 ; free virtual = 49596 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.119 | TNS=-0.119 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U0_busy_flag_fsm/busy_flag_i_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U0_busy_flag_fsm/busy_flag_i0_carry__0_n_3. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U0_busy_flag_fsm/busy_flag_i0_carry_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/S[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.116 | TNS=-0.116 | INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/S[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.032 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/S[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U0_busy_flag_fsm/busy_flag_i_i_1_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_data_count[1]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_reg[1] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_data_count[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.003 | TNS=-0.003 | INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/S[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.026 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.026 | TNS=0.000 | Phase 3 Critical Path Optimization | Checksum: 2551fda56 Time (s): cpu = 00:02:17 ; elapsed = 00:02:18 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45354 ; free virtual = 49601 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.026 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.026 | TNS=0.000 | Phase 4 Critical Path Optimization | Checksum: 2551fda56 Time (s): cpu = 00:02:17 ; elapsed = 00:02:18 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45354 ; free virtual = 49601 Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45373 ; free virtual = 49620 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.026 | TNS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:05 | | Critical Path | 0.145 | 0.119 | 0 | 0 | 4 | 0 | 2 | 00:00:04 | | Total | 0.145 | 0.119 | 0 | 0 | 4 | 0 | 3 | 00:00:09 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45373 ; free virtual = 49620 Ending Physical Synthesis Task | Checksum: 1b26527f2 Time (s): cpu = 00:02:19 ; elapsed = 00:02:19 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45373 ; free virtual = 49620 INFO: [Common 17-83] Releasing license: Implementation 232 Infos, 50 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:04:28 ; elapsed = 00:04:29 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45647 ; free virtual = 49894 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 44714 ; free virtual = 49830 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:38 ; elapsed = 00:02:53 . Memory (MB): peak = 36056.996 ; gain = 0.000 ; free physical = 45439 ; free virtual = 49857 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: b098b1b ConstDB: 0 ShapeSum: bccd1d80 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 14216f43 Time (s): cpu = 00:01:50 ; elapsed = 00:01:50 . Memory (MB): peak = 36125.859 ; gain = 0.000 ; free physical = 44842 ; free virtual = 49260 Post Restoration Checksum: NetGraph: 612a564 NumContArr: e0ec9df Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 14216f43 Time (s): cpu = 00:01:54 ; elapsed = 00:01:55 . Memory (MB): peak = 36125.859 ; gain = 0.000 ; free physical = 45067 ; free virtual = 49484 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 14216f43 Time (s): cpu = 00:01:57 ; elapsed = 00:01:58 . Memory (MB): peak = 36125.859 ; gain = 0.000 ; free physical = 45038 ; free virtual = 49456 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 14216f43 Time (s): cpu = 00:01:58 ; elapsed = 00:01:58 . Memory (MB): peak = 36125.859 ; gain = 0.000 ; free physical = 45038 ; free virtual = 49456 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 18f22cf04 Time (s): cpu = 00:05:05 ; elapsed = 00:05:08 . Memory (MB): peak = 36383.859 ; gain = 258.000 ; free physical = 44890 ; free virtual = 49307 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.138 | TNS=-0.702 | WHS=-0.476 | THS=-12003.184| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1f487fe9b Time (s): cpu = 00:07:00 ; elapsed = 00:07:04 . Memory (MB): peak = 36383.859 ; gain = 258.000 ; free physical = 44811 ; free virtual = 49229 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.138 | TNS=-0.153 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 131ded35f Time (s): cpu = 00:07:02 ; elapsed = 00:07:06 . Memory (MB): peak = 36383.859 ; gain = 258.000 ; free physical = 44806 ; free virtual = 49224 Phase 2 Router Initialization | Checksum: de1158c4 Time (s): cpu = 00:07:03 ; elapsed = 00:07:06 . Memory (MB): peak = 36383.859 ; gain = 258.000 ; free physical = 44806 ; free virtual = 49224 Router Utilization Summary Global Vertical Routing Utilization = 3.01103e-05 % Global Horizontal Routing Utilization = 2.94904e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 402981 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 402979 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: de1158c4 Time (s): cpu = 00:07:06 ; elapsed = 00:07:10 . Memory (MB): peak = 36383.859 ; gain = 258.000 ; free physical = 44803 ; free virtual = 49221 Phase 3 Initial Routing | Checksum: 1551e06bc Time (s): cpu = 00:12:38 ; elapsed = 00:12:44 . Memory (MB): peak = 36383.859 ; gain = 258.000 ; free physical = 44753 ; free virtual = 49171 INFO: [Route 35-580] Design has 2 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk280 | clk40 |READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[28]| | clk280 | clk280 |READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.gpf.wrpf/gdiff.gcry_1_sym.diff_pntr_pad_reg[9]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 38802 Number of Nodes with overlaps = 3765 Number of Nodes with overlaps = 856 Number of Nodes with overlaps = 184 Number of Nodes with overlaps = 66 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.065 | TNS=-0.114 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 108048fb0 Time (s): cpu = 00:23:46 ; elapsed = 00:23:59 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44766 ; free virtual = 49184 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1624 Number of Nodes with overlaps = 333 Number of Nodes with overlaps = 143 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.027 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1da9c5a5b Time (s): cpu = 00:25:28 ; elapsed = 00:25:44 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44764 ; free virtual = 49182 Phase 4 Rip-up And Reroute | Checksum: 1da9c5a5b Time (s): cpu = 00:25:29 ; elapsed = 00:25:45 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44764 ; free virtual = 49182 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1da9c5a5b Time (s): cpu = 00:25:31 ; elapsed = 00:25:46 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44764 ; free virtual = 49182 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1da9c5a5b Time (s): cpu = 00:25:32 ; elapsed = 00:25:47 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44764 ; free virtual = 49182 Phase 5 Delay and Skew Optimization | Checksum: 1da9c5a5b Time (s): cpu = 00:25:33 ; elapsed = 00:25:48 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44764 ; free virtual = 49182 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 19f2a9fdf Time (s): cpu = 00:26:17 ; elapsed = 00:26:33 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44730 ; free virtual = 49148 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.062 | TNS=0.000 | WHS=0.009 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1a0052429 Time (s): cpu = 00:26:19 ; elapsed = 00:26:34 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44730 ; free virtual = 49147 Phase 6 Post Hold Fix | Checksum: 1a0052429 Time (s): cpu = 00:26:20 ; elapsed = 00:26:35 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44730 ; free virtual = 49147 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 29.1384 % Global Horizontal Routing Utilization = 27.156 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 14bf99733 Time (s): cpu = 00:26:24 ; elapsed = 00:26:39 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44726 ; free virtual = 49143 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 14bf99733 Time (s): cpu = 00:26:25 ; elapsed = 00:26:40 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44722 ; free virtual = 49139 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 944444c9 Time (s): cpu = 00:26:56 ; elapsed = 00:27:11 . Memory (MB): peak = 36421.266 ; gain = 295.406 ; free physical = 44691 ; free virtual = 49109 Phase 10 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.061 | TNS=0.000 | WHS=0.009 | THS=0.000 | Phase 10 Post Router Timing | Checksum: 16d042f4e Time (s): cpu = 00:29:22 ; elapsed = 00:29:38 . Memory (MB): peak = 36518.363 ; gain = 392.504 ; free physical = 44308 ; free virtual = 48725 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+-------+-------+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+-------+-------+--------+--------------+-------------------+ | 1 | 0.062 | 0.000 | 0.009 | 0.000 | Pass | 00:25:20 | x | +------+-------+-------+-------+-------+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+-------+-------+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:29:22 ; elapsed = 00:29:38 . Memory (MB): peak = 36518.367 ; gain = 392.508 ; free physical = 44856 ; free virtual = 49273 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 251 Infos, 50 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:32:05 ; elapsed = 00:32:23 . Memory (MB): peak = 36518.367 ; gain = 461.371 ; free physical = 44856 ; free virtual = 49273 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.1... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.1 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.5-323C6FE INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_processor.1 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.1 clean. INFO: [Hog:Msg-0] The git SHA value 323c6fe will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.1... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.1 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.5-323C6FE INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.1-v1.6.5-323C6FE... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 36518.367 ; gain = 0.000 ; free physical = 44849 ; free virtual = 49270