## Repository info
- Merge request number: 322
- Branch name: feature/tau-bdt-min-et-and-max-et

## MR Description
* Introduce and implement an additional parameter for tau BDT algorithm - min. energy threshold below which BDT condition is set to "11". Was shown to improve low-pt efficiency while retaining the mid-high pt one (e.g. see [here](https://indico.cern.ch/event/1382847/contributions/5813534/attachments/2819559/4923306/L1CaloDaq.pdf), slide 18).
* Implement the max. ET cutoff which was so far not implemented for the BDT tau algorithm (above which BDT condition is set to "11").

Some details about non trivial changes:

  DelayTree.vhd - used to implement all delays within the algorithm. This obviously changed because of the addition of the new threshold as well as a small optimization where the BDT condition input parameters are read at clock cycle 10 (because the BDT score is ready at clock cycle 10 and to avoid dragging the parameters from clock cycle 5) while the parameters used by the had. frac. condition and the energy conditions are read at clock cycle 5.

AdderTree.vhd - Implements all sums in the algorithm. The "new" version is functionally identical to the previous one. The difference is the re-ordering of the signal declarations. This is a "bug" in my python generation code which doesn't affect the firmware functionality. Nevertheless, I just took the new version, because I'd like to stick to the automatic pipeline as much as possible.


## Changelog


## efex_processor.2


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.010684       |
| TNS:          | 0.000000       |
| WHS:          | 0.033399       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.2 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    183024   |   0         |    346400        |    52.84     |      
| Slice  Registers |    246577   |   0         |    692800        |    35.59     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    501      |   0         |    600           |    83.50     |      
                                                                                        
## efex_processor.2 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    192034   |     0         |    346400        |    55.44     |       
| Slice  Registers |    273748   |     0         |    692800        |    39.51     |       
| Block  RAM       Tile |        759.5 |         0    |             1180 |         64.36 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    449      |     449       |    600           |    74.83     |       
                                                                                           
## efex_processor.2 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | edff053        | 1.6.5       |
| Constraints                 | edff053f       | 1.6.5       |
| IPbus XML                   | 8f38057        | 1.6.2       |
| Top Directory               | 544c0a0        | 0.8.0       |
| Hog                         | 5f889f7        | 7.31.1      |
| **Lib:** TOB_rdout_lib      | 8a425db        | 1.6.4       |
| **Lib:** algolib            | 323c6fe        | 1.6.5       |
| **Lib:** infrastructure_lib | 294d13e        | 1.6.4       |
| **Lib:** others             | 8107f27        | 1.6.3       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | 8cc83f5        | 1.6.4       |



</details>
</p>

 
## efex_processor.3


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.3 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.052185       |
| TNS:          | 0.000000       |
| WHS:          | 0.015736       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.3 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    178939   |   0         |    346400        |    51.66     |      
| Slice  Registers |    235057   |   0         |    692800        |    33.93     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    503      |   0         |    600           |    83.83     |      
                                                                                        
## efex_processor.3 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    187765   |     0         |    346400        |    54.20     |       
| Slice  Registers |    262514   |     0         |    692800        |    37.89     |       
| Block  RAM       Tile |        748.5 |         0    |             1180 |         63.43 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    253      |     251       |    600           |    42.17     |       
                                                                                           
## efex_processor.3 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 323c6fe        | 1.6.5       |
| Constraints                 | 6e70c54a       | 1.6.3       |
| IPbus XML                   | 8f38057        | 1.6.2       |
| Top Directory               | 544c0a0        | 0.8.0       |
| Hog                         | 5f889f7        | 7.31.1      |
| **Lib:** TOB_rdout_lib      | 8a425db        | 1.6.4       |
| **Lib:** algolib            | 323c6fe        | 1.6.5       |
| **Lib:** infrastructure_lib | 294d13e        | 1.6.4       |
| **Lib:** others             | 8107f27        | 1.6.3       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | 8cc83f5        | 1.6.4       |



</details>
</p>

 
## efex_processor.4


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.4 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.080696       |
| TNS:          | 0.000000       |
| WHS:          | 0.009953       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.4 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    178931   |   0         |    346400        |    51.65     |      
| Slice  Registers |    235057   |   0         |    692800        |    33.93     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    503      |   0         |    600           |    83.83     |      
                                                                                        
## efex_processor.4 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    187656   |     0         |    346400        |    54.17     |       
| Slice  Registers |    263534   |     0         |    692800        |    38.04     |       
| Block  RAM       Tile |        748.5 |         0    |             1180 |         63.43 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    253      |     251       |    600           |    42.17     |       
                                                                                           
## efex_processor.4 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 323c6fe        | 1.6.5       |
| Constraints                 | a3338ac5       | 1.6.4       |
| IPbus XML                   | 8f38057        | 1.6.2       |
| Top Directory               | 544c0a0        | 0.8.0       |
| Hog                         | 5f889f7        | 7.31.1      |
| **Lib:** TOB_rdout_lib      | 8a425db        | 1.6.4       |
| **Lib:** algolib            | 323c6fe        | 1.6.5       |
| **Lib:** infrastructure_lib | 294d13e        | 1.6.4       |
| **Lib:** others             | 8107f27        | 1.6.3       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | 8cc83f5        | 1.6.4       |



</details>
</p>

 
## efex_processor.1


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.1 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.060869       |
| TNS:          | 0.000000       |
| WHS:          | 0.008769       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.1 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    182976   |   0         |    346400        |    52.82     |      
| Slice  Registers |    246567   |   0         |    692800        |    35.59     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    501      |   0         |    600           |    83.50     |      
                                                                                        
## efex_processor.1 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    191087   |     0         |    346400        |    55.16     |       
| Slice  Registers |    273326   |     0         |    692800        |    39.45     |       
| Block  RAM       Tile |        759.5 |         0    |             1180 |         64.36 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    449      |     449       |    600           |    74.83     |       
                                                                                           
## efex_processor.1 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 323c6fe        | 1.6.5       |
| Constraints                 | 1e62041f       | 1.6.3       |
| IPbus XML                   | 8f38057        | 1.6.2       |
| Top Directory               | 6fb4826        | 0.14.0      |
| Hog                         | 5f889f7        | 7.31.1      |
| **Lib:** TOB_rdout_lib      | 8a425db        | 1.6.4       |
| **Lib:** algolib            | 323c6fe        | 1.6.5       |
| **Lib:** infrastructure_lib | 294d13e        | 1.6.4       |
| **Lib:** others             | 8107f27        | 1.6.3       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | 8cc83f5        | 1.6.4       |



</details>
</p>