*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2565.645 ; gain = 0.000 ; free physical = 63593 ; free virtual = 66964 INFO: [Netlist 29-17] Analyzing 6744 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 3508.023 ; gain = 654.164 ; free physical = 65213 ; free virtual = 68585 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/efex_control.gen/sources_1/ip/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3540.023 ; gain = 0.000 ; free physical = 64499 ; free virtual = 67871 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:10 ; elapsed = 00:01:08 . Memory (MB): peak = 3540.023 ; gain = 1018.949 ; free physical = 64491 ; free virtual = 67863 source /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3548.027 ; gain = 8.000 ; free physical = 63183 ; free virtual = 66555 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 14a2363ef Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3548.027 ; gain = 0.000 ; free physical = 62740 ; free virtual = 66112 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3758.770 ; gain = 0.000 ; free physical = 61976 ; free virtual = 65355 Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3758.770 ; gain = 0.000 ; free physical = 61963 ; free virtual = 65341 Phase 1 Generate And Synthesize Debug Cores | Checksum: 187fdf14f Time (s): cpu = 00:01:53 ; elapsed = 00:02:31 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 61969 ; free virtual = 65347 Phase 2 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 9 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 185f9aa46 Time (s): cpu = 00:02:00 ; elapsed = 00:02:38 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62224 ; free virtual = 65604 INFO: [Opt 31-389] Phase Retarget created 117 cells and removed 354 cells INFO: [Opt 31-1021] In phase Retarget, 438 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 1af59d947 Time (s): cpu = 00:02:01 ; elapsed = 00:02:39 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62417 ; free virtual = 65797 INFO: [Opt 31-389] Phase Constant propagation created 175 cells and removed 625 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 131cfeb4e Time (s): cpu = 00:02:04 ; elapsed = 00:02:42 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62540 ; free virtual = 65921 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 746 cells INFO: [Opt 31-1021] In phase Sweep, 4690 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 1a02eadb6 Time (s): cpu = 00:02:05 ; elapsed = 00:02:44 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62562 ; free virtual = 65943 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 190dbcd04 Time (s): cpu = 00:02:06 ; elapsed = 00:02:44 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62541 ; free virtual = 65922 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 15bc553e1 Time (s): cpu = 00:02:06 ; elapsed = 00:02:45 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62467 ; free virtual = 65848 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 117 | 354 | 438 | | Constant propagation | 175 | 625 | 141 | | Sweep | 6 | 746 | 4690 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3758.770 ; gain = 0.000 ; free physical = 62515 ; free virtual = 65904 Ending Logic Optimization Task | Checksum: 1a68411a3 Time (s): cpu = 00:02:09 ; elapsed = 00:02:48 . Memory (MB): peak = 3758.770 ; gain = 43.777 ; free physical = 62514 ; free virtual = 65904 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 180ea187d Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4789.230 ; gain = 0.000 ; free physical = 61664 ; free virtual = 65049 Ending Power Optimization Task | Checksum: 180ea187d Time (s): cpu = 00:01:10 ; elapsed = 00:01:04 . Memory (MB): peak = 4789.230 ; gain = 1030.461 ; free physical = 61768 ; free virtual = 65153 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1fcf984d9 Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 4789.230 ; gain = 0.000 ; free physical = 62322 ; free virtual = 65710 Ending Final Cleanup Task | Checksum: 1fcf984d9 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 4789.230 ; gain = 0.000 ; free physical = 62314 ; free virtual = 65706 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4789.230 ; gain = 0.000 ; free physical = 62314 ; free virtual = 65706 Ending Netlist Obfuscation Task | Checksum: 1fcf984d9 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4789.230 ; gain = 0.000 ; free physical = 62314 ; free virtual = 65706 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:03:56 ; elapsed = 00:04:30 . Memory (MB): peak = 4789.230 ; gain = 1249.207 ; free physical = 62314 ; free virtual = 65706 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4789.230 ; gain = 0.000 ; free physical = 63104 ; free virtual = 66555 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 4789.234 ; gain = 0.004 ; free physical = 62895 ; free virtual = 66314 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63577 ; free virtual = 67000 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63563 ; free virtual = 66989 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17f9e3c24 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63561 ; free virtual = 66988 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63558 ; free virtual = 66984 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9be4476b Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63026 ; free virtual = 66449 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: f070e7d6 Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63102 ; free virtual = 66529 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: f070e7d6 Time (s): cpu = 00:01:01 ; elapsed = 00:01:01 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63076 ; free virtual = 66504 Phase 1 Placer Initialization | Checksum: f070e7d6 Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63036 ; free virtual = 66464 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1755eed39 Time (s): cpu = 00:01:14 ; elapsed = 00:01:14 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63300 ; free virtual = 66723 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18677b9f0 Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 62464 ; free virtual = 65889 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 86 LUTNM shape to break, 2503 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 69, two critical 17, total 86, new lutff created 6 INFO: [Physopt 32-775] End 1 Pass. Optimized 984 nets or cells. Created 86 new cells, deleted 898 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 7 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 48 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 55 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 55 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.33 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 62047 ; free virtual = 65485 INFO: [Physopt 32-76] Pass 1. Identified 16 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 7 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 16 nets. Created 85 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 16 nets or cells. Created 85 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 62018 ; free virtual = 65456 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-46] Identified 125 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[3]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[2]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[12]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/write_ptr[6]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-232] Optimized 9 nets. Created 9 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 9 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 62027 ; free virtual = 65469 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 10 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 7 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 62000 ; free virtual = 65442 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 62002 ; free virtual = 65444 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 86 | 898 | 984 | 0 | 1 | 00:00:03 | | Very High Fanout | 55 | 0 | 2 | 0 | 1 | 00:00:04 | | Fanout | 85 | 0 | 16 | 0 | 1 | 00:00:01 | | Critical Cell | 9 | 0 | 9 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 7 | 0 | 7 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 242 | 898 | 1018 | 0 | 10 | 00:00:09 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 5793c62c Time (s): cpu = 00:03:45 ; elapsed = 00:03:49 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63040 ; free virtual = 66486 Phase 2.3 Global Placement Core | Checksum: 1e955ff1d Time (s): cpu = 00:03:50 ; elapsed = 00:03:54 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 65139 ; free virtual = 68577 Phase 2 Global Placement | Checksum: 1e955ff1d Time (s): cpu = 00:03:50 ; elapsed = 00:03:54 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 65538 ; free virtual = 68976 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 146cbae9a Time (s): cpu = 00:04:04 ; elapsed = 00:04:07 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 64290 ; free virtual = 67727 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14c15b8a8 Time (s): cpu = 00:04:23 ; elapsed = 00:04:27 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63964 ; free virtual = 67402 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 166000e1b Time (s): cpu = 00:04:25 ; elapsed = 00:04:29 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63822 ; free virtual = 67260 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 12f9934a9 Time (s): cpu = 00:04:25 ; elapsed = 00:04:29 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 63723 ; free virtual = 67161 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1d9b3a18d Time (s): cpu = 00:04:49 ; elapsed = 00:04:53 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 61236 ; free virtual = 64676 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 11581d22c Time (s): cpu = 00:05:25 ; elapsed = 00:05:30 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 60001 ; free virtual = 63473 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: d2b62cba Time (s): cpu = 00:05:29 ; elapsed = 00:05:34 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 59654 ; free virtual = 63126 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1dda0a426 Time (s): cpu = 00:05:31 ; elapsed = 00:05:35 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 59561 ; free virtual = 63033 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 132c79e50 Time (s): cpu = 00:06:13 ; elapsed = 00:06:19 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 56813 ; free virtual = 60287 Phase 3 Detail Placement | Checksum: 132c79e50 Time (s): cpu = 00:06:14 ; elapsed = 00:06:19 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 56811 ; free virtual = 60285 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: c6c1fb66 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.439 | TNS=-94.027 | Phase 1 Physical Synthesis Initialization | Checksum: 183aecab7 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 57841 ; free virtual = 61675 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 115698cb1 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 58102 ; free virtual = 61669 Phase 4.1.1.1 BUFG Insertion | Checksum: c6c1fb66 Time (s): cpu = 00:07:02 ; elapsed = 00:07:08 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 58054 ; free virtual = 61621 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.098. For the most accurate timing information please run report_timing. Time (s): cpu = 00:09:43 ; elapsed = 00:09:49 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 54179 ; free virtual = 59379 Phase 4.1 Post Commit Optimization | Checksum: 13afb9eac Time (s): cpu = 00:09:44 ; elapsed = 00:09:49 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 54175 ; free virtual = 59379 Post Placement Optimization Initialization | Checksum: 1942ee10d Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.406 | TNS=-93.004 | Phase 1 Physical Synthesis Initialization | Checksum: 1ca14d9bf Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 54277 ; free virtual = 59197 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 19c706350 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 54304 ; free virtual = 59218 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.055. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 10e356239 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.483 | Phase 1 Physical Synthesis Initialization | Checksum: 105ff41b8 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 54166 ; free virtual = 58875 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1da8c7c83 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 54177 ; free virtual = 58872 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.055. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 132d82844 Time (s): cpu = 00:16:57 ; elapsed = 00:17:03 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53880 ; free virtual = 58627 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 2x2| 2x2| |___________|___________________|___________________| | East| 2x2| 4x4| |___________|___________________|___________________| | West| 2x2| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 132d82844 Time (s): cpu = 00:16:58 ; elapsed = 00:17:04 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53860 ; free virtual = 58637 Phase 4.3 Placer Reporting | Checksum: 132d82844 Time (s): cpu = 00:16:59 ; elapsed = 00:17:05 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53833 ; free virtual = 58604 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53838 ; free virtual = 58609 Time (s): cpu = 00:16:59 ; elapsed = 00:17:05 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53838 ; free virtual = 58609 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1746c87d7 Time (s): cpu = 00:17:00 ; elapsed = 00:17:06 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53826 ; free virtual = 58597 Ending Placer Task | Checksum: 14ecba618 Time (s): cpu = 00:17:00 ; elapsed = 00:17:06 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53801 ; free virtual = 58572 INFO: [Common 17-83] Releasing license: Implementation 194 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:17:07 ; elapsed = 00:17:13 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53873 ; free virtual = 58644 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52986 ; free virtual = 58274 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52946 ; free virtual = 58220 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.47 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52902 ; free virtual = 58176 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.66 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52900 ; free virtual = 58176 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52358 ; free virtual = 57711 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.483 | Phase 1 Physical Synthesis Initialization | Checksum: 170492a51 Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51456 ; free virtual = 57109 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.483 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 170492a51 Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51441 ; free virtual = 57094 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.483 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[18]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[18] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.469 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[19]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[19] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[19]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.455 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[1]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[1] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.441 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[29]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[29] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[29]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.427 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[30]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[30] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[30]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.420 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[32]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[32] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[32]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.413 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[38]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[38] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[38]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.055 | TNS=-4.406 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[40]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[40] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[40]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.053 | TNS=-4.397 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[45]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[45] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[45]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.053 | TNS=-4.445 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[6]. Did not re-place instance GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[6] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[6]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/Running. Did not re-place instance GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/fifo_proc.Running_i_1__22 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data[63]_i_1__8_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data[63]_i_1__8_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/Running. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.051 | TNS=-4.237 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/in_valid_reg. Re-placed instance GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/in_valid_reg_reg INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/in_valid_reg. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.049 | TNS=-4.185 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[45]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[45] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_fifo/out_data_reg[63]_0[45]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.048 | TNS=-4.136 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[0]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[0] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__1 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.dout_valid_i_2__10_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.dout_valid_i_2__10 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.dout_valid_i_2__10_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/packet_valid_bus_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/src[3]_i_4 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/packet_valid_bus_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/active2__5. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/round_robin[3]_i_4 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/active2__5. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/round_robin[3]_i_7_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/round_robin[3]_i_7 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/round_robin[3]_i_7_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[64]_i_1__4_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[64]_i_1__4 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[64]_i_1__4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_A/mux_valid_A_reg_bus[0]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_A/out_valid_reg INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[2].MUX_register_A/mux_valid_A_reg_bus[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.046 | TNS=-2.340 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_B/Q[31]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_B/out_data_reg[31] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].TOB_register_B/Q[31]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.043 | TNS=-2.293 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/tob_packet_source_sig[0]. Re-placed instance GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/src_reg[0] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_A/TOB_merger/tob_packet_source_sig[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.041 | TNS=-2.250 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/write_block14_in. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/i__carry_i_2_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/write_block2[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/write_block2__0_carry_i_6_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.041 | TNS=-2.170 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3__1_n_0. Re-placed instance GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3__1 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3__1_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.040 | TNS=-2.154 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/out_data_reg[63]_0[15]. Did not re-place instance GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/out_data_reg[15] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/out_data_reg[63]_0[15]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/Fatal. Did not re-place instance GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/fifo_proc.last_i_2__14 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/Fatal. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/Watchdog[4]. Did not re-place instance GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/fifo_proc.Watchdog[4]_i_1__31 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/Watchdog[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/fifo_proc.Watchdog[4]_i_2__20_n_0. Re-placed instance GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/fifo_proc.Watchdog[4]_i_2__20 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_fifo_A/fifo_proc.Watchdog[4]_i_2__20_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-2.005 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3__1_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3__1 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_i_3__1_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/write_block14_in. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/MGT_receiver/i__carry_i_2__4_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.973 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[45]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[45] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[45]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.940 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.940 | Phase 3 Critical Path Optimization | Checksum: 170492a51 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51264 ; free virtual = 56914 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.940 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[52]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[52] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[52]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-1.908 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[9]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[9] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[9]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.876 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[12]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[12] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.848 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[14]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[14] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[14]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.820 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[1]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[1] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.792 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[5]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[5] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.764 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[6]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[6] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.736 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[8]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[8] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[8]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-1.708 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[9]. Re-placed instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data_reg[9] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/prefetched_data[9]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.680 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[13]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[13] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[13]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.650 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[18]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[18] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.621 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[28]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.591 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[39]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[39] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[39]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.562 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[46]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[46] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[46]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.533 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[48]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[48] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[48]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.503 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[4]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[4] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-1.474 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[56]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[56] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[56]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.444 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i. Did not re-place instance GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg INFO: [Physopt 32-702] Processed net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/comp2. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net GOLDEN_IF.hub1_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/v1_reg_0[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.438 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[27]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[27] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[27]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.410 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[30]. Re-placed instance GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data_reg[30] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].TOB_register_A/middle_data[30]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.382 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.028 | TNS=-1.382 | Phase 4 Critical Path Optimization | Checksum: 170492a51 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51218 ; free virtual = 56868 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51221 ; free virtual = 56871 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.028 | TNS=-1.382 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.027 | 3.102 | 0 | 0 | 40 | 0 | 2 | 00:00:07 | | Total | 0.027 | 3.102 | 0 | 0 | 40 | 0 | 3 | 00:00:07 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51237 ; free virtual = 56877 Ending Physical Synthesis Task | Checksum: 1800c62a6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51244 ; free virtual = 56883 INFO: [Common 17-83] Releasing license: Implementation 370 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51298 ; free virtual = 56941 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50668 ; free virtual = 56628 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:41 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50852 ; free virtual = 56702 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 8e14e350 ConstDB: 0 ShapeSum: 25a1a9ee RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 105da87e5 Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50537 ; free virtual = 56403 Post Restoration Checksum: NetGraph: d64182fb NumContArr: 2f9904ea Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 105da87e5 Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50551 ; free virtual = 56417 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 105da87e5 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50528 ; free virtual = 56389 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 105da87e5 Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50543 ; free virtual = 56404 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 2212f8f31 Time (s): cpu = 00:01:47 ; elapsed = 00:01:48 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50675 ; free virtual = 56304 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.032 | TNS=-0.253 | WHS=-2.778 | THS=-5763.160| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1e12f1be3 Time (s): cpu = 00:02:19 ; elapsed = 00:02:20 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50663 ; free virtual = 56257 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.032 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 2027dc151 Time (s): cpu = 00:02:20 ; elapsed = 00:02:21 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50663 ; free virtual = 56257 Phase 2 Router Initialization | Checksum: 207fd5765 Time (s): cpu = 00:02:20 ; elapsed = 00:02:21 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50663 ; free virtual = 56257 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 101874 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 101872 Number of Partially Routed Nets = 2 Number of Node Overlaps = 1 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 207fd5765 Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 50662 ; free virtual = 56255 Phase 3 Initial Routing | Checksum: 222828122 Time (s): cpu = 00:05:33 ; elapsed = 00:05:37 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 49706 ; free virtual = 55750 INFO: [Route 35-580] Design has 26 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[3]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[2]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[3]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 9429 Number of Nodes with overlaps = 1483 Number of Nodes with overlaps = 522 Number of Nodes with overlaps = 192 Number of Nodes with overlaps = 74 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.070 | TNS=-0.244 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 24621f615 Time (s): cpu = 00:07:46 ; elapsed = 00:07:51 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 51901 ; free virtual = 57859 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1059 Number of Nodes with overlaps = 167 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.048 | TNS=-0.343 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 8641802b Time (s): cpu = 00:08:19 ; elapsed = 00:08:24 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53056 ; free virtual = 58972 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 768 Number of Nodes with overlaps = 80 Number of Nodes with overlaps = 57 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.048 | TNS=-0.102 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 125dc6aad Time (s): cpu = 00:08:43 ; elapsed = 00:08:49 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53065 ; free virtual = 59070 Phase 4 Rip-up And Reroute | Checksum: 125dc6aad Time (s): cpu = 00:08:43 ; elapsed = 00:08:49 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53054 ; free virtual = 59070 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1c525492d Time (s): cpu = 00:08:54 ; elapsed = 00:08:59 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52419 ; free virtual = 58839 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.024 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 1836ab305 Time (s): cpu = 00:08:54 ; elapsed = 00:09:00 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52365 ; free virtual = 58802 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1836ab305 Time (s): cpu = 00:08:54 ; elapsed = 00:09:00 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52353 ; free virtual = 58801 Phase 5 Delay and Skew Optimization | Checksum: 1836ab305 Time (s): cpu = 00:08:55 ; elapsed = 00:09:00 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52341 ; free virtual = 58800 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 17a61cf75 Time (s): cpu = 00:09:07 ; elapsed = 00:09:13 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52185 ; free virtual = 58758 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.024 | TNS=0.000 | WHS=-1.171 | THS=-23.211| Phase 6.1 Hold Fix Iter | Checksum: 1bbe82b71 Time (s): cpu = 00:09:08 ; elapsed = 00:09:14 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52183 ; free virtual = 58757 Phase 6 Post Hold Fix | Checksum: 176bda0a6 Time (s): cpu = 00:09:08 ; elapsed = 00:09:14 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52183 ; free virtual = 58756 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 2228781ee Time (s): cpu = 00:09:24 ; elapsed = 00:09:30 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52156 ; free virtual = 58737 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.024 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 2228781ee Time (s): cpu = 00:09:25 ; elapsed = 00:09:30 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52156 ; free virtual = 58737 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 9.25917 % Global Horizontal Routing Utilization = 10.3204 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 2228781ee Time (s): cpu = 00:09:26 ; elapsed = 00:09:31 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52154 ; free virtual = 58736 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 2228781ee Time (s): cpu = 00:09:26 ; elapsed = 00:09:32 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52152 ; free virtual = 58734 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 157a5cce5 Time (s): cpu = 00:09:34 ; elapsed = 00:09:40 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 52139 ; free virtual = 58727 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.024 | TNS=0.000 | WHS=0.051 | THS=0.000 | Phase 11 Post Router Timing | Checksum: 154b7ec90 Time (s): cpu = 00:10:14 ; elapsed = 00:10:20 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53249 ; free virtual = 59931 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+-------+-------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 1 | 0.024 | 0.000 | -1.171 | - | Pass | 00:08:51 | x | +------+-------+-------+--------+-----+--------+--------------+-------------------+ | 2 | - | - | - | - | Fail | 00:00:00 | | +------+-------+-------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:10:14 ; elapsed = 00:10:20 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53443 ; free virtual = 60143 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 394 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:10:56 ; elapsed = 00:11:02 . Memory (MB): peak = 4789.234 ; gain = 0.000 ; free physical = 53442 ; free virtual = 60143 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.6-CBB604B INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value cbb604b will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.6-CBB604B INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/2/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.6.6-CBB604B... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.