*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.dcp' for cell 'GLOBAL_MERGE.IO_DELAY_A1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.dcp' for cell 'GLOBAL_MERGE.IO_DELAY_BC_A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM.dcp' for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_1/ALGO_OUTPUT_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_209b_512/DPR_209b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U4_T_TOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_1.dcp' for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3421.656 ; gain = 29.988 ; free physical = 63838 ; free virtual = 68889 INFO: [Netlist 29-17] Analyzing 30204 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Chipscope 16-324] Core: READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity UUID: d422f308-f24a-5302-b8c8-8392916aaf97 Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/efex_control.gen/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'READOUT_IF.Readout_block/U17_bcn_l1a_valid_checker/debug_bcn_l1a_parity/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] get_clocks: Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 5252.441 ; gain = 1073.512 ; free physical = 59205 ; free virtual = 64256 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 5710.113 ; gain = 457.672 ; free physical = 58724 ; free virtual = 63775 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249370 which will be rounded to 0.249 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] create_generated_clock: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 5854.113 ; gain = 144.000 ; free physical = 58576 ; free virtual = 63627 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] create_generated_clock: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 6068.113 ; gain = 214.000 ; free physical = 58355 ; free virtual = 63407 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga2.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga2.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga2.xdc] get_pins: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7187.043 ; gain = 1110.930 ; free physical = 57299 ; free virtual = 62350 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga2.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga2.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga2.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.gen/sources_1/ip/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1715] 4 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 7251.047 ; gain = 0.000 ; free physical = 60137 ; free virtual = 65188 INFO: [Project 1-111] Unisim Transformation Summary: A total of 114 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 48 instances OBUFDS => OBUFDS: 66 instances 32 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:05:43 ; elapsed = 00:05:35 . Memory (MB): peak = 7251.047 ; gain = 4747.188 ; free physical = 60179 ; free virtual = 65230 source /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 7267.055 ; gain = 8.004 ; free physical = 59854 ; free virtual = 64905 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 2bedceabe Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 57989 ; free virtual = 63059 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 58707 ; free virtual = 63765 Netlist sorting complete. Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.43 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 58707 ; free virtual = 63765 Phase 1 Generate And Synthesize Debug Cores | Checksum: 1d0f01ddf Time (s): cpu = 00:02:17 ; elapsed = 00:02:55 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 58706 ; free virtual = 63764 Phase 2 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 155f5db16 Time (s): cpu = 00:02:45 ; elapsed = 00:03:24 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 59283 ; free virtual = 64341 INFO: [Opt 31-389] Phase Retarget created 169 cells and removed 559 cells INFO: [Opt 31-1021] In phase Retarget, 289 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 19183bc7d Time (s): cpu = 00:02:49 ; elapsed = 00:03:28 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 59287 ; free virtual = 64346 INFO: [Opt 31-389] Phase Constant propagation created 54 cells and removed 266 cells INFO: [Opt 31-1021] In phase Constant propagation, 205 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 167a2257f Time (s): cpu = 00:03:04 ; elapsed = 00:03:43 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 59227 ; free virtual = 64285 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3589 cells INFO: [Opt 31-1021] In phase Sweep, 1805 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 1cc4e0ac0 Time (s): cpu = 00:03:13 ; elapsed = 00:03:52 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 58664 ; free virtual = 63723 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1d9a38ab3 Time (s): cpu = 00:03:15 ; elapsed = 00:03:53 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 58609 ; free virtual = 63667 INFO: [Opt 31-389] Phase Shift Register Optimization created 64 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 1b99b6d38 Time (s): cpu = 00:03:17 ; elapsed = 00:03:55 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 58517 ; free virtual = 63576 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 359 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 169 | 559 | 289 | | Constant propagation | 54 | 266 | 205 | | Sweep | 0 | 3589 | 1805 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 64 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 359 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 57610 ; free virtual = 62669 Ending Logic Optimization Task | Checksum: 28290daa5 Time (s): cpu = 00:03:32 ; elapsed = 00:04:10 . Memory (MB): peak = 7267.055 ; gain = 0.000 ; free physical = 57600 ; free virtual = 62658 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 800 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 98 newly gated: 189 Total Ports: 1600 Ending PowerOpt Patch Enables Task | Checksum: 1dda1f17c Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 10144.805 ; gain = 0.000 ; free physical = 57394 ; free virtual = 62452 Ending Power Optimization Task | Checksum: 1dda1f17c Time (s): cpu = 00:04:17 ; elapsed = 00:03:42 . Memory (MB): peak = 10144.805 ; gain = 2877.750 ; free physical = 57785 ; free virtual = 62844 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1e9267a78 Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 10144.805 ; gain = 0.000 ; free physical = 57083 ; free virtual = 62142 Ending Final Cleanup Task | Checksum: 1e9267a78 Time (s): cpu = 00:01:06 ; elapsed = 00:01:07 . Memory (MB): peak = 10144.805 ; gain = 0.000 ; free physical = 56715 ; free virtual = 61773 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10144.805 ; gain = 0.000 ; free physical = 56717 ; free virtual = 61775 Ending Netlist Obfuscation Task | Checksum: 1e9267a78 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10144.805 ; gain = 0.000 ; free physical = 56717 ; free virtual = 61775 INFO: [Common 17-83] Releasing license: Implementation 71 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:09:41 ; elapsed = 00:09:47 . Memory (MB): peak = 10144.805 ; gain = 2893.758 ; free physical = 56718 ; free virtual = 61777 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 10144.805 ; gain = 0.000 ; free physical = 54945 ; free virtual = 60546 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:09:59 ; elapsed = 00:10:20 . Memory (MB): peak = 10144.809 ; gain = 0.004 ; free physical = 55243 ; free virtual = 60561 INFO: [runtcl-4] Executing : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:57 ; elapsed = 00:01:59 . Memory (MB): peak = 10144.809 ; gain = 0.000 ; free physical = 54612 ; free virtual = 59929 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[5] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[0]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[6] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[1]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[7] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[2]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[3]) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/addr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has an input control pin MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/ENBWREN (net: MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/enb) which is driven by a register (MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/sm_playback/en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[10] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[9]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[11] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[10]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[12] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[11]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[13] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[12]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[1] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[0]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[2] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[1]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[3] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[2]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[4] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[3]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[5] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[4]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[6] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[5]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[7] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[6]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[8] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[7]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRARDADDR[9] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/Q[8]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[10] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[9]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[11] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[10]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[12] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[11]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[13] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[12]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[7] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[6]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[8] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[7]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ADDRBWRADDR[9] (net: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_2[8]) which is driven by a register (READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 10144.809 ; gain = 0.000 ; free physical = 54604 ; free virtual = 59921 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cb84dcb2 Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 10144.809 ; gain = 0.000 ; free physical = 54603 ; free virtual = 59920 Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 10144.809 ; gain = 0.000 ; free physical = 54603 ; free virtual = 59920 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 117c15f7f Time (s): cpu = 00:21:02 ; elapsed = 00:28:15 . Memory (MB): peak = 34377.805 ; gain = 24232.996 ; free physical = 3305 ; free virtual = 8623 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 106bbc8d2 Time (s): cpu = 00:22:50 ; elapsed = 00:30:04 . Memory (MB): peak = 35587.781 ; gain = 25442.973 ; free physical = 2338 ; free virtual = 7656 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 106bbc8d2 Time (s): cpu = 00:22:51 ; elapsed = 00:30:06 . Memory (MB): peak = 35587.781 ; gain = 25442.973 ; free physical = 2431 ; free virtual = 7749 Phase 1 Placer Initialization | Checksum: 106bbc8d2 Time (s): cpu = 00:22:53 ; elapsed = 00:30:07 . Memory (MB): peak = 35587.781 ; gain = 25442.973 ; free physical = 2413 ; free virtual = 7731 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1935de448 Time (s): cpu = 00:23:27 ; elapsed = 00:30:42 . Memory (MB): peak = 35587.781 ; gain = 25442.973 ; free physical = 1943 ; free virtual = 7262 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 16917f172 Time (s): cpu = 00:23:56 ; elapsed = 00:31:11 . Memory (MB): peak = 35587.781 ; gain = 25442.973 ; free physical = 1872 ; free virtual = 7191 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 61 LUTNM shape to break, 12814 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 36, two critical 25, total 61, new lutff created 6 INFO: [Physopt 32-775] End 1 Pass. Optimized 6048 nets or cells. Created 61 new cells, deleted 5987 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 4 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_hdr_BCN_in_i. Replicated 20 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/IN_Load. Replicated 74 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 64 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start. Replicated 34 times. INFO: [Physopt 32-232] Optimized 4 nets. Created 192 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 192 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 35626.234 ; gain = 0.000 ; free physical = 2062 ; free virtual = 7380 INFO: [Physopt 32-76] Pass 1. Identified 11 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/enb. Replicated 9 times. INFO: [Physopt 32-232] Optimized 11 nets. Created 99 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 99 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.57 . Memory (MB): peak = 35626.234 ; gain = 0.000 ; free physical = 2063 ; free virtual = 7381 INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/enb_array[0] could not be optimized because driver READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/bindec_b.bindec_inst_b/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/tmp_ram_rd_en could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-117] Net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I could not be optimized because driver READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 could not be replicated INFO: [Physopt 32-46] Identified 20 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[2]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[6]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[4]. Replicated 1 times. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[4]_rep_n_0 was not replicated. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[9]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[8]. Replicated 1 times. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[3] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[5] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[8]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[9]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[0]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_ParameterRAMaddress[1] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[5]_rep_n_0 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[6]_rep_n_0 was not replicated. INFO: [Physopt 32-232] Optimized 8 nets. Created 8 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 8 nets or cells. Created 8 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.47 . Memory (MB): peak = 35626.234 ; gain = 0.000 ; free physical = 2080 ; free virtual = 7399 INFO: [Physopt 32-457] Pass 1. Identified 1 candidate cell for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 1 net or cell. Created 24 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 35626.234 ; gain = 0.000 ; free physical = 2036 ; free virtual = 7354 INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 34 nets or cells. Created 55 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.40 . Memory (MB): peak = 35626.234 ; gain = 0.000 ; free physical = 1802 ; free virtual = 7121 INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 35626.234 ; gain = 0.000 ; free physical = 1771 ; free virtual = 7089 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 61 | 5987 | 6048 | 0 | 1 | 00:00:13 | | Very High Fanout | 192 | 0 | 4 | 0 | 1 | 00:00:14 | | Fanout | 99 | 0 | 11 | 0 | 1 | 00:00:01 | | Critical Cell | 8 | 0 | 8 | 0 | 1 | 00:00:01 | | DSP Register | 24 | 0 | 1 | 0 | 1 | 00:00:01 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 55 | 0 | 34 | 0 | 1 | 00:00:01 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 439 | 5987 | 6106 | 0 | 10 | 00:00:32 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 16cc3a2ea Time (s): cpu = 00:30:45 ; elapsed = 00:38:12 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 2085 ; free virtual = 7403 Phase 2.3 Global Placement Core | Checksum: 1eae2970c Time (s): cpu = 00:31:02 ; elapsed = 00:38:29 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 2208 ; free virtual = 7526 Phase 2 Global Placement | Checksum: 1eae2970c Time (s): cpu = 00:31:02 ; elapsed = 00:38:29 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 2355 ; free virtual = 7673 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2208a7844 Time (s): cpu = 00:31:37 ; elapsed = 00:39:05 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 2077 ; free virtual = 7396 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17a571d9d Time (s): cpu = 00:32:55 ; elapsed = 00:40:22 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 2120 ; free virtual = 7439 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 16b44998c Time (s): cpu = 00:33:01 ; elapsed = 00:40:29 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 1715 ; free virtual = 7033 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b0467246 Time (s): cpu = 00:33:03 ; elapsed = 00:40:31 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 1714 ; free virtual = 7033 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 167b2ffbd Time (s): cpu = 00:34:07 ; elapsed = 00:41:35 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 2075 ; free virtual = 7393 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: f5d7515c Time (s): cpu = 00:37:07 ; elapsed = 00:44:36 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 1392 ; free virtual = 6711 Phase 3.6 Small Shape Detail Placement | Checksum: f5d7515c Time (s): cpu = 00:37:12 ; elapsed = 00:44:41 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 1495 ; free virtual = 6813 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: b6afe070 Time (s): cpu = 00:37:32 ; elapsed = 00:45:01 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 1097 ; free virtual = 6415 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 18a0f7284 Time (s): cpu = 00:37:37 ; elapsed = 00:45:07 . Memory (MB): peak = 35626.234 ; gain = 25481.426 ; free physical = 1093 ; free virtual = 6412 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 16b62b945 Time (s): cpu = 00:39:38 ; elapsed = 00:47:09 . Memory (MB): peak = 35639.492 ; gain = 25494.684 ; free physical = 2185 ; free virtual = 7504 Phase 3 Detail Placement | Checksum: 16b62b945 Time (s): cpu = 00:39:41 ; elapsed = 00:47:12 . Memory (MB): peak = 35639.492 ; gain = 25494.684 ; free physical = 1933 ; free virtual = 7251 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1914f3b73 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.685 | TNS=-12.520 | Phase 1 Physical Synthesis Initialization | Checksum: 1bf7bfc23 Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 35761.527 ; gain = 41.469 ; free physical = 442 ; free virtual = 5709 INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 195a1c5e0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 35783.531 ; gain = 63.473 ; free physical = 503 ; free virtual = 5735 Phase 4.1.1.1 BUFG Insertion | Checksum: 1914f3b73 Time (s): cpu = 00:42:45 ; elapsed = 00:50:17 . Memory (MB): peak = 35783.531 ; gain = 25638.723 ; free physical = 521 ; free virtual = 5752 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.019. For the most accurate timing information please run report_timing. Time (s): cpu = 00:49:02 ; elapsed = 00:56:35 . Memory (MB): peak = 35851.531 ; gain = 25706.723 ; free physical = 752 ; free virtual = 5767 Phase 4.1 Post Commit Optimization | Checksum: 17f7340d1 Time (s): cpu = 00:49:05 ; elapsed = 00:56:38 . Memory (MB): peak = 35851.531 ; gain = 25706.723 ; free physical = 750 ; free virtual = 5765 Post Placement Optimization Initialization | Checksum: 182a77ddc Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-2.574 | Phase 1 Physical Synthesis Initialization | Checksum: 176bcaabc Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 36073.805 ; gain = 0.000 ; free physical = 881 ; free virtual = 5868 INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1cfb959b0 Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 36073.805 ; gain = 0.000 ; free physical = 936 ; free virtual = 5924 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.078. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1b202fa59 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.078 | TNS=-0.078 | Phase 1 Physical Synthesis Initialization | Checksum: 198f463aa Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 36073.805 ; gain = 0.000 ; free physical = 900 ; free virtual = 5887 INFO: [Place 46-33] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_RAW_fsm/U2_rd_addr/RAW_FIFO_sw_rst_i_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/RESET_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 4 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 4, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1dcdd1d3f Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 36073.805 ; gain = 0.000 ; free physical = 905 ; free virtual = 5892 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.078. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1245b3bea Time (s): cpu = 01:05:01 ; elapsed = 01:12:36 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1318 ; free virtual = 6230 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 32x32| 8x8| |___________|___________________|___________________| | South| 8x8| 4x4| |___________|___________________|___________________| | East| 4x4| 4x4| |___________|___________________|___________________| | West| 4x4| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1245b3bea Time (s): cpu = 01:05:05 ; elapsed = 01:12:40 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1321 ; free virtual = 6232 Phase 4.3 Placer Reporting | Checksum: 1245b3bea Time (s): cpu = 01:05:08 ; elapsed = 01:12:43 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1321 ; free virtual = 6232 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 36073.805 ; gain = 0.000 ; free physical = 1329 ; free virtual = 6240 Time (s): cpu = 01:05:09 ; elapsed = 01:12:44 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1329 ; free virtual = 6240 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1126dee15 Time (s): cpu = 01:05:12 ; elapsed = 01:12:47 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1318 ; free virtual = 6230 Ending Placer Task | Checksum: b0f13aaf Time (s): cpu = 01:05:12 ; elapsed = 01:12:47 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1304 ; free virtual = 6215 INFO: [Common 17-83] Releasing license: Implementation 180 Infos, 50 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 01:05:59 ; elapsed = 01:13:35 . Memory (MB): peak = 36073.805 ; gain = 25928.996 ; free physical = 1644 ; free virtual = 6555 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 36073.805 ; gain = 0.000 ; free physical = 595 ; free virtual = 6204 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:43 ; elapsed = 00:02:58 . Memory (MB): peak = 36073.809 ; gain = 0.004 ; free physical = 1334 ; free virtual = 6183 INFO: [runtcl-4] Executing : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.49 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1291 ; free virtual = 6141 INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1339 ; free virtual = 6192 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1057 ; free virtual = 6270 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.078 | TNS=-0.078 | Phase 1 Physical Synthesis Initialization | Checksum: 1fa886f8d Time (s): cpu = 00:02:08 ; elapsed = 00:02:09 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1220 ; free virtual = 6250 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.078 | TNS=-0.078 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 1fa886f8d Time (s): cpu = 00:02:16 ; elapsed = 00:02:17 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1184 ; free virtual = 6214 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.078 | TNS=-0.078 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/in15[30]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_2_n_0. Did not re-place instance READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_2 INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_1_n_0. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_2_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.020 | TNS=-0.020 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_2_n_0. Re-placed instance READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_2_comp_1 INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/rec_err_flg_4b_i[2]_i_2_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | Phase 3 Critical Path Optimization | Checksum: 1fa886f8d Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1168 ; free virtual = 6202 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | Phase 4 Critical Path Optimization | Checksum: 1fa886f8d Time (s): cpu = 00:02:21 ; elapsed = 00:02:22 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1168 ; free virtual = 6202 Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1187 ; free virtual = 6221 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.008 | TNS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:06 | | Critical Path | 0.086 | 0.078 | 0 | 0 | 2 | 0 | 2 | 00:00:05 | | Total | 0.086 | 0.078 | 0 | 0 | 2 | 0 | 3 | 00:00:11 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1184 ; free virtual = 6218 Ending Physical Synthesis Task | Checksum: 1f6147032 Time (s): cpu = 00:02:23 ; elapsed = 00:02:24 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1172 ; free virtual = 6206 INFO: [Common 17-83] Releasing license: Implementation 209 Infos, 50 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:04:36 ; elapsed = 00:04:37 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1452 ; free virtual = 6485 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 594 ; free virtual = 5741 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:42 ; elapsed = 00:02:57 . Memory (MB): peak = 36073.809 ; gain = 0.000 ; free physical = 1310 ; free virtual = 5759 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2023.11' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: 24d3dc0e ConstDB: 0 ShapeSum: ec55a495 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1d7eb934 Time (s): cpu = 00:01:52 ; elapsed = 00:01:53 . Memory (MB): peak = 36117.875 ; gain = 0.000 ; free physical = 959 ; free virtual = 5241 Post Restoration Checksum: NetGraph: d198a38 NumContArr: 10652efc Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 1d7eb934 Time (s): cpu = 00:01:57 ; elapsed = 00:01:57 . Memory (MB): peak = 36117.875 ; gain = 0.000 ; free physical = 854 ; free virtual = 5136 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 1d7eb934 Time (s): cpu = 00:02:00 ; elapsed = 00:02:00 . Memory (MB): peak = 36117.875 ; gain = 0.000 ; free physical = 810 ; free virtual = 5092 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 1d7eb934 Time (s): cpu = 00:02:00 ; elapsed = 00:02:01 . Memory (MB): peak = 36117.875 ; gain = 0.000 ; free physical = 801 ; free virtual = 5083 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 16eb96be0 Time (s): cpu = 00:05:12 ; elapsed = 00:05:15 . Memory (MB): peak = 36379.875 ; gain = 262.000 ; free physical = 911 ; free virtual = 5170 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.140 | TNS=-0.932 | WHS=-0.484 | THS=-11628.605| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1d48ba1df Time (s): cpu = 00:07:11 ; elapsed = 00:07:15 . Memory (MB): peak = 36379.875 ; gain = 262.000 ; free physical = 847 ; free virtual = 5106 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.140 | TNS=-0.351 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 160e23ddf Time (s): cpu = 00:07:12 ; elapsed = 00:07:16 . Memory (MB): peak = 36379.875 ; gain = 262.000 ; free physical = 841 ; free virtual = 5100 Phase 2 Router Initialization | Checksum: 18ca64e82 Time (s): cpu = 00:07:13 ; elapsed = 00:07:17 . Memory (MB): peak = 36379.875 ; gain = 262.000 ; free physical = 841 ; free virtual = 5100 Router Utilization Summary Global Vertical Routing Utilization = 1.80662e-05 % Global Horizontal Routing Utilization = 9.83014e-06 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 402490 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 402488 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 18ca64e82 Time (s): cpu = 00:07:17 ; elapsed = 00:07:21 . Memory (MB): peak = 36379.875 ; gain = 262.000 ; free physical = 836 ; free virtual = 5095 Phase 3 Initial Routing | Checksum: fa8d89df Time (s): cpu = 00:11:03 ; elapsed = 00:11:10 . Memory (MB): peak = 36379.875 ; gain = 262.000 ; free physical = 731 ; free virtual = 5009 INFO: [Route 35-580] Design has 2 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk280 | clk40 |READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[28]| | clk40 | clk200 |DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/column_for[0].row_for[6].layer2_for[2].EnergyConverter2/ENCODING_IF.special_reg[0]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 36696 Number of Nodes with overlaps = 3691 Number of Nodes with overlaps = 768 Number of Nodes with overlaps = 191 Number of Nodes with overlaps = 57 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.141 | TNS=-0.678 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1e2b53239 Time (s): cpu = 00:24:04 ; elapsed = 00:24:19 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 877 ; free virtual = 5004 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1282 Number of Nodes with overlaps = 196 Number of Nodes with overlaps = 99 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.177 | TNS=-0.798 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1d8bb3760 Time (s): cpu = 00:25:28 ; elapsed = 00:25:45 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 809 ; free virtual = 4936 Phase 4 Rip-up And Reroute | Checksum: 1d8bb3760 Time (s): cpu = 00:25:29 ; elapsed = 00:25:46 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 809 ; free virtual = 4936 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1dca7ac99 Time (s): cpu = 00:26:09 ; elapsed = 00:26:26 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 599 ; free virtual = 4729 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.096 | TNS=-0.203 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 1f8335e6f Time (s): cpu = 00:26:15 ; elapsed = 00:26:32 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 580 ; free virtual = 4712 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1f8335e6f Time (s): cpu = 00:26:16 ; elapsed = 00:26:33 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 545 ; free virtual = 4677 Phase 5 Delay and Skew Optimization | Checksum: 1f8335e6f Time (s): cpu = 00:26:17 ; elapsed = 00:26:34 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 518 ; free virtual = 4650 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1dbaa7334 Time (s): cpu = 00:27:03 ; elapsed = 00:27:20 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 34843 ; free virtual = 39161 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.096 | TNS=-0.203 | WHS=-0.051 | THS=-0.051 | Phase 6.1 Hold Fix Iter | Checksum: 197781012 Time (s): cpu = 00:27:06 ; elapsed = 00:27:22 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35661 ; free virtual = 40040 Phase 6 Post Hold Fix | Checksum: 207533b5c Time (s): cpu = 00:27:07 ; elapsed = 00:27:24 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35661 ; free virtual = 40040 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 171d6b7a2 Time (s): cpu = 00:28:08 ; elapsed = 00:28:25 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35663 ; free virtual = 40041 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.096 | TNS=-0.203 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 171d6b7a2 Time (s): cpu = 00:28:10 ; elapsed = 00:28:27 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35663 ; free virtual = 40041 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 28.5767 % Global Horizontal Routing Utilization = 25.6185 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 4x4 Area, Max Cong = 89.4144%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X124Y100 -> INT_R_X127Y103 South Dir 2x2 Area, Max Cong = 91.2162%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X136Y298 -> INT_R_X137Y299 INT_L_X144Y260 -> INT_R_X145Y261 INT_L_X126Y246 -> INT_R_X127Y247 INT_L_X140Y222 -> INT_R_X141Y223 INT_L_X140Y220 -> INT_R_X141Y221 East Dir 1x1 Area, Max Cong = 100%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X131Y357 -> INT_R_X131Y357 INT_L_X88Y345 -> INT_L_X88Y345 INT_R_X123Y344 -> INT_R_X123Y344 INT_R_X91Y343 -> INT_R_X91Y343 INT_R_X81Y341 -> INT_R_X81Y341 West Dir 2x2 Area, Max Cong = 89.3382%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X138Y308 -> INT_R_X139Y309 INT_L_X138Y304 -> INT_R_X139Y305 INT_L_X86Y300 -> INT_R_X87Y301 INT_L_X90Y298 -> INT_R_X91Y299 INT_L_X126Y196 -> INT_R_X127Y197 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 2 Effective congestion level: 3 Aspect Ratio: 0.666667 Sparse Ratio: 1.25 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 0.857143 Sparse Ratio: 3.3125 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.333333 Sparse Ratio: 0.75 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 0.428571 Sparse Ratio: 0.8125 Phase 8 Route finalize | Checksum: 171d6b7a2 Time (s): cpu = 00:28:13 ; elapsed = 00:28:30 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35659 ; free virtual = 40037 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 171d6b7a2 Time (s): cpu = 00:28:14 ; elapsed = 00:28:31 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35655 ; free virtual = 40033 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 186330f88 Time (s): cpu = 00:28:46 ; elapsed = 00:29:03 . Memory (MB): peak = 36424.281 ; gain = 306.406 ; free physical = 35622 ; free virtual = 40001 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 36424.281 ; gain = 0.000 ; free physical = 35363 ; free virtual = 39741 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.029. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 7deca9a9 Time (s): cpu = 00:05:51 ; elapsed = 00:05:54 . Memory (MB): peak = 37225.102 ; gain = 800.820 ; free physical = 35291 ; free virtual = 39670 Phase 11 Incr Placement Change | Checksum: 186330f88 Time (s): cpu = 00:34:47 ; elapsed = 00:35:08 . Memory (MB): peak = 37227.176 ; gain = 1109.301 ; free physical = 35291 ; free virtual = 39670 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: ec67f516 Time (s): cpu = 00:35:38 ; elapsed = 00:35:59 . Memory (MB): peak = 37227.176 ; gain = 1109.301 ; free physical = 35119 ; free virtual = 39497 Post Restoration Checksum: NetGraph: c84e49ce NumContArr: b7cc456b Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: 1801a8f39 Time (s): cpu = 00:35:54 ; elapsed = 00:36:14 . Memory (MB): peak = 37227.176 ; gain = 1109.301 ; free physical = 35211 ; free virtual = 39589 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: 1801a8f39 Time (s): cpu = 00:35:57 ; elapsed = 00:36:18 . Memory (MB): peak = 37227.176 ; gain = 1109.301 ; free physical = 35184 ; free virtual = 39562 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: b4e77be1 Time (s): cpu = 00:35:59 ; elapsed = 00:36:20 . Memory (MB): peak = 37227.176 ; gain = 1109.301 ; free physical = 35184 ; free virtual = 39562 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: 18920ae10 Time (s): cpu = 00:39:24 ; elapsed = 00:39:46 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34872 ; free virtual = 39251 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.034 | TNS=-0.153 | WHS=-0.484 | THS=-11553.746| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 171ec4729 Time (s): cpu = 00:41:20 ; elapsed = 00:41:43 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34791 ; free virtual = 39169 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.034 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: 20a5c66b5 Time (s): cpu = 00:41:22 ; elapsed = 00:41:45 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34785 ; free virtual = 39163 Phase 13 Router Initialization | Checksum: 1c1300c6a Time (s): cpu = 00:41:24 ; elapsed = 00:41:47 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34814 ; free virtual = 39192 Router Utilization Summary Global Vertical Routing Utilization = 28.5482 % Global Horizontal Routing Utilization = 25.5922 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 502 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 358 Number of Partially Routed Nets = 144 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14.1 Global Routing Phase 14.1 Global Routing | Checksum: 1c1300c6a Time (s): cpu = 00:41:28 ; elapsed = 00:41:51 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34837 ; free virtual = 39215 Phase 14 Initial Routing | Checksum: 1da217a13 Time (s): cpu = 00:41:37 ; elapsed = 00:42:00 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34817 ; free virtual = 39195 INFO: [Route 35-580] Design has 757 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk280 | clk40 |READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[28]| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U2_PISO_RAW/RAW_data_in_i_reg[103]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U2_PISO_RAW/RAW_data_in_i_reg[80]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U2_PISO_RAW/RAW_data_in_i_reg[10]/D| | clk40 | clk280 | READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U2_PISO_RAW/RAW_data_in_i_reg[49]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 1012 Number of Nodes with overlaps = 454 Number of Nodes with overlaps = 214 Number of Nodes with overlaps = 80 Number of Nodes with overlaps = 57 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.034 | TNS=-0.073 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: 1ddbb80f5 Time (s): cpu = 00:44:34 ; elapsed = 00:45:00 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34854 ; free virtual = 39232 Phase 15.2 Global Iteration 1 Number of Nodes with overlaps = 2113 Number of Nodes with overlaps = 686 Number of Nodes with overlaps = 176 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.005 | TNS=-0.005 | WHS=N/A | THS=N/A | Phase 15.2 Global Iteration 1 | Checksum: 1e4d4decb Time (s): cpu = 00:46:58 ; elapsed = 00:47:27 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34853 ; free virtual = 39232 Phase 15.3 Global Iteration 2 Number of Nodes with overlaps = 1490 Number of Nodes with overlaps = 389 Number of Nodes with overlaps = 175 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 53 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.033 | TNS=-0.070 | WHS=N/A | THS=N/A | Phase 15.3 Global Iteration 2 | Checksum: 19d720eb3 Time (s): cpu = 00:49:09 ; elapsed = 00:49:42 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34856 ; free virtual = 39235 Phase 15 Rip-up And Reroute | Checksum: 19d720eb3 Time (s): cpu = 00:49:10 ; elapsed = 00:49:43 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34856 ; free virtual = 39235 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 1a07d8cb0 Time (s): cpu = 00:49:50 ; elapsed = 00:50:23 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34773 ; free virtual = 39152 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.044 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 16.1 Delay CleanUp | Checksum: 1c2ec24c3 Time (s): cpu = 00:49:52 ; elapsed = 00:50:24 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34810 ; free virtual = 39188 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: 1c2ec24c3 Time (s): cpu = 00:49:53 ; elapsed = 00:50:25 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34810 ; free virtual = 39188 Phase 16 Delay and Skew Optimization | Checksum: 1c2ec24c3 Time (s): cpu = 00:49:54 ; elapsed = 00:50:26 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34810 ; free virtual = 39188 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 17eeef9b7 Time (s): cpu = 00:50:39 ; elapsed = 00:51:12 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34830 ; free virtual = 39208 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.044 | TNS=0.000 | WHS=0.050 | THS=0.000 | Phase 17.1 Hold Fix Iter | Checksum: 16523d6a7 Time (s): cpu = 00:50:41 ; elapsed = 00:51:13 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34828 ; free virtual = 39207 Phase 17 Post Hold Fix | Checksum: 16523d6a7 Time (s): cpu = 00:50:42 ; elapsed = 00:51:14 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34828 ; free virtual = 39207 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 13d7d9d35 Time (s): cpu = 00:51:43 ; elapsed = 00:52:16 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34828 ; free virtual = 39207 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.044 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 13d7d9d35 Time (s): cpu = 00:51:44 ; elapsed = 00:52:17 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34828 ; free virtual = 39207 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 28.5991 % Global Horizontal Routing Utilization = 25.6475 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 13d7d9d35 Time (s): cpu = 00:51:47 ; elapsed = 00:52:20 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34824 ; free virtual = 39203 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 13d7d9d35 Time (s): cpu = 00:51:48 ; elapsed = 00:52:22 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34820 ; free virtual = 39199 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: 16d01c3a4 Time (s): cpu = 00:52:19 ; elapsed = 00:52:52 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 34819 ; free virtual = 39197 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.044 | TNS=0.000 | WHS=0.050 | THS=0.000 | Phase 22 Post Router Timing | Checksum: 14d337aa3 Time (s): cpu = 00:54:46 ; elapsed = 00:55:20 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 35078 ; free virtual = 39456 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+--------+--------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 1 | -0.096 | -0.203 | -0.051 | - | Pass | 00:27:09 | | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 2 | 0.044 | 0.000 | 0.050 | - | Pass | 00:16:41 | x | +------+--------+--------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:54:47 ; elapsed = 00:55:20 . Memory (MB): peak = 37300.176 ; gain = 1182.301 ; free physical = 35704 ; free virtual = 40082 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 242 Infos, 50 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:57:29 ; elapsed = 00:58:04 . Memory (MB): peak = 37300.176 ; gain = 1226.367 ; free physical = 35704 ; free virtual = 40083 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.2... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.6-CBB604B INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_processor.2 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] The git SHA value cbb604b will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.2... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] Git describe set to: v1.6.6-CBB604B INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/1/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.2-v1.6.6-CBB604B... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 37300.176 ; gain = 0.000 ; free physical = 33574 ; free virtual = 38009