## efex_processor.2 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    183020   |   0         |    346400        |    52.83     |      
| Slice  Registers |    246577   |   0         |    692800        |    35.59     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    501      |   0         |    600           |    83.50     |      
                                                                                        
## efex_processor.2 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    191018   |     0         |    346400        |    55.14     |       
| Slice  Registers |    273070   |     0         |    692800        |    39.42     |       
| Block  RAM       Tile |        759.5 |         0    |             1180 |         64.36 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    449      |     449       |    600           |    74.83     |