*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2646.102 ; gain = 0.000 ; free physical = 29143 ; free virtual = 51986 INFO: [Netlist 29-17] Analyzing 6766 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 3589.488 ; gain = 655.133 ; free physical = 28606 ; free virtual = 51443 Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3622.488 ; gain = 0.000 ; free physical = 28425 ; free virtual = 51264 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 33 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:13 ; elapsed = 00:01:08 . Memory (MB): peak = 3622.488 ; gain = 1022.949 ; free physical = 28420 ; free virtual = 51258 source /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Parsing TCL File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Parsing TCL File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3630.492 ; gain = 8.004 ; free physical = 43630 ; free virtual = 66255 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 167bf3f06 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3630.492 ; gain = 0.000 ; free physical = 44888 ; free virtual = 67509 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3841.234 ; gain = 0.000 ; free physical = 46384 ; free virtual = 67179 Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3841.234 ; gain = 0.000 ; free physical = 46363 ; free virtual = 67158 Phase 1 Generate And Synthesize Debug Cores | Checksum: 8c39305a Time (s): cpu = 00:02:04 ; elapsed = 00:02:24 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 46361 ; free virtual = 67156 Phase 2 Retarget INFO: [Opt 31-138] Pushed 5 inverter(s) to 8 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1c03699a3 Time (s): cpu = 00:02:12 ; elapsed = 00:02:31 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45857 ; free virtual = 66652 INFO: [Opt 31-389] Phase Retarget created 117 cells and removed 368 cells INFO: [Opt 31-1021] In phase Retarget, 457 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 13782904b Time (s): cpu = 00:02:13 ; elapsed = 00:02:32 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45817 ; free virtual = 66611 INFO: [Opt 31-389] Phase Constant propagation created 174 cells and removed 623 cells INFO: [Opt 31-1021] In phase Constant propagation, 141 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 11d683742 Time (s): cpu = 00:02:16 ; elapsed = 00:02:36 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45717 ; free virtual = 66511 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 742 cells INFO: [Opt 31-1021] In phase Sweep, 4738 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 5 BUFG optimization | Checksum: 1ae336beb Time (s): cpu = 00:02:18 ; elapsed = 00:02:38 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45702 ; free virtual = 66496 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: e593773e Time (s): cpu = 00:02:18 ; elapsed = 00:02:38 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45685 ; free virtual = 66480 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 199375099 Time (s): cpu = 00:02:19 ; elapsed = 00:02:38 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45667 ; free virtual = 66462 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 117 | 368 | 457 | | Constant propagation | 174 | 623 | 141 | | Sweep | 6 | 742 | 4738 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 3841.234 ; gain = 0.000 ; free physical = 45545 ; free virtual = 66340 Ending Logic Optimization Task | Checksum: 1368a057f Time (s): cpu = 00:02:22 ; elapsed = 00:02:42 . Memory (MB): peak = 3841.234 ; gain = 43.773 ; free physical = 45543 ; free virtual = 66339 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 1da90a966 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 45411 ; free virtual = 66267 Ending Power Optimization Task | Checksum: 1da90a966 Time (s): cpu = 00:01:17 ; elapsed = 00:01:12 . Memory (MB): peak = 4870.805 ; gain = 1029.570 ; free physical = 45513 ; free virtual = 66369 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: bd5d509d Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 44914 ; free virtual = 65770 Ending Final Cleanup Task | Checksum: bd5d509d Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 44887 ; free virtual = 65744 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 44887 ; free virtual = 65743 Ending Netlist Obfuscation Task | Checksum: bd5d509d Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 44883 ; free virtual = 65739 INFO: [Common 17-83] Releasing license: Implementation 72 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:20 ; elapsed = 00:04:36 . Memory (MB): peak = 4870.805 ; gain = 1248.316 ; free physical = 44882 ; free virtual = 65739 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 42964 ; free virtual = 64641 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:40 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 42974 ; free virtual = 64763 INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 42702 ; free virtual = 64713 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 42707 ; free virtual = 64717 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 965d2a70 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 42707 ; free virtual = 64717 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 42715 ; free virtual = 64724 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1c56e00a7 Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 41189 ; free virtual = 63178 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 15df940cb Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 40640 ; free virtual = 62647 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 15df940cb Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 40628 ; free virtual = 62635 Phase 1 Placer Initialization | Checksum: 15df940cb Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 40624 ; free virtual = 62632 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1694f1d32 Time (s): cpu = 00:01:09 ; elapsed = 00:01:10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 40527 ; free virtual = 62546 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 17cb1e348 Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 40495 ; free virtual = 62510 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 67 LUTNM shape to break, 2316 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 52, two critical 15, total 67, new lutff created 4 INFO: [Physopt 32-775] End 1 Pass. Optimized 953 nets or cells. Created 67 new cells, deleted 886 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 11 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 52 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 63 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 63 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39895 ; free virtual = 61732 INFO: [Physopt 32-76] Pass 1. Identified 12 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 8 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-232] Optimized 12 nets. Created 64 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 64 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39877 ; free virtual = 61714 INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN could not be optimized because driver GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1 could not be replicated INFO: [Physopt 32-117] Net GOLDEN_IF.hub2_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver GOLDEN_IF.hub2_axi_stream_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2 could not be replicated INFO: [Physopt 32-46] Identified 73 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[3]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[6]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[8]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[2]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[10]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[4]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/write_ptr[0]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-232] Optimized 12 nets. Created 12 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 12 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39872 ; free virtual = 61709 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 83 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_14. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_14. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_14. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_14. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_14. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/Memory_reg_16. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 15 nets or cells. Created 15 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39884 ; free virtual = 61716 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39892 ; free virtual = 61724 INFO: [Physopt 32-736] Net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg0_n_0 has fanout of one; hence not performing Critical-cell optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39882 ; free virtual = 61714 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 67 | 886 | 953 | 0 | 1 | 00:00:02 | | Very High Fanout | 63 | 0 | 2 | 0 | 1 | 00:00:04 | | Fanout | 64 | 0 | 12 | 0 | 1 | 00:00:01 | | Critical Cell | 12 | 0 | 12 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 15 | 0 | 15 | 0 | 1 | 00:00:03 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 221 | 886 | 994 | 0 | 11 | 00:00:11 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 21ed23ee5 Time (s): cpu = 00:03:24 ; elapsed = 00:03:30 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39879 ; free virtual = 61699 Phase 2.3 Global Placement Core | Checksum: 187fd6970 Time (s): cpu = 00:03:30 ; elapsed = 00:03:35 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39867 ; free virtual = 61688 Phase 2 Global Placement | Checksum: 187fd6970 Time (s): cpu = 00:03:30 ; elapsed = 00:03:35 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39900 ; free virtual = 61721 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1763e9895 Time (s): cpu = 00:03:41 ; elapsed = 00:03:46 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39879 ; free virtual = 61694 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15d016847 Time (s): cpu = 00:04:02 ; elapsed = 00:04:08 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39875 ; free virtual = 61675 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 14f5fc462 Time (s): cpu = 00:04:04 ; elapsed = 00:04:10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39899 ; free virtual = 61700 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 131982f03 Time (s): cpu = 00:04:04 ; elapsed = 00:04:10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39905 ; free virtual = 61705 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1c5a04744 Time (s): cpu = 00:04:32 ; elapsed = 00:04:39 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39864 ; free virtual = 61650 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: 25ddf2e0d Time (s): cpu = 00:05:12 ; elapsed = 00:05:19 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39561 ; free virtual = 61504 Phase 3.6 Small Shape Detail Placement | Checksum: 25ddf2e0d Time (s): cpu = 00:05:14 ; elapsed = 00:05:21 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39556 ; free virtual = 61501 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1e5c12f2d Time (s): cpu = 00:05:19 ; elapsed = 00:05:26 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39572 ; free virtual = 61505 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1f305845f Time (s): cpu = 00:05:20 ; elapsed = 00:05:27 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39576 ; free virtual = 61509 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1c566ab8f Time (s): cpu = 00:06:11 ; elapsed = 00:06:19 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39392 ; free virtual = 61321 Phase 3 Detail Placement | Checksum: 1c566ab8f Time (s): cpu = 00:06:12 ; elapsed = 00:06:20 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39391 ; free virtual = 61323 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1a392f589 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.677 | TNS=-213.008 | Phase 1 Physical Synthesis Initialization | Checksum: 23863bcea Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39047 ; free virtual = 61112 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1b097cd5e Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39064 ; free virtual = 61090 Phase 4.1.1.1 BUFG Insertion | Checksum: 1a392f589 Time (s): cpu = 00:07:06 ; elapsed = 00:07:15 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 39069 ; free virtual = 61095 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.027. For the most accurate timing information please run report_timing. Time (s): cpu = 00:10:20 ; elapsed = 00:10:31 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 37289 ; free virtual = 59956 Phase 4.1 Post Commit Optimization | Checksum: 1ebb31435 Time (s): cpu = 00:10:20 ; elapsed = 00:10:32 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 37271 ; free virtual = 59938 Post Placement Optimization Initialization | Checksum: e1328932 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.594 | TNS=-284.214 | Phase 1 Physical Synthesis Initialization | Checksum: 1a46118ca Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22325 ; free virtual = 45898 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1823a0527 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22226 ; free virtual = 45799 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.045. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 198a9b4b3 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.045 | TNS=-1.177 | Phase 1 Physical Synthesis Initialization | Checksum: 1a1f420a9 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 26005 ; free virtual = 49366 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/control_registers/status_counter_rst_i, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 23c1e28c9 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 25643 ; free virtual = 49121 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.045. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 175b42a4e Time (s): cpu = 00:19:48 ; elapsed = 00:20:04 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21733 ; free virtual = 45520 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 2x2| 4x4| |___________|___________________|___________________| | West| 2x2| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 175b42a4e Time (s): cpu = 00:19:49 ; elapsed = 00:20:05 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21663 ; free virtual = 45451 Phase 4.3 Placer Reporting | Checksum: 175b42a4e Time (s): cpu = 00:19:50 ; elapsed = 00:20:06 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21591 ; free virtual = 45377 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21589 ; free virtual = 45375 Time (s): cpu = 00:19:50 ; elapsed = 00:20:06 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21589 ; free virtual = 45375 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d46f459b Time (s): cpu = 00:19:51 ; elapsed = 00:20:07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21514 ; free virtual = 45299 Ending Placer Task | Checksum: 1addd9d04 Time (s): cpu = 00:19:51 ; elapsed = 00:20:07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21456 ; free virtual = 45243 INFO: [Common 17-83] Releasing license: Implementation 284 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:19:58 ; elapsed = 00:20:15 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21547 ; free virtual = 45334 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 26010 ; free virtual = 50174 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 25745 ; free virtual = 49585 INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.51 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 25717 ; free virtual = 49557 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.66 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 25501 ; free virtual = 49342 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 21377 ; free virtual = 45223 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.045 | TNS=-1.177 | Phase 1 Physical Synthesis Initialization | Checksum: 1fab4553d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20843 ; free virtual = 44648 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.045 | TNS=-1.177 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 1fab4553d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20809 ; free virtual = 44613 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.045 | TNS=-1.177 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_B/in_ready_sig_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[1]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.dout_valid_i_2__14 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_B/in_ready_sig_i_1__15_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_B/in_ready_sig_i_1__15_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.035 | TNS=-1.156 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[19]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[19] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[19]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.035 | TNS=-1.120 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[23]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[23] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[23]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.035 | TNS=-1.085 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[25]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[25] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[25]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.035 | TNS=-1.049 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[52]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[52] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[52]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.035 | TNS=-1.014 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[61]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[61] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[61]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.035 | TNS=-0.979 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[63]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[63] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[63]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.943 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[51]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[51] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[51]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.911 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[53]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data_reg[53] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/prefetched_data[53]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.878 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[18]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[18] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.854 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[1]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[1] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.830 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[24]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[24] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[24]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.806 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[30]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[30] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[30]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.782 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[31]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[31] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[31]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.758 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[34]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[34] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[34]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.734 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[37]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[37] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[37]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.031 | TNS=-0.703 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[43]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[43] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[43]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.672 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[50]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[50] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[50]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.669 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[51]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[51] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[51]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.666 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[52]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[52] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[52]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.663 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.663 | Phase 3 Critical Path Optimization | Checksum: 1fab4553d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20562 ; free virtual = 44366 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.019 | TNS=-0.663 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[7]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[7] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.016 | TNS=-0.660 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[50]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data_reg[50] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[50]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_1. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__3 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[64]_i_1__5_n_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/MUX_registers[5].MUX_register_A/prefetched_data[64]_i_1__5_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.289 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[14]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[14] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[14]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.275 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[27]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[27] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[27]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.260 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[28]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[28] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[28]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.246 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[54]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[54] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[54]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.009 | TNS=-0.231 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/middle_data[19]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/middle_data_reg[19] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[3].MUX_register_B/middle_data[19]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[3]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.dout_valid_i_2__15 INFO: [Physopt 32-572] Net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[3] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[3]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/packet_ready_bus_1. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/FSM_onehot_state_sig[2]_i_2__0 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[3]. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.dout_valid_i_2__15_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/packet_ready_bus_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.009 | TNS=-0.189 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[18]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data_reg[18] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_A/prefetched_data[18]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__2 INFO: [Physopt 32-572] Net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/active_reg. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/register_process.dout_valid_i_2__2 INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_reg_0. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/Packet_MUX_A/register_process.middle_valid_i_2__2_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/Packet_builders[0].Packet_Builder_register/active_reg. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.008 | TNS=-0.111 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[2]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[2] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.008 | TNS=-0.102 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[43]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[43] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[43]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.008 | TNS=-0.094 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[57]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[57] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[57]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.008 | TNS=-0.085 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[61]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data_reg[61] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[1].MUX_register_A/middle_data[61]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.077 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[64]_0[16]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[16] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[64]_0[16]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.071 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[64]_0[2]. Re-placed instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[2] INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[64]_0[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.064 | INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[64]_0[34]. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[34] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data_reg[64]_0[34]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[0]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.dout_valid_i_2__13 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/mux_ready_B_reg_bus[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/packet_ready_bus_1. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/FSM_onehot_state_sig[2]_i_2__0 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/packet_ready_bus_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/packet_valid_bus_1. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.middle_valid_i_2__4 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/packet_valid_bus_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.middle_valid_i_4__0_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.middle_valid_i_4__0 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/register_process.middle_valid_i_4__0_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data[64]_i_1__18_n_0. Did not re-place instance GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data[64]_i_1__18 INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/MUX_registers[0].MUX_register_B/out_data[64]_i_1__18_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/src_reg[3]_0[0]. Did not re-place instance GOLDEN_IF.readout_packet_block/Packet_MUX_B/src_reg[0] INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/Packet_MUX_B/src_reg[3]_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.006 | TNS=-0.064 | Phase 4 Critical Path Optimization | Checksum: 1fab4553d Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20392 ; free virtual = 44197 Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20391 ; free virtual = 44196 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.006 | TNS=-0.064 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.039 | 1.113 | 0 | 0 | 34 | 0 | 2 | 00:00:10 | | Total | 0.039 | 1.113 | 0 | 0 | 34 | 0 | 3 | 00:00:10 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20387 ; free virtual = 44192 Ending Physical Synthesis Task | Checksum: 1cf3aa41e Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20341 ; free virtual = 44146 INFO: [Common 17-83] Releasing license: Implementation 439 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:36 ; elapsed = 00:01:37 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20409 ; free virtual = 44213 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 25923 ; free virtual = 49856 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 25655 ; free virtual = 49459 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: b25faaf1 ConstDB: 0 ShapeSum: d7f56ce8 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 10f1af7a3 Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20410 ; free virtual = 44895 Post Restoration Checksum: NetGraph: 21f25851 NumContArr: ed289f52 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 10f1af7a3 Time (s): cpu = 00:00:54 ; elapsed = 00:00:55 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20452 ; free virtual = 44938 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 10f1af7a3 Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20434 ; free virtual = 44921 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 10f1af7a3 Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20434 ; free virtual = 44921 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1fb71759b Time (s): cpu = 00:01:59 ; elapsed = 00:02:01 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 24884 ; free virtual = 49481 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.040 | TNS=-0.075 | WHS=-2.781 | THS=-4906.305| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 20e50b091 Time (s): cpu = 00:02:36 ; elapsed = 00:02:38 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22429 ; free virtual = 47051 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.040 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1edb3a8bc Time (s): cpu = 00:02:37 ; elapsed = 00:02:39 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22421 ; free virtual = 47044 Phase 2 Router Initialization | Checksum: 16cf7fa16 Time (s): cpu = 00:02:37 ; elapsed = 00:02:39 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22402 ; free virtual = 47025 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 101893 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 101891 Number of Partially Routed Nets = 2 Number of Node Overlaps = 1 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 16cf7fa16 Time (s): cpu = 00:02:39 ; elapsed = 00:02:41 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22373 ; free virtual = 46997 Phase 3 Initial Routing | Checksum: 19100d5e1 Time (s): cpu = 00:05:17 ; elapsed = 00:05:22 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 29534 ; free virtual = 51979 INFO: [Route 35-580] Design has 32 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[0]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Reg_enable_reg/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[1]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 8495 Number of Nodes with overlaps = 742 Number of Nodes with overlaps = 182 Number of Nodes with overlaps = 54 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.136 | TNS=-13.155| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 18666c87b Time (s): cpu = 00:07:40 ; elapsed = 00:07:48 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 29213 ; free virtual = 51690 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 681 Number of Nodes with overlaps = 98 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.170 | TNS=-16.568| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 18b98d0e6 Time (s): cpu = 00:08:08 ; elapsed = 00:08:17 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 23486 ; free virtual = 45965 Phase 4 Rip-up And Reroute | Checksum: 18b98d0e6 Time (s): cpu = 00:08:09 ; elapsed = 00:08:17 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 23285 ; free virtual = 45765 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1fbfd433a Time (s): cpu = 00:08:22 ; elapsed = 00:08:31 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20545 ; free virtual = 43026 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.096 | TNS=-4.948 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 11c77148e Time (s): cpu = 00:08:27 ; elapsed = 00:08:36 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20066 ; free virtual = 42548 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 11c77148e Time (s): cpu = 00:08:27 ; elapsed = 00:08:36 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20047 ; free virtual = 42529 Phase 5 Delay and Skew Optimization | Checksum: 11c77148e Time (s): cpu = 00:08:28 ; elapsed = 00:08:36 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 20068 ; free virtual = 42550 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 16b3de56a Time (s): cpu = 00:08:43 ; elapsed = 00:08:52 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 19124 ; free virtual = 41608 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.023 | TNS=-0.185 | WHS=-0.972 | THS=-19.941| Phase 6.1 Hold Fix Iter | Checksum: 1a88d1931 Time (s): cpu = 00:08:45 ; elapsed = 00:08:54 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 19207 ; free virtual = 41690 Phase 6 Post Hold Fix | Checksum: 22fa9ee65 Time (s): cpu = 00:08:46 ; elapsed = 00:08:55 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 19163 ; free virtual = 41647 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1db03e4f8 Time (s): cpu = 00:09:07 ; elapsed = 00:09:16 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 23147 ; free virtual = 45630 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.023 | TNS=-0.185 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 1db03e4f8 Time (s): cpu = 00:09:08 ; elapsed = 00:09:17 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 23119 ; free virtual = 45602 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.21759 % Global Horizontal Routing Utilization = 9.88689 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 74.7748%, No Congested Regions. South Dir 1x1 Area, Max Cong = 75.6757%, No Congested Regions. East Dir 1x1 Area, Max Cong = 88.2353%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X27Y161 -> INT_R_X27Y161 INT_R_X33Y98 -> INT_R_X33Y98 INT_R_X31Y97 -> INT_R_X31Y97 INT_L_X32Y97 -> INT_L_X32Y97 INT_L_X34Y92 -> INT_L_X34Y92 West Dir 1x1 Area, Max Cong = 92.6471%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X34Y75 -> INT_L_X34Y75 INT_R_X31Y73 -> INT_R_X31Y73 INT_L_X36Y71 -> INT_L_X36Y71 INT_R_X57Y68 -> INT_R_X57Y68 INT_L_X58Y68 -> INT_L_X58Y68 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 1 Sparse Ratio: 0.75 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Phase 8 Route finalize | Checksum: 1db03e4f8 Time (s): cpu = 00:09:09 ; elapsed = 00:09:18 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 23049 ; free virtual = 45532 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1db03e4f8 Time (s): cpu = 00:09:09 ; elapsed = 00:09:18 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 23019 ; free virtual = 45503 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 164268d7f Time (s): cpu = 00:09:20 ; elapsed = 00:09:29 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22484 ; free virtual = 44975 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4870.805 ; gain = 0.000 ; free physical = 22861 ; free virtual = 45353 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.051. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 11e2bdedf Time (s): cpu = 00:02:16 ; elapsed = 00:02:17 . Memory (MB): peak = 4971.281 ; gain = 100.477 ; free physical = 18685 ; free virtual = 41176 Phase 11 Incr Placement Change | Checksum: 164268d7f Time (s): cpu = 00:11:38 ; elapsed = 00:11:49 . Memory (MB): peak = 4973.355 ; gain = 102.551 ; free physical = 18602 ; free virtual = 41094 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: c6bb588a Time (s): cpu = 00:11:58 ; elapsed = 00:12:09 . Memory (MB): peak = 4973.355 ; gain = 102.551 ; free physical = 21154 ; free virtual = 43645 Post Restoration Checksum: NetGraph: f20e1e11 NumContArr: 5b094df9 Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: 14d176c0a Time (s): cpu = 00:12:03 ; elapsed = 00:12:14 . Memory (MB): peak = 4973.355 ; gain = 102.551 ; free physical = 25098 ; free virtual = 47587 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: 14d176c0a Time (s): cpu = 00:12:04 ; elapsed = 00:12:15 . Memory (MB): peak = 4973.355 ; gain = 102.551 ; free physical = 24823 ; free virtual = 47312 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: 11972688e Time (s): cpu = 00:12:05 ; elapsed = 00:12:16 . Memory (MB): peak = 4973.355 ; gain = 102.551 ; free physical = 24553 ; free virtual = 47042 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: 160ccba11 Time (s): cpu = 00:13:32 ; elapsed = 00:13:44 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 17376 ; free virtual = 39869 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.039 | TNS=-0.227 | WHS=-2.781 | THS=-4894.368| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 199d8a862 Time (s): cpu = 00:14:08 ; elapsed = 00:14:21 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 13160 ; free virtual = 35656 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.039 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: 1ad45a033 Time (s): cpu = 00:14:09 ; elapsed = 00:14:22 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 13071 ; free virtual = 35567 Phase 13 Router Initialization | Checksum: ec18347f Time (s): cpu = 00:14:10 ; elapsed = 00:14:23 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 13015 ; free virtual = 35511 Router Utilization Summary Global Vertical Routing Utilization = 8.21488 % Global Horizontal Routing Utilization = 9.8832 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 147 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 55 Number of Partially Routed Nets = 92 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14.1 Global Routing Phase 14.1 Global Routing | Checksum: ec18347f Time (s): cpu = 00:14:12 ; elapsed = 00:14:24 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 12912 ; free virtual = 35408 Phase 14 Initial Routing | Checksum: 1a9850edf Time (s): cpu = 00:14:14 ; elapsed = 00:14:27 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 12736 ; free virtual = 35232 INFO: [Route 35-580] Design has 48 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[3]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/Mux_Value_reg[2]/R| | clk40_clk_ttc |GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt0_MGT_TX_RX_6G4_i/gthe2_i/RXOUTCLK | GOLDEN_IF.synch_ttc_combined/state_machine/delay_count_reg[3]/R| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 274 Number of Nodes with overlaps = 344 Number of Nodes with overlaps = 231 Number of Nodes with overlaps = 102 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 46 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.022 | TNS=-0.425 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: 11e809e2b Time (s): cpu = 00:15:43 ; elapsed = 00:15:58 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 18040 ; free virtual = 40537 Phase 15.2 Global Iteration 1 Number of Nodes with overlaps = 1178 Number of Nodes with overlaps = 259 Number of Nodes with overlaps = 117 Number of Nodes with overlaps = 52 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.026 | WHS=N/A | THS=N/A | Phase 15.2 Global Iteration 1 | Checksum: 2424d7866 Time (s): cpu = 00:16:26 ; elapsed = 00:16:43 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 17749 ; free virtual = 40247 Phase 15.3 Global Iteration 2 Number of Nodes with overlaps = 720 Number of Nodes with overlaps = 141 Number of Nodes with overlaps = 91 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.039 | WHS=N/A | THS=N/A | Phase 15.3 Global Iteration 2 | Checksum: 1fe4539d0 Time (s): cpu = 00:17:22 ; elapsed = 00:17:40 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 21279 ; free virtual = 43788 Phase 15 Rip-up And Reroute | Checksum: 1fe4539d0 Time (s): cpu = 00:17:23 ; elapsed = 00:17:41 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 21237 ; free virtual = 43747 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 1cad2a19e Time (s): cpu = 00:17:38 ; elapsed = 00:17:56 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 27648 ; free virtual = 50150 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.007 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 16.1 Delay CleanUp | Checksum: 2a8f20250 Time (s): cpu = 00:17:39 ; elapsed = 00:17:57 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 27552 ; free virtual = 50053 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: 2a8f20250 Time (s): cpu = 00:17:39 ; elapsed = 00:17:57 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 27493 ; free virtual = 49995 Phase 16 Delay and Skew Optimization | Checksum: 2a8f20250 Time (s): cpu = 00:17:39 ; elapsed = 00:17:57 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 27479 ; free virtual = 49980 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 2289dbb30 Time (s): cpu = 00:17:54 ; elapsed = 00:18:12 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 24502 ; free virtual = 47003 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.007 | TNS=0.000 | WHS=-0.104 | THS=-2.972 | Phase 17.1 Hold Fix Iter | Checksum: 260012b1d Time (s): cpu = 00:17:55 ; elapsed = 00:18:13 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 24398 ; free virtual = 46900 Phase 17 Post Hold Fix | Checksum: 29bba0ba4 Time (s): cpu = 00:17:55 ; elapsed = 00:18:13 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 24264 ; free virtual = 46765 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 2afcf6e7e Time (s): cpu = 00:18:16 ; elapsed = 00:18:34 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 21124 ; free virtual = 43626 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.007 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 2afcf6e7e Time (s): cpu = 00:18:16 ; elapsed = 00:18:35 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 21082 ; free virtual = 43585 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.24944 % Global Horizontal Routing Utilization = 9.92861 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 2afcf6e7e Time (s): cpu = 00:18:17 ; elapsed = 00:18:36 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 20641 ; free virtual = 43144 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 2afcf6e7e Time (s): cpu = 00:18:18 ; elapsed = 00:18:36 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 20515 ; free virtual = 43109 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: 20d635d99 Time (s): cpu = 00:18:28 ; elapsed = 00:18:46 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 23593 ; free virtual = 46095 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.006 | TNS=0.000 | WHS=0.056 | THS=0.000 | Phase 22 Post Router Timing | Checksum: 1ff62bb04 Time (s): cpu = 00:19:20 ; elapsed = 00:19:39 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 17718 ; free virtual = 40221 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 72-16] Aggressive Explore Summary +------+--------+--------+--------+-----+--------+--------------+-------------------+ | Pass | WNS | TNS | WHS | THS | Status | Elapsed Time | Solution Selected | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 1 | -0.023 | -0.185 | -0.972 | - | Pass | 00:08:34 | | +------+--------+--------+--------+-----+--------+--------------+-------------------+ | 2 | 0.007 | 0.000 | -0.104 | - | Pass | 00:06:33 | x | +------+--------+--------+--------+-----+--------+--------------+-------------------+ INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:19:20 ; elapsed = 00:19:40 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 17880 ; free virtual = 40383 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 471 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:20:11 ; elapsed = 00:20:30 . Memory (MB): peak = 5024.355 ; gain = 153.551 ; free physical = 17890 ; free virtual = 40394 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.0-71681FB INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value 71681fb will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.0-71681FB INFO: [Hog:Msg-0] Creating /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.7.0-71681FB... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5024.355 ; gain = 0.000 ; free physical = 21946 ; free virtual = 44449